From 7a39cbdddcd79d7e2257f6a78f48ca29f9ef7565 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 2 Oct 2019 00:34:29 -0700 Subject: [PATCH 1/7] bump down to innovus 18.1 --- docs/VLSI/Tutorial.rst | 5 +- vlsi/example-vlsi | 4 +- vlsi/example.yml | 2 +- vlsi/extra_libraries/example/ExampleDCO.gds | Bin 9536 -> 8556 bytes vlsi/extra_libraries/example/ExampleDCO.lef | 668 ++++++++++---------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- 7 files changed, 341 insertions(+), 342 deletions(-) diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index 7c2e0d2f..de6e0166 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -54,8 +54,9 @@ Prerequisites * Genus, Innovus, and Calibre licenses * For ASAP7 specifically: - * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it + * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin will extract and setup the PDK for you into a cache directory. * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion. + * Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded). Initial Setup ------------- @@ -83,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB -The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. +The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. Note this will dramatically increase synthesis runtimes if your design has a lot of caches. The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module. diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index a17f4f0c..264d0d8d 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -36,9 +36,7 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: set fp [open "{script_file}" "w"] puts -nonewline $fp "{script_text}" close $fp -if {{ [catch {{ exec python3 {script_file} }} msg] }} {{ - puts "$::errorInfo" -}} +exec python3 {script_file} '''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py"))) return True diff --git a/vlsi/example.yml b/vlsi/example.yml index d8ca594b..3f8c0f23 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -124,7 +124,7 @@ synthesis.genus.version: "1813" vlsi.core.par_tool: "innovus" vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] vlsi.core.par_tool_path_meta: "append" -par.innovus.version: "191" +par.innovus.version: "181" par.innovus.design_flow_effort: "standard" par.inputs.gds_merge: true # Calibre options diff --git a/vlsi/extra_libraries/example/ExampleDCO.gds b/vlsi/extra_libraries/example/ExampleDCO.gds index 9990b41cb9422c5e429e78f59005ab44cd04acc0..556f117ced6baa701af624cb5670c1bafdc0e7fe 100644 GIT binary patch literal 8556 zcmbuDUuc$99LLZ5I-i*>XZa@wCK&WjL+77T!D7}FN>FK%qRFP)TUoQov=j_Ffk6g_ z6&PgTpdy2c?5fLMb=`HBb=OsNSvP%u@7c#4ACG5e+YcT;_I-a}KJVF{$6j7nxn}dQ zTis}O{^{;sG{ncT1Yp?(@e_ogQuVKfm8CU$F4mU6;1){q@_wcl7_VapKyM zgKqW0OuLHP9gCc+?rXZoUA3g?oO^QV0{y9J_%@vVXZM7=MRKv@e&=rQ|2NNm zb^73k_`5^^4fIivhzc7G3#fK9wblpBY(HaHA{W)Lvk_eXOA8vPxd4K zGI?!Q=(6)eaxv>?j~*mX_9Oo)lWTf>@I!Jj>t~N1Bv1Au|7v+{*66bHLvk_eXOA8v zPxd4KT9a!Y_Q4Oy#jKw_dXPNXkNl6wYx9^cJ3k~BvwrsILGolj@~<KO`5ke)i}=@?<~q_sMJXoGv>*Bp0)O_UJ+KWIyunHo0bx z4}M54X8r8ZgXGD6xazt7~F{XY01xtR5{M-P%G`;q@8 zd2J5rvhzc7G3#fK9wblpBmW_jYYzM1hvZ_`&mKKUp6o~dqw?Au(`Dy}_`3~d2NpS;DPh7W#7F5cOXK7X@E50WSQ(fLowYcr86{p`_$Ie@|YU_jTF% zA-S0Kvquk-C;O5AqRBNM_~3`+V%Eaz1gaxv>?j~*mX_9OpwlWQh?@I!Jj>t~N1Bv1Au|5x(be51?G56Q)>pFMhz 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PORT - LAYER M7 ; - RECT 32.96 124.0 33.6 128.0 ; - END + PORT + LAYER M5 ; + RECT 10.608 121.536 11.088 125.536 ; + END END VDD PIN VSS DIRECTION INOUT ; USE GROUND ; - PORT + PORT LAYER M5 ; - RECT 93.12 124.0 93.76 128.0 ; - END + RECT 11.712 121.536 12.192 125.536 ; + END END VSS - PIN col_sel_b[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 113.28 4.0 113.664 ; - END - END col_sel_b[13] - PIN col_sel_b[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 107.648 4.0 108.032 ; - END - END col_sel_b[11] - PIN col_sel_b[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 90.752 4.0 91.136 ; - END - END col_sel_b[5] - PIN col_sel_b[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 110.464 4.0 110.848 ; - END - END col_sel_b[12] - PIN col_sel_b[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 104.832 4.0 105.216 ; - END - END col_sel_b[10] - PIN col_sel_b[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 102.016 4.0 102.4 ; - END - END col_sel_b[9] - PIN col_sel_b[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 99.2 4.0 99.584 ; - END - END col_sel_b[8] - PIN col_sel_b[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 96.384 4.0 96.768 ; - END - END col_sel_b[7] - PIN col_sel_b[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 93.568 4.0 93.952 ; - END - END col_sel_b[6] - PIN col_sel_b[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 87.936 4.0 88.32 ; - END - END col_sel_b[4] - PIN col_sel_b[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 85.12 4.0 85.504 ; - END - END col_sel_b[3] - PIN col_sel_b[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 82.304 4.0 82.688 ; - END - END col_sel_b[2] - PIN col_sel_b[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 79.488 4.0 79.872 ; - END - END col_sel_b[1] - PIN col_sel_b[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 76.672 4.0 77.056 ; - END - END col_sel_b[0] - PIN row_sel_b[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 71.04 4.0 71.424 ; - END - END row_sel_b[14] - PIN row_sel_b[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 68.224 4.0 68.608 ; - END - END row_sel_b[13] - PIN row_sel_b[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 65.408 4.0 65.792 ; - END - END row_sel_b[12] - PIN row_sel_b[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 62.592 4.0 62.976 ; - END - END row_sel_b[11] - PIN row_sel_b[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 59.776 4.0 60.16 ; - END - END row_sel_b[10] - PIN row_sel_b[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 56.96 4.0 57.344 ; - END - END row_sel_b[9] - PIN row_sel_b[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 54.144 4.0 54.528 ; - END - END row_sel_b[8] - PIN row_sel_b[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 51.328 4.0 51.712 ; - END - END row_sel_b[7] - PIN row_sel_b[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 48.512 4.0 48.896 ; - END - END row_sel_b[6] - PIN row_sel_b[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 45.696 4.0 46.08 ; - END - END row_sel_b[5] - PIN row_sel_b[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 42.88 4.0 43.264 ; - END - END row_sel_b[4] - PIN row_sel_b[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 40.064 4.0 40.448 ; - END - END row_sel_b[3] - PIN row_sel_b[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 37.248 4.0 37.632 ; - END - END row_sel_b[2] - PIN row_sel_b[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 34.432 4.0 34.816 ; - END - END row_sel_b[1] - PIN row_sel_b[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 31.616 4.0 32.0 ; - END - END row_sel_b[0] - PIN code_regulator[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 28.8 4.0 29.184 ; - END - END code_regulator[7] - PIN code_regulator[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 25.984 4.0 26.368 ; - END - END code_regulator[6] - PIN code_regulator[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 23.168 4.0 23.552 ; - END - END code_regulator[5] - PIN code_regulator[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 20.352 4.0 20.736 ; - END - END code_regulator[4] - PIN code_regulator[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 17.536 4.0 17.92 ; - END - END code_regulator[3] - PIN code_regulator[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 14.72 4.0 15.104 ; - END - END code_regulator[2] - PIN code_regulator[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 11.904 4.0 12.288 ; - END - END code_regulator[1] - PIN code_regulator[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 9.088 4.0 9.472 ; - END - END code_regulator[0] - PIN row_sel_b[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 73.856 4.0 74.24 ; - END - END row_sel_b[15] PIN dither DIRECTION INPUT ; USE SIGNAL ; - PORT + PORT LAYER M4 ; - RECT 0.0 6.272 4.0 6.656 ; - END + RECT 0.0 0.384 4.0 0.768 ; + END END dither + PIN row_sel_b[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 1.536 4.0 1.92 ; + END + END row_sel_b[0] + PIN row_sel_b[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 2.688 4.0 3.072 ; + END + END row_sel_b[1] + PIN row_sel_b[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 3.84 4.0 4.224 ; + END + END row_sel_b[2] + PIN row_sel_b[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 4.992 4.0 5.376 ; + END + END row_sel_b[3] + PIN row_sel_b[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 6.144 4.0 6.528 ; + END + END row_sel_b[4] + PIN row_sel_b[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 7.296 4.0 7.68 ; + END + END row_sel_b[5] + PIN row_sel_b[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 8.448 4.0 8.832 ; + END + END row_sel_b[6] + PIN row_sel_b[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 9.6 4.0 9.984 ; + END + END row_sel_b[7] + PIN row_sel_b[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 10.752 4.0 11.136 ; + END + END row_sel_b[8] + PIN row_sel_b[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 11.904 4.0 12.288 ; + END + END row_sel_b[9] + PIN row_sel_b[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 13.056 4.0 13.44 ; + END + END row_sel_b[10] + PIN row_sel_b[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 14.208 4.0 14.592 ; + END + END row_sel_b[11] + PIN row_sel_b[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 15.36 4.0 15.744 ; + END + END row_sel_b[12] + PIN row_sel_b[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 16.512 4.0 16.896 ; + END + END row_sel_b[13] + PIN row_sel_b[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 17.664 4.0 18.048 ; + END + END row_sel_b[14] + PIN row_sel_b[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 18.816 4.0 19.2 ; + END + END row_sel_b[15] + PIN col_sel_b[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 19.968 4.0 20.352 ; + END + END col_sel_b[0] + PIN col_sel_b[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 21.12 4.0 21.504 ; + END + END col_sel_b[1] + PIN col_sel_b[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 22.272 4.0 22.656 ; + END + END col_sel_b[2] + PIN col_sel_b[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 23.424 4.0 23.808 ; + END + END col_sel_b[3] + PIN col_sel_b[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 24.576 4.0 24.96 ; + END + END col_sel_b[4] + PIN col_sel_b[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 25.728 4.0 26.112 ; + END + END col_sel_b[5] + PIN col_sel_b[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 26.88 4.0 27.264 ; + END + END col_sel_b[6] + PIN col_sel_b[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 28.032 4.0 28.416 ; + END + END col_sel_b[7] + PIN col_sel_b[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 29.184 4.0 29.568 ; + END + END col_sel_b[8] + PIN col_sel_b[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 30.336 4.0 30.72 ; + END + END col_sel_b[9] + PIN col_sel_b[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 31.488 4.0 31.872 ; + END + END col_sel_b[10] + PIN col_sel_b[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 32.64 4.0 33.024 ; + END + END col_sel_b[11] + PIN col_sel_b[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 33.792 4.0 34.176 ; + END + END col_sel_b[12] + PIN col_sel_b[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 34.944 4.0 35.328 ; + END + END col_sel_b[13] + PIN code_regulator[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 36.096 4.0 36.48 ; + END + END code_regulator[0] + PIN code_regulator[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 37.248 4.0 37.632 ; + END + END code_regulator[1] + PIN code_regulator[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 38.4 4.0 38.784 ; + END + END code_regulator[2] + PIN code_regulator[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 39.552 4.0 39.936 ; + END + END code_regulator[3] + PIN code_regulator[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 40.704 4.0 41.088 ; + END + END code_regulator[4] + PIN code_regulator[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 41.856 4.0 42.24 ; + END + END code_regulator[5] + PIN code_regulator[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 43.008 4.0 43.392 ; + END + END code_regulator[6] + PIN code_regulator[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 44.16 4.0 44.544 ; + END + END code_regulator[7] PIN sleep_b DIRECTION INPUT ; USE SIGNAL ; - PORT - LAYER M5 ; - RECT 9.792 0.0 10.176 4.0 ; - END + PORT + LAYER M4 ; + RECT 0.0 45.312 4.0 45.696 ; + END END sleep_b PIN clock DIRECTION OUTPUT ; USE SIGNAL ; - PORT + PORT LAYER M4 ; - RECT 124.0 70.864 128.0 71.248 ; - END + RECT 125.536 0.384 129.536 0.768 ; + END END clock - OBS + OBS LAYER M1 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M2 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M3 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M4 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M5 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M6 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M7 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M8 ; - RECT 0.0 0.0 128.0 128.0 ; + RECT 0.0 0.0 129.536 121.536 ; LAYER M9 ; - RECT 0.0 0.0 128.0 128.0 ; + RECT 0.0 0.0 129.536 121.536 ; LAYER Pad ; - RECT 0.0 0.0 128.0 128.0 ; - END + RECT 0.0 0.0 129.536 121.536 ; + END END ExampleDCO END LIBRARY diff --git a/vlsi/hammer b/vlsi/hammer index 1b07b9a3..88226815 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 1b07b9a378c2936389b95f7ee1436e1f492d55e2 +Subproject commit 88226815243ae922ccd0d9d3810e3b6fcb6c97fd diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 06ce365b..5e93f2e7 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 06ce365b36e4b8520372968a5ef2a301afe8d5d6 +Subproject commit 5e93f2e72f5af06aaca0fbfa53e8d043d92e2341 From bb19f67aba60b2c5a99855708adca32a83397241 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 2 Oct 2019 18:50:34 -0700 Subject: [PATCH 2/7] fix innovus 18.1 not executing python script --- vlsi/example-vlsi | 7 ++++++- vlsi/hammer | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 264d0d8d..516ef588 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -24,6 +24,8 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here +set_db route_design_bottom_routing_layer 2 +set_db route_design_top_routing_layer 7 ''') return True @@ -36,7 +38,10 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: set fp [open "{script_file}" "w"] puts -nonewline $fp "{script_text}" close $fp -exec python3 {script_file} + +# Innovus <19.1 appends some bad LD_LIBRARY_PATHS, so remove them before executing python +set env(LD_LIBRARY_PATH) [join [lsearch -not -all -inline [split $env(LD_LIBRARY_PATH) ":"] "*INNOVUS*"] ":"] +python3 {script_file} '''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py"))) return True diff --git a/vlsi/hammer b/vlsi/hammer index 88226815..d8fad54d 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 88226815243ae922ccd0d9d3810e3b6fcb6c97fd +Subproject commit d8fad54d125548e50bd65dffa3a53f001e412300 From dd79c54c965b926f6a44fcb7789ad3372ac7493f Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 2 Oct 2019 19:04:57 -0700 Subject: [PATCH 3/7] bump hammer --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index d8fad54d..b5024772 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit d8fad54d125548e50bd65dffa3a53f001e412300 +Subproject commit b50247729bc536522ae42e8adb5e38277095775b From fcd48ad262532b2b782b72e33a4836f00f43a73f Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 3 Oct 2019 19:36:00 -0700 Subject: [PATCH 4/7] fix power straps --- .gitmodules | 6 +++--- vlsi/example-vlsi | 14 ++++++++++---- vlsi/example.yml | 4 ++++ vlsi/hammer | 2 +- 4 files changed, 18 insertions(+), 8 deletions(-) diff --git a/.gitmodules b/.gitmodules index 35addf76..901df05f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -60,10 +60,10 @@ url = https://github.com/freechipsproject/firrtl-interpreter.git [submodule "vlsi/hammer-cadence-plugins"] path = vlsi/hammer-cadence-plugins - url = git@github.com:ucb-bar/hammer-cadence-plugins.git + url = https://github.com/ucb-bar/hammer-cadence-plugins.git [submodule "vlsi/hammer-synopsys-plugins"] path = vlsi/hammer-synopsys-plugins - url = git@github.com:ucb-bar/hammer-synopsys-plugins.git + url = https://github.com/ucb-bar/hammer-synopsys-plugins.git [submodule "vlsi/hammer-mentor-plugins"] path = vlsi/hammer-mentor-plugins - url = git@github.com:ucb-bar/hammer-mentor-plugins.git + url = https://github.com/ucb-bar/hammer-mentor-plugins.git diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 516ef588..21ff9598 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -24,7 +24,7 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here -set_db route_design_bottom_routing_layer 2 +set_db route_design_bottom_routing_layer 1 set_db route_design_top_routing_layer 7 ''') return True @@ -32,6 +32,7 @@ set_db route_design_top_routing_layer 7 def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: """ Scale the final GDS by a factor of 4 + hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script """ x.append(''' # Write script out to a temporary file and execute it @@ -53,16 +54,21 @@ class ExampleDriver(CLIDriver): # Default set of steps can be found in the CAD tool plugin's __init__.py # make_pre_insertion_hook will execute the custom hook before the specified step - hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) + # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) + # hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), + # make_post_insertion_hook will execute the custom hook after the specified step hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings), + # make_replacement_hook will replace the specified step with a custom hook - hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), + # hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), + # make_removal_hook will remove the specified step from the flow hammer_vlsi.HammerTool.make_removal_hook("place_bumps"), + # The target step in any of the above calls may be a default step or another one of your custom hooks - # This is an example of a technology-supplied hook (look in hammer/src/hammer-vlsi/technology/asap7/__init__.py) + # This is an example of a technology-supplied hook hammer_vlsi.HammerTool.make_post_insertion_hook("write_design", scale_final_gds) ] return extra_hooks diff --git a/vlsi/example.yml b/vlsi/example.yml index 3f8c0f23..32dc23d3 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -34,7 +34,11 @@ par.generate_power_straps_options: - M7 - M8 - M9 + pin_layers: + - M9 track_width: 5 + track_width_M2: 7 # minimum allowed + track_width_M3: 7 # minimum allowed track_spacing: 0 track_start: 10 power_utilization: 0.05 diff --git a/vlsi/hammer b/vlsi/hammer index b5024772..e30da8cc 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit b50247729bc536522ae42e8adb5e38277095775b +Subproject commit e30da8cc55297db0d6fe28cfe3309f77450944c0 From ff9f54525d0c9887433130840b0f12cd371896e0 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 3 Oct 2019 21:35:05 -0700 Subject: [PATCH 5/7] turns out you need to place a 1 core site tall obstruction or else V1's will short from power straps --- vlsi/example.yml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/vlsi/example.yml b/vlsi/example.yml index 32dc23d3..024e844f 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -36,9 +36,7 @@ par.generate_power_straps_options: - M9 pin_layers: - M9 - track_width: 5 - track_width_M2: 7 # minimum allowed - track_width_M3: 7 # minimum allowed + track_width: 7 # minimum allowed for M2 & M3 track_spacing: 0 track_start: 10 power_utilization: 0.05 @@ -58,7 +56,7 @@ vlsi.inputs.placement_constraints: left: 0 right: 0 top: 0 - bottom: 1.08 #must be at least this number + bottom: 0 - path: "Sha3AccelwBB/dco" type: hardmacro x: 108 @@ -67,6 +65,13 @@ vlsi.inputs.placement_constraints: height: 128 orientation: r0 top_layer: M9 + - path: "Sha3AccelwBB/place_obs_bottom" + type: obstruction + obs_types: ["place"] + x: 0 + y: 0 + width: 300 + height: 1.08 # 1 core site tall, necessary to avoid shorts # Pin placement constraints vlsi.inputs.pin_mode: generated From 9fa76f61417d757e35dc85f6470e957ad1f01e2c Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Fri, 4 Oct 2019 00:27:44 -0700 Subject: [PATCH 6/7] post-par sim, align dco straps --- vlsi/example-vlsi | 2 +- vlsi/extra_libraries/example/ExampleDCO.gds | Bin 8556 -> 8556 bytes vlsi/extra_libraries/example/ExampleDCO.lef | 108 ++++++++++---------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- 5 files changed, 56 insertions(+), 58 deletions(-) diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 21ff9598..f853a1ed 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -24,7 +24,7 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here -set_db route_design_bottom_routing_layer 1 +set_db route_design_bottom_routing_layer 2 set_db route_design_top_routing_layer 7 ''') return True diff --git a/vlsi/extra_libraries/example/ExampleDCO.gds b/vlsi/extra_libraries/example/ExampleDCO.gds index 556f117ced6baa701af624cb5670c1bafdc0e7fe..4864e115aa2875efd1cc3ceb0dbabe47dda18668 100644 GIT binary patch literal 8556 zcmbuEUuf1<7{{OY_4T(gr_MC<1(O-{2aBA}(!q*ZQz$_rB}J1>x3^lo_Ks;O81xGa zGBElB1{o++Xi$+|b@^UJmtA)g{kiI@`)+!kbN0#O&(ra=9XNjGch8s4&h|U=63=o8Vo;{74>4*nPVqr+pX~@_sNrUNven_rN`kA8#$)o+izs}i3nx*$ca%Ixb96d-L?Fat#>b12&x1Ar7E0cca=t1&m zKk#pKc9DBZ?}y~dq@Ou@kUZKC{P(KY*8RHe{E%Fk^fN~fl1KZ2f0MI|JXm@^Bv&T= z%+Z77(SG26SiQD}bldqMxiaZzjvgeB_5=U0vx{siy&sY*lYZvtLGoxn@NZYItr6XJ zen_rN`kA8#$)o+iKkDovkComJ$(2bzbMzp2v>*7#)NAVr-FALRu1xxwqX)^O{lLG= z*+q7j-Ve!@Nk4P+AbGSO_@7d*tv$N!{E%Fk^fN~fl1KZ2f3LHP>?^$=k}H#b=IBB4 zXg}~jt6p0NbldqMxiaZzjvgeB_5=SxXBRnCdOsvrCjHFOgXGbE;6I{XTSs-<`60P7 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z%3FBWYbkHxd9SCuh5x>Mo$?m`8*?M&)k9M9bN(Ua)uU3 Date: Sun, 6 Oct 2019 14:28:03 -0700 Subject: [PATCH 7/7] [skip ci] address John's comments --- docs/VLSI/Tutorial.rst | 6 +++--- vlsi/example.yml | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index de6e0166..db1cee60 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -54,7 +54,7 @@ Prerequisites * Genus, Innovus, and Calibre licenses * For ASAP7 specifically: - * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin will extract and setup the PDK for you into a cache directory. + * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin is configured to extract the PDK into a cache directory for you. * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion. * Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded). @@ -84,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB -The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. Note this will dramatically increase synthesis runtimes if your design has a lot of caches. +The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches). The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module. @@ -99,7 +99,7 @@ example-vlsi ^^^^^^^^^^^^ This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. -The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter. This hook is run after ``write_design`` because the ASAP7 PDK requires post-par GDSs to be scaled down by a factor of 4. +The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter, and should be inserted after ``write_design``. This hook is necessary because the ASAP7 PDK does place-and-route using 4x upscaled LEFs for Innovus licensing reasons, thereby requiring the cells created in the post-P&R GDS to be scaled down by a factor of 4. example.yml ^^^^^^^^^^^ diff --git a/vlsi/example.yml b/vlsi/example.yml index 024e844f..c8e4a72b 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -38,6 +38,7 @@ par.generate_power_straps_options: - M9 track_width: 7 # minimum allowed for M2 & M3 track_spacing: 0 + track_spacing_M3: 1 # to avoid M2 shorts at higher density track_start: 10 power_utilization: 0.05 power_utilization_M8: 1.0