From a8834c77669e978658f24610e0743306bc4ce1cd Mon Sep 17 00:00:00 2001 From: James Dunn Date: Wed, 2 Sep 2020 12:48:44 -0700 Subject: [PATCH 001/157] First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build. --- .gitmodules | 3 + build.sbt | 7 + fpga/Makefile.e300artydevkit | 23 +++ fpga/bootrom/xip/Makefile | 45 ++++++ fpga/bootrom/xip/xip.S | 16 ++ fpga/common.mk | 119 +++++++++++++++ fpga/fpga-shells | 1 + fpga/src/main/scala/arty/Config.scala | 65 ++++++++ fpga/src/main/scala/arty/FPGAChip.scala | 193 ++++++++++++++++++++++++ fpga/src/main/scala/arty/Platform.scala | 178 ++++++++++++++++++++++ fpga/src/main/scala/arty/System.scala | 51 +++++++ 11 files changed, 701 insertions(+) create mode 100644 fpga/Makefile.e300artydevkit create mode 100644 fpga/bootrom/xip/Makefile create mode 100644 fpga/bootrom/xip/xip.S create mode 100644 fpga/common.mk create mode 160000 fpga/fpga-shells create mode 100644 fpga/src/main/scala/arty/Config.scala create mode 100644 fpga/src/main/scala/arty/FPGAChip.scala create mode 100644 fpga/src/main/scala/arty/Platform.scala create mode 100644 fpga/src/main/scala/arty/System.scala diff --git a/.gitmodules b/.gitmodules index aab9a8f7..ea3cb2c7 100644 --- a/.gitmodules +++ b/.gitmodules @@ -128,3 +128,6 @@ [submodule "tools/dromajo/dromajo-src"] path = tools/dromajo/dromajo-src url = https://github.com/riscv-boom/dromajo.git +[submodule "fpga/fpga-shells"] + path = fpga/fpga-shells + url = git@github.com:sifive/fpga-shells.git diff --git a/build.sbt b/build.sbt index 5d642c1d..31bb3f88 100644 --- a/build.sbt +++ b/build.sbt @@ -217,3 +217,10 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) testGrouping in Test := isolateAllTests( (definedTests in Test).value ), testOptions in Test += Tests.Argument("-oF") ) +lazy val fpgaShells = (project in file("./fpga/fpga-shells")) + .dependsOn(rocketchip, sifive_blocks) + .settings(commonSettings) + +lazy val freedomPlatforms = (project in file("./fpga")) + .dependsOn(chipyard, fpgaShells) + .settings(commonSettings) diff --git a/fpga/Makefile.e300artydevkit b/fpga/Makefile.e300artydevkit new file mode 100644 index 00000000..5f5c595b --- /dev/null +++ b/fpga/Makefile.e300artydevkit @@ -0,0 +1,23 @@ +# See LICENSE for license details. +base_dir=$(abspath ..) +BUILD_DIR := $(base_dir)/fpga/builds/e300artydevkit +FPGA_DIR := $(base_dir)/fpga/fpga-shells/xilinx +MODEL := E300ArtyDevKitFPGAChip +PROJECT := sifive.freedom.everywhere.e300artydevkit +export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit +export CONFIG := E300ArtyDevKitConfig +export BOARD := arty +export BOOTROM_DIR := $(base_dir)/fpga/bootrom/xip + +rocketchip_dir := $(base_dir)/generators/rocket-chip +sifiveblocks_dir := $(base_dir)/generators/sifive-blocks +VSRCS := \ + $(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \ + $(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \ + $(rocketchip_dir)/src/main/resources/vsrc/EICG_wrapper.v \ + $(sifiveblocks_dir)/vsrc/SRLatch.v \ + $(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \ + $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \ + $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v + +include common.mk diff --git a/fpga/bootrom/xip/Makefile b/fpga/bootrom/xip/Makefile new file mode 100644 index 00000000..57f94d49 --- /dev/null +++ b/fpga/bootrom/xip/Makefile @@ -0,0 +1,45 @@ +# RISCV environment variable must be set + +CC=$(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy +CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g +LFLAGS=-static -nostdlib + +dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb +$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts + dtc -I dts -O dtb -o $@ $< + +.PHONY: dtb +dtb: $(dtb) + +elf := $(BUILD_DIR)/xip.elf +$(elf): xip.S $(dtb) + $(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $< + +.PHONY: elf +elf: $(elf) + +bin := $(BUILD_DIR)/xip.bin +$(bin): $(elf) + $(OBJCOPY) -O binary $< $@ + +.PHONY: bin +bin: $(bin) + +hex := $(BUILD_DIR)/xip.hex +$(hex): $(bin) + od -t x4 -An -w4 -v $< > $@ + +.PHONY: hex +hex: $(hex) + +romgen := $(BUILD_DIR)/rom.v +$(romgen): $(hex) + $(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ + +.PHONY: romgen +romgen: $(romgen) + +.PHONY: clean +clean:: + rm -rf $(hex) $(elf) diff --git a/fpga/bootrom/xip/xip.S b/fpga/bootrom/xip/xip.S new file mode 100644 index 00000000..7445f4c9 --- /dev/null +++ b/fpga/bootrom/xip/xip.S @@ -0,0 +1,16 @@ +// See LICENSE for license details. +// Execute in place +// Jump directly to XIP_TARGET_ADDR + + .section .text.init + .option norvc + .globl _start +_start: + csrr a0, mhartid + la a1, dtb + li t0, XIP_TARGET_ADDR + jr t0 + + .section .rodata +dtb: + .incbin DEVICE_TREE diff --git a/fpga/common.mk b/fpga/common.mk new file mode 100644 index 00000000..5466ed7b --- /dev/null +++ b/fpga/common.mk @@ -0,0 +1,119 @@ +# See LICENSE for license details. + +# Required variables: +# - MODEL +# - PROJECT +# - CONFIG_PROJECT +# - CONFIG +# - BUILD_DIR +# - FPGA_DIR + +# Optional variables: +# - EXTRA_FPGA_VSRCS + +# export to bootloader +export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf + +# export to fpga-shells +export FPGA_TOP_SYSTEM=$(MODEL) +export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM) +export fpga_common_script_dir=$(FPGA_DIR)/common/tcl +export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl + +export BUILD_DIR + +EXTRA_FPGA_VSRCS ?= +PATCHVERILOG ?= "" +BOOTROM_DIR ?= "" + +base_dir=$(abspath ..) +export rocketchip_dir := $(base_dir)/generators/rocket-chip +SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.10 +SBT_PROJECT ?= chipyard +firrtl_dir := $(base_dir)/tools/firrtl + +# Build firrtl.jar and put it where chisel3 can find it. +FIRRTL_JAR := $(base_dir)/lib/firrtl.jar +FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver + +$(FIRRTL_JAR): $(shell find $(firrtl_dir)/src/main/scala -iname "*.scala") + $(MAKE) -C $(firrtl_dir) SBT="$(SBT)" root_dir=$(firrtl_dir) build-scala + mkdir -p $(base_dir)/lib + cp $(firrtl_dir)/utils/bin/firrtl.jar $(FIRRTL_JAR) + +# Build .fir +long_name := $(CONFIG_PROJECT).$(CONFIG) +firrtl := $(BUILD_DIR)/$(long_name).fir +$(firrtl): $(shell find $(base_dir) -name '*.scala') $(FIRRTL_JAR) + mkdir -p $(dir $@) + cd $(base_dir) && $(SBT) "project freedomPlatforms" \ + "runMain chipyard.Generator \ + --target-dir $(BUILD_DIR) \ + --name $(long_name) \ + --top-module $(PROJECT).$(MODEL) \ + --legacy-configs $(CONFIG_PROJECT).$(CONFIG)" + +.PHONY: firrtl +firrtl: $(firrtl) + +# Build .v +verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v +$(verilog): $(firrtl) $(FIRRTL_JAR) + $(FIRRTL) -i $(firrtl) -o $@ -X verilog +ifneq ($(PATCHVERILOG),"") + $(PATCHVERILOG) +endif + +.PHONY: verilog +verilog: $(verilog) + +romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v +$(romgen): $(verilog) +ifneq ($(BOOTROM_DIR),"") + $(MAKE) -C $(BOOTROM_DIR) romgen + mv $(BUILD_DIR)/rom.v $@ +endif + +.PHONY: romgen +romgen: $(romgen) + +f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F +$(f): + echo $(VSRCS) > $@ + +bit := $(BUILD_DIR)/obj/$(MODEL).bit +$(bit): $(romgen) $(f) + cd $(BUILD_DIR); vivado \ + -nojournal -mode batch \ + -source $(fpga_common_script_dir)/vivado.tcl \ + -tclargs \ + -top-module "$(MODEL)" \ + -F "$(f)" \ + -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \ + -board "$(BOARD)" + + +# Build .mcs +mcs := $(BUILD_DIR)/obj/$(MODEL).mcs +$(mcs): $(bit) + cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< + +.PHONY: mcs +mcs: $(mcs) + +# Build Libero project +prjx := $(BUILD_DIR)/libero/$(MODEL).prjx +$(prjx): $(verilog) + cd $(BUILD_DIR); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(BUILD_DIR) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)" + +.PHONY: prjx +prjx: $(prjx) + +# Clean +.PHONY: clean +clean: +ifneq ($(BOOTROM_DIR),"") + $(MAKE) -C $(BOOTROM_DIR) clean +endif + $(MAKE) -C $(FPGA_DIR) clean + rm -rf $(BUILD_DIR) diff --git a/fpga/fpga-shells b/fpga/fpga-shells new file mode 160000 index 00000000..e8e7f8a3 --- /dev/null +++ b/fpga/fpga-shells @@ -0,0 +1 @@ +Subproject commit e8e7f8a321ebde213ebc79db06422278d9aa477f diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/Config.scala new file mode 100644 index 00000000..45f83036 --- /dev/null +++ b/fpga/src/main/scala/arty/Config.scala @@ -0,0 +1,65 @@ +// See LICENSE for license details. +package sifive.freedom.everywhere.e300artydevkit + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} +import freechips.rocketchip.system._ +import freechips.rocketchip.tile._ + +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.i2c._ + +// Default FreedomEConfig +class DefaultFreedomEConfig extends Config ( + new WithNBreakpoints(2) ++ + new WithNExtTopInterrupts(0) ++ + new WithJtagDTM ++ + new TinyConfig +) + +// Freedom E300 Arty Dev Kit Peripherals +class E300DevKitPeripherals extends Config((site, here, up) => { + case PeripheryGPIOKey => List( + GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) + case PeripheryPWMKey => List( + PWMParams(address = 0x10015000, cmpWidth = 8), + PWMParams(address = 0x10025000, cmpWidth = 16), + PWMParams(address = 0x10035000, cmpWidth = 16)) + case PeripherySPIKey => List( + SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3), + SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3)) + case PeripherySPIFlashKey => List( + SPIFlashParams( + fAddress = 0x20000000, + rAddress = 0x10014000, + defaultSampleDel = 3)) + case PeripheryUARTKey => List( + UARTParams(address = 0x10013000), + UARTParams(address = 0x10023000)) + case PeripheryI2CKey => List( + I2CParams(address = 0x10016000)) + case PeripheryMockAONKey => + MockAONParams(address = 0x10000000) + case PeripheryMaskROMKey => List( + MaskROMParams(address = 0x10000, name = "BootROM")) +}) + +// Freedom E300 Arty Dev Kit Peripherals +class E300ArtyDevKitConfig extends Config( + new E300DevKitPeripherals ++ + new DefaultFreedomEConfig().alter((site,here,up) => { + case DTSTimebase => BigInt(32768) + case JtagDTMKey => new JtagDTMConfig ( + idcodeVersion = 2, + idcodePartNum = 0x000, + idcodeManufId = 0x489, + debugIdleCycles = 5) + }) +) diff --git a/fpga/src/main/scala/arty/FPGAChip.scala b/fpga/src/main/scala/arty/FPGAChip.scala new file mode 100644 index 00000000..e0b0634c --- /dev/null +++ b/fpga/src/main/scala/arty/FPGAChip.scala @@ -0,0 +1,193 @@ +// See LICENSE for license details. +package sifive.freedom.everywhere.e300artydevkit + +import Chisel._ +import chisel3.core.{attach} +import chisel3.experimental.{withClockAndReset} + +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy.{LazyModule} + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.spi._ + +import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} +import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} + +//------------------------------------------------------------------------- +// E300ArtyDevKitFPGAChip +//------------------------------------------------------------------------- + +class E300ArtyDevKitFPGAChip(implicit override val p: Parameters) extends ArtyShell { + + //----------------------------------------------------------------------- + // Clock divider + //----------------------------------------------------------------------- + val slow_clock = Wire(Bool()) + + // Divide clock by 256, used to generate 32.768 kHz clock for AON block + withClockAndReset(clock_8MHz, ~mmcm_locked) { + val clockToggleReg = RegInit(false.B) + val (_, slowTick) = Counter(true.B, 256) + when (slowTick) {clockToggleReg := ~clockToggleReg} + slow_clock := clockToggleReg + } + + //----------------------------------------------------------------------- + // DUT + //----------------------------------------------------------------------- + + withClockAndReset(clock_32MHz, ck_rst) { + val dut = Module(new E300ArtyDevKitPlatform) + + //--------------------------------------------------------------------- + // SPI flash IOBUFs + //--------------------------------------------------------------------- + + IOBUF(qspi_sck, dut.io.pins.qspi.sck) + IOBUF(qspi_cs, dut.io.pins.qspi.cs(0)) + + IOBUF(qspi_dq(0), dut.io.pins.qspi.dq(0)) + IOBUF(qspi_dq(1), dut.io.pins.qspi.dq(1)) + IOBUF(qspi_dq(2), dut.io.pins.qspi.dq(2)) + IOBUF(qspi_dq(3), dut.io.pins.qspi.dq(3)) + + //--------------------------------------------------------------------- + // JTAG IOBUFs + //--------------------------------------------------------------------- + + dut.io.pins.jtag.TCK.i.ival := IBUFG(IOBUF(jd_2).asClock).asUInt + + IOBUF(jd_5, dut.io.pins.jtag.TMS) + PULLUP(jd_5) + + IOBUF(jd_4, dut.io.pins.jtag.TDI) + PULLUP(jd_4) + + IOBUF(jd_0, dut.io.pins.jtag.TDO) + + // mimic putting a pullup on this line (part of reset vote) + SRST_n := IOBUF(jd_6) + PULLUP(jd_6) + + // jtag reset + val jtag_power_on_reset = PowerOnResetFPGAOnly(clock_32MHz) + dut.io.jtag_reset := jtag_power_on_reset + + // debug reset + dut_ndreset := dut.io.ndreset + + //--------------------------------------------------------------------- + // Assignment to package pins + //--------------------------------------------------------------------- + // Pins IO0-IO13 + // + // FTDI UART TX/RX are not connected to ck_io[0,1] + // the way they are on Arduino boards. We copy outgoing + // data to both places, switch 3 (sw[3]) determines whether + // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) + + val iobuf_ck0 = Module(new IOBUF()) + iobuf_ck0.io.I := dut.io.pins.gpio.pins(16).o.oval + iobuf_ck0.io.T := ~dut.io.pins.gpio.pins(16).o.oe + attach(iobuf_ck0.io.IO, ck_io(0)) // UART0 RX + + val iobuf_uart_txd = Module(new IOBUF()) + iobuf_uart_txd.io.I := dut.io.pins.gpio.pins(16).o.oval + iobuf_uart_txd.io.T := ~dut.io.pins.gpio.pins(16).o.oe + attach(iobuf_uart_txd.io.IO, uart_txd_in) + + // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] + val sw_3_in = IOBUF(sw_3) + dut.io.pins.gpio.pins(16).i.ival := Mux(sw_3_in, + iobuf_ck0.io.O & dut.io.pins.gpio.pins(16).o.ie, + iobuf_uart_txd.io.O & dut.io.pins.gpio.pins(16).o.ie) + + IOBUF(uart_rxd_out, dut.io.pins.gpio.pins(17)) + + // Shield header row 0: PD2-PD7 + IOBUF(ck_io(2), dut.io.pins.gpio.pins(18)) + IOBUF(ck_io(3), dut.io.pins.gpio.pins(19)) // PWM1(1) + IOBUF(ck_io(4), dut.io.pins.gpio.pins(20)) // PWM1(0) + IOBUF(ck_io(5), dut.io.pins.gpio.pins(21)) // PWM1(2) + IOBUF(ck_io(6), dut.io.pins.gpio.pins(22)) // PWM1(3) + IOBUF(ck_io(7), dut.io.pins.gpio.pins(23)) + + // Header row 1: PB0-PB5 + IOBUF(ck_io(8), dut.io.pins.gpio.pins(0)) // PWM0(0) + IOBUF(ck_io(9), dut.io.pins.gpio.pins(1)) // PWM0(1) + IOBUF(ck_io(10), dut.io.pins.gpio.pins(2)) // SPI CS(0) / PWM0(2) + IOBUF(ck_io(11), dut.io.pins.gpio.pins(3)) // SPI MOSI / PWM0(3) + IOBUF(ck_io(12), dut.io.pins.gpio.pins(4)) // SPI MISO + IOBUF(ck_io(13), dut.io.pins.gpio.pins(5)) // SPI SCK + + dut.io.pins.gpio.pins(6).i.ival := 0.U + dut.io.pins.gpio.pins(7).i.ival := 0.U + dut.io.pins.gpio.pins(8).i.ival := 0.U + + // Header row 3: A0-A5 (we don't support using them as analog inputs) + // just treat them as regular digital GPIOs + IOBUF(ck_io(15), dut.io.pins.gpio.pins(9)) // A1 = CS(2) + IOBUF(ck_io(16), dut.io.pins.gpio.pins(10)) // A2 = CS(3) / PWM2(0) + IOBUF(ck_io(17), dut.io.pins.gpio.pins(11)) // A3 = PWM2(1) + IOBUF(ck_io(18), dut.io.pins.gpio.pins(12)) // A4 = PWM2(2) / SDA + IOBUF(ck_io(19), dut.io.pins.gpio.pins(13)) // A5 = PWM2(3) / SCL + + // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty + // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active + IOBUF(led0_r, dut.io.pins.gpio.pins(1)) + IOBUF(led0_g, dut.io.pins.gpio.pins(2)) + IOBUF(led0_b, dut.io.pins.gpio.pins(3)) + + // Note that this is the one which is actually connected on the HiFive/Crazy88 + // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active + IOBUF(led1_r, dut.io.pins.gpio.pins(19)) + IOBUF(led1_g, dut.io.pins.gpio.pins(21)) + IOBUF(led1_b, dut.io.pins.gpio.pins(22)) + + // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active + IOBUF(led2_r, dut.io.pins.gpio.pins(11)) + IOBUF(led2_g, dut.io.pins.gpio.pins(12)) + IOBUF(led2_b, dut.io.pins.gpio.pins(13)) + + // Only 19 out of 20 shield pins connected to GPIO pins + // Shield pin A5 (pin 14) left unconnected + // The buttons are connected to some extra GPIO pins not connected on the + // HiFive1 board + IOBUF(btn_0, dut.io.pins.gpio.pins(15)) + IOBUF(btn_1, dut.io.pins.gpio.pins(30)) + IOBUF(btn_2, dut.io.pins.gpio.pins(31)) + + val iobuf_btn_3 = Module(new IOBUF()) + iobuf_btn_3.io.I := ~dut.io.pins.aon.pmu.dwakeup_n.o.oval + iobuf_btn_3.io.T := ~dut.io.pins.aon.pmu.dwakeup_n.o.oe + attach(btn_3, iobuf_btn_3.io.IO) + dut.io.pins.aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & dut.io.pins.aon.pmu.dwakeup_n.o.ie + + // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 + IOBUF(ja_0, dut.io.pins.gpio.pins(25)) // UART1 TX + IOBUF(ja_1, dut.io.pins.gpio.pins(24)) // UART1 RX + + // SPI2 pins mapped to 6 pin ICSP connector (standard on later + // arduinos) These are connected to some extra GPIO pins not connected + // on the HiFive1 board + IOBUF(ck_ss, dut.io.pins.gpio.pins(26)) + IOBUF(ck_mosi, dut.io.pins.gpio.pins(27)) + IOBUF(ck_miso, dut.io.pins.gpio.pins(28)) + IOBUF(ck_sck, dut.io.pins.gpio.pins(29)) + + // Use the LEDs for some more useful debugging things + IOBUF(led_0, ck_rst) + IOBUF(led_1, SRST_n) + IOBUF(led_2, dut.io.pins.aon.pmu.dwakeup_n.i.ival) + IOBUF(led_3, dut.io.pins.gpio.pins(14)) + + //--------------------------------------------------------------------- + // Unconnected inputs + //--------------------------------------------------------------------- + + dut.io.pins.aon.erst_n.i.ival := ~reset_periph + dut.io.pins.aon.lfextclk.i.ival := slow_clock + dut.io.pins.aon.pmu.vddpaden.i.ival := 1.U + } +} diff --git a/fpga/src/main/scala/arty/Platform.scala b/fpga/src/main/scala/arty/Platform.scala new file mode 100644 index 00000000..0f76cb15 --- /dev/null +++ b/fpga/src/main/scala/arty/Platform.scala @@ -0,0 +1,178 @@ +// See LICENSE for license details. +package sifive.freedom.everywhere.e300artydevkit + +import Chisel._ + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.util.ResetCatchAndSync +import freechips.rocketchip.system._ + +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.jtag._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.pinctrl._ + +//------------------------------------------------------------------------- +// PinGen +//------------------------------------------------------------------------- + +object PinGen { + def apply(): BasePin = { + val pin = new BasePin() + pin + } +} + +//------------------------------------------------------------------------- +// E300ArtyDevKitPlatformIO +//------------------------------------------------------------------------- + +class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle { + val pins = new Bundle { + val jtag = new JTAGPins(() => PinGen(), false) + val gpio = new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0)) + val qspi = new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0)) + val aon = new MockAONWrapperPins() + } + val jtag_reset = Bool(INPUT) + val ndreset = Bool(OUTPUT) +} + +//------------------------------------------------------------------------- +// E300ArtyDevKitPlatform +//------------------------------------------------------------------------- + +class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { + val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) + val io = new E300ArtyDevKitPlatformIO + + // This needs to be de-asserted synchronously to the coreClk. + val async_corerst = sys.aon.rsts.corerst + // Add in debug-controlled reset. + sys.reset := ResetCatchAndSync(clock, async_corerst, 20) + Debug.connectDebugClockAndReset(sys.debug, clock) + + //----------------------------------------------------------------------- + // Check for unsupported rocket-chip connections + //----------------------------------------------------------------------- + + require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); + + //----------------------------------------------------------------------- + // Build GPIO Pin Mux + //----------------------------------------------------------------------- + // Pin Mux for UART, SPI, PWM + // First convert the System outputs into "IOF" using the respective *GPIOPort + // converters. + + val sys_uart = sys.uart + val sys_pwm = sys.pwm + val sys_spi = sys.spi + val sys_i2c = sys.i2c + + val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} + val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} + val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} + val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} + + (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} + (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } + (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} + (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} + + //----------------------------------------------------------------------- + // Default Pin connections before attaching pinmux + + for (iof_0 <- sys.gpio(0).iof_0.get) { + iof_0.default() + } + + for (iof_1 <- sys.gpio(0).iof_1.get) { + iof_1.default() + } + + //----------------------------------------------------------------------- + + val iof_0 = sys.gpio(0).iof_0.get + val iof_1 = sys.gpio(0).iof_1.get + + // SPI1 (0 is the dedicated) + BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) + BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) + BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) + BasePinToIOF(spi_pins(0).sck, iof_0(5)) + BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) + BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) + BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) + BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) + BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) + + // SPI2 + BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) + BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) + BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) + BasePinToIOF(spi_pins(1).sck, iof_0(29)) + BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) + BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) + + // I2C + if (p(PeripheryI2CKey).length == 1) { + BasePinToIOF(i2c_pins(0).sda, iof_0(12)) + BasePinToIOF(i2c_pins(0).scl, iof_0(13)) + } + + // UART0 + BasePinToIOF(uart_pins(0).rxd, iof_0(16)) + BasePinToIOF(uart_pins(0).txd, iof_0(17)) + + // UART1 + BasePinToIOF(uart_pins(1).rxd, iof_0(24)) + BasePinToIOF(uart_pins(1).txd, iof_0(25)) + + //PWM + BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) + BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) + BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) + BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) + + BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) + BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) + BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) + BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) + + BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) + BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) + BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) + BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) + + //----------------------------------------------------------------------- + // Drive actual Pads + //----------------------------------------------------------------------- + + // Result of Pin Mux + GPIOPinsFromPort(io.pins.gpio, sys.gpio(0)) + + // Dedicated SPI Pads + SPIPinsFromPort(io.pins.qspi, sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3) + + // JTAG Debug Interface + val sjtag = sys.debug.get.systemjtag.get + JTAGPinsFromPort(io.pins.jtag, sjtag.jtag) + sjtag.reset := io.jtag_reset + sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) + + io.ndreset := sys.debug.get.ndreset + + // AON Pads -- direct connection is OK because + // EnhancedPin is hard-coded in MockAONPads + // and thus there is no .fromPort method. + io.pins.aon <> sys.aon.pins +} diff --git a/fpga/src/main/scala/arty/System.scala b/fpga/src/main/scala/arty/System.scala new file mode 100644 index 00000000..f614c06c --- /dev/null +++ b/fpga/src/main/scala/arty/System.scala @@ -0,0 +1,51 @@ +// See LICENSE for license details. +package sifive.freedom.everywhere.e300artydevkit + +import Chisel._ + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.system._ + +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.i2c._ + +//------------------------------------------------------------------------- +// E300ArtyDevKitSystem +//------------------------------------------------------------------------- + +class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem + with HasPeripheryDebug + with HasPeripheryMockAON + with chipyard.example.CanHavePeripheryGCD + with HasPeripheryUART + with HasPeripherySPIFlash + with HasPeripherySPI + with HasPeripheryGPIO + with HasPeripheryPWM + with HasPeripheryI2C { + override lazy val module = new E300ArtyDevKitSystemModule(this) +} + +class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L) + extends RocketSubsystemModuleImp(_outer) + with HasPeripheryDebugModuleImp + with chipyard.example.CanHavePeripheryGCDModuleImp + with HasPeripheryUARTModuleImp + with HasPeripherySPIModuleImp + with HasPeripheryGPIOModuleImp + with HasPeripherySPIFlashModuleImp + with HasPeripheryMockAONModuleImp + with HasPeripheryPWMModuleImp + with HasPeripheryI2CModuleImp { + // Reset vector is set to the location of the mask rom + val maskROMParams = p(PeripheryMaskROMKey) + global_reset_vector := maskROMParams(0).address.U +} From 3b6d5846729bd4ed2c8f75869251558fd6340f0c Mon Sep 17 00:00:00 2001 From: James Dunn Date: Wed, 2 Sep 2020 13:27:31 -0700 Subject: [PATCH 002/157] Adding submodule update script for FPGA tools. --- scripts/init-fpga.sh | 11 +++++++++++ scripts/init-submodules-no-riscv-tools-nolog.sh | 2 ++ 2 files changed, 13 insertions(+) create mode 100755 scripts/init-fpga.sh diff --git a/scripts/init-fpga.sh b/scripts/init-fpga.sh new file mode 100755 index 00000000..08203259 --- /dev/null +++ b/scripts/init-fpga.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +# exit script if any command fails +set -e +set -o pipefail + +# Enable submodule update for FPGA tools. +git config --unset submodule.fpga/fpga-shells.update +# Initialize local FPGA tools. +git submodule update --init --recursive fpga/fpga-shells +# Disable submodule update for FPGA tools. +git config submodule.fpga/fpga-shells.update none diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index cede5e47..c243a86f 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -39,6 +39,8 @@ git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none git config submodule.software/firemarshal.update none +# Disable updates to the local FPGA tools +git config submodule.fpga/fpga-shells.update none git submodule update --init --recursive #--jobs 8 # Un-ignore toolchain submodules From 0656c5da4f0e99e0be5a4a18626a96c6462f5006 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Sep 2020 20:29:19 -0700 Subject: [PATCH 003/157] First pass on using CY make system --- fpga/Makefile | 93 +++++++++++++++++++++++++ fpga/src/main/scala/arty/Config.scala | 4 +- fpga/src/main/scala/arty/Platform.scala | 1 + fpga/src/main/scala/arty/System.scala | 12 +++- 4 files changed, 105 insertions(+), 5 deletions(-) create mode 100644 fpga/Makefile diff --git a/fpga/Makefile b/fpga/Makefile new file mode 100644 index 00000000..dcafb930 --- /dev/null +++ b/fpga/Makefile @@ -0,0 +1,93 @@ +######################################################################################### +# fpga prototype makefile +######################################################################################### + +######################################################################################### +# general path variables +######################################################################################### +base_dir=$(abspath ..) +sim_dir=$(abspath .) + +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/variables.mk + +export SUB_PROJECT=fpga +export SBT_PROJECT=freedomPlatforms +export MODEL=E300ArtyDevKitFPGAChip +export VLOG_MODEL=E300ArtyDevKitFPGAChip +export MODEL_PACKAGE=sifive.freedom.everywhere.e300artydevkit +export CONFIG=E300ArtyDevKitConfig +export CONFIG_PACKAGE=sifive.freedom.everywhere.e300artydevkit +export GENERATOR_PACKAGE=chipyard +export TB=none +export TOP=E300ArtyDevKitPlatform +export BOARD=arty + +export bootrom_dir := $(base_dir)/fpga/bootrom/xip +fpga_dir=$(base_dir)/fpga/fpga-shells/xilinx + +sim_name = verilator # unused + +######################################################################################### +# import other necessary rules and variables +######################################################################################### +include $(base_dir)/common.mk + +######################################################################################### +# copy from other directory +######################################################################################### +romgen := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).rom.v +$(romgen): $(verilog) +ifneq ($(bootrom_dir),"") + $(MAKE) -C $(bootrom_dir) romgen + mv $(build_dir)/rom.v $@ +endif + +.PHONY: romgen +romgen: $(romgen) + +f := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F +$(f): + echo $(VSRCS) > $@ + +bit := $(build_dir)/obj/$(MODEL).bit +$(bit): $(romgen) $(f) + cd $(build_dir); vivado \ + -nojournal -mode batch \ + -source $(fpga_common_script_dir)/vivado.tcl \ + -tclargs \ + -top-module "$(MODEL)" \ + -F "$(f)" \ + -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ + -board "$(BOARD)" + + +# Build .mcs +mcs := $(build_dir)/obj/$(MODEL).mcs +$(mcs): $(bit) + cd $(build_dir); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< + +.PHONY: mcs +mcs: $(mcs) + +# Build Libero project +prjx := $(build_dir)/libero/$(MODEL).prjx +$(prjx): $(verilog) + cd $(build_dir); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(build_dir) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)" + +.PHONY: prjx +prjx: $(prjx) + + +######################################################################################### +# general cleanup rules +######################################################################################### +.PHONY: clean +clean: + rm -rf $(gen_dir) +ifneq ($(bootrom_dir),"") + $(MAKE) -C $(bootrom_dir) clean +endif + $(MAKE) -C $(FPGA_DIR) clean diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/Config.scala index 45f83036..11642164 100644 --- a/fpga/src/main/scala/arty/Config.scala +++ b/fpga/src/main/scala/arty/Config.scala @@ -47,8 +47,8 @@ class E300DevKitPeripherals extends Config((site, here, up) => { I2CParams(address = 0x10016000)) case PeripheryMockAONKey => MockAONParams(address = 0x10000000) - case PeripheryMaskROMKey => List( - MaskROMParams(address = 0x10000, name = "BootROM")) + case MaskROMLocated(InSubsystem) => List(MaskROMParams(address = 0x10000, name = "BootROM")) + case BootROMLocated(InSubsystem) => None }) // Freedom E300 Arty Dev Kit Peripherals diff --git a/fpga/src/main/scala/arty/Platform.scala b/fpga/src/main/scala/arty/Platform.scala index 0f76cb15..14c31628 100644 --- a/fpga/src/main/scala/arty/Platform.scala +++ b/fpga/src/main/scala/arty/Platform.scala @@ -51,6 +51,7 @@ class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle { //------------------------------------------------------------------------- class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { + //val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) This can be DigitalTop? val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) val io = new E300ArtyDevKitPlatformIO diff --git a/fpga/src/main/scala/arty/System.scala b/fpga/src/main/scala/arty/System.scala index f614c06c..46e5c34e 100644 --- a/fpga/src/main/scala/arty/System.scala +++ b/fpga/src/main/scala/arty/System.scala @@ -31,6 +31,12 @@ class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem with HasPeripheryGPIO with HasPeripheryPWM with HasPeripheryI2C { + val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } + val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } + + val maskROMResetVectorSourceNode = BundleBridgeSource[UInt]() + tileResetVectorNexusNode := maskROMResetVectorSourceNode + override lazy val module = new E300ArtyDevKitSystemModule(this) } @@ -45,7 +51,7 @@ class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L) with HasPeripheryMockAONModuleImp with HasPeripheryPWMModuleImp with HasPeripheryI2CModuleImp { - // Reset vector is set to the location of the mask rom - val maskROMParams = p(PeripheryMaskROMKey) - global_reset_vector := maskROMParams(0).address.U + + // connect reset vector to 1st MaskROM + _outer.maskROMResetVectorSourceNode.bundle := p(MaskROMLocated(_outer.location))(0).address.U } From 5a885fdcfd621fffe6b1ad7c9a92d0dbbdf5db9c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Sep 2020 21:28:05 -0700 Subject: [PATCH 004/157] Delete old makefiles | Full switch to CY make system --- fpga/.gitignore | 3 + fpga/Makefile | 73 +++++++---- fpga/Makefile.e300artydevkit | 23 ---- fpga/bootrom/xip/Makefile | 13 +- fpga/common.mk | 119 ------------------ .../utilities/src/main/scala/Simulator.scala | 50 ++++---- 6 files changed, 93 insertions(+), 188 deletions(-) create mode 100644 fpga/.gitignore delete mode 100644 fpga/Makefile.e300artydevkit delete mode 100644 fpga/common.mk diff --git a/fpga/.gitignore b/fpga/.gitignore new file mode 100644 index 00000000..a0991ff4 --- /dev/null +++ b/fpga/.gitignore @@ -0,0 +1,3 @@ +* +!.gitignore +!Makefile diff --git a/fpga/Makefile b/fpga/Makefile index dcafb930..837902bc 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -8,27 +8,35 @@ base_dir=$(abspath ..) sim_dir=$(abspath .) +# do not generate simulation files +sim_name := none + ######################################################################################### # include shared variables ######################################################################################### include $(base_dir)/variables.mk -export SUB_PROJECT=fpga -export SBT_PROJECT=freedomPlatforms -export MODEL=E300ArtyDevKitFPGAChip -export VLOG_MODEL=E300ArtyDevKitFPGAChip -export MODEL_PACKAGE=sifive.freedom.everywhere.e300artydevkit -export CONFIG=E300ArtyDevKitConfig -export CONFIG_PACKAGE=sifive.freedom.everywhere.e300artydevkit -export GENERATOR_PACKAGE=chipyard -export TB=none -export TOP=E300ArtyDevKitPlatform -export BOARD=arty +# default variables to build the arty example +SUB_PROJECT := fpga +SBT_PROJECT := freedomPlatforms +MODEL := E300ArtyDevKitFPGAChip +VLOG_MODEL := E300ArtyDevKitFPGAChip +MODEL_PACKAGE := sifive.freedom.everywhere.e300artydevkit +CONFIG := E300ArtyDevKitConfig +CONFIG_PACKAGE := sifive.freedom.everywhere.e300artydevkit +GENERATOR_PACKAGE := chipyard +TB := none # unused +TOP := E300ArtyDevKitPlatform -export bootrom_dir := $(base_dir)/fpga/bootrom/xip -fpga_dir=$(base_dir)/fpga/fpga-shells/xilinx +# setup the board to use +BOARD ?= arty -sim_name = verilator # unused +######################################################################################### +# misc. directories +######################################################################################### +bootrom_dir := $(base_dir)/fpga/bootrom/xip +fpga_common_script_dir := $(FPGA_DIR)/common/tcl +fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx ######################################################################################### # import other necessary rules and variables @@ -38,8 +46,23 @@ include $(base_dir)/common.mk ######################################################################################### # copy from other directory ######################################################################################### -romgen := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).rom.v -$(romgen): $(verilog) +all_vsrcs := \ + $(sim_vsrcs) \ + $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \ + $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v \ + $(build_dir)/$(long_name).rom.v + +######################################################################################### +# build rom for the fpga +######################################################################################### +# needed for bootrom makefile +export BUILD_DIR=$(build_dir) +export ROCKETCHIP_DIR +export LONG_NAME=$(long_name) +export ROMCONF=$(build_dir)/$(long_name).rom.conf + +romgen := $(build_dir)/$(long_name).rom.v +$(romgen): $(sim_vsrcs) ifneq ($(bootrom_dir),"") $(MAKE) -C $(bootrom_dir) romgen mv $(build_dir)/rom.v $@ @@ -48,9 +71,14 @@ endif .PHONY: romgen romgen: $(romgen) -f := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F -$(f): - echo $(VSRCS) > $@ +######################################################################################### +# vivado rules +######################################################################################### +# combine all sources into single .F +f := $(build_dir)/$(long_name).vsrcs.F +$(f): $(sim_common_files) $(all_vsrcs) + $(foreach file,$(all_vsrcs),echo "$(file)" >> $@;) + cat $(sim_common_files) >> $@ bit := $(build_dir)/obj/$(MODEL).bit $(bit): $(romgen) $(f) @@ -63,6 +91,8 @@ $(bit): $(romgen) $(f) -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ -board "$(BOARD)" +.PHONY: bit +bit: $(bit) # Build .mcs mcs := $(build_dir)/obj/$(MODEL).mcs @@ -72,6 +102,9 @@ $(mcs): $(bit) .PHONY: mcs mcs: $(mcs) +######################################################################################### +# mircosemi rules +######################################################################################### # Build Libero project prjx := $(build_dir)/libero/$(MODEL).prjx $(prjx): $(verilog) @@ -80,7 +113,6 @@ $(prjx): $(verilog) .PHONY: prjx prjx: $(prjx) - ######################################################################################### # general cleanup rules ######################################################################################### @@ -90,4 +122,3 @@ clean: ifneq ($(bootrom_dir),"") $(MAKE) -C $(bootrom_dir) clean endif - $(MAKE) -C $(FPGA_DIR) clean diff --git a/fpga/Makefile.e300artydevkit b/fpga/Makefile.e300artydevkit deleted file mode 100644 index 5f5c595b..00000000 --- a/fpga/Makefile.e300artydevkit +++ /dev/null @@ -1,23 +0,0 @@ -# See LICENSE for license details. -base_dir=$(abspath ..) -BUILD_DIR := $(base_dir)/fpga/builds/e300artydevkit -FPGA_DIR := $(base_dir)/fpga/fpga-shells/xilinx -MODEL := E300ArtyDevKitFPGAChip -PROJECT := sifive.freedom.everywhere.e300artydevkit -export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit -export CONFIG := E300ArtyDevKitConfig -export BOARD := arty -export BOOTROM_DIR := $(base_dir)/fpga/bootrom/xip - -rocketchip_dir := $(base_dir)/generators/rocket-chip -sifiveblocks_dir := $(base_dir)/generators/sifive-blocks -VSRCS := \ - $(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \ - $(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \ - $(rocketchip_dir)/src/main/resources/vsrc/EICG_wrapper.v \ - $(sifiveblocks_dir)/vsrc/SRLatch.v \ - $(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \ - $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \ - $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v - -include common.mk diff --git a/fpga/bootrom/xip/Makefile b/fpga/bootrom/xip/Makefile index 57f94d49..e51fd9c5 100644 --- a/fpga/bootrom/xip/Makefile +++ b/fpga/bootrom/xip/Makefile @@ -1,12 +1,17 @@ # RISCV environment variable must be set +# needs the following variables +# LONG_NAME +# BUILD_DIR +# ROCKETCHIP_DIR +# ROMCONF CC=$(RISCV)/bin/riscv64-unknown-elf-gcc OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g LFLAGS=-static -nostdlib -dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb -$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts +dtb := $(BUILD_DIR)/$(LONG_NAME).dtb +$(dtb): $(BUILD_DIR)/$(LONG_NAME).dts dtc -I dts -O dtb -o $@ $< .PHONY: dtb @@ -35,11 +40,11 @@ hex: $(hex) romgen := $(BUILD_DIR)/rom.v $(romgen): $(hex) - $(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ + $(ROCKETCHIP_DIR)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ .PHONY: romgen romgen: $(romgen) .PHONY: clean clean:: - rm -rf $(hex) $(elf) + rm -rf $(hex) $(elf) diff --git a/fpga/common.mk b/fpga/common.mk deleted file mode 100644 index 5466ed7b..00000000 --- a/fpga/common.mk +++ /dev/null @@ -1,119 +0,0 @@ -# See LICENSE for license details. - -# Required variables: -# - MODEL -# - PROJECT -# - CONFIG_PROJECT -# - CONFIG -# - BUILD_DIR -# - FPGA_DIR - -# Optional variables: -# - EXTRA_FPGA_VSRCS - -# export to bootloader -export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf - -# export to fpga-shells -export FPGA_TOP_SYSTEM=$(MODEL) -export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM) -export fpga_common_script_dir=$(FPGA_DIR)/common/tcl -export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl - -export BUILD_DIR - -EXTRA_FPGA_VSRCS ?= -PATCHVERILOG ?= "" -BOOTROM_DIR ?= "" - -base_dir=$(abspath ..) -export rocketchip_dir := $(base_dir)/generators/rocket-chip -SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.10 -SBT_PROJECT ?= chipyard -firrtl_dir := $(base_dir)/tools/firrtl - -# Build firrtl.jar and put it where chisel3 can find it. -FIRRTL_JAR := $(base_dir)/lib/firrtl.jar -FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver - -$(FIRRTL_JAR): $(shell find $(firrtl_dir)/src/main/scala -iname "*.scala") - $(MAKE) -C $(firrtl_dir) SBT="$(SBT)" root_dir=$(firrtl_dir) build-scala - mkdir -p $(base_dir)/lib - cp $(firrtl_dir)/utils/bin/firrtl.jar $(FIRRTL_JAR) - -# Build .fir -long_name := $(CONFIG_PROJECT).$(CONFIG) -firrtl := $(BUILD_DIR)/$(long_name).fir -$(firrtl): $(shell find $(base_dir) -name '*.scala') $(FIRRTL_JAR) - mkdir -p $(dir $@) - cd $(base_dir) && $(SBT) "project freedomPlatforms" \ - "runMain chipyard.Generator \ - --target-dir $(BUILD_DIR) \ - --name $(long_name) \ - --top-module $(PROJECT).$(MODEL) \ - --legacy-configs $(CONFIG_PROJECT).$(CONFIG)" - -.PHONY: firrtl -firrtl: $(firrtl) - -# Build .v -verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v -$(verilog): $(firrtl) $(FIRRTL_JAR) - $(FIRRTL) -i $(firrtl) -o $@ -X verilog -ifneq ($(PATCHVERILOG),"") - $(PATCHVERILOG) -endif - -.PHONY: verilog -verilog: $(verilog) - -romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v -$(romgen): $(verilog) -ifneq ($(BOOTROM_DIR),"") - $(MAKE) -C $(BOOTROM_DIR) romgen - mv $(BUILD_DIR)/rom.v $@ -endif - -.PHONY: romgen -romgen: $(romgen) - -f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F -$(f): - echo $(VSRCS) > $@ - -bit := $(BUILD_DIR)/obj/$(MODEL).bit -$(bit): $(romgen) $(f) - cd $(BUILD_DIR); vivado \ - -nojournal -mode batch \ - -source $(fpga_common_script_dir)/vivado.tcl \ - -tclargs \ - -top-module "$(MODEL)" \ - -F "$(f)" \ - -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \ - -board "$(BOARD)" - - -# Build .mcs -mcs := $(BUILD_DIR)/obj/$(MODEL).mcs -$(mcs): $(bit) - cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< - -.PHONY: mcs -mcs: $(mcs) - -# Build Libero project -prjx := $(BUILD_DIR)/libero/$(MODEL).prjx -$(prjx): $(verilog) - cd $(BUILD_DIR); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(BUILD_DIR) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)" - -.PHONY: prjx -prjx: $(prjx) - -# Clean -.PHONY: clean -clean: -ifneq ($(BOOTROM_DIR),"") - $(MAKE) -C $(BOOTROM_DIR) clean -endif - $(MAKE) -C $(FPGA_DIR) clean - rm -rf $(BUILD_DIR) diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index b2982db7..43edd33a 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -11,6 +11,7 @@ case class GenerateSimConfig( sealed trait Simulator object VerilatorSimulator extends Simulator object VCSSimulator extends Simulator +object NotSimulator extends Simulator trait HasGenerateSimConfig { val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { @@ -22,15 +23,16 @@ trait HasGenerateSimConfig { .action((x, c) => x match { case "verilator" => c.copy(simulator = VerilatorSimulator) case "vcs" => c.copy(simulator = VCSSimulator) + case "none" => c.copy(simulator = NotSimulator) case _ => throw new Exception(s"Unrecognized simulator $x") }) - .text("Name of simulator to generate files for (verilator, vcs)") + .text("Name of simulator to generate files for (verilator, vcs, none)") opt[String]("target-dir") .abbr("td") .valueName("") .action((x, c) => c.copy(targetDir = x)) - .text("Target director to put files") + .text("Target directory to put files") opt[String]("dotFName") .abbr("df") @@ -50,6 +52,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { case VerilatorSimulator => s"-FI ${fname}" // vcs pulls headers in with +incdir, doesn't have anything like verilator.h case VCSSimulator => "" + case _ => "" } } else { // do nothing otherwise fname @@ -82,26 +85,31 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { out.close() } def resources(sim: Simulator): Seq[String] = Seq( - "/testchipip/csrc/SimSerial.cc", - "/testchipip/csrc/SimDRAM.cc", - "/testchipip/csrc/mm.h", - "/testchipip/csrc/mm.cc", - "/testchipip/csrc/mm_dramsim2.h", - "/testchipip/csrc/mm_dramsim2.cc", - "/csrc/SimDTM.cc", - "/csrc/SimJTAG.cc", - "/csrc/remote_bitbang.h", - "/csrc/remote_bitbang.cc", "/vsrc/EICG_wrapper.v", - ) ++ (sim match { // simulator specific files to include - case VerilatorSimulator => Seq( - "/csrc/emulator.cc", - "/csrc/verilator.h", - ) - case VCSSimulator => Seq( - "/vsrc/TestDriver.v", - ) - }) + ) ++ (sim match { + case NotSimulator => Seq() + case _ => Seq( + "/testchipip/csrc/SimSerial.cc", + "/testchipip/csrc/SimDRAM.cc", + "/testchipip/csrc/mm.h", + "/testchipip/csrc/mm.cc", + "/testchipip/csrc/mm_dramsim2.h", + "/testchipip/csrc/mm_dramsim2.cc", + "/csrc/SimDTM.cc", + "/csrc/SimJTAG.cc", + "/csrc/remote_bitbang.h", + "/csrc/remote_bitbang.cc", + ) + }) ++ (sim match { // simulator specific files to include + case VerilatorSimulator => Seq( + "/csrc/emulator.cc", + "/csrc/verilator.h", + ) + case VCSSimulator => Seq( + "/vsrc/TestDriver.v", + ) + case _ => Seq() + }) def writeBootrom(): Unit = { firrtl.FileUtils.makeDirectory("./bootrom/") From 990362933db4c3b5c40ff0f762ecc1bb6eaa2f79 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 4 Sep 2020 14:16:42 -0700 Subject: [PATCH 005/157] Simple makefile variable fix to allow make mcs --- fpga/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/Makefile b/fpga/Makefile index 837902bc..ab538116 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -35,8 +35,8 @@ BOARD ?= arty # misc. directories ######################################################################################### bootrom_dir := $(base_dir)/fpga/bootrom/xip -fpga_common_script_dir := $(FPGA_DIR)/common/tcl fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx +fpga_common_script_dir := $(fpga_dir)/common/tcl ######################################################################################### # import other necessary rules and variables From 8eb807a2fdc4b2cf3397ac2ff7a1cbf316e6421a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 4 Sep 2020 18:55:56 -0700 Subject: [PATCH 006/157] Use DigitalTop in Platform | Use Chipyard BootRom --- fpga/Makefile | 30 +--------- fpga/bootrom/xip/Makefile | 50 ---------------- fpga/bootrom/xip/xip.S | 16 ------ fpga/src/main/scala/arty/Config.scala | 47 ++++++++------- fpga/src/main/scala/arty/FPGAChip.scala | 2 +- fpga/src/main/scala/arty/Platform.scala | 7 ++- fpga/src/main/scala/arty/System.scala | 57 ------------------- .../chipyard/src/main/scala/DigitalTop.scala | 8 +++ 8 files changed, 39 insertions(+), 178 deletions(-) delete mode 100644 fpga/bootrom/xip/Makefile delete mode 100644 fpga/bootrom/xip/xip.S delete mode 100644 fpga/src/main/scala/arty/System.scala diff --git a/fpga/Makefile b/fpga/Makefile index ab538116..835ffb59 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -21,9 +21,9 @@ SUB_PROJECT := fpga SBT_PROJECT := freedomPlatforms MODEL := E300ArtyDevKitFPGAChip VLOG_MODEL := E300ArtyDevKitFPGAChip -MODEL_PACKAGE := sifive.freedom.everywhere.e300artydevkit +MODEL_PACKAGE := chipyard.fpga CONFIG := E300ArtyDevKitConfig -CONFIG_PACKAGE := sifive.freedom.everywhere.e300artydevkit +CONFIG_PACKAGE := chipyard.fpga GENERATOR_PACKAGE := chipyard TB := none # unused TOP := E300ArtyDevKitPlatform @@ -34,7 +34,6 @@ BOARD ?= arty ######################################################################################### # misc. directories ######################################################################################### -bootrom_dir := $(base_dir)/fpga/bootrom/xip fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx fpga_common_script_dir := $(fpga_dir)/common/tcl @@ -49,27 +48,7 @@ include $(base_dir)/common.mk all_vsrcs := \ $(sim_vsrcs) \ $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \ - $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v \ - $(build_dir)/$(long_name).rom.v - -######################################################################################### -# build rom for the fpga -######################################################################################### -# needed for bootrom makefile -export BUILD_DIR=$(build_dir) -export ROCKETCHIP_DIR -export LONG_NAME=$(long_name) -export ROMCONF=$(build_dir)/$(long_name).rom.conf - -romgen := $(build_dir)/$(long_name).rom.v -$(romgen): $(sim_vsrcs) -ifneq ($(bootrom_dir),"") - $(MAKE) -C $(bootrom_dir) romgen - mv $(build_dir)/rom.v $@ -endif - -.PHONY: romgen -romgen: $(romgen) + $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v ######################################################################################### # vivado rules @@ -119,6 +98,3 @@ prjx: $(prjx) .PHONY: clean clean: rm -rf $(gen_dir) -ifneq ($(bootrom_dir),"") - $(MAKE) -C $(bootrom_dir) clean -endif diff --git a/fpga/bootrom/xip/Makefile b/fpga/bootrom/xip/Makefile deleted file mode 100644 index e51fd9c5..00000000 --- a/fpga/bootrom/xip/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# RISCV environment variable must be set -# needs the following variables -# LONG_NAME -# BUILD_DIR -# ROCKETCHIP_DIR -# ROMCONF - -CC=$(RISCV)/bin/riscv64-unknown-elf-gcc -OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy -CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g -LFLAGS=-static -nostdlib - -dtb := $(BUILD_DIR)/$(LONG_NAME).dtb -$(dtb): $(BUILD_DIR)/$(LONG_NAME).dts - dtc -I dts -O dtb -o $@ $< - -.PHONY: dtb -dtb: $(dtb) - -elf := $(BUILD_DIR)/xip.elf -$(elf): xip.S $(dtb) - $(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $< - -.PHONY: elf -elf: $(elf) - -bin := $(BUILD_DIR)/xip.bin -$(bin): $(elf) - $(OBJCOPY) -O binary $< $@ - -.PHONY: bin -bin: $(bin) - -hex := $(BUILD_DIR)/xip.hex -$(hex): $(bin) - od -t x4 -An -w4 -v $< > $@ - -.PHONY: hex -hex: $(hex) - -romgen := $(BUILD_DIR)/rom.v -$(romgen): $(hex) - $(ROCKETCHIP_DIR)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ - -.PHONY: romgen -romgen: $(romgen) - -.PHONY: clean -clean:: - rm -rf $(hex) $(elf) diff --git a/fpga/bootrom/xip/xip.S b/fpga/bootrom/xip/xip.S deleted file mode 100644 index 7445f4c9..00000000 --- a/fpga/bootrom/xip/xip.S +++ /dev/null @@ -1,16 +0,0 @@ -// See LICENSE for license details. -// Execute in place -// Jump directly to XIP_TARGET_ADDR - - .section .text.init - .option norvc - .globl _start -_start: - csrr a0, mhartid - la a1, dtb - li t0, XIP_TARGET_ADDR - jr t0 - - .section .rodata -dtb: - .incbin DEVICE_TREE diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/Config.scala index 11642164..73fb8b31 100644 --- a/fpga/src/main/scala/arty/Config.scala +++ b/fpga/src/main/scala/arty/Config.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package sifive.freedom.everywhere.e300artydevkit +package chipyard.fpga import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -16,16 +16,7 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ -// Default FreedomEConfig -class DefaultFreedomEConfig extends Config ( - new WithNBreakpoints(2) ++ - new WithNExtTopInterrupts(0) ++ - new WithJtagDTM ++ - new TinyConfig -) - -// Freedom E300 Arty Dev Kit Peripherals -class E300DevKitPeripherals extends Config((site, here, up) => { +class E300DevKitExtra extends Config((site, here, up) => { case PeripheryGPIOKey => List( GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) case PeripheryPWMKey => List( @@ -47,19 +38,27 @@ class E300DevKitPeripherals extends Config((site, here, up) => { I2CParams(address = 0x10016000)) case PeripheryMockAONKey => MockAONParams(address = 0x10000000) - case MaskROMLocated(InSubsystem) => List(MaskROMParams(address = 0x10000, name = "BootROM")) - case BootROMLocated(InSubsystem) => None + case DTSTimebase => BigInt(32768) + case JtagDTMKey => new JtagDTMConfig ( + idcodeVersion = 2, + idcodePartNum = 0x000, + idcodeManufId = 0x489, + debugIdleCycles = 5) }) -// Freedom E300 Arty Dev Kit Peripherals class E300ArtyDevKitConfig extends Config( - new E300DevKitPeripherals ++ - new DefaultFreedomEConfig().alter((site,here,up) => { - case DTSTimebase => BigInt(32768) - case JtagDTMKey => new JtagDTMConfig ( - idcodeVersion = 2, - idcodePartNum = 0x000, - idcodeManufId = 0x489, - debugIdleCycles = 5) - }) -) + new E300DevKitExtra ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.With1TinyCore ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/arty/FPGAChip.scala b/fpga/src/main/scala/arty/FPGAChip.scala index e0b0634c..26e75500 100644 --- a/fpga/src/main/scala/arty/FPGAChip.scala +++ b/fpga/src/main/scala/arty/FPGAChip.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package sifive.freedom.everywhere.e300artydevkit +package chipyard.fpga import Chisel._ import chisel3.core.{attach} diff --git a/fpga/src/main/scala/arty/Platform.scala b/fpga/src/main/scala/arty/Platform.scala index 14c31628..514ff74c 100644 --- a/fpga/src/main/scala/arty/Platform.scala +++ b/fpga/src/main/scala/arty/Platform.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package sifive.freedom.everywhere.e300artydevkit +package chipyard.fpga import Chisel._ @@ -20,6 +20,8 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.pinctrl._ +import chipyard.{DigitalTop} + //------------------------------------------------------------------------- // PinGen //------------------------------------------------------------------------- @@ -51,8 +53,7 @@ class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle { //------------------------------------------------------------------------- class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { - //val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) This can be DigitalTop? - val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) + val sys = Module(LazyModule(new DigitalTop).module) val io = new E300ArtyDevKitPlatformIO // This needs to be de-asserted synchronously to the coreClk. diff --git a/fpga/src/main/scala/arty/System.scala b/fpga/src/main/scala/arty/System.scala deleted file mode 100644 index 46e5c34e..00000000 --- a/fpga/src/main/scala/arty/System.scala +++ /dev/null @@ -1,57 +0,0 @@ -// See LICENSE for license details. -package sifive.freedom.everywhere.e300artydevkit - -import Chisel._ - -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.system._ - -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ - -//------------------------------------------------------------------------- -// E300ArtyDevKitSystem -//------------------------------------------------------------------------- - -class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem - with HasPeripheryDebug - with HasPeripheryMockAON - with chipyard.example.CanHavePeripheryGCD - with HasPeripheryUART - with HasPeripherySPIFlash - with HasPeripherySPI - with HasPeripheryGPIO - with HasPeripheryPWM - with HasPeripheryI2C { - val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } - val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } - - val maskROMResetVectorSourceNode = BundleBridgeSource[UInt]() - tileResetVectorNexusNode := maskROMResetVectorSourceNode - - override lazy val module = new E300ArtyDevKitSystemModule(this) -} - -class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L) - extends RocketSubsystemModuleImp(_outer) - with HasPeripheryDebugModuleImp - with chipyard.example.CanHavePeripheryGCDModuleImp - with HasPeripheryUARTModuleImp - with HasPeripherySPIModuleImp - with HasPeripheryGPIOModuleImp - with HasPeripherySPIFlashModuleImp - with HasPeripheryMockAONModuleImp - with HasPeripheryPWMModuleImp - with HasPeripheryI2CModuleImp { - - // connect reset vector to 1st MaskROM - _outer.maskROMResetVectorSourceNode.bundle := p(MaskROMLocated(_outer.location))(0).address.U -} diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 81d0003d..160e6acf 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -13,6 +13,10 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem + with sifive.blocks.devices.mockaon.HasPeripheryMockAON + with sifive.blocks.devices.spi.HasPeripherySPI + with sifive.blocks.devices.pwm.HasPeripheryPWM + with sifive.blocks.devices.i2c.HasPeripheryI2C with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device @@ -31,6 +35,10 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem } class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) + with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIModuleImp + with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp + with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp From 1fa1b6d57f1bc5dc0e2a1cbe248501af843f7e82 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 4 Sep 2020 19:03:26 -0700 Subject: [PATCH 007/157] Small makefile cleanup --- fpga/Makefile | 34 +++++++++++++--------------------- 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index 835ffb59..e0882e63 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -31,6 +31,9 @@ TOP := E300ArtyDevKitPlatform # setup the board to use BOARD ?= arty +.PHONY: default +default: $(mcs) + ######################################################################################### # misc. directories ######################################################################################### @@ -53,44 +56,33 @@ all_vsrcs := \ ######################################################################################### # vivado rules ######################################################################################### -# combine all sources into single .F -f := $(build_dir)/$(long_name).vsrcs.F -$(f): $(sim_common_files) $(all_vsrcs) +# combine all sources into single .f +synth_list_f := $(build_dir)/$(long_name).vsrcs.f +$(synth_list_f): $(sim_common_files) $(all_vsrcs) $(foreach file,$(all_vsrcs),echo "$(file)" >> $@;) cat $(sim_common_files) >> $@ -bit := $(build_dir)/obj/$(MODEL).bit -$(bit): $(romgen) $(f) +BIT_FILE := $(build_dir)/obj/$(MODEL).bit +$(BIT_FILE): $(synth_list_f) cd $(build_dir); vivado \ -nojournal -mode batch \ -source $(fpga_common_script_dir)/vivado.tcl \ -tclargs \ -top-module "$(MODEL)" \ - -F "$(f)" \ + -F "$(synth_list_f)" \ -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ -board "$(BOARD)" .PHONY: bit -bit: $(bit) +bit: $(BIT_FILE) # Build .mcs -mcs := $(build_dir)/obj/$(MODEL).mcs -$(mcs): $(bit) +MCS_FILE := $(build_dir)/obj/$(MODEL).mcs +$(MCS_FILE): $(BIT_FILE) cd $(build_dir); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< .PHONY: mcs -mcs: $(mcs) - -######################################################################################### -# mircosemi rules -######################################################################################### -# Build Libero project -prjx := $(build_dir)/libero/$(MODEL).prjx -$(prjx): $(verilog) - cd $(build_dir); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(build_dir) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)" - -.PHONY: prjx -prjx: $(prjx) +mcs: $(MCS_FILE) ######################################################################################### # general cleanup rules From a8083aa5709d9c17591de3d55bd146cba6ced532 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 7 Sep 2020 11:47:37 -0700 Subject: [PATCH 008/157] First pass at fpga-shells with IOBinders --- build.sbt | 6 +- common.mk | 2 +- fpga/Makefile | 12 +- fpga/src/main/scala/arty/Config.scala | 3 +- fpga/src/main/scala/arty/FPGAChip.scala | 193 ----------- fpga/src/main/scala/arty/IOBinders.scala | 357 +++++++++++++++++++++ fpga/src/main/scala/arty/Platform.scala | 180 ----------- fpga/src/main/scala/arty/TestHarness.scala | 34 ++ 8 files changed, 403 insertions(+), 384 deletions(-) delete mode 100644 fpga/src/main/scala/arty/FPGAChip.scala create mode 100644 fpga/src/main/scala/arty/IOBinders.scala delete mode 100644 fpga/src/main/scala/arty/Platform.scala create mode 100644 fpga/src/main/scala/arty/TestHarness.scala diff --git a/build.sbt b/build.sbt index 31bb3f88..ffe8bfe8 100644 --- a/build.sbt +++ b/build.sbt @@ -217,10 +217,10 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) testGrouping in Test := isolateAllTests( (definedTests in Test).value ), testOptions in Test += Tests.Argument("-oF") ) -lazy val fpgaShells = (project in file("./fpga/fpga-shells")) +lazy val fpga_shells = (project in file("./fpga/fpga-shells")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) -lazy val freedomPlatforms = (project in file("./fpga")) - .dependsOn(chipyard, fpgaShells) +lazy val fpga_platforms = (project in file("./fpga")) + .dependsOn(chipyard, fpga_shells) .settings(commonSettings) diff --git a/common.mk b/common.mk index 89ebbea3..ee290ddc 100644 --- a/common.mk +++ b/common.mk @@ -58,7 +58,7 @@ include $(base_dir)/tools/dromajo/dromajo.mk # Returns a list of files in directory $1 with file extension $2. lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources diff --git a/fpga/Makefile b/fpga/Makefile index e0882e63..0110bb10 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -18,15 +18,15 @@ include $(base_dir)/variables.mk # default variables to build the arty example SUB_PROJECT := fpga -SBT_PROJECT := freedomPlatforms -MODEL := E300ArtyDevKitFPGAChip -VLOG_MODEL := E300ArtyDevKitFPGAChip -MODEL_PACKAGE := chipyard.fpga +SBT_PROJECT := fpga_platforms +MODEL := ArtyFPGATestHarness +VLOG_MODEL := ArtyFPGATestHarness +MODEL_PACKAGE := chipyard.fpga.arty CONFIG := E300ArtyDevKitConfig -CONFIG_PACKAGE := chipyard.fpga +CONFIG_PACKAGE := chipyard.fpga.arty GENERATOR_PACKAGE := chipyard TB := none # unused -TOP := E300ArtyDevKitPlatform +TOP := ChipTop # setup the board to use BOARD ?= arty diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/Config.scala index 73fb8b31..bcea7c78 100644 --- a/fpga/src/main/scala/arty/Config.scala +++ b/fpga/src/main/scala/arty/Config.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package chipyard.fpga +package chipyard.fpga.arty import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -47,6 +47,7 @@ class E300DevKitExtra extends Config((site, here, up) => { }) class E300ArtyDevKitConfig extends Config( + new WithE300Connections ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/arty/FPGAChip.scala b/fpga/src/main/scala/arty/FPGAChip.scala deleted file mode 100644 index 26e75500..00000000 --- a/fpga/src/main/scala/arty/FPGAChip.scala +++ /dev/null @@ -1,193 +0,0 @@ -// See LICENSE for license details. -package chipyard.fpga - -import Chisel._ -import chisel3.core.{attach} -import chisel3.experimental.{withClockAndReset} - -import freechips.rocketchip.config._ -import freechips.rocketchip.diplomacy.{LazyModule} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.spi._ - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - -//------------------------------------------------------------------------- -// E300ArtyDevKitFPGAChip -//------------------------------------------------------------------------- - -class E300ArtyDevKitFPGAChip(implicit override val p: Parameters) extends ArtyShell { - - //----------------------------------------------------------------------- - // Clock divider - //----------------------------------------------------------------------- - val slow_clock = Wire(Bool()) - - // Divide clock by 256, used to generate 32.768 kHz clock for AON block - withClockAndReset(clock_8MHz, ~mmcm_locked) { - val clockToggleReg = RegInit(false.B) - val (_, slowTick) = Counter(true.B, 256) - when (slowTick) {clockToggleReg := ~clockToggleReg} - slow_clock := clockToggleReg - } - - //----------------------------------------------------------------------- - // DUT - //----------------------------------------------------------------------- - - withClockAndReset(clock_32MHz, ck_rst) { - val dut = Module(new E300ArtyDevKitPlatform) - - //--------------------------------------------------------------------- - // SPI flash IOBUFs - //--------------------------------------------------------------------- - - IOBUF(qspi_sck, dut.io.pins.qspi.sck) - IOBUF(qspi_cs, dut.io.pins.qspi.cs(0)) - - IOBUF(qspi_dq(0), dut.io.pins.qspi.dq(0)) - IOBUF(qspi_dq(1), dut.io.pins.qspi.dq(1)) - IOBUF(qspi_dq(2), dut.io.pins.qspi.dq(2)) - IOBUF(qspi_dq(3), dut.io.pins.qspi.dq(3)) - - //--------------------------------------------------------------------- - // JTAG IOBUFs - //--------------------------------------------------------------------- - - dut.io.pins.jtag.TCK.i.ival := IBUFG(IOBUF(jd_2).asClock).asUInt - - IOBUF(jd_5, dut.io.pins.jtag.TMS) - PULLUP(jd_5) - - IOBUF(jd_4, dut.io.pins.jtag.TDI) - PULLUP(jd_4) - - IOBUF(jd_0, dut.io.pins.jtag.TDO) - - // mimic putting a pullup on this line (part of reset vote) - SRST_n := IOBUF(jd_6) - PULLUP(jd_6) - - // jtag reset - val jtag_power_on_reset = PowerOnResetFPGAOnly(clock_32MHz) - dut.io.jtag_reset := jtag_power_on_reset - - // debug reset - dut_ndreset := dut.io.ndreset - - //--------------------------------------------------------------------- - // Assignment to package pins - //--------------------------------------------------------------------- - // Pins IO0-IO13 - // - // FTDI UART TX/RX are not connected to ck_io[0,1] - // the way they are on Arduino boards. We copy outgoing - // data to both places, switch 3 (sw[3]) determines whether - // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) - - val iobuf_ck0 = Module(new IOBUF()) - iobuf_ck0.io.I := dut.io.pins.gpio.pins(16).o.oval - iobuf_ck0.io.T := ~dut.io.pins.gpio.pins(16).o.oe - attach(iobuf_ck0.io.IO, ck_io(0)) // UART0 RX - - val iobuf_uart_txd = Module(new IOBUF()) - iobuf_uart_txd.io.I := dut.io.pins.gpio.pins(16).o.oval - iobuf_uart_txd.io.T := ~dut.io.pins.gpio.pins(16).o.oe - attach(iobuf_uart_txd.io.IO, uart_txd_in) - - // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] - val sw_3_in = IOBUF(sw_3) - dut.io.pins.gpio.pins(16).i.ival := Mux(sw_3_in, - iobuf_ck0.io.O & dut.io.pins.gpio.pins(16).o.ie, - iobuf_uart_txd.io.O & dut.io.pins.gpio.pins(16).o.ie) - - IOBUF(uart_rxd_out, dut.io.pins.gpio.pins(17)) - - // Shield header row 0: PD2-PD7 - IOBUF(ck_io(2), dut.io.pins.gpio.pins(18)) - IOBUF(ck_io(3), dut.io.pins.gpio.pins(19)) // PWM1(1) - IOBUF(ck_io(4), dut.io.pins.gpio.pins(20)) // PWM1(0) - IOBUF(ck_io(5), dut.io.pins.gpio.pins(21)) // PWM1(2) - IOBUF(ck_io(6), dut.io.pins.gpio.pins(22)) // PWM1(3) - IOBUF(ck_io(7), dut.io.pins.gpio.pins(23)) - - // Header row 1: PB0-PB5 - IOBUF(ck_io(8), dut.io.pins.gpio.pins(0)) // PWM0(0) - IOBUF(ck_io(9), dut.io.pins.gpio.pins(1)) // PWM0(1) - IOBUF(ck_io(10), dut.io.pins.gpio.pins(2)) // SPI CS(0) / PWM0(2) - IOBUF(ck_io(11), dut.io.pins.gpio.pins(3)) // SPI MOSI / PWM0(3) - IOBUF(ck_io(12), dut.io.pins.gpio.pins(4)) // SPI MISO - IOBUF(ck_io(13), dut.io.pins.gpio.pins(5)) // SPI SCK - - dut.io.pins.gpio.pins(6).i.ival := 0.U - dut.io.pins.gpio.pins(7).i.ival := 0.U - dut.io.pins.gpio.pins(8).i.ival := 0.U - - // Header row 3: A0-A5 (we don't support using them as analog inputs) - // just treat them as regular digital GPIOs - IOBUF(ck_io(15), dut.io.pins.gpio.pins(9)) // A1 = CS(2) - IOBUF(ck_io(16), dut.io.pins.gpio.pins(10)) // A2 = CS(3) / PWM2(0) - IOBUF(ck_io(17), dut.io.pins.gpio.pins(11)) // A3 = PWM2(1) - IOBUF(ck_io(18), dut.io.pins.gpio.pins(12)) // A4 = PWM2(2) / SDA - IOBUF(ck_io(19), dut.io.pins.gpio.pins(13)) // A5 = PWM2(3) / SCL - - // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty - // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active - IOBUF(led0_r, dut.io.pins.gpio.pins(1)) - IOBUF(led0_g, dut.io.pins.gpio.pins(2)) - IOBUF(led0_b, dut.io.pins.gpio.pins(3)) - - // Note that this is the one which is actually connected on the HiFive/Crazy88 - // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active - IOBUF(led1_r, dut.io.pins.gpio.pins(19)) - IOBUF(led1_g, dut.io.pins.gpio.pins(21)) - IOBUF(led1_b, dut.io.pins.gpio.pins(22)) - - // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active - IOBUF(led2_r, dut.io.pins.gpio.pins(11)) - IOBUF(led2_g, dut.io.pins.gpio.pins(12)) - IOBUF(led2_b, dut.io.pins.gpio.pins(13)) - - // Only 19 out of 20 shield pins connected to GPIO pins - // Shield pin A5 (pin 14) left unconnected - // The buttons are connected to some extra GPIO pins not connected on the - // HiFive1 board - IOBUF(btn_0, dut.io.pins.gpio.pins(15)) - IOBUF(btn_1, dut.io.pins.gpio.pins(30)) - IOBUF(btn_2, dut.io.pins.gpio.pins(31)) - - val iobuf_btn_3 = Module(new IOBUF()) - iobuf_btn_3.io.I := ~dut.io.pins.aon.pmu.dwakeup_n.o.oval - iobuf_btn_3.io.T := ~dut.io.pins.aon.pmu.dwakeup_n.o.oe - attach(btn_3, iobuf_btn_3.io.IO) - dut.io.pins.aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & dut.io.pins.aon.pmu.dwakeup_n.o.ie - - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 - IOBUF(ja_0, dut.io.pins.gpio.pins(25)) // UART1 TX - IOBUF(ja_1, dut.io.pins.gpio.pins(24)) // UART1 RX - - // SPI2 pins mapped to 6 pin ICSP connector (standard on later - // arduinos) These are connected to some extra GPIO pins not connected - // on the HiFive1 board - IOBUF(ck_ss, dut.io.pins.gpio.pins(26)) - IOBUF(ck_mosi, dut.io.pins.gpio.pins(27)) - IOBUF(ck_miso, dut.io.pins.gpio.pins(28)) - IOBUF(ck_sck, dut.io.pins.gpio.pins(29)) - - // Use the LEDs for some more useful debugging things - IOBUF(led_0, ck_rst) - IOBUF(led_1, SRST_n) - IOBUF(led_2, dut.io.pins.aon.pmu.dwakeup_n.i.ival) - IOBUF(led_3, dut.io.pins.gpio.pins(14)) - - //--------------------------------------------------------------------- - // Unconnected inputs - //--------------------------------------------------------------------- - - dut.io.pins.aon.erst_n.i.ival := ~reset_periph - dut.io.pins.aon.lfextclk.i.ival := slow_clock - dut.io.pins.aon.pmu.vddpaden.i.ival := 1.U - } -} diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala new file mode 100644 index 00000000..e8833827 --- /dev/null +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -0,0 +1,357 @@ +package chipyard.fpga.arty + +import chisel3._ +import chisel3.experimental.{attach, IO} + +import freechips.rocketchip.util._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.subsystem.{NExtTopInterrupts} + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.jtag._ +import sifive.blocks.devices.pinctrl._ + +import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} +import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} + +import chipsalliance.rocketchip.config._ + +import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} +import chipyard.{HasHarnessSignalReferences} + +class WithE300Connections extends OverrideIOBinder({ + (system: HasPeripheryGPIOModuleImp + with HasPeripheryUARTModuleImp + with HasPeripherySPIModuleImp + with HasPeripheryDebugModuleImp + with HasPeripheryPWMModuleImp + with HasPeripherySPIFlashModuleImp + with HasPeripheryMockAONModuleImp + with HasPeripheryI2CModuleImp) => { + // match the E300 connections using a "Chipyard"-like structure + + implicit val p: Parameters = GetSystemParameters(system) + + object PinGen { + def apply(): BasePin = { + val pin = new BasePin() + pin + } + } + + val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") + val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") + val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") + val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") + val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") + val io_ndreset = IO(Output(Bool())).suggestName("ndreset") + + // TODO: Fix + // add iocells (or none) + // This needs to be de-asserted synchronously to the coreClk. + val async_corerst = system.aon.rsts.corerst + // Add in debug-controlled reset. + system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) + Debug.connectDebugClockAndReset(system.debug, system.clock) + + //----------------------------------------------------------------------- + // Check for unsupported rocket-chip connections + //----------------------------------------------------------------------- + + require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); + + //----------------------------------------------------------------------- + // Build GPIO Pin Mux + //----------------------------------------------------------------------- + // Pin Mux for UART, SPI, PWM + // First convert the System outputs into "IOF" using the respective *GPIOPort + // converters. + + val sys_uart = system.uart + val sys_pwm = system.pwm + val sys_spi = system.spi + val sys_i2c = system.i2c + + val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} + val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} + val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} + val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} + + (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} + (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } + (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} + (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} + + //----------------------------------------------------------------------- + // Default Pin connections before attaching pinmux + + for (iof_0 <- system.gpio(0).iof_0.get) { + iof_0.default() + } + + for (iof_1 <- system.gpio(0).iof_1.get) { + iof_1.default() + } + + //----------------------------------------------------------------------- + + val iof_0 = system.gpio(0).iof_0.get + val iof_1 = system.gpio(0).iof_1.get + + // SPI1 (0 is the dedicated) + BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) + BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) + BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) + BasePinToIOF(spi_pins(0).sck, iof_0(5)) + BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) + BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) + BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) + BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) + BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) + + // SPI2 + BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) + BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) + BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) + BasePinToIOF(spi_pins(1).sck, iof_0(29)) + BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) + BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) + + // I2C + if (p(PeripheryI2CKey).length == 1) { + BasePinToIOF(i2c_pins(0).sda, iof_0(12)) + BasePinToIOF(i2c_pins(0).scl, iof_0(13)) + } + + // UART0 + BasePinToIOF(uart_pins(0).rxd, iof_0(16)) + BasePinToIOF(uart_pins(0).txd, iof_0(17)) + + // UART1 + BasePinToIOF(uart_pins(1).rxd, iof_0(24)) + BasePinToIOF(uart_pins(1).txd, iof_0(25)) + + //PWM + BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) + BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) + BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) + BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) + + BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) + BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) + BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) + BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) + + BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) + BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) + BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) + BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) + + //----------------------------------------------------------------------- + // Drive actual Pads + //----------------------------------------------------------------------- + + // Result of Pin Mux + GPIOPinsFromPort(io_gpio, system.gpio(0)) + + // Dedicated SPI Pads + SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) + + // JTAG Debug Interface + val sjtag = system.debug.get.systemjtag.get + JTAGPinsFromPort(io_jtag, sjtag.jtag) + sjtag.reset := io_jtag_reset + sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) + + io_ndreset := system.debug.get.ndreset + + // AON Pads -- direct connection is OK because + // EnhancedPin is hard-coded in MockAONPads + // and thus there is no .fromPort method. + io_aon <> system.aon.pins + + val harnessFn = (baseTh: HasHarnessSignalReferences) => { + baseTh match { case th: ArtyShell => + + //----------------------------------------------------------------------- + // Clock divider + //----------------------------------------------------------------------- + val slow_clock = Wire(Bool()) + + // Divide clock by 256, used to generate 32.768 kHz clock for AON block + withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { + val clockToggleReg = RegInit(false.B) + val (_, slowTick) = chisel3.util.Counter(true.B, 256) + when (slowTick) {clockToggleReg := ~clockToggleReg} + slow_clock := clockToggleReg + } + + //----------------------------------------------------------------------- + // DUT + //----------------------------------------------------------------------- + withClockAndReset(th.clock_32MHz, th.ck_rst) { + + //--------------------------------------------------------------------- + // SPI flash IOBUFs + //--------------------------------------------------------------------- + + IOBUF(th.qspi_sck, io_qspi.sck) + IOBUF(th.qspi_cs, io_qspi.cs(0)) + + IOBUF(th.qspi_dq(0), io_qspi.dq(0)) + IOBUF(th.qspi_dq(1), io_qspi.dq(1)) + IOBUF(th.qspi_dq(2), io_qspi.dq(2)) + IOBUF(th.qspi_dq(3), io_qspi.dq(3)) + + //--------------------------------------------------------------------- + // JTAG IOBUFs + //--------------------------------------------------------------------- + + io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt + + IOBUF(th.jd_5, io_jtag.TMS) + PULLUP(th.jd_5) + + IOBUF(th.jd_4, io_jtag.TDI) + PULLUP(th.jd_4) + + IOBUF(th.jd_0, io_jtag.TDO) + + // mimic putting a pullup on this line (part of reset vote) + th.SRST_n := IOBUF(th.jd_6) + PULLUP(th.jd_6) + + // jtag reset + val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) + io_jtag_reset := jtag_power_on_reset + + // debug reset + th.dut_ndreset := io_ndreset + + //--------------------------------------------------------------------- + // Assignment to package pins + //--------------------------------------------------------------------- + // Pins IO0-IO13 + // + // FTDI UART TX/RX are not connected to th.ck_io[0,1] + // the way they are on Arduino boards. We copy outgoing + // data to both places, switch 3 (sw[3]) determines whether + // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) + + val iobuf_ck0 = Module(new IOBUF()) + iobuf_ck0.io.I := io_gpio.pins(16).o.oval + iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe + attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX + + val iobuf_uart_txd = Module(new IOBUF()) + iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval + iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe + attach(iobuf_uart_txd.io.IO, th.uart_txd_in) + + // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] + val sw_3_in = IOBUF(th.sw_3) + io_gpio.pins(16).i.ival := Mux(sw_3_in, + iobuf_ck0.io.O & io_gpio.pins(16).o.ie, + iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) + + IOBUF(th.uart_rxd_out, io_gpio.pins(17)) + + // Shield header row 0: PD2-PD7 + IOBUF(th.ck_io(2), io_gpio.pins(18)) + IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) + IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) + IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) + IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) + IOBUF(th.ck_io(7), io_gpio.pins(23)) + + // Header row 1: PB0-PB5 + IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) + IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) + IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) + IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) + IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO + IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK + + io_gpio.pins(6).i.ival := 0.U + io_gpio.pins(7).i.ival := 0.U + io_gpio.pins(8).i.ival := 0.U + + // Header row 3: A0-A5 (we don't support using them as analog inputs) + // just treat them as regular digital GPIOs + IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) + IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) + IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) + IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA + IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL + + // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty + // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active + IOBUF(th.led0_r, io_gpio.pins(1)) + IOBUF(th.led0_g, io_gpio.pins(2)) + IOBUF(th.led0_b, io_gpio.pins(3)) + + // Note that this is the one which is actually connected on the HiFive/Crazy88 + // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active + IOBUF(th.led1_r, io_gpio.pins(19)) + IOBUF(th.led1_g, io_gpio.pins(21)) + IOBUF(th.led1_b, io_gpio.pins(22)) + + // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active + IOBUF(th.led2_r, io_gpio.pins(11)) + IOBUF(th.led2_g, io_gpio.pins(12)) + IOBUF(th.led2_b, io_gpio.pins(13)) + + // Only 19 out of 20 shield pins connected to GPIO pins + // Shield pin A5 (pin 14) left unconnected + // The buttons are connected to some extra GPIO pins not connected on the + // HiFive1 board + IOBUF(th.btn_0, io_gpio.pins(15)) + IOBUF(th.btn_1, io_gpio.pins(30)) + IOBUF(th.btn_2, io_gpio.pins(31)) + + val iobuf_btn_3 = Module(new IOBUF()) + iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval + iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe + attach(th.btn_3, iobuf_btn_3.io.IO) + io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie + + // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 + IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX + IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX + + // SPI2 pins mapped to 6 pin ICSP connector (standard on later + // arduinos) These are connected to some extra GPIO pins not connected + // on the HiFive1 board + IOBUF(th.ck_ss, io_gpio.pins(26)) + IOBUF(th.ck_mosi, io_gpio.pins(27)) + IOBUF(th.ck_miso, io_gpio.pins(28)) + IOBUF(th.ck_sck, io_gpio.pins(29)) + + // Use the LEDs for some more useful debugging things + IOBUF(th.led_0, th.ck_rst) + IOBUF(th.led_1, th.SRST_n) + IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) + IOBUF(th.led_3, io_gpio.pins(14)) + + //--------------------------------------------------------------------- + // Unconnected inputs + //--------------------------------------------------------------------- + + io_aon.erst_n.i.ival := ~th.reset_periph + io_aon.lfextclk.i.ival := slow_clock + io_aon.pmu.vddpaden.i.ival := 1.U + } + + Nil + } + } + + Seq((Nil, Nil, Some(harnessFn))) + } +}) + diff --git a/fpga/src/main/scala/arty/Platform.scala b/fpga/src/main/scala/arty/Platform.scala deleted file mode 100644 index 514ff74c..00000000 --- a/fpga/src/main/scala/arty/Platform.scala +++ /dev/null @@ -1,180 +0,0 @@ -// See LICENSE for license details. -package chipyard.fpga - -import Chisel._ - -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.util.ResetCatchAndSync -import freechips.rocketchip.system._ - -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.pinctrl._ - -import chipyard.{DigitalTop} - -//------------------------------------------------------------------------- -// PinGen -//------------------------------------------------------------------------- - -object PinGen { - def apply(): BasePin = { - val pin = new BasePin() - pin - } -} - -//------------------------------------------------------------------------- -// E300ArtyDevKitPlatformIO -//------------------------------------------------------------------------- - -class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle { - val pins = new Bundle { - val jtag = new JTAGPins(() => PinGen(), false) - val gpio = new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0)) - val qspi = new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0)) - val aon = new MockAONWrapperPins() - } - val jtag_reset = Bool(INPUT) - val ndreset = Bool(OUTPUT) -} - -//------------------------------------------------------------------------- -// E300ArtyDevKitPlatform -//------------------------------------------------------------------------- - -class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module { - val sys = Module(LazyModule(new DigitalTop).module) - val io = new E300ArtyDevKitPlatformIO - - // This needs to be de-asserted synchronously to the coreClk. - val async_corerst = sys.aon.rsts.corerst - // Add in debug-controlled reset. - sys.reset := ResetCatchAndSync(clock, async_corerst, 20) - Debug.connectDebugClockAndReset(sys.debug, clock) - - //----------------------------------------------------------------------- - // Check for unsupported rocket-chip connections - //----------------------------------------------------------------------- - - require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); - - //----------------------------------------------------------------------- - // Build GPIO Pin Mux - //----------------------------------------------------------------------- - // Pin Mux for UART, SPI, PWM - // First convert the System outputs into "IOF" using the respective *GPIOPort - // converters. - - val sys_uart = sys.uart - val sys_pwm = sys.pwm - val sys_spi = sys.spi - val sys_i2c = sys.i2c - - val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} - val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} - val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} - val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} - - (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} - (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } - (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} - (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)} - - //----------------------------------------------------------------------- - // Default Pin connections before attaching pinmux - - for (iof_0 <- sys.gpio(0).iof_0.get) { - iof_0.default() - } - - for (iof_1 <- sys.gpio(0).iof_1.get) { - iof_1.default() - } - - //----------------------------------------------------------------------- - - val iof_0 = sys.gpio(0).iof_0.get - val iof_1 = sys.gpio(0).iof_1.get - - // SPI1 (0 is the dedicated) - BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) - BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) - BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) - BasePinToIOF(spi_pins(0).sck, iof_0(5)) - BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) - BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) - BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) - BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) - BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) - - // SPI2 - BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) - BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) - BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) - BasePinToIOF(spi_pins(1).sck, iof_0(29)) - BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) - BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) - - // I2C - if (p(PeripheryI2CKey).length == 1) { - BasePinToIOF(i2c_pins(0).sda, iof_0(12)) - BasePinToIOF(i2c_pins(0).scl, iof_0(13)) - } - - // UART0 - BasePinToIOF(uart_pins(0).rxd, iof_0(16)) - BasePinToIOF(uart_pins(0).txd, iof_0(17)) - - // UART1 - BasePinToIOF(uart_pins(1).rxd, iof_0(24)) - BasePinToIOF(uart_pins(1).txd, iof_0(25)) - - //PWM - BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) - BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) - BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) - BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) - - BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) - BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) - BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) - BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) - - BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) - BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) - BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) - BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) - - //----------------------------------------------------------------------- - // Drive actual Pads - //----------------------------------------------------------------------- - - // Result of Pin Mux - GPIOPinsFromPort(io.pins.gpio, sys.gpio(0)) - - // Dedicated SPI Pads - SPIPinsFromPort(io.pins.qspi, sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3) - - // JTAG Debug Interface - val sjtag = sys.debug.get.systemjtag.get - JTAGPinsFromPort(io.pins.jtag, sjtag.jtag) - sjtag.reset := io.jtag_reset - sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) - - io.ndreset := sys.debug.get.ndreset - - // AON Pads -- direct connection is OK because - // EnhancedPin is hard-coded in MockAONPads - // and thus there is no .fromPort method. - io.pins.aon <> sys.aon.pins -} diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala new file mode 100644 index 00000000..919e5c99 --- /dev/null +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -0,0 +1,34 @@ +package chipyard.fpga.arty + +import chisel3._ +import chisel3.experimental.{Analog} + +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.config.{Parameters} + +import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} + +import chipyard.{BuildTop, HasHarnessSignalReferences} + +class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { + + val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") + + // turn IO clock into Reset type + val hReset = Wire(Reset()) + hReset := ck_rst + + // default to 32MHz clock + withClockAndReset(clock_32MHz, hReset) { + val dut = Module(ldut.module) + } + + val harnessClock = clock_32MHz + val harnessReset = hReset + val success = false.B + val dutReset = hReset + + // must be after HasHarnessSignalReferences assignments + ldut.harnessFunctions.foreach(_(this)) +} + From c49eef32241ff2a112628d5999ffec89c2f8179d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 7 Sep 2020 15:26:30 -0700 Subject: [PATCH 009/157] Small cleanup to CY DigitalTop | Move E300 configs to unique folder --- fpga/Makefile | 2 +- .../arty/{Config.scala => e300/Configs.scala} | 9 +++++++- .../src/main/scala/arty/e300/DigitalTop.scala | 23 +++++++++++++++++++ .../scala/arty/{ => e300}/IOBinders.scala | 2 +- .../chipyard/src/main/scala/DigitalTop.scala | 14 +++++------ 5 files changed, 39 insertions(+), 11 deletions(-) rename fpga/src/main/scala/arty/{Config.scala => e300/Configs.scala} (92%) create mode 100644 fpga/src/main/scala/arty/e300/DigitalTop.scala rename fpga/src/main/scala/arty/{ => e300}/IOBinders.scala (99%) diff --git a/fpga/Makefile b/fpga/Makefile index 0110bb10..c1e4fb2d 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -23,7 +23,7 @@ MODEL := ArtyFPGATestHarness VLOG_MODEL := ArtyFPGATestHarness MODEL_PACKAGE := chipyard.fpga.arty CONFIG := E300ArtyDevKitConfig -CONFIG_PACKAGE := chipyard.fpga.arty +CONFIG_PACKAGE := chipyard.fpga.arty.e300 GENERATOR_PACKAGE := chipyard TB := none # unused TOP := ChipTop diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/e300/Configs.scala similarity index 92% rename from fpga/src/main/scala/arty/Config.scala rename to fpga/src/main/scala/arty/e300/Configs.scala index bcea7c78..dd9213fc 100644 --- a/fpga/src/main/scala/arty/Config.scala +++ b/fpga/src/main/scala/arty/e300/Configs.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package chipyard.fpga.arty +package chipyard.fpga.arty.e300 import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -16,6 +16,8 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ +import chipyard.{BuildSystem} + class E300DevKitExtra extends Config((site, here, up) => { case PeripheryGPIOKey => List( GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) @@ -46,7 +48,12 @@ class E300DevKitExtra extends Config((site, here, up) => { debugIdleCycles = 5) }) +class WithE300System extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) +}) + class E300ArtyDevKitConfig extends Config( + new WithE300System ++ new WithE300Connections ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/e300/DigitalTop.scala new file mode 100644 index 00000000..1bda2680 --- /dev/null +++ b/fpga/src/main/scala/arty/e300/DigitalTop.scala @@ -0,0 +1,23 @@ +package chipyard.fpga.arty.e300 + +import chisel3._ + +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.devices.tilelink._ + +import chipyard.{DigitalTop, DigitalTopModule} + +// ------------------------------------ +// E300 DigitalTop +// ------------------------------------ + +class E300DigitalTop(implicit p: Parameters) extends DigitalTop + with sifive.blocks.devices.mockaon.HasPeripheryMockAON +{ + override lazy val module = new E300DigitalTopModule(this) +} + +class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) + with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala similarity index 99% rename from fpga/src/main/scala/arty/IOBinders.scala rename to fpga/src/main/scala/arty/e300/IOBinders.scala index e8833827..d9a2e1cc 100644 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.arty +package chipyard.fpga.arty.e300 import chisel3._ import chisel3.experimental.{attach, IO} diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 160e6acf..9e40cfab 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -13,10 +13,6 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem - with sifive.blocks.devices.mockaon.HasPeripheryMockAON - with sifive.blocks.devices.spi.HasPeripherySPI - with sifive.blocks.devices.pwm.HasPeripheryPWM - with sifive.blocks.devices.i2c.HasPeripheryI2C with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device @@ -24,6 +20,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller + with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI + with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM + with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget @@ -35,16 +34,15 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem } class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) - with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIModuleImp - with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp - with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIModuleImp + with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp + with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch From 2580073d75cd98838f4ccf9ae3757e158a2d25f2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 7 Sep 2020 15:30:21 -0700 Subject: [PATCH 010/157] Comment cleanup --- fpga/src/main/scala/arty/e300/IOBinders.scala | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index d9a2e1cc..8d866619 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -33,10 +33,15 @@ class WithE300Connections extends OverrideIOBinder({ with HasPeripherySPIFlashModuleImp with HasPeripheryMockAONModuleImp with HasPeripheryI2CModuleImp) => { - // match the E300 connections using a "Chipyard"-like structure implicit val p: Parameters = GetSystemParameters(system) + //----------------------------------------------------------------------- + //----------------------------------------------------------------------- + // E300DigitalTop <-> ChipTop connections + //----------------------------------------------------------------------- + //----------------------------------------------------------------------- + object PinGen { def apply(): BasePin = { val pin = new BasePin() @@ -51,8 +56,6 @@ class WithE300Connections extends OverrideIOBinder({ val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - // TODO: Fix - // add iocells (or none) // This needs to be de-asserted synchronously to the coreClk. val async_corerst = system.aon.rsts.corerst // Add in debug-controlled reset. @@ -175,6 +178,11 @@ class WithE300Connections extends OverrideIOBinder({ // and thus there is no .fromPort method. io_aon <> system.aon.pins + //----------------------------------------------------------------------- + //----------------------------------------------------------------------- + // Harness Function (ArtyHarness <-> ChipTop) + //----------------------------------------------------------------------- + //----------------------------------------------------------------------- val harnessFn = (baseTh: HasHarnessSignalReferences) => { baseTh match { case th: ArtyShell => From 56eead4053df7f7a2c284e9aa7602ca544e18011 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 8 Sep 2020 17:04:56 -0700 Subject: [PATCH 011/157] NOT WORKING: VCU118 Commit --- build.sbt | 2 +- fpga/Makefile | 10 +-- fpga/src/main/scala/vcu118/Configs.scala | 51 ++++++++++++++ fpga/src/main/scala/vcu118/IOBinders.scala | 69 +++++++++++++++++++ fpga/src/main/scala/vcu118/Shell.scala | 0 fpga/src/main/scala/vcu118/TestHarness.scala | 36 ++++++++++ .../chipyard/src/main/scala/ChipTop.scala | 1 + 7 files changed, 163 insertions(+), 6 deletions(-) create mode 100644 fpga/src/main/scala/vcu118/Configs.scala create mode 100644 fpga/src/main/scala/vcu118/IOBinders.scala create mode 100644 fpga/src/main/scala/vcu118/Shell.scala create mode 100644 fpga/src/main/scala/vcu118/TestHarness.scala diff --git a/build.sbt b/build.sbt index ffe8bfe8..3420955b 100644 --- a/build.sbt +++ b/build.sbt @@ -218,7 +218,7 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) testOptions in Test += Tests.Argument("-oF") ) lazy val fpga_shells = (project in file("./fpga/fpga-shells")) - .dependsOn(rocketchip, sifive_blocks) + .dependsOn(rocketchip, sifive_blocks, chipyard) .settings(commonSettings) lazy val fpga_platforms = (project in file("./fpga")) diff --git a/fpga/Makefile b/fpga/Makefile index c1e4fb2d..643e0c67 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -19,11 +19,11 @@ include $(base_dir)/variables.mk # default variables to build the arty example SUB_PROJECT := fpga SBT_PROJECT := fpga_platforms -MODEL := ArtyFPGATestHarness -VLOG_MODEL := ArtyFPGATestHarness -MODEL_PACKAGE := chipyard.fpga.arty -CONFIG := E300ArtyDevKitConfig -CONFIG_PACKAGE := chipyard.fpga.arty.e300 +MODEL := VCU118FPGATestHarness +VLOG_MODEL := VCU118FPGATestHarness +MODEL_PACKAGE := chipyard.fpga.vcu118 +CONFIG := FakeBringupConfig +CONFIG_PACKAGE := chipyard.fpga.vcu118 GENERATOR_PACKAGE := chipyard TB := none # unused TOP := ChipTop diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala new file mode 100644 index 00000000..a98aa3cf --- /dev/null +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -0,0 +1,51 @@ +// See LICENSE for license details. +package chipyard.fpga.vcu118 + +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} +import freechips.rocketchip.system._ +import freechips.rocketchip.tile._ + +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.i2c._ + +import sifive.fpgashells.shell.{DesignKey} + +import chipyard.{BuildTop} + +class WithChipyardBuildTop extends Config((site, here, up) => { + //case DesignKey => { (p:Parameters) => p(BuildTop)(p) } + case DesignKey => {(p: Parameters) => new chipyard.ChipTop()(p) } +}) + +class WithBringupUARTs extends Config((site, here, up) => { + case PeripheryUARTKey => List( + UARTParams(address = BigInt(0x64000000L)), + UARTParams(address = BigInt(0x64003000L))) +}) + +class FakeBringupConfig extends Config( + new WithUARTConnection1 ++ + new WithBringupUARTs ++ + new WithChipyardBuildTop ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.With1TinyCore ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala new file mode 100644 index 00000000..dfec55cc --- /dev/null +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -0,0 +1,69 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{attach, IO} + +import freechips.rocketchip.util._ +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.subsystem.{NExtTopInterrupts} + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.pwm._ +import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.mockaon._ +import sifive.blocks.devices.jtag._ +import sifive.blocks.devices.pinctrl._ + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} + +import chipsalliance.rocketchip.config._ +import sifive.fpgashells.shell._ + +import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} +import chipyard.{HasHarnessSignalReferences} +import freechips.rocketchip.diplomacy._ + +class WithUARTConnection1 extends OverrideIOBinder({ + (system: HasPeripheryUARTModuleImp) => { + + implicit val p: Parameters = GetSystemParameters(system) + + val io_uart_pins = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") } + (io_uart_pins zip system.uart) map { case (p, r) => p <> r } + + val harnessFn = (th: HasHarnessSignalReferences) => { + println(th) + println("Got here - -- - - - ") + Nil + } + //val harnessFn = (baseTh: HasHarnessSignalReferences) => { + // println("DEBUG: ---------------------- 0") + // baseTh match { case th: VCU118Shell => + // println("DEBUG: ---------------------- 1") + + // val io_uart_pins_bb = p(PeripheryUARTKey) map { c => BundleBridgeSource(() => (new UARTPortIO(c))) } + + // InModuleBody { + // (io_uart_pins_bb zip io_uart_pins) map { case (p, r) => p.bundle <> r } + // } + + // require(p(PeripheryUARTKey).size >= 1) + + // println("DEBUG: ---------------------- 2") + + // th.designParameters(UARTOverlayKey).foreach { uok => + // println("DEBUG: ---------------------- 3") + // uok.place(UARTDesignInput(io_uart_pins_bb(0))).overlayOutput + // } + + // Nil + // } + //} + + Seq((Nil, Nil, Some(harnessFn))) + } +}) + diff --git a/fpga/src/main/scala/vcu118/Shell.scala b/fpga/src/main/scala/vcu118/Shell.scala new file mode 100644 index 00000000..e69de29b diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala new file mode 100644 index 00000000..6da984bf --- /dev/null +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -0,0 +1,36 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{Analog, IO} + +import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp} +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.diplomacy.{InModuleBody} + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.clocks._ + +import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} + +class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell with HasHarnessSignalReferences { + val pllResetAsReset = InModuleBody{ Wire(Reset()) } + + InModuleBody { + pllResetAsReset := pllReset + } + + lazy val harnessClock = this.module.sysclk + lazy val harnessReset = pllResetAsReset.getWrappedValue + val success = false.B + lazy val dutReset = pllResetAsReset.getWrappedValue + + // must be after HasHarnessSignalReferences assignments + println(s"DEBUG: ----- sz:${topDesign.harnessFunctions.size}") + topDesign match { case d: HasTestHarnessFunctions => + println(s"DEBUG: ----- sz:${d.harnessFunctions.size}") + d.harnessFunctions.foreach(_(this)) + } +} + diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index cf71987b..2df79ec2 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -55,6 +55,7 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc // We ignore _ports for now... iocells ++= _iocells.flatten harnessFunctions ++= _harnessFunctions.flatten + println(s"ChipTop: sz:${harnessFunctions.size}") } // Connect the implicit clock/reset, if present From e98a0f172f92cbf37d6aed258267a502b90fc1fa Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Sep 2020 16:55:25 -0700 Subject: [PATCH 012/157] Connected UART nicely --- fpga/Makefile | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 6 +- fpga/src/main/scala/vcu118/IOBinders.scala | 69 -------------------- fpga/src/main/scala/vcu118/Shell.scala | 0 fpga/src/main/scala/vcu118/TestHarness.scala | 25 +++---- 5 files changed, 11 insertions(+), 91 deletions(-) delete mode 100644 fpga/src/main/scala/vcu118/IOBinders.scala delete mode 100644 fpga/src/main/scala/vcu118/Shell.scala diff --git a/fpga/Makefile b/fpga/Makefile index 643e0c67..f3f6308b 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -26,7 +26,7 @@ CONFIG := FakeBringupConfig CONFIG_PACKAGE := chipyard.fpga.vcu118 GENERATOR_PACKAGE := chipyard TB := none # unused -TOP := ChipTop +TOP := VCU118Platform # setup the board to use BOARD ?= arty diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index a98aa3cf..ba88377f 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -21,8 +21,7 @@ import sifive.fpgashells.shell.{DesignKey} import chipyard.{BuildTop} class WithChipyardBuildTop extends Config((site, here, up) => { - //case DesignKey => { (p:Parameters) => p(BuildTop)(p) } - case DesignKey => {(p: Parameters) => new chipyard.ChipTop()(p) } + case DesignKey => {(p: Parameters) => new VCU118Platform()(p) } }) class WithBringupUARTs extends Config((site, here, up) => { @@ -32,7 +31,6 @@ class WithBringupUARTs extends Config((site, here, up) => { }) class FakeBringupConfig extends Config( - new WithUARTConnection1 ++ new WithBringupUARTs ++ new WithChipyardBuildTop ++ new chipyard.config.WithBootROM ++ @@ -47,5 +45,5 @@ class FakeBringupConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala deleted file mode 100644 index dfec55cc..00000000 --- a/fpga/src/main/scala/vcu118/IOBinders.scala +++ /dev/null @@ -1,69 +0,0 @@ -package chipyard.fpga.vcu118 - -import chisel3._ -import chisel3.experimental.{attach, IO} - -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.subsystem.{NExtTopInterrupts} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pinctrl._ - -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - -import chipsalliance.rocketchip.config._ -import sifive.fpgashells.shell._ - -import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} -import chipyard.{HasHarnessSignalReferences} -import freechips.rocketchip.diplomacy._ - -class WithUARTConnection1 extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => { - - implicit val p: Parameters = GetSystemParameters(system) - - val io_uart_pins = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") } - (io_uart_pins zip system.uart) map { case (p, r) => p <> r } - - val harnessFn = (th: HasHarnessSignalReferences) => { - println(th) - println("Got here - -- - - - ") - Nil - } - //val harnessFn = (baseTh: HasHarnessSignalReferences) => { - // println("DEBUG: ---------------------- 0") - // baseTh match { case th: VCU118Shell => - // println("DEBUG: ---------------------- 1") - - // val io_uart_pins_bb = p(PeripheryUARTKey) map { c => BundleBridgeSource(() => (new UARTPortIO(c))) } - - // InModuleBody { - // (io_uart_pins_bb zip io_uart_pins) map { case (p, r) => p.bundle <> r } - // } - - // require(p(PeripheryUARTKey).size >= 1) - - // println("DEBUG: ---------------------- 2") - - // th.designParameters(UARTOverlayKey).foreach { uok => - // println("DEBUG: ---------------------- 3") - // uok.place(UARTDesignInput(io_uart_pins_bb(0))).overlayOutput - // } - - // Nil - // } - //} - - Seq((Nil, Nil, Some(harnessFn))) - } -}) - diff --git a/fpga/src/main/scala/vcu118/Shell.scala b/fpga/src/main/scala/vcu118/Shell.scala deleted file mode 100644 index e69de29b..00000000 diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 6da984bf..0bce7c97 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -5,32 +5,23 @@ import chisel3.experimental.{Analog, IO} import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp} import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.diplomacy.{InModuleBody} +import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell._ import sifive.fpgashells.clocks._ -import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} +import sifive.blocks.devices.uart._ -class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell with HasHarnessSignalReferences { - val pllResetAsReset = InModuleBody{ Wire(Reset()) } +class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell { - InModuleBody { - pllResetAsReset := pllReset - } + require(p(PeripheryUARTKey).size >= 1) - lazy val harnessClock = this.module.sysclk - lazy val harnessReset = pllResetAsReset.getWrappedValue - val success = false.B - lazy val dutReset = pllResetAsReset.getWrappedValue - - // must be after HasHarnessSignalReferences assignments - println(s"DEBUG: ----- sz:${topDesign.harnessFunctions.size}") - topDesign match { case d: HasTestHarnessFunctions => - println(s"DEBUG: ----- sz:${d.harnessFunctions.size}") - d.harnessFunctions.foreach(_(this)) + designParameters(UARTOverlayKey).foreach { uok => + topDesign match { case td: HasPlatformIO => + io_uart_bb)) + } } } From 382e5f1ae8061b0934e5d53d7aa89d473c852a50 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Sep 2020 17:02:22 -0700 Subject: [PATCH 013/157] Add forgotten file --- fpga/src/main/scala/vcu118/Platform.scala | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 fpga/src/main/scala/vcu118/Platform.scala diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala new file mode 100644 index 00000000..3a4cac8a --- /dev/null +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -0,0 +1,40 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{Analog, IO} + +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} +import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource} +import freechips.rocketchip.config.{Parameters} + +import chipyard.{BuildSystem} + +import sifive.blocks.devices.uart._ + +trait HasPlatformIO { + val io_uart_bb: BundleBridgeSource[UARTPortIO] +} + +class VCU118Platform(override implicit val p: Parameters) extends LazyModule + with HasPlatformIO { + + val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") + + // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design + // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey)(0)))) + + override lazy val module = new VCU118PlatformModule(this) +} + +class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) { + + _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => + // create UART pins in Platform + //val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") } + + //(io_uart_pins_temp zip sys.uart) map { case (p, r) => p <> r } + _outer.io_uart_bb.bundle <> sys.uart(0) + } + +} From 69bf39bf13053f566a32a5c6d2e05403b95bfd60 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 12 Sep 2020 18:18:13 -0700 Subject: [PATCH 014/157] Added more overlays | Closer to bringup platform --- fpga/src/main/scala/vcu118/Configs.scala | 11 +- .../main/scala/vcu118/CustomOverlays.scala | 65 ++++ fpga/src/main/scala/vcu118/FMCUtil.scala | 334 ++++++++++++++++++ fpga/src/main/scala/vcu118/Platform.scala | 45 ++- fpga/src/main/scala/vcu118/TestHarness.scala | 54 ++- 5 files changed, 488 insertions(+), 21 deletions(-) create mode 100644 fpga/src/main/scala/vcu118/CustomOverlays.scala create mode 100644 fpga/src/main/scala/vcu118/FMCUtil.scala diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index ba88377f..42663f0b 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -17,6 +17,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import sifive.fpgashells.shell.{DesignKey} +import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} @@ -24,14 +25,20 @@ class WithChipyardBuildTop extends Config((site, here, up) => { case DesignKey => {(p: Parameters) => new VCU118Platform()(p) } }) -class WithBringupUARTs extends Config((site, here, up) => { +class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) + case PeripherySPIKey => List( + SPIParams(rAddress = BigInt(0x64001000L)), + SPIParams(rAddress = BigInt(0x64004000L))) + case PeripheryI2CKey => List( + I2CParams(address = BigInt(0x64005000L))) + case VCU118ShellPMOD => "SDIO" }) class FakeBringupConfig extends Config( - new WithBringupUARTs ++ + new WithBringupPeripherals ++ new WithChipyardBuildTop ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala new file mode 100644 index 00000000..3d51c3e7 --- /dev/null +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -0,0 +1,65 @@ +package chipyard.fpga.vcu118.bringup + +import chisel3._ + +import freechips.rocketchip.diplomacy._ + +import sifive.fpgashells.shell._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell.xilinx._ + +import chipyard.fpga.vcu118.{FMCPMap} + +/* Connect the I2C to certain FMC pins */ +class BringupI2CVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) + extends I2CXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + require(shellInput.index == 0) // only support 1 I2C <-> FMC connection + val i2cLocations = List(List(FMCPMap("K11"), FMCPMap("E2"))) + val packagePinsWithPackageIOs = Seq((i2cLocations(shellInput.index)(0), IOPin(io.scl)), + (i2cLocations(shellInput.index)(1), IOPin(io.sda))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + shell.xdc.addIOB(io) + } } + } } +} + +class BringupI2CVCU118ShellPlacer(val shell: VCU118Shell, val shellInput: I2CShellInput)(implicit val valName: ValName) + extends I2CShellPlacer[VCU118Shell] +{ + def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +/* Connect the UART to certain FMC pins */ +class BringupUARTVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) + extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) +{ + shell { InModuleBody { + val packagePinsWithPackageIOs = Seq((FMCPMap("E9"), IOPin(io.ctsn.get)), // unused + (FMCPMap("E10"), IOPin(io.rtsn.get)), // unused + (FMCPMap("C15"), IOPin(io.rxd)), + (FMCPMap("C14"), IOPin(io.txd))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + shell.xdc.addIOB(io) + } } + + // add pullup on ctsn (ctsn is an input that is not used or driven) + packagePinsWithPackageIOs take 1 foreach { case (pin, io) => { + shell.xdc.addPullup(io) + } } + } } +} + +class BringupUARTVCU118ShellPlacer(shell: VCU118Shell, val shellInput: UARTShellInput)(implicit val valName: ValName) + extends UARTShellPlacer[VCU118Shell] { + def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +/* Connect SPI to ADI device */ diff --git a/fpga/src/main/scala/vcu118/FMCUtil.scala b/fpga/src/main/scala/vcu118/FMCUtil.scala new file mode 100644 index 00000000..00982585 --- /dev/null +++ b/fpga/src/main/scala/vcu118/FMCUtil.scala @@ -0,0 +1,334 @@ +package chipyard.fpga.vcu118 + +import scala.collection.immutable.HashMap + +// TODO: was typed by hand, so this needs a once-over before it can be considered trustworthy + +object FMCMap { + // Take an FMC pin name and return the VCU118 package pin + // See https://www.xilinx.com/support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf + // Pages 97-98 + // Omitted pins are not connected to a GPIO + def apply(fmcPin: String): String = HashMap( + "C10" -> "BD13", + "C11" -> "BE13", + "C14" -> "BB13", + "C15" -> "BB12", + "C18" -> "AW8", + "C19" -> "AW7", + "C22" -> "AP12", + "C23" -> "AR12", + "C26" -> "AL14", + "C27" -> "AM14", + "D1" -> "AK35", + "D8" -> "BF10", + "D9" -> "BF9", + "D11" -> "BE14", + "D12" -> "BF14", + "D14" -> "BA14", + "D15" -> "BB14", + "D17" -> "AY8", + "D18" -> "AY7", + "D20" -> "AR14", + "D21" -> "AT14", + "D23" -> "AN16", + "D24" -> "AP16", + "D26" -> "AK15", + "D27" -> "AL15", + "F1" -> "BA7", + "G2" -> "AV14", + "G3" -> "AV13", + "G6" -> "AY9", + "G7" -> "BA9", + "G9" -> "BD12", + "G10" -> "BE12", + "G12" -> "BE15", + "G13" -> "BF15", + "G15" -> "BC14", + "G16" -> "BC13", + "G18" -> "AV9", + "G19" -> "AV8", + "G21" -> "AW11", + "G22" -> "AY10", + "G24" -> "AW13", + "G25" -> "AY13", + "G27" -> "AT12", + "G28" -> "AU12", + "G30" -> "AN15", + "G31" -> "AP15", + "G33" -> "AM13", + "G34" -> "AM12", + "G36" -> "AK14", + "G37" -> "AK13", + "H2" -> "BB7", + "H4" -> "BC9", + "H5" -> "BC8", + "H7" -> "BC11", + "H8" -> "BD11", + "H10" -> "BF12", + "H11" -> "BF11", + "H13" -> "BC15", + "H14" -> "BD15", + "H16" -> "BA16", + "H17" -> "BA15", + "H19" -> "BB16", + "H20" -> "BC16", + "H22" -> "AW12", + "H23" -> "AY12", + "H25" -> "AU11", + "H26" -> "AV11", + "H28" -> "AP13", + "H29" -> "AR13", + "H31" -> "AV10", + "H32" -> "AW10", + "H34" -> "AK12", + "H35" -> "AL12", + "H37" -> "AJ13", + "H38" -> "AJ12" + )(fmcPin) +} + +object FMCPMap { + // Take an FMC+ pin name and return the VCU118 package pin + // See https://www.xilinx.com/support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf + // Pages 100-106 + // Omitted pins are not connected to a GPIO + def apply(fmcpPin: String): String = HashMap( + "A2" -> "AN45", + "A3" -> "AN46", + "A6" -> "AL45", + "A7" -> "AL45", + "A10" -> "AJ45", + "A11" -> "AJ46", + "A14" -> "W45", + "A15" -> "W46", + "A18" -> "U45", + "A19" -> "U46", + "A22" -> "AP42", + "A23" -> "AP43", + "A26" -> "AM42", + "A27" -> "AM43", + "A30" -> "AL40", + "A31" -> "AL41", + "A34" -> "T42", + "A35" -> "T43", + "A38" -> "P42", + "A39" -> "P43", + "B4" -> "AF43", + "B5" -> "AF44", + "B8" -> "AG45", + "B9" -> "AG46", + "B12" -> "N45", + "B13" -> "N46", + "B16" -> "R45", + "B17" -> "R46", + "B24" -> "AJ40", + "B25" -> "AJ41", + "B28" -> "AK42", + "B29" -> "AK43", + "B32" -> "K42", + "B33" -> "K43", + "B36" -> "M42", + "B37" -> "M43", + "C2" -> "AT42", + "C3" -> "AT43", + "C6" -> "AR45", + "C7" -> "AR46", + "C10" -> "AT35", + "C11" -> "AT36", + "C14" -> "AP35", + "C15" -> "AR35", + "C18" -> "AG31", + "C19" -> "AH31", + "C22" -> "R31", + "C23" -> "P31", + "C26" -> "V33", + "C27" -> "V34", + "D1" -> "AK35", + "D8" -> "AL30", + "D9" -> "AL31", + "D11" -> "AP38", + "D12" -> "AR38", + "D14" -> "AJ33", + "D15" -> "AK33", + "D17" -> "AJ35", + "D18" -> "AJ36", + "D20" -> "R34", + "D21" -> "P34", + "D23" -> "Y32", + "D24" -> "W32", + "D26" -> "V32", + "D27" -> "U33", + "E2" -> "V15", + "E3" -> "U15", + "E6" -> "R14", + "E7" -> "P14", + "E9" -> "W14", + "E10" -> "V14", + "E12" -> "V13", + "E13" -> "U12", + "E15" -> "T14", + "E16" -> "R13", + "E18" -> "M15", + "E19" -> "L15", + "F1" -> "AM34", + "F4" -> "N14", + "F5" -> "N13", + "F7" -> "AA13", + "F8" -> "Y13", + "F10" -> "U11", + "F11" -> "T11", + "F13" -> "T16", + "F14" -> "T15", + "F16" -> "M13", + "F17" -> "M12", + "F19" -> "L14", + "F20" -> "L13", + "G2" -> "P35", + "G3" -> "P36", + "G6" -> "AL35", + "G7" -> "AL36", + "G9" -> "AT39", + "G10" -> "AT40", + "G12" -> "AK29", + "G13" -> "AK30", + "G15" -> "AH33", + "G16" -> "AH34", + "G18" -> "AG34", + "G19" -> "AH35", + "G21" -> "N32", + "G22" -> "M32", + "G24" -> "N34", + "G25" -> "N35", + "G27" -> "Y34", + "G28" -> "W34", + "G30" -> "U35", + "G31" -> "T36", + "G33" -> "P37", + "G34" -> "N37", + "G36" -> "L34", + "G37" -> "K34", + "H2" -> "AM33", + "H4" -> "AL32", + "H5" -> "AM32", + "H7" -> "AJ32", + "H8" -> "AK32", + "H10" -> "AR37", + "H11" -> "AT37", + "H13" -> "AP36", + "H14" -> "AP37", + "H16" -> "AJ30", + "H17" -> "AJ31", + "H19" -> "AG32", + "H20" -> "AG33", + "H22" -> "N33", + "H23" -> "M33", + "H25" -> "M35", + "H26" -> "L35", + "H28" -> "T34", + "H29" -> "T35", + "H31" -> "M36", + "H32" -> "L36", + "H34" -> "N38", + "H35" -> "M38", + "H37" -> "L33", + "H38" -> "K33", + "J6" -> "W12", + "J7" -> "V12", + "J9" -> "AA14", + "J10" -> "Y14", + "J12" -> "R12", + "J13" -> "P12", + "J15" -> "M11", + "J16" -> "L11", + "J18" -> "P15", + "J19" -> "N15", + "J21" -> "K12", + "J22" -> "J12", + "K7" -> "AA12", + "K8" -> "Y12", + "K10" -> "U13", + "K11" -> "T13", + "K13" -> "V16", + "K14" -> "U16", + "K16" -> "R11", + "K17" -> "P11", + "K19" -> "K14", + "K20" -> "K13", + "K22" -> "K11", + "K23" -> "J11", + "L4" -> "R40", + "L5" -> "R41", + "L8" -> "AB38", + "L9" -> "AB39", + "L12" -> "AF38", + "L13" -> "AF39", + "L16" -> "AN34", + "L17" -> "AN35", + "L20" -> "AN33", + "L21" -> "AP33", + "L24" -> "AK34", + "L25" -> "AL34", + "L28" -> "AM36", + "L29" -> "AN36", + "M2" -> "AU45", + "M3" -> "AU46", + "M6" -> "AW45", + "M7" -> "AW46", + "M10" -> "BA45", + "M11" -> "BA46", + "M14" -> "BC45", + "M15" -> "BC46", + "M18" -> "W40", + "M19" -> "W41", + "M22" -> "U40", + "M23" -> "U41", + "M26" -> "H42", + "M27" -> "H43", + "M30" -> "F42", + "M31" -> "F43", + "M34" -> "D42", + "M35" -> "D43", + "M38" -> "B42", + "M39" -> "B43", + "Y2" -> "AV42", + "Y3" -> "AV43", + "Y6" -> "BB42", + "Y7" -> "BB43", + "Y10" -> "AE45", + "Y11" -> "AE46", + "Y14" -> "AC45", + "Y15" -> "AC46", + "Y18" -> "AA45", + "Y19" -> "AA46", + "Y22" -> "Y43", + "Y23" -> "Y44", + "Y26" -> "AE40", + "Y27" -> "AE41", + "Y30" -> "AA40", + "Y31" -> "AA41", + "Y34" -> "J45", + "Y35" -> "J46", + "Y38" -> "E45", + "Y39" -> "E46", + "Z1" -> "AM29", + "Z4" -> "AY42", + "Z5" -> "AY43", + "Z8" -> "BD42", + "Z9" -> "BD43", + "Z12" -> "AD43", + "Z13" -> "AD44", + "Z16" -> "AB43", + "Z17" -> "AB44", + "Z20" -> "AN40", + "Z21" -> "AN41", + "Z24" -> "AG40", + "Z25" -> "AG41", + "Z28" -> "AC40", + "Z29" -> "AC41", + "Z32" -> "L45", + "Z33" -> "L46", + "Z36" -> "G45", + "Z37" -> "G46" + )(fmcpPin) +} diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala index 3a4cac8a..47e64de0 100644 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -10,31 +10,46 @@ import freechips.rocketchip.config.{Parameters} import chipyard.{BuildSystem} import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ -trait HasPlatformIO { - val io_uart_bb: BundleBridgeSource[UARTPortIO] +trait HasVCU118PlatformIO { + val io_uart: Seq[UARTPortIO] + val io_spi: Seq[SPIPortIO] + val io_i2c: Seq[I2CPort] } -class VCU118Platform(override implicit val p: Parameters) extends LazyModule - with HasPlatformIO { +class VCU118Platform(override implicit val p: Parameters) extends LazyModule { val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") - // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design - // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey)(0)))) - override lazy val module = new VCU118PlatformModule(this) } -class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) { +class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) + with HasVCU118PlatformIO { - _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => - // create UART pins in Platform - //val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") } - - //(io_uart_pins_temp zip sys.uart) map { case (p, r) => p <> r } - _outer.io_uart_bb.bundle <> sys.uart(0) + val io_uart = _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => + val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex.map { case (p, i) => IO(new UARTPortIO(p)).suggestName(s"uart_$i") } + (io_uart_pins_temp zip sys.uart).map { case (io, sysio) => + io <> sysio + } + io_uart_pins_temp } + val io_spi = _outer.lazySystem.module match { case sys: HasPeripherySPIModuleImp => + val io_spi_pins_temp = p(PeripherySPIKey).zipWithIndex.map { case (p, i) => IO(new SPIPortIO(p)).suggestName(s"spi_$i") } + (io_spi_pins_temp zip sys.spi).map { case (io, sysio) => + io <> sysio + } + io_spi_pins_temp + } + + val io_i2c = _outer.lazySystem.module match { case sys: HasPeripheryI2CModuleImp => + val io_i2c_pins_temp = p(PeripheryI2CKey).zipWithIndex.map { case (p, i) => IO(new I2CPort).suggestName(s"i2c_$i") } + (io_i2c_pins_temp zip sys.i2c).map { case (io, sysio) => + io <> sysio + } + io_i2c_pins_temp + } } diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 0bce7c97..31f3c0ff 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -13,14 +13,60 @@ import sifive.fpgashells.shell._ import sifive.fpgashells.clocks._ import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell { - require(p(PeripheryUARTKey).size >= 1) - designParameters(UARTOverlayKey).foreach { uok => - topDesign match { case td: HasPlatformIO => - io_uart_bb)) + /*** UART ***/ + require(p(PeripheryUARTKey).size == 2) + + // 1st UART goes to the VCU118 dedicated UART + + // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design + // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).head))) + designParameters(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_uart_bb.bundle <> dutMod.io_uart.head + } + } + + // 2nd UART goes to the FMC UART + + val uart_fmc = Overlay(UARTOverlayKey, new chipyard.fpga.vcu118.bringup.BringupUARTVCU118ShellPlacer(this, UARTShellInput())) + + val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).last))) + designParameters(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_uart_bb_2.bundle <> dutMod.io_uart.last + } + } + + /*** SPI ***/ + require(p(PeripherySPIKey).size >= 1) + + val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).head))) + designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_spi_bb.bundle <> dutMod.io_spi.head + } + } + + /*** I2C ***/ + require(p(PeripheryI2CKey).size >= 1) + + val i2c = Overlay(I2COverlayKey, new chipyard.fpga.vcu118.bringup.BringupI2CVCU118ShellPlacer(this, I2CShellInput())) + + val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) + designParameters(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_i2c_bb.bundle <> dutMod.io_i2c.head } } } From 72c0f4b3d3f2236c2477b0ab405f5fd26c58b520 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 13 Sep 2020 16:37:20 -0700 Subject: [PATCH 015/157] Add GPIO Overlay --- fpga/src/main/scala/vcu118/BringupGPIOs.scala | 28 ++++++ fpga/src/main/scala/vcu118/Configs.scala | 19 +++- .../main/scala/vcu118/CustomOverlays.scala | 86 +++++++++++++++++++ fpga/src/main/scala/vcu118/Platform.scala | 10 +++ fpga/src/main/scala/vcu118/TestHarness.scala | 57 ++++++++++-- 5 files changed, 193 insertions(+), 7 deletions(-) create mode 100644 fpga/src/main/scala/vcu118/BringupGPIOs.scala diff --git a/fpga/src/main/scala/vcu118/BringupGPIOs.scala b/fpga/src/main/scala/vcu118/BringupGPIOs.scala new file mode 100644 index 00000000..1e11dfa2 --- /dev/null +++ b/fpga/src/main/scala/vcu118/BringupGPIOs.scala @@ -0,0 +1,28 @@ +package chipyard.fpga.vcu118.bringup + +import scala.collection.mutable.{LinkedHashMap} + +object BringupGPIOs { + // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD) + val pinMapping = LinkedHashMap( + // these connect to LEDs and switches on the VCU118 (and use 1.2V) + "led0" -> ("AT32", "LVCMOS12"), // 0 + "led1" -> ("AV34", "LVCMOS12"), // 1 + "led2" -> ("AY30", "LVCMOS12"), // 2 + "led3" -> ("BB32", "LVCMOS12"), // 3 + "led4" -> ("BF32", "LVCMOS12"), // 4 + "led5" -> ("AU37", "LVCMOS12"), // 5 + "led6" -> ("AV36", "LVCMOS12"), // 6 + "led7" -> ("BA37", "LVCMOS12"), // 7 + "sw0" -> ("B17", "LVCMOS12"), // 8 + "sw1" -> ("G16", "LVCMOS12"), // 9 + "sw2" -> ("J16", "LVCMOS12"), // 10 + "sw3" -> ("D21", "LVCMOS12") // 11 + ) + + // return list of names (ordered) + def names: Seq[String] = pinMapping.keys.toSeq + + // return number of GPIOs + def width: Int = pinMapping.size +} diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 42663f0b..7cc106d5 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. package chipyard.fpga.vcu118 +import math.min + import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ @@ -9,7 +11,6 @@ import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ -import sifive.blocks.devices.mockaon._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.pwm._ import sifive.blocks.devices.spi._ @@ -20,6 +21,7 @@ import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} +import chipyard.fpga.vcu118.bringup.{BringupGPIOs} class WithChipyardBuildTop extends Config((site, here, up) => { case DesignKey => {(p: Parameters) => new VCU118Platform()(p) } @@ -32,9 +34,22 @@ class WithBringupPeripherals extends Config((site, here, up) => { case PeripherySPIKey => List( SPIParams(rAddress = BigInt(0x64001000L)), SPIParams(rAddress = BigInt(0x64004000L))) + case VCU118ShellPMOD => "SDIO" case PeripheryI2CKey => List( I2CParams(address = BigInt(0x64005000L))) - case VCU118ShellPMOD => "SDIO" + case PeripheryGPIOKey => { + if (BringupGPIOs.width > 0) { + require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) + val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000)) + val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32) + List.tabulate(((BringupGPIOs.width - 1)/maxGPIOSupport) + 1)(n => { + GPIOParams(address = gpioAddrs(n), width = min(BringupGPIOs.width - maxGPIOSupport*n, maxGPIOSupport)) + }) + } + else { + List.empty[GPIOParams] + } + } }) class FakeBringupConfig extends Config( diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala index 3d51c3e7..ccb61f0e 100644 --- a/fpga/src/main/scala/vcu118/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -1,13 +1,17 @@ package chipyard.fpga.vcu118.bringup import chisel3._ +import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ +import chipsalliance.rocketchip.config.{Parameters, Field} import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell.xilinx._ +import sifive.blocks.devices.gpio._ + import chipyard.fpga.vcu118.{FMCPMap} /* Connect the I2C to certain FMC pins */ @@ -63,3 +67,85 @@ class BringupUARTVCU118ShellPlacer(shell: VCU118Shell, val shellInput: UARTShell } /* Connect SPI to ADI device */ +class BringupSPIVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: SPIDesignInput, val shellInput: SPIShellInput) + extends SDIOXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + val packagePinsWithPackageIOs = Seq((FMCPMap("H37"), IOPin(io.spi_clk)), + (FMCPMap("H19"), IOPin(io.spi_cs)), + (FMCPMap("H17"), IOPin(io.spi_dat(0))), + (FMCPMap("H28"), IOPin(io.spi_dat(1))), + (FMCPMap("H29"), IOPin(io.spi_dat(2))), + (FMCPMap("H16"), IOPin(io.spi_dat(3)))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + } } + packagePinsWithPackageIOs drop 1 foreach { case (pin, io) => { + shell.xdc.addPullup(io) + shell.xdc.addIOB(io) + } } + } } +} + +class BringupSPIVCU118ShellPlacer(shell: VCU118Shell, val shellInput: SPIShellInput)(implicit val valName: ValName) + extends SPIShellPlacer[VCU118Shell] { + def place(designInput: SPIDesignInput) = new BringupSPIVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +// TODO: Move this to a different location +// SPI device description for ADI part +class ADISPIDevice(spi: Device, maxMHz: Double = 1) extends SimpleDevice("clkgen", Seq("analog,adi9516-4")) { + override def parent = Some(spi) + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + val extra = Map("spi-max-frequency" -> Seq(ResourceInt(maxMHz * 1000000))) + Description(name, mapping ++ extra) + } +} + +/* Connect GPIOs to FMC */ +abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput) + extends GPIOPlacedOverlay(name, di, si) +{ + def shell: XilinxShell + + shell { InModuleBody { + (io.gpio zip tlgpioSink.bundle.pins).map { case (ioPin, sinkPin) => + val iobuf = Module(new IOBUF) + iobuf.suggestName(s"gpio_iobuf") + attach(ioPin, iobuf.io.IO) + sinkPin.i.ival := iobuf.io.O + iobuf.io.T := !sinkPin.o.oe + iobuf.io.I := sinkPin.o.oval + } + } } +} + +class BringupGPIOVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) + extends GPIOXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + require(gpioNames.length == io.gpio.length) + + val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) => + val (pin, iostd) = BringupGPIOs.pinMapping(name) + (pin, iostd, IOPin(io)) + } + + packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, iostd) + // TODO: no drive strength found + //if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } + } } + } } +} + +class BringupGPIOVCU118ShellPlacer(shell: VCU118Shell, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) + extends GPIOShellPlacer[VCU118Shell] { + def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) +} + + diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala index 47e64de0..8f9a1ae8 100644 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -12,11 +12,13 @@ import chipyard.{BuildSystem} import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.gpio._ trait HasVCU118PlatformIO { val io_uart: Seq[UARTPortIO] val io_spi: Seq[SPIPortIO] val io_i2c: Seq[I2CPort] + val io_gpio: Seq[GPIOPortIO] } class VCU118Platform(override implicit val p: Parameters) extends LazyModule { @@ -52,4 +54,12 @@ class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleIm } io_i2c_pins_temp } + + val io_gpio = _outer.lazySystem.module match { case sys: HasPeripheryGPIOModuleImp => + val io_gpio_pins_temp = p(PeripheryGPIOKey).zipWithIndex.map { case (p, i) => IO(new GPIOPortIO(p)).suggestName(s"gpio_$i") } + (io_gpio_pins_temp zip sys.gpio).map { case (io, sysio) => + io <> sysio + } + io_gpio_pins_temp + } } diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 31f3c0ff..9a58960f 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -3,9 +3,8 @@ package chipyard.fpga.vcu118 import chisel3._ import chisel3.experimental.{Analog, IO} -import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp} +import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx._ @@ -15,6 +14,9 @@ import sifive.fpgashells.clocks._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.gpio._ + +import chipyard.fpga.vcu118.bringup._ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell { @@ -47,18 +49,44 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } /*** SPI ***/ - require(p(PeripherySPIKey).size >= 1) + require(p(PeripherySPIKey).size == 2) + + // 1st SPI goes to the VCU118 SDIO port val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).head))) - designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb)) + val sdio_placed = designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_spi_bb.bundle <> dutMod.io_spi.head } } + // TODO: No access to the TLSPI node... + //val mmcDev = new MMCDevice(sdio_placed.device, 1) + //ResourceBinding { + // Resource(mmcDev, "reg").bind(ResourceAddress(0)) + //} + + // 2nd SPI goes to the ADI port + + val adi = Overlay(SPIOverlayKey, new chipyard.fpga.vcu118.bringup.BringupSPIVCU118ShellPlacer(this, SPIShellInput())) + + val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).last))) + val adi_placed = designParameters(SPIOverlayKey).last.place(SPIDesignInput(p(PeripherySPIKey).last, io_spi_bb_2)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + io_spi_bb_2.bundle <> dutMod.io_spi.last + } + } + + // TODO: No access to the TLSPI node... + //val adiDev = new chipyard.fpga.vcu118.bringup.ADISPIDevice(adi_placed.device, 1) + //ResourceBinding { + // Resource(adiDev, "reg").bind(ResourceAddress(0)) + //} + /*** I2C ***/ - require(p(PeripheryI2CKey).size >= 1) + require(p(PeripheryI2CKey).size == 1) val i2c = Overlay(I2COverlayKey, new chipyard.fpga.vcu118.bringup.BringupI2CVCU118ShellPlacer(this, I2CShellInput())) @@ -69,5 +97,24 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S io_i2c_bb.bundle <> dutMod.io_i2c.head } } + + /*** GPIO ***/ + val gpio = Seq.tabulate(p(PeripheryGPIOKey).size)(i => { + val maxGPIOSupport = 32 + val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) + Overlay(GPIOOverlayKey, new chipyard.fpga.vcu118.bringup.BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) + }) + + val io_gpio_bb = p(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } + (designParameters(GPIOOverlayKey) zip p(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => + placer.place(GPIODesignInput(params, io_gpio_bb(i))) + } + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + (io_gpio_bb zip dutMod.io_gpio).map { case (bb_io, dut_io) => + bb_io.bundle <> dut_io + } + } + } } From f1b40d51afdba1e1d7c9bd95742aec2e85adef3d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 15 Sep 2020 12:58:58 -0700 Subject: [PATCH 016/157] Connected clocks | Exposed Master TL port --- fpga/src/main/scala/vcu118/Configs.scala | 29 ++++-- .../main/scala/vcu118/CustomOverlays.scala | 25 ++--- fpga/src/main/scala/vcu118/Platform.scala | 16 +++- fpga/src/main/scala/vcu118/TestHarness.scala | 94 ++++++++++++++----- .../chipyard/src/main/scala/DigitalTop.scala | 40 ++++++++ .../chipyard/src/main/scala/System.scala | 1 - 6 files changed, 159 insertions(+), 46 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 7cc106d5..ab087afa 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ @@ -52,20 +52,35 @@ class WithBringupPeripherals extends Config((site, here, up) => { } }) +class SmallModifications extends Config((site, here, up) => { + case SystemBusKey => up(SystemBusKey).copy( + errorDevice = Some(DevNullParams( + Seq(AddressSet(0x3000, 0xfff)), + maxAtomic=site(XLen)/8, + maxTransfer=128, + region = RegionType.TRACKED))) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = + Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt), + errorDevice = None) + case DTSTimebase => BigInt(1000000) + case JtagDTMKey => new JtagDTMConfig( + idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai). + idcodePartNum = 0x000, // Decided to simplify. + idcodeManufId = 0x489, // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses. + debugIdleCycles = 5) // Reasonable guess for synchronization +}) + + class FakeBringupConfig extends Config( new WithBringupPeripherals ++ new WithChipyardBuildTop ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.With1TinyCore ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ - new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala index ccb61f0e..2c438a34 100644 --- a/fpga/src/main/scala/vcu118/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -12,10 +12,11 @@ import sifive.fpgashells.shell.xilinx._ import sifive.blocks.devices.gpio._ + import chipyard.fpga.vcu118.{FMCPMap} /* Connect the I2C to certain FMC pins */ -class BringupI2CVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) +class BringupI2CVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) extends I2CXilinxPlacedOverlay(name, designInput, shellInput) { shell { InModuleBody { @@ -32,14 +33,14 @@ class BringupI2CVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val de } } } -class BringupI2CVCU118ShellPlacer(val shell: VCU118Shell, val shellInput: I2CShellInput)(implicit val valName: ValName) - extends I2CShellPlacer[VCU118Shell] +class BringupI2CVCU118ShellPlacer(val shell: VCU118ShellBasicOverlays, val shellInput: I2CShellInput)(implicit val valName: ValName) + extends I2CShellPlacer[VCU118ShellBasicOverlays] { def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } /* Connect the UART to certain FMC pins */ -class BringupUARTVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) +class BringupUARTVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) { shell { InModuleBody { @@ -61,13 +62,13 @@ class BringupUARTVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val d } } } -class BringupUARTVCU118ShellPlacer(shell: VCU118Shell, val shellInput: UARTShellInput)(implicit val valName: ValName) - extends UARTShellPlacer[VCU118Shell] { +class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: UARTShellInput)(implicit val valName: ValName) + extends UARTShellPlacer[VCU118ShellBasicOverlays] { def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } /* Connect SPI to ADI device */ -class BringupSPIVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: SPIDesignInput, val shellInput: SPIShellInput) +class BringupSPIVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: SPIDesignInput, val shellInput: SPIShellInput) extends SDIOXilinxPlacedOverlay(name, designInput, shellInput) { shell { InModuleBody { @@ -89,8 +90,8 @@ class BringupSPIVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val de } } } -class BringupSPIVCU118ShellPlacer(shell: VCU118Shell, val shellInput: SPIShellInput)(implicit val valName: ValName) - extends SPIShellPlacer[VCU118Shell] { +class BringupSPIVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: SPIShellInput)(implicit val valName: ValName) + extends SPIShellPlacer[VCU118ShellBasicOverlays] { def place(designInput: SPIDesignInput) = new BringupSPIVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } @@ -123,7 +124,7 @@ abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GP } } } -class BringupGPIOVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) +class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) extends GPIOXilinxPlacedOverlay(name, designInput, shellInput) { shell { InModuleBody { @@ -143,8 +144,8 @@ class BringupGPIOVCU118PlacedOverlay(val shell: VCU118Shell, name: String, val d } } } -class BringupGPIOVCU118ShellPlacer(shell: VCU118Shell, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) - extends GPIOShellPlacer[VCU118Shell] { +class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) + extends GPIOShellPlacer[VCU118ShellBasicOverlays] { def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) } diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala index 8f9a1ae8..bdacdf42 100644 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -1,11 +1,12 @@ package chipyard.fpga.vcu118 import chisel3._ -import chisel3.experimental.{Analog, IO} +import chisel3.experimental.{Analog, IO, DataMirror} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} -import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyScope, InModuleBody, BundleBridgeSource, ValName} import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} import chipyard.{BuildSystem} @@ -19,9 +20,10 @@ trait HasVCU118PlatformIO { val io_spi: Seq[SPIPortIO] val io_i2c: Seq[I2CPort] val io_gpio: Seq[GPIOPortIO] + val io_tl_mem: HeterogeneousBag[TLBundle] } -class VCU118Platform(override implicit val p: Parameters) extends LazyModule { +class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope { val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") @@ -62,4 +64,10 @@ class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleIm } io_gpio_pins_temp } + + val io_tl_mem = _outer.lazySystem match { case sys: chipyard.CanHaveMasterTLMemPort => + val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](sys.mem_tl)).suggestName("tl_slave") + io_tl_mem_pins_temp <> sys.mem_tl + io_tl_mem_pins_temp + } } diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 9a58960f..d4e299a5 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -4,7 +4,8 @@ import chisel3._ import chisel3.experimental.{Analog, IO} import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx._ @@ -16,20 +17,55 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.fpga.vcu118.bringup._ +import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} -class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell { +case object DUTFrequencyKey extends Field[Double](100.0) +class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell { + + def dp = designParameters + + /*** Connect/Generate clocks ***/ + + // connect to the PLL that will generate multiple clocks + val harnessSysPLL = dp(PLLFactoryKey)() + sys_clock.get() match { + case Some(x : SysClockVCU118PlacedOverlay) => { + harnessSysPLL := x.node + } + } + + // create and connect to the dutClock + val dutClock = ClockSinkNode(freqMHz = dp(DUTFrequencyKey)) + val dutWrangler = LazyModule(new ResetWrangler) + val dutGroup = ClockGroup() + dutClock := dutWrangler.node := dutGroup := harnessSysPLL + + InModuleBody { + topDesign.module match { case td: LazyModuleImp => { + td.clock := dutClock.in.head._1.clock + td.reset := dutClock.in.head._1.reset + } + } + } + + // connect ref clock to dummy sink node + ref_clock.get() match { + case Some(x : RefClockVCU118PlacedOverlay) => { + val sink = ClockSinkNode(Seq(ClockSinkParameters())) + sink := x.node + } + } /*** UART ***/ - require(p(PeripheryUARTKey).size == 2) + require(dp(PeripheryUARTKey).size == 2) // 1st UART goes to the VCU118 dedicated UART // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).head))) - designParameters(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) + dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_uart_bb.bundle <> dutMod.io_uart.head @@ -38,10 +74,10 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S // 2nd UART goes to the FMC UART - val uart_fmc = Overlay(UARTOverlayKey, new chipyard.fpga.vcu118.bringup.BringupUARTVCU118ShellPlacer(this, UARTShellInput())) + val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) - val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).last))) - designParameters(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) + dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_uart_bb_2.bundle <> dutMod.io_uart.last @@ -49,12 +85,12 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } /*** SPI ***/ - require(p(PeripherySPIKey).size == 2) + require(dp(PeripherySPIKey).size == 2) // 1st SPI goes to the VCU118 SDIO port - val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).head))) - val sdio_placed = designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb)) + val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) + val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_spi_bb.bundle <> dutMod.io_spi.head @@ -69,10 +105,10 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S // 2nd SPI goes to the ADI port - val adi = Overlay(SPIOverlayKey, new chipyard.fpga.vcu118.bringup.BringupSPIVCU118ShellPlacer(this, SPIShellInput())) + val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) - val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).last))) - val adi_placed = designParameters(SPIOverlayKey).last.place(SPIDesignInput(p(PeripherySPIKey).last, io_spi_bb_2)) + val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) + val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_spi_bb_2.bundle <> dutMod.io_spi.last @@ -86,12 +122,12 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S //} /*** I2C ***/ - require(p(PeripheryI2CKey).size == 1) + require(dp(PeripheryI2CKey).size == 1) - val i2c = Overlay(I2COverlayKey, new chipyard.fpga.vcu118.bringup.BringupI2CVCU118ShellPlacer(this, I2CShellInput())) + val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) - designParameters(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) + dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) InModuleBody { topDesign.module match { case dutMod: HasVCU118PlatformIO => io_i2c_bb.bundle <> dutMod.io_i2c.head @@ -99,14 +135,14 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } /*** GPIO ***/ - val gpio = Seq.tabulate(p(PeripheryGPIOKey).size)(i => { + val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { val maxGPIOSupport = 32 val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) - Overlay(GPIOOverlayKey, new chipyard.fpga.vcu118.bringup.BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) + Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) }) - val io_gpio_bb = p(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } - (designParameters(GPIOOverlayKey) zip p(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => + val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } + (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => placer.place(GPIODesignInput(params, io_gpio_bb(i))) } InModuleBody { @@ -116,5 +152,19 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } } } + + /*** Experimental DDR ***/ + + //val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) + + //topDesign match { case lazyDut: VCU118Platform => + // lazyDut.lazySystem match { case lazyDutWBus: BaseSubsystem => + // lazyDutWBus { + // InModuleBody { + // ddrPlaced.overlayOutput.ddr := lazyDutWBus.mbus.toDRAMController(Some("xilinxvcu118mig"))() + // } + // } + // } + //} } diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 9e40cfab..dedcfbf8 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -29,6 +29,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA + with CanHaveMasterTLMemPort { override lazy val module = new DigitalTopModule(this) } @@ -47,3 +48,42 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ + +/** Adds a TileLink port to the system intended to master an MMIO device bus */ +trait CanHaveMasterTLMemPort { this: BaseSubsystem => + private val memPortParamsOpt = p(ExtMem) + private val portName = "tl_mem" + private val device = new MemoryDevice + private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) + + val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => + Seq.tabulate(nMemoryChannels) { channel => + val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) + val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) + + TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = base.flatMap(_.intersect(filter)), + resources = device.reg, + regionType = RegionType.UNCACHED, // cacheable + executable = true, + supportsGet = TransferSizes(1, mbus.blockBytes), + supportsPutFull = TransferSizes(1, mbus.blockBytes), + supportsPutPartial = TransferSizes(1, mbus.blockBytes))), + beatBytes = memPortParams.beatBytes) + } + }).toList.flatten) + + mbus.coupleTo(s"memory_controller_port_named_$portName") { + (memTLNode + :*= TLBuffer() + :*= TLSourceShrinker(1 << idBits) + :*= TLWidthWidget(mbus.beatBytes) + :*= _) + } + + val mem_tl = InModuleBody { memTLNode.makeIOs() } +} diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index bd20ddc7..f8906e04 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -23,7 +23,6 @@ import freechips.rocketchip.util.{DontTouch} */ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem with HasAsyncExtInterrupts - with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort with CanHaveSlaveAXI4Port { From 9135cda9597546805ca58fd9aeefb5c273d90593 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Thu, 17 Sep 2020 13:43:28 -0700 Subject: [PATCH 017/157] Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core. --- fpga/src/main/scala/arty/TestHarness.scala | 2 +- fpga/src/main/scala/arty/e300/IOBinders.scala | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 919e5c99..8f0b7143 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -26,7 +26,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell val harnessClock = clock_32MHz val harnessReset = hReset val success = false.B - val dutReset = hReset + val dutReset = reset_core // must be after HasHarnessSignalReferences assignments ldut.harnessFunctions.foreach(_(this)) diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index 8d866619..6cab4b1e 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -56,10 +56,8 @@ class WithE300Connections extends OverrideIOBinder({ val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - // This needs to be de-asserted synchronously to the coreClk. - val async_corerst = system.aon.rsts.corerst - // Add in debug-controlled reset. - system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) + val io_async_corerst = IO(Input(Bool())).suggestName("core_reset") + system.reset := ResetCatchAndSync(system.clock, io_async_corerst, 20) Debug.connectDebugClockAndReset(system.debug, system.clock) //----------------------------------------------------------------------- @@ -186,6 +184,8 @@ class WithE300Connections extends OverrideIOBinder({ val harnessFn = (baseTh: HasHarnessSignalReferences) => { baseTh match { case th: ArtyShell => + io_async_corerst := th.reset_core + //----------------------------------------------------------------------- // Clock divider //----------------------------------------------------------------------- From afc085a5f4e072195726b33d989d1523346adbfb Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sun, 4 Oct 2020 18:13:47 -0700 Subject: [PATCH 018/157] Removed AON block from E300 design. Debug over JTAG still functioning. --- fpga/src/main/scala/arty/e300/Configs.scala | 3 --- fpga/src/main/scala/arty/e300/DigitalTop.scala | 2 -- fpga/src/main/scala/arty/e300/IOBinders.scala | 14 -------------- 3 files changed, 19 deletions(-) diff --git a/fpga/src/main/scala/arty/e300/Configs.scala b/fpga/src/main/scala/arty/e300/Configs.scala index dd9213fc..ee90848e 100644 --- a/fpga/src/main/scala/arty/e300/Configs.scala +++ b/fpga/src/main/scala/arty/e300/Configs.scala @@ -9,7 +9,6 @@ import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ -import sifive.blocks.devices.mockaon._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.pwm._ import sifive.blocks.devices.spi._ @@ -38,8 +37,6 @@ class E300DevKitExtra extends Config((site, here, up) => { UARTParams(address = 0x10023000)) case PeripheryI2CKey => List( I2CParams(address = 0x10016000)) - case PeripheryMockAONKey => - MockAONParams(address = 0x10000000) case DTSTimebase => BigInt(32768) case JtagDTMKey => new JtagDTMConfig ( idcodeVersion = 2, diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/e300/DigitalTop.scala index 1bda2680..f7d4d8e7 100644 --- a/fpga/src/main/scala/arty/e300/DigitalTop.scala +++ b/fpga/src/main/scala/arty/e300/DigitalTop.scala @@ -14,10 +14,8 @@ import chipyard.{DigitalTop, DigitalTopModule} // ------------------------------------ class E300DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.mockaon.HasPeripheryMockAON { override lazy val module = new E300DigitalTopModule(this) } class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) - with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index 6cab4b1e..6675c325 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -12,7 +12,6 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.pwm._ import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.mockaon._ import sifive.blocks.devices.jtag._ import sifive.blocks.devices.pinctrl._ @@ -31,7 +30,6 @@ class WithE300Connections extends OverrideIOBinder({ with HasPeripheryDebugModuleImp with HasPeripheryPWMModuleImp with HasPeripherySPIFlashModuleImp - with HasPeripheryMockAONModuleImp with HasPeripheryI2CModuleImp) => { implicit val p: Parameters = GetSystemParameters(system) @@ -52,7 +50,6 @@ class WithE300Connections extends OverrideIOBinder({ val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") - val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") val io_ndreset = IO(Output(Bool())).suggestName("ndreset") @@ -174,7 +171,6 @@ class WithE300Connections extends OverrideIOBinder({ // AON Pads -- direct connection is OK because // EnhancedPin is hard-coded in MockAONPads // and thus there is no .fromPort method. - io_aon <> system.aon.pins //----------------------------------------------------------------------- //----------------------------------------------------------------------- @@ -322,12 +318,6 @@ class WithE300Connections extends OverrideIOBinder({ IOBUF(th.btn_1, io_gpio.pins(30)) IOBUF(th.btn_2, io_gpio.pins(31)) - val iobuf_btn_3 = Module(new IOBUF()) - iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval - iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe - attach(th.btn_3, iobuf_btn_3.io.IO) - io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX @@ -343,16 +333,12 @@ class WithE300Connections extends OverrideIOBinder({ // Use the LEDs for some more useful debugging things IOBUF(th.led_0, th.ck_rst) IOBUF(th.led_1, th.SRST_n) - IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) IOBUF(th.led_3, io_gpio.pins(14)) //--------------------------------------------------------------------- // Unconnected inputs //--------------------------------------------------------------------- - io_aon.erst_n.i.ival := ~th.reset_periph - io_aon.lfextclk.i.ival := slow_clock - io_aon.pmu.vddpaden.i.ival := 1.U } Nil From 9664b848e945dc2eda242d7a0309a01a2a5f9ff9 Mon Sep 17 00:00:00 2001 From: dunn Date: Tue, 6 Oct 2020 11:20:27 -0700 Subject: [PATCH 019/157] Pointing common.mk's SOURCE_DIR to subdirectories of fpga, to avoid circular dependency caused by pointing to fpga, which contains generated-src. --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index ee290ddc..dba98751 100644 --- a/common.mk +++ b/common.mk @@ -58,7 +58,7 @@ include $(base_dir)/tools/dromajo/dromajo.mk # Returns a list of files in directory $1 with file extension $2. lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga/fpga-shells fpga/src) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources From a67318928a377c6cf4d8ac8ea6fc7ca48ac71116 Mon Sep 17 00:00:00 2001 From: dunn Date: Wed, 7 Oct 2020 09:02:30 -0700 Subject: [PATCH 020/157] Bumping submodules to upstream dev's commits. --- generators/icenet | 2 +- generators/testchipip | 2 +- sims/firesim | 2 +- tools/barstools | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/icenet b/generators/icenet index 705ca506..277a9080 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 705ca50690383aa589dc560a5e7c152af04c46ad +Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 diff --git a/generators/testchipip b/generators/testchipip index 1e7373f6..10351d36 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 1e7373f6398c198e2dee2bcf692917ec2ac21b53 +Subproject commit 10351d36a961d89e6f5ac1177dff0e9f3efb8c0f diff --git a/sims/firesim b/sims/firesim index 05edd6be..801baeb9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 05edd6be8c0464ea53a664a2164d3eba6a7f62aa +Subproject commit 801baeb901c207beb0511311e09ae10e0dbb8b5f diff --git a/tools/barstools b/tools/barstools index aa1c90c4..4a5c75fc 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit aa1c90c4ccb73c2c379550f3296892cc81e8a195 +Subproject commit 4a5c75fcf85f03af858f1d7db04303d4b0733de7 From 252f9c6a121889367f1c86354fab8710be1a37c1 Mon Sep 17 00:00:00 2001 From: dunn Date: Wed, 7 Oct 2020 11:55:16 -0700 Subject: [PATCH 021/157] Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging. --- fpga/src/main/scala/arty/TestHarness.scala | 25 +++++++++++++++---- .../chipyard/src/main/scala/DigitalTop.scala | 3 --- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 8f0b7143..cd327243 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -2,13 +2,25 @@ package chipyard.fpga.arty import chisel3._ import chisel3.experimental.{Analog} - +import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Parameters} - +import freechips.rocketchip.config.{Field, Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} - import chipyard.{BuildTop, HasHarnessSignalReferences} +import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} + +trait HasTestHarnessFunctions { + val lazySystem: LazyModule + val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]] + val portMap = scala.collection.mutable.Map[String, Seq[Data]]() +} + +trait HasHarnessSignalReferences { + def harnessClock: Clock + def harnessReset: Reset + def dutReset: Reset + def success: Bool +} class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { @@ -29,6 +41,9 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell val dutReset = reset_core // must be after HasHarnessSignalReferences assignments - ldut.harnessFunctions.foreach(_(this)) + ldut match { case d: HasTestHarnessFunctions => + d.harnessFunctions.foreach(_(this)) + ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } } diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 868286eb..c0ac1ff7 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -32,12 +32,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with testchipip.CanHaveTraceIOModuleImp - with testchipip.CanHavePeripheryBlockDeviceModuleImp - with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp - with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop From 7d1a1539e6b716e79725974ae9ebe6cace0f07a2 Mon Sep 17 00:00:00 2001 From: dunn Date: Fri, 9 Oct 2020 23:17:36 -0700 Subject: [PATCH 022/157] Initial pass at HarnessBinders for Arty. --- .../main/scala/arty/{e300 => }/Configs.scala | 8 +- .../scala/arty/{e300 => }/DigitalTop.scala | 2 +- fpga/src/main/scala/arty/HarnessBinders.scala | 73 +++++++++++++++++++ .../scala/arty/{e300 => }/IOBinders.scala | 2 +- 4 files changed, 81 insertions(+), 4 deletions(-) rename fpga/src/main/scala/arty/{e300 => }/Configs.scala (92%) rename fpga/src/main/scala/arty/{e300 => }/DigitalTop.scala (94%) create mode 100644 fpga/src/main/scala/arty/HarnessBinders.scala rename fpga/src/main/scala/arty/{e300 => }/IOBinders.scala (99%) diff --git a/fpga/src/main/scala/arty/e300/Configs.scala b/fpga/src/main/scala/arty/Configs.scala similarity index 92% rename from fpga/src/main/scala/arty/e300/Configs.scala rename to fpga/src/main/scala/arty/Configs.scala index ee90848e..e074dd03 100644 --- a/fpga/src/main/scala/arty/e300/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package chipyard.fpga.arty.e300 +package chipyard.fpga.arty import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -16,6 +16,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import chipyard.{BuildSystem} +import chipyard.iobinders class E300DevKitExtra extends Config((site, here, up) => { case PeripheryGPIOKey => List( @@ -51,7 +52,10 @@ class WithE300System extends Config((site, here, up) => { class E300ArtyDevKitConfig extends Config( new WithE300System ++ - new WithE300Connections ++ + new chipyard.iobinders.WithDebugIOCells ++ + new chipyard.iobinders.WithUARTIOCells ++ + new WithArtyJTAGHarnessBinder ++ + new WithArtyUARTHarnessBinder ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/DigitalTop.scala similarity index 94% rename from fpga/src/main/scala/arty/e300/DigitalTop.scala rename to fpga/src/main/scala/arty/DigitalTop.scala index f7d4d8e7..858b6215 100644 --- a/fpga/src/main/scala/arty/e300/DigitalTop.scala +++ b/fpga/src/main/scala/arty/DigitalTop.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.arty.e300 +package chipyard.fpga.arty import chisel3._ diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala new file mode 100644 index 00000000..0d9a8399 --- /dev/null +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -0,0 +1,73 @@ +package chipyard.fpga.arty + +import chisel3._ +import chisel3.experimental.{Analog} + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.jtag.{JTAGIO} +import freechips.rocketchip.system.{SimAXIMem} +import freechips.rocketchip.subsystem._ + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ + +import barstools.iocell.chisel._ + +import testchipip._ + +import chipyard.harness.OverrideHarnessBinder +import chipyard.HasHarnessSignalReferences +import chipyard.iobinders.GetSystemParameters + +import tracegen.{TraceGenSystemModuleImp} +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} + +import scala.reflect.{ClassTag} + +import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} + + + +class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ + (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { + ports.map { + case d: ClockedDMIIO => + // Want to error here. + case j: JTAGIO => + //val dtm_success = WireInit(false.B) + //when (dtm_success) { th.success := true.B } + //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) + + j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt + + IOBUF(th.jd_5, j.TMS) + PULLUP(th.jd_5) + + IOBUF(th.jd_4, j.TDI) + PULLUP(th.jd_4) + + IOBUF(th.jd_0, j.TDO) + + // mimic putting a pullup on this line (part of reset vote) + th.SRST_n := IOBUF(th.jd_6) + PULLUP(th.jd_6) + + IOBUF(th.jd_1, j.TRSTn) + PULLUP(th.jd_1) + } + Nil + } +}) + +class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { + //UARTAdapter.connect(ports)(system.p) + IOBUF(th.ck_io(2), ports.txd) + IOBUF(th.ck_io(3), ports.rxd) + Nil + } +}) \ No newline at end of file diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala similarity index 99% rename from fpga/src/main/scala/arty/e300/IOBinders.scala rename to fpga/src/main/scala/arty/IOBinders.scala index 6675c325..2b4b332b 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.arty.e300 +package chipyard.fpga.arty import chisel3._ import chisel3.experimental.{attach, IO} From 54acfe71fce0983c9760b7bead421292767f96c0 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sat, 10 Oct 2020 13:45:27 -0700 Subject: [PATCH 023/157] Some HarnessBinder testing with Jerry's debug suggestions. --- fpga/src/main/scala/arty/HarnessBinders.scala | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 0d9a8399..4ee847a5 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -30,44 +30,44 @@ import scala.reflect.{ClassTag} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - - class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { - ports.map { - case d: ClockedDMIIO => - // Want to error here. - case j: JTAGIO => - //val dtm_success = WireInit(false.B) - //when (dtm_success) { th.success := true.B } - //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) + (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[JTAGIO]) => { + // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { + // ports.map { + // case d: ClockedDMIIO => + // // Want to error here. + // case j: JTAGIO => + // //val dtm_success = WireInit(false.B) + // //when (dtm_success) { th.success := true.B } + // //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) - j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt + // j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt - IOBUF(th.jd_5, j.TMS) - PULLUP(th.jd_5) + // IOBUF(th.jd_5, j.TMS) + // PULLUP(th.jd_5) - IOBUF(th.jd_4, j.TDI) - PULLUP(th.jd_4) + // IOBUF(th.jd_4, j.TDI) + // PULLUP(th.jd_4) - IOBUF(th.jd_0, j.TDO) + // IOBUF(th.jd_0, j.TDO) - // mimic putting a pullup on this line (part of reset vote) - th.SRST_n := IOBUF(th.jd_6) - PULLUP(th.jd_6) + // // mimic putting a pullup on this line (part of reset vote) + // th.SRST_n := IOBUF(th.jd_6) + // PULLUP(th.jd_6) - IOBUF(th.jd_1, j.TRSTn) - PULLUP(th.jd_1) - } + // IOBUF(th.jd_1, j.TRSTn) + // PULLUP(th.jd_1) + // } Nil } }) class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { - //UARTAdapter.connect(ports)(system.p) - IOBUF(th.ck_io(2), ports.txd) - IOBUF(th.ck_io(3), ports.rxd) + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { + // UARTAdapter.connect(ports)(system.p) + // IOBUF(th.ck_io(2), ports.txd) + // IOBUF(th.ck_io(3), ports.rxd) Nil } }) \ No newline at end of file From dca56cd858f5f7b4e7e17e531833b50de6480e72 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sat, 10 Oct 2020 19:55:02 -0700 Subject: [PATCH 024/157] Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala. --- fpga/src/main/scala/arty/Configs.scala | 4 +- fpga/src/main/scala/arty/HarnessBinders.scala | 4 +- fpga/src/main/scala/arty/IOBinders.scala | 351 ------------------ fpga/src/main/scala/arty/TestHarness.scala | 15 +- 4 files changed, 5 insertions(+), 369 deletions(-) delete mode 100644 fpga/src/main/scala/arty/IOBinders.scala diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index e074dd03..e96bcd9c 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -52,10 +52,10 @@ class WithE300System extends Config((site, here, up) => { class E300ArtyDevKitConfig extends Config( new WithE300System ++ - new chipyard.iobinders.WithDebugIOCells ++ - new chipyard.iobinders.WithUARTIOCells ++ new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ + new chipyard.iobinders.WithDebugIOCells ++ + new chipyard.iobinders.WithUARTIOCells ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 4ee847a5..3dd380ea 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -31,7 +31,7 @@ import scala.reflect.{ClassTag} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[JTAGIO]) => { + (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => { // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { // ports.map { // case d: ClockedDMIIO => @@ -63,7 +63,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ }) class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // UARTAdapter.connect(ports)(system.p) // IOBUF(th.ck_io(2), ports.txd) diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala deleted file mode 100644 index 2b4b332b..00000000 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ /dev/null @@ -1,351 +0,0 @@ -package chipyard.fpga.arty - -import chisel3._ -import chisel3.experimental.{attach, IO} - -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.subsystem.{NExtTopInterrupts} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pinctrl._ - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - -import chipsalliance.rocketchip.config._ - -import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} -import chipyard.{HasHarnessSignalReferences} - -class WithE300Connections extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp - with HasPeripheryUARTModuleImp - with HasPeripherySPIModuleImp - with HasPeripheryDebugModuleImp - with HasPeripheryPWMModuleImp - with HasPeripherySPIFlashModuleImp - with HasPeripheryI2CModuleImp) => { - - implicit val p: Parameters = GetSystemParameters(system) - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // E300DigitalTop <-> ChipTop connections - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - - object PinGen { - def apply(): BasePin = { - val pin = new BasePin() - pin - } - } - - val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") - val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") - val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") - val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") - val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - - val io_async_corerst = IO(Input(Bool())).suggestName("core_reset") - system.reset := ResetCatchAndSync(system.clock, io_async_corerst, 20) - Debug.connectDebugClockAndReset(system.debug, system.clock) - - //----------------------------------------------------------------------- - // Check for unsupported rocket-chip connections - //----------------------------------------------------------------------- - - require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); - - //----------------------------------------------------------------------- - // Build GPIO Pin Mux - //----------------------------------------------------------------------- - // Pin Mux for UART, SPI, PWM - // First convert the System outputs into "IOF" using the respective *GPIOPort - // converters. - - val sys_uart = system.uart - val sys_pwm = system.pwm - val sys_spi = system.spi - val sys_i2c = system.i2c - - val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} - val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} - val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} - val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} - - (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } - (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - - //----------------------------------------------------------------------- - // Default Pin connections before attaching pinmux - - for (iof_0 <- system.gpio(0).iof_0.get) { - iof_0.default() - } - - for (iof_1 <- system.gpio(0).iof_1.get) { - iof_1.default() - } - - //----------------------------------------------------------------------- - - val iof_0 = system.gpio(0).iof_0.get - val iof_1 = system.gpio(0).iof_1.get - - // SPI1 (0 is the dedicated) - BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) - BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) - BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) - BasePinToIOF(spi_pins(0).sck, iof_0(5)) - BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) - BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) - BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) - BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) - BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) - - // SPI2 - BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) - BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) - BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) - BasePinToIOF(spi_pins(1).sck, iof_0(29)) - BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) - BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) - - // I2C - if (p(PeripheryI2CKey).length == 1) { - BasePinToIOF(i2c_pins(0).sda, iof_0(12)) - BasePinToIOF(i2c_pins(0).scl, iof_0(13)) - } - - // UART0 - BasePinToIOF(uart_pins(0).rxd, iof_0(16)) - BasePinToIOF(uart_pins(0).txd, iof_0(17)) - - // UART1 - BasePinToIOF(uart_pins(1).rxd, iof_0(24)) - BasePinToIOF(uart_pins(1).txd, iof_0(25)) - - //PWM - BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) - BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) - BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) - BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) - - BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) - BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) - BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) - BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) - - BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) - BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) - BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) - BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) - - //----------------------------------------------------------------------- - // Drive actual Pads - //----------------------------------------------------------------------- - - // Result of Pin Mux - GPIOPinsFromPort(io_gpio, system.gpio(0)) - - // Dedicated SPI Pads - SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) - - // JTAG Debug Interface - val sjtag = system.debug.get.systemjtag.get - JTAGPinsFromPort(io_jtag, sjtag.jtag) - sjtag.reset := io_jtag_reset - sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) - - io_ndreset := system.debug.get.ndreset - - // AON Pads -- direct connection is OK because - // EnhancedPin is hard-coded in MockAONPads - // and thus there is no .fromPort method. - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // Harness Function (ArtyHarness <-> ChipTop) - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - val harnessFn = (baseTh: HasHarnessSignalReferences) => { - baseTh match { case th: ArtyShell => - - io_async_corerst := th.reset_core - - //----------------------------------------------------------------------- - // Clock divider - //----------------------------------------------------------------------- - val slow_clock = Wire(Bool()) - - // Divide clock by 256, used to generate 32.768 kHz clock for AON block - withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { - val clockToggleReg = RegInit(false.B) - val (_, slowTick) = chisel3.util.Counter(true.B, 256) - when (slowTick) {clockToggleReg := ~clockToggleReg} - slow_clock := clockToggleReg - } - - //----------------------------------------------------------------------- - // DUT - //----------------------------------------------------------------------- - withClockAndReset(th.clock_32MHz, th.ck_rst) { - - //--------------------------------------------------------------------- - // SPI flash IOBUFs - //--------------------------------------------------------------------- - - IOBUF(th.qspi_sck, io_qspi.sck) - IOBUF(th.qspi_cs, io_qspi.cs(0)) - - IOBUF(th.qspi_dq(0), io_qspi.dq(0)) - IOBUF(th.qspi_dq(1), io_qspi.dq(1)) - IOBUF(th.qspi_dq(2), io_qspi.dq(2)) - IOBUF(th.qspi_dq(3), io_qspi.dq(3)) - - //--------------------------------------------------------------------- - // JTAG IOBUFs - //--------------------------------------------------------------------- - - io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt - - IOBUF(th.jd_5, io_jtag.TMS) - PULLUP(th.jd_5) - - IOBUF(th.jd_4, io_jtag.TDI) - PULLUP(th.jd_4) - - IOBUF(th.jd_0, io_jtag.TDO) - - // mimic putting a pullup on this line (part of reset vote) - th.SRST_n := IOBUF(th.jd_6) - PULLUP(th.jd_6) - - // jtag reset - val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) - io_jtag_reset := jtag_power_on_reset - - // debug reset - th.dut_ndreset := io_ndreset - - //--------------------------------------------------------------------- - // Assignment to package pins - //--------------------------------------------------------------------- - // Pins IO0-IO13 - // - // FTDI UART TX/RX are not connected to th.ck_io[0,1] - // the way they are on Arduino boards. We copy outgoing - // data to both places, switch 3 (sw[3]) determines whether - // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) - - val iobuf_ck0 = Module(new IOBUF()) - iobuf_ck0.io.I := io_gpio.pins(16).o.oval - iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX - - val iobuf_uart_txd = Module(new IOBUF()) - iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval - iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_uart_txd.io.IO, th.uart_txd_in) - - // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] - val sw_3_in = IOBUF(th.sw_3) - io_gpio.pins(16).i.ival := Mux(sw_3_in, - iobuf_ck0.io.O & io_gpio.pins(16).o.ie, - iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) - - IOBUF(th.uart_rxd_out, io_gpio.pins(17)) - - // Shield header row 0: PD2-PD7 - IOBUF(th.ck_io(2), io_gpio.pins(18)) - IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) - IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) - IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) - IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) - IOBUF(th.ck_io(7), io_gpio.pins(23)) - - // Header row 1: PB0-PB5 - IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) - IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) - IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) - IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) - IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO - IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK - - io_gpio.pins(6).i.ival := 0.U - io_gpio.pins(7).i.ival := 0.U - io_gpio.pins(8).i.ival := 0.U - - // Header row 3: A0-A5 (we don't support using them as analog inputs) - // just treat them as regular digital GPIOs - IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) - IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) - IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) - IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA - IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL - - // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty - // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active - IOBUF(th.led0_r, io_gpio.pins(1)) - IOBUF(th.led0_g, io_gpio.pins(2)) - IOBUF(th.led0_b, io_gpio.pins(3)) - - // Note that this is the one which is actually connected on the HiFive/Crazy88 - // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active - IOBUF(th.led1_r, io_gpio.pins(19)) - IOBUF(th.led1_g, io_gpio.pins(21)) - IOBUF(th.led1_b, io_gpio.pins(22)) - - // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active - IOBUF(th.led2_r, io_gpio.pins(11)) - IOBUF(th.led2_g, io_gpio.pins(12)) - IOBUF(th.led2_b, io_gpio.pins(13)) - - // Only 19 out of 20 shield pins connected to GPIO pins - // Shield pin A5 (pin 14) left unconnected - // The buttons are connected to some extra GPIO pins not connected on the - // HiFive1 board - IOBUF(th.btn_0, io_gpio.pins(15)) - IOBUF(th.btn_1, io_gpio.pins(30)) - IOBUF(th.btn_2, io_gpio.pins(31)) - - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 - IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX - IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX - - // SPI2 pins mapped to 6 pin ICSP connector (standard on later - // arduinos) These are connected to some extra GPIO pins not connected - // on the HiFive1 board - IOBUF(th.ck_ss, io_gpio.pins(26)) - IOBUF(th.ck_mosi, io_gpio.pins(27)) - IOBUF(th.ck_miso, io_gpio.pins(28)) - IOBUF(th.ck_sck, io_gpio.pins(29)) - - // Use the LEDs for some more useful debugging things - IOBUF(th.led_0, th.ck_rst) - IOBUF(th.led_1, th.SRST_n) - IOBUF(th.led_3, io_gpio.pins(14)) - - //--------------------------------------------------------------------- - // Unconnected inputs - //--------------------------------------------------------------------- - - } - - Nil - } - } - - Seq((Nil, Nil, Some(harnessFn))) - } -}) - diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index cd327243..76dc6a3c 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -6,22 +6,9 @@ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import chipyard.{BuildTop, HasHarnessSignalReferences} +import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} -trait HasTestHarnessFunctions { - val lazySystem: LazyModule - val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]] - val portMap = scala.collection.mutable.Map[String, Seq[Data]]() -} - -trait HasHarnessSignalReferences { - def harnessClock: Clock - def harnessReset: Reset - def dutReset: Reset - def success: Bool -} - class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") From 895dcd6831c7fbcfaf74da5a080c45f0a6ebe55d Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sun, 11 Oct 2020 11:12:33 -0700 Subject: [PATCH 025/157] referencing fully qualified chipyard.harness.OverrideHarnessBinder to debug import issue. --- fpga/src/main/scala/arty/HarnessBinders.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 3dd380ea..89105d78 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -30,7 +30,7 @@ import scala.reflect.{ClassTag} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} -class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ +class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => { // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { // ports.map { @@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ } }) -class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ +class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // UARTAdapter.connect(ports)(system.p) @@ -70,4 +70,4 @@ class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ // IOBUF(th.ck_io(3), ports.rxd) Nil } -}) \ No newline at end of file +}) From 8257775e96650c83b232aa921a8e53038be153fb Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 12 Oct 2020 21:50:50 -0700 Subject: [PATCH 026/157] Connect DDR from harness --- fpga/src/main/scala/vcu118/TestHarness.scala | 29 +++++++++++++------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index d4e299a5..4275f68d 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -6,6 +6,7 @@ import chisel3.experimental.{Analog, IO} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem} +import freechips.rocketchip.tilelink._ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx._ @@ -155,16 +156,24 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends Chipyar /*** Experimental DDR ***/ - //val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) + val ddrWrangler = LazyModule(new ResetWrangler) + val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL)) - //topDesign match { case lazyDut: VCU118Platform => - // lazyDut.lazySystem match { case lazyDutWBus: BaseSubsystem => - // lazyDutWBus { - // InModuleBody { - // ddrPlaced.overlayOutput.ddr := lazyDutWBus.mbus.toDRAMController(Some("xilinxvcu118mig"))() - // } - // } - // } - //} + // connect 1 mem. channel to the FPGA DDR + val inParams = topDesign match { case td: VCU118Platform => + td.lazySystem match { case lsys: chipyard.CanHaveMasterTLMemPort => + lsys.memTLNode.edges.in(0) + } + } + val ddrClient = TLClientNode(Seq(inParams.master)) + InModuleBody { + topDesign.module match { case dutMod: HasVCU118PlatformIO => + val bundles = ddrClient.out.map(_._1) + val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType))) + bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } + ddrClientBundle <> dutMod.io_tl_mem + } + } + ddrPlaced.overlayOutput.ddr := ddrClient } From 9c298eedfe539e05aa409d4b60595f5a0ab2ada1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 13 Oct 2020 15:10:41 -0700 Subject: [PATCH 027/157] Support evaluation of HarnessBinders in LazyModule context --- .../src/main/scala/HarnessBinders.scala | 75 ++++++++++--------- .../chipyard/src/main/scala/IOBinders.scala | 46 +++++------- .../chipyard/src/main/scala/TestHarness.scala | 2 +- .../src/main/scala/BridgeBinders.scala | 16 ++-- 4 files changed, 66 insertions(+), 73 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index e5cfacfb..6f7d2dd8 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -1,7 +1,7 @@ package chipyard.harness import chisel3._ -import chisel3.experimental.{Analog} +import chisel3.experimental.{Analog, BaseModule} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} @@ -33,40 +33,41 @@ case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalRefer object ApplyHarnessBinders { - def apply(th: HasHarnessSignalReferences, sys: LazyModule, map: Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]], portMap: Map[String, Seq[Data]]) = { + def apply(th: HasHarnessSignalReferences, sys: LazyModule, portMap: Map[String, Seq[Data]])(implicit p: Parameters) = { val pm = portMap.withDefaultValue(Nil) - map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } + p(HarnessBinders).map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } } } -class OverrideHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { +class HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T, S, Seq[U]) => Seq[Any]) => (T, S, Seq[U]) => Seq[Any])(implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) extends Config((site, here, up) => { case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val pts = ports.collect({case p: S => p}) + val pts = ports.collect({case p: U => p}) require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") - t match { - case system: T => fn(system, th, pts) + val upfn = up(HarnessBinders, site)(tag.runtimeClass.toString) + th match { + case th: S => + t match { + case system: T => composer(upfn)(system, th, pts) + case _ => Nil + } case _ => Nil } }) ) }) -class ComposeHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { - case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> - ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val pts = ports.collect({case p: S => p}) - require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") - t match { - case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, pts) ++ fn(system, th, pts) - case _ => Nil - } - }) - ) -}) +class OverrideHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) + (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) + extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => fn) + +class ComposeHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) + (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) + extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => (t, th, p) => upfn(t, th, p) ++ fn(t, th, p)) + class WithGPIOTiedOff extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Analog]) => { + (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Analog]) => { ports.foreach { _ <> AnalogConst(0) } Nil } @@ -74,7 +75,7 @@ class WithGPIOTiedOff extends OverrideHarnessBinder({ // DOC include start: WithUARTAdapter class WithUARTAdapter extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { UARTAdapter.connect(ports)(system.p) Nil } @@ -82,14 +83,14 @@ class WithUARTAdapter extends OverrideHarnessBinder({ // DOC include end: WithUARTAdapter class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({ - (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { + (system: HasPeripherySPIFlashModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p) Nil } }) class WithSimBlockDevice extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => SimBlockDevice.connect(b.clock, th.harnessReset.asBool, Some(b.bits)) } Nil @@ -97,7 +98,7 @@ class WithSimBlockDevice extends OverrideHarnessBinder({ }) class WithBlockDeviceModel extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => withClockAndReset(b.clock, th.harnessReset) { BlockDeviceModel.connect(Some(b.bits)) } } Nil @@ -105,7 +106,7 @@ class WithBlockDeviceModel extends OverrideHarnessBinder({ }) class WithLoopbackNIC extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => withClockAndReset(n.clock, th.harnessReset) { @@ -117,7 +118,7 @@ class WithLoopbackNIC extends OverrideHarnessBinder({ }) class WithSimNetwork extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.harnessReset.asBool) } Nil @@ -125,7 +126,7 @@ class WithSimNetwork extends OverrideHarnessBinder({ }) class WithSimAXIMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p)) @@ -139,7 +140,7 @@ class WithSimAXIMem extends OverrideHarnessBinder({ }) class WithBlackBoxSimMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val memSize = p(ExtMem).get.master.size @@ -154,7 +155,7 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ }) class WithSimAXIMMIO extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MMIOPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.mmioAXI4Node.edges.in).map { case (port, edge) => val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p)) @@ -168,21 +169,21 @@ class WithSimAXIMMIO extends OverrideHarnessBinder({ }) class WithTieOffInterrupts extends OverrideHarnessBinder({ - (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[UInt]) => { + (system: HasExtInterruptsModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UInt]) => { ports.foreach { _ := 0.U } Nil } }) class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ - (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveSlaveAXI4Port, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { ports.foreach({ p => p := DontCare; p.bits.tieoff() }) Nil } }) class WithSimDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebugModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { case d: ClockedDMIIO => val dtm_success = WireInit(false.B) @@ -198,7 +199,7 @@ class WithSimDebug extends OverrideHarnessBinder({ }) class WithTiedOffDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebugModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { case j: JTAGIO => j.TCK := true.B.asClock @@ -224,7 +225,7 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -234,7 +235,7 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ }) class WithSimSerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -245,14 +246,14 @@ class WithSimSerial extends OverrideHarnessBinder({ }) class WithTraceGenSuccess extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { + (system: TraceGenSystemModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Bool]) => { ports.map { p => when (p) { th.success := true.B } } Nil } }) class WithSimDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } Nil } diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 4a31e2c0..5259cbb1 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -72,41 +72,33 @@ object GetSystemParameters { } } -class IOBinder(f: (View, View, View) => PartialFunction[Any, Any]) extends Config(f) +class IOBinder[T, S <: Data](composer: (Any => (Seq[Data], Seq[IOCell])) => T => (Seq[Data], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> + ((t: Any) => { + val upfn = up(IOBinders, site)(tag.runtimeClass.toString) + t match { + case system: T => composer(upfn)(system) + case _ => (Nil, Nil) + } + }) + ) +}) + // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { - case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any) => { - t match { - case system: T => - val (ports, cells) = fn(system) - (ports, cells) - case _ => (Nil, Nil) - } - }) - ) -}) +class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder[T, S](upfn => fn) + // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { - case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any) => { - t match { - case system: T => - val r = up(IOBinders, site)(tag.runtimeClass.toString)(system) - val h = fn(system) - val ports = r._1 ++ h._1 - val cells = r._2 ++ h._2 - (ports, cells) - case _ => (Nil, Nil) - } - }) - ) +class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder[T, S](upfn => t => { + val r = upfn(t) + val h = fn(t) + (r._1 ++ h._1, r._2 ++ h._2) }) + object BoreHelper { def apply(name: String, source: Clock): Clock = { val clock_io = IO(Output(Clock())).suggestName(name) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 2faff565..64b889e3 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -44,7 +44,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + ApplyHarnessBinders(this, d.lazySystem, d.portMap.toMap) } } diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 444c7b33..2fa49fc3 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -66,7 +66,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { }) class WithSerialBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { port => implicit val p = GetSystemParameters(system) val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -77,7 +77,7 @@ class WithSerialBridge extends OverrideHarnessBinder({ }) class WithNICBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: FireSim, ports: Seq[ClockedIO[NICIOvonly]]) => { val p: Parameters = GetSystemParameters(system) ports.map { n => NICBridge(n.clock, n.bits)(p) } Nil @@ -85,12 +85,12 @@ class WithNICBridge extends OverrideHarnessBinder({ }) class WithUARTBridge extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => + (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) => ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: FireSim, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => BlockDevBridge(b.clock, b.bits, th.harnessReset.toBool) } Nil @@ -98,7 +98,7 @@ class WithBlockDeviceBridge extends OverrideHarnessBinder({ }) class WithFASEDBridge extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: FireSim, ports: Seq[ClockedIO[AXI4Bundle]]) => { implicit val p: Parameters = GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (axi4, edge) => val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth, @@ -118,20 +118,20 @@ class WithFASEDBridge extends OverrideHarnessBinder({ }) class WithTracerVBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p)) } Nil } }) class WithDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => + (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => ports.map { p => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil }) class WithTraceGenBridge extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => + (system: TraceGenSystemModuleImp, th: FireSim, ports: Seq[Bool]) => ports.map { p => GroundTestBridge(th.harnessClock, p)(system.p) }; Nil }) From 5bbd8654470a004c1f06cb7abd5f9060b64e24b3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 13 Oct 2020 16:18:00 -0700 Subject: [PATCH 028/157] Add MMC Device section to the DTS --- .gitmodules | 2 +- fpga/src/main/scala/vcu118/Platform.scala | 12 ++++++++++-- generators/sifive-blocks | 2 +- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/.gitmodules b/.gitmodules index ea3cb2c7..f406a5c2 100644 --- a/.gitmodules +++ b/.gitmodules @@ -21,7 +21,7 @@ url = https://github.com/riscv-boom/riscv-boom.git [submodule "generators/sifive-blocks"] path = generators/sifive-blocks - url = https://github.com/sifive/sifive-blocks.git + url = https://github.com/abejgonzalez/sifive-blocks.git [submodule "generators/hwacha"] path = generators/hwacha url = https://github.com/ucb-bar/hwacha.git diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala index bdacdf42..342f7328 100644 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ b/fpga/src/main/scala/vcu118/Platform.scala @@ -3,7 +3,7 @@ package chipyard.fpga.vcu118 import chisel3._ import chisel3.experimental.{Analog, IO, DataMirror} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyScope, InModuleBody, BundleBridgeSource, ValName} +import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.tilelink.{TLBundle} @@ -23,10 +23,18 @@ trait HasVCU118PlatformIO { val io_tl_mem: HeterogeneousBag[TLBundle] } -class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope { +class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope with BindingScope { val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") + // add MMC to the DTS + lazySystem match { case lsys: HasPeripherySPI => + val mmcDev = new MMCDevice(lsys.tlspi.head.device, 1) + ResourceBinding { + Resource(mmcDev, "reg").bind(ResourceAddress(0)) + } + } + override lazy val module = new VCU118PlatformModule(this) } diff --git a/generators/sifive-blocks b/generators/sifive-blocks index c240e629..413e0a88 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit c240e629e2fc111cbb12e4fe707be898b5204984 +Subproject commit 413e0a88a4e48b1966b9444d613a7f3a776e65aa From dda7622c29c1bd00abdb74bcd7251915886ed323 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 14 Oct 2020 14:49:22 -0700 Subject: [PATCH 029/157] temp commit --- fpga/src/main/scala/arty/TestHarness.scala | 68 +- fpga/src/main/scala/arty/e300/Configs.scala | 144 ++-- .../src/main/scala/arty/e300/DigitalTop.scala | 46 +- fpga/src/main/scala/arty/e300/IOBinders.scala | 730 +++++++++--------- fpga/src/main/scala/vcu118/Configs.scala | 28 +- fpga/src/main/scala/vcu118/Platform.scala | 81 -- fpga/src/main/scala/vcu118/TestHarness.scala | 130 +--- .../chipyard/src/main/scala/ChipTop.scala | 4 +- 8 files changed, 529 insertions(+), 702 deletions(-) delete mode 100644 fpga/src/main/scala/vcu118/Platform.scala diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 919e5c99..6571f3d6 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -1,34 +1,34 @@ -package chipyard.fpga.arty - -import chisel3._ -import chisel3.experimental.{Analog} - -import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Parameters} - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} - -import chipyard.{BuildTop, HasHarnessSignalReferences} - -class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { - - val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") - - // turn IO clock into Reset type - val hReset = Wire(Reset()) - hReset := ck_rst - - // default to 32MHz clock - withClockAndReset(clock_32MHz, hReset) { - val dut = Module(ldut.module) - } - - val harnessClock = clock_32MHz - val harnessReset = hReset - val success = false.B - val dutReset = hReset - - // must be after HasHarnessSignalReferences assignments - ldut.harnessFunctions.foreach(_(this)) -} - +//package chipyard.fpga.arty +// +//import chisel3._ +//import chisel3.experimental.{Analog} +// +//import freechips.rocketchip.diplomacy.{LazyModule} +//import freechips.rocketchip.config.{Parameters} +// +//import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} +// +//import chipyard.{BuildTop, HasHarnessSignalReferences} +// +//class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { +// +// val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") +// +// // turn IO clock into Reset type +// val hReset = Wire(Reset()) +// hReset := ck_rst +// +// // default to 32MHz clock +// withClockAndReset(clock_32MHz, hReset) { +// val dut = Module(ldut.module) +// } +// +// val harnessClock = clock_32MHz +// val harnessReset = hReset +// val success = false.B +// val dutReset = hReset +// +// // must be after HasHarnessSignalReferences assignments +// ldut.harnessFunctions.foreach(_(this)) +//} +// diff --git a/fpga/src/main/scala/arty/e300/Configs.scala b/fpga/src/main/scala/arty/e300/Configs.scala index dd9213fc..9e04d8df 100644 --- a/fpga/src/main/scala/arty/e300/Configs.scala +++ b/fpga/src/main/scala/arty/e300/Configs.scala @@ -1,72 +1,72 @@ -// See LICENSE for license details. -package chipyard.fpga.arty.e300 - -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} -import freechips.rocketchip.system._ -import freechips.rocketchip.tile._ - -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ - -import chipyard.{BuildSystem} - -class E300DevKitExtra extends Config((site, here, up) => { - case PeripheryGPIOKey => List( - GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) - case PeripheryPWMKey => List( - PWMParams(address = 0x10015000, cmpWidth = 8), - PWMParams(address = 0x10025000, cmpWidth = 16), - PWMParams(address = 0x10035000, cmpWidth = 16)) - case PeripherySPIKey => List( - SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3), - SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3)) - case PeripherySPIFlashKey => List( - SPIFlashParams( - fAddress = 0x20000000, - rAddress = 0x10014000, - defaultSampleDel = 3)) - case PeripheryUARTKey => List( - UARTParams(address = 0x10013000), - UARTParams(address = 0x10023000)) - case PeripheryI2CKey => List( - I2CParams(address = 0x10016000)) - case PeripheryMockAONKey => - MockAONParams(address = 0x10000000) - case DTSTimebase => BigInt(32768) - case JtagDTMKey => new JtagDTMConfig ( - idcodeVersion = 2, - idcodePartNum = 0x000, - idcodeManufId = 0x489, - debugIdleCycles = 5) -}) - -class WithE300System extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) -}) - -class E300ArtyDevKitConfig extends Config( - new WithE300System ++ - new WithE300Connections ++ - new E300DevKitExtra ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.With1TinyCore ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ - new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) +//// See LICENSE for license details. +//package chipyard.fpga.arty.e300 +// +//import freechips.rocketchip.config._ +//import freechips.rocketchip.subsystem._ +//import freechips.rocketchip.devices.debug._ +//import freechips.rocketchip.devices.tilelink._ +//import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} +//import freechips.rocketchip.system._ +//import freechips.rocketchip.tile._ +// +//import sifive.blocks.devices.mockaon._ +//import sifive.blocks.devices.gpio._ +//import sifive.blocks.devices.pwm._ +//import sifive.blocks.devices.spi._ +//import sifive.blocks.devices.uart._ +//import sifive.blocks.devices.i2c._ +// +//import chipyard.{BuildSystem} +// +//class E300DevKitExtra extends Config((site, here, up) => { +// case PeripheryGPIOKey => List( +// GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) +// case PeripheryPWMKey => List( +// PWMParams(address = 0x10015000, cmpWidth = 8), +// PWMParams(address = 0x10025000, cmpWidth = 16), +// PWMParams(address = 0x10035000, cmpWidth = 16)) +// case PeripherySPIKey => List( +// SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3), +// SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3)) +// case PeripherySPIFlashKey => List( +// SPIFlashParams( +// fAddress = 0x20000000, +// rAddress = 0x10014000, +// defaultSampleDel = 3)) +// case PeripheryUARTKey => List( +// UARTParams(address = 0x10013000), +// UARTParams(address = 0x10023000)) +// case PeripheryI2CKey => List( +// I2CParams(address = 0x10016000)) +// case PeripheryMockAONKey => +// MockAONParams(address = 0x10000000) +// case DTSTimebase => BigInt(32768) +// case JtagDTMKey => new JtagDTMConfig ( +// idcodeVersion = 2, +// idcodePartNum = 0x000, +// idcodeManufId = 0x489, +// debugIdleCycles = 5) +//}) +// +//class WithE300System extends Config((site, here, up) => { +// case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) +//}) +// +//class E300ArtyDevKitConfig extends Config( +// new WithE300System ++ +// new WithE300Connections ++ +// new E300DevKitExtra ++ +// new chipyard.config.WithBootROM ++ +// new chipyard.config.WithL2TLBs(1024) ++ +// new freechips.rocketchip.subsystem.With1TinyCore ++ +// new freechips.rocketchip.subsystem.WithNBanks(0) ++ +// new freechips.rocketchip.subsystem.WithNoMemPort ++ +// new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ +// new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ +// new freechips.rocketchip.subsystem.WithJtagDTM ++ +// new freechips.rocketchip.subsystem.WithNoMMIOPort ++ +// new freechips.rocketchip.subsystem.WithNoSlavePort ++ +// new freechips.rocketchip.subsystem.WithInclusiveCache ++ +// new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ +// new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ +// new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/e300/DigitalTop.scala index 1bda2680..45018c00 100644 --- a/fpga/src/main/scala/arty/e300/DigitalTop.scala +++ b/fpga/src/main/scala/arty/e300/DigitalTop.scala @@ -1,23 +1,23 @@ -package chipyard.fpga.arty.e300 - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ - -import chipyard.{DigitalTop, DigitalTopModule} - -// ------------------------------------ -// E300 DigitalTop -// ------------------------------------ - -class E300DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.mockaon.HasPeripheryMockAON -{ - override lazy val module = new E300DigitalTopModule(this) -} - -class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) - with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp +//package chipyard.fpga.arty.e300 +// +//import chisel3._ +// +//import freechips.rocketchip.subsystem._ +//import freechips.rocketchip.system._ +//import freechips.rocketchip.config.Parameters +//import freechips.rocketchip.devices.tilelink._ +// +//import chipyard.{DigitalTop, DigitalTopModule} +// +//// ------------------------------------ +//// E300 DigitalTop +//// ------------------------------------ +// +//class E300DigitalTop(implicit p: Parameters) extends DigitalTop +// with sifive.blocks.devices.mockaon.HasPeripheryMockAON +//{ +// override lazy val module = new E300DigitalTopModule(this) +//} +// +//class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) +// with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index 8d866619..82da669c 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -1,365 +1,365 @@ -package chipyard.fpga.arty.e300 - -import chisel3._ -import chisel3.experimental.{attach, IO} - -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.subsystem.{NExtTopInterrupts} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pinctrl._ - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - -import chipsalliance.rocketchip.config._ - -import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} -import chipyard.{HasHarnessSignalReferences} - -class WithE300Connections extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp - with HasPeripheryUARTModuleImp - with HasPeripherySPIModuleImp - with HasPeripheryDebugModuleImp - with HasPeripheryPWMModuleImp - with HasPeripherySPIFlashModuleImp - with HasPeripheryMockAONModuleImp - with HasPeripheryI2CModuleImp) => { - - implicit val p: Parameters = GetSystemParameters(system) - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // E300DigitalTop <-> ChipTop connections - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - - object PinGen { - def apply(): BasePin = { - val pin = new BasePin() - pin - } - } - - val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") - val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") - val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") - val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") - val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") - val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - - // This needs to be de-asserted synchronously to the coreClk. - val async_corerst = system.aon.rsts.corerst - // Add in debug-controlled reset. - system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) - Debug.connectDebugClockAndReset(system.debug, system.clock) - - //----------------------------------------------------------------------- - // Check for unsupported rocket-chip connections - //----------------------------------------------------------------------- - - require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); - - //----------------------------------------------------------------------- - // Build GPIO Pin Mux - //----------------------------------------------------------------------- - // Pin Mux for UART, SPI, PWM - // First convert the System outputs into "IOF" using the respective *GPIOPort - // converters. - - val sys_uart = system.uart - val sys_pwm = system.pwm - val sys_spi = system.spi - val sys_i2c = system.i2c - - val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} - val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} - val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} - val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} - - (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } - (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - - //----------------------------------------------------------------------- - // Default Pin connections before attaching pinmux - - for (iof_0 <- system.gpio(0).iof_0.get) { - iof_0.default() - } - - for (iof_1 <- system.gpio(0).iof_1.get) { - iof_1.default() - } - - //----------------------------------------------------------------------- - - val iof_0 = system.gpio(0).iof_0.get - val iof_1 = system.gpio(0).iof_1.get - - // SPI1 (0 is the dedicated) - BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) - BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) - BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) - BasePinToIOF(spi_pins(0).sck, iof_0(5)) - BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) - BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) - BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) - BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) - BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) - - // SPI2 - BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) - BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) - BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) - BasePinToIOF(spi_pins(1).sck, iof_0(29)) - BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) - BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) - - // I2C - if (p(PeripheryI2CKey).length == 1) { - BasePinToIOF(i2c_pins(0).sda, iof_0(12)) - BasePinToIOF(i2c_pins(0).scl, iof_0(13)) - } - - // UART0 - BasePinToIOF(uart_pins(0).rxd, iof_0(16)) - BasePinToIOF(uart_pins(0).txd, iof_0(17)) - - // UART1 - BasePinToIOF(uart_pins(1).rxd, iof_0(24)) - BasePinToIOF(uart_pins(1).txd, iof_0(25)) - - //PWM - BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) - BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) - BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) - BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) - - BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) - BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) - BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) - BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) - - BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) - BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) - BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) - BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) - - //----------------------------------------------------------------------- - // Drive actual Pads - //----------------------------------------------------------------------- - - // Result of Pin Mux - GPIOPinsFromPort(io_gpio, system.gpio(0)) - - // Dedicated SPI Pads - SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) - - // JTAG Debug Interface - val sjtag = system.debug.get.systemjtag.get - JTAGPinsFromPort(io_jtag, sjtag.jtag) - sjtag.reset := io_jtag_reset - sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) - - io_ndreset := system.debug.get.ndreset - - // AON Pads -- direct connection is OK because - // EnhancedPin is hard-coded in MockAONPads - // and thus there is no .fromPort method. - io_aon <> system.aon.pins - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // Harness Function (ArtyHarness <-> ChipTop) - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - val harnessFn = (baseTh: HasHarnessSignalReferences) => { - baseTh match { case th: ArtyShell => - - //----------------------------------------------------------------------- - // Clock divider - //----------------------------------------------------------------------- - val slow_clock = Wire(Bool()) - - // Divide clock by 256, used to generate 32.768 kHz clock for AON block - withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { - val clockToggleReg = RegInit(false.B) - val (_, slowTick) = chisel3.util.Counter(true.B, 256) - when (slowTick) {clockToggleReg := ~clockToggleReg} - slow_clock := clockToggleReg - } - - //----------------------------------------------------------------------- - // DUT - //----------------------------------------------------------------------- - withClockAndReset(th.clock_32MHz, th.ck_rst) { - - //--------------------------------------------------------------------- - // SPI flash IOBUFs - //--------------------------------------------------------------------- - - IOBUF(th.qspi_sck, io_qspi.sck) - IOBUF(th.qspi_cs, io_qspi.cs(0)) - - IOBUF(th.qspi_dq(0), io_qspi.dq(0)) - IOBUF(th.qspi_dq(1), io_qspi.dq(1)) - IOBUF(th.qspi_dq(2), io_qspi.dq(2)) - IOBUF(th.qspi_dq(3), io_qspi.dq(3)) - - //--------------------------------------------------------------------- - // JTAG IOBUFs - //--------------------------------------------------------------------- - - io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt - - IOBUF(th.jd_5, io_jtag.TMS) - PULLUP(th.jd_5) - - IOBUF(th.jd_4, io_jtag.TDI) - PULLUP(th.jd_4) - - IOBUF(th.jd_0, io_jtag.TDO) - - // mimic putting a pullup on this line (part of reset vote) - th.SRST_n := IOBUF(th.jd_6) - PULLUP(th.jd_6) - - // jtag reset - val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) - io_jtag_reset := jtag_power_on_reset - - // debug reset - th.dut_ndreset := io_ndreset - - //--------------------------------------------------------------------- - // Assignment to package pins - //--------------------------------------------------------------------- - // Pins IO0-IO13 - // - // FTDI UART TX/RX are not connected to th.ck_io[0,1] - // the way they are on Arduino boards. We copy outgoing - // data to both places, switch 3 (sw[3]) determines whether - // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) - - val iobuf_ck0 = Module(new IOBUF()) - iobuf_ck0.io.I := io_gpio.pins(16).o.oval - iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX - - val iobuf_uart_txd = Module(new IOBUF()) - iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval - iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_uart_txd.io.IO, th.uart_txd_in) - - // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] - val sw_3_in = IOBUF(th.sw_3) - io_gpio.pins(16).i.ival := Mux(sw_3_in, - iobuf_ck0.io.O & io_gpio.pins(16).o.ie, - iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) - - IOBUF(th.uart_rxd_out, io_gpio.pins(17)) - - // Shield header row 0: PD2-PD7 - IOBUF(th.ck_io(2), io_gpio.pins(18)) - IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) - IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) - IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) - IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) - IOBUF(th.ck_io(7), io_gpio.pins(23)) - - // Header row 1: PB0-PB5 - IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) - IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) - IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) - IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) - IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO - IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK - - io_gpio.pins(6).i.ival := 0.U - io_gpio.pins(7).i.ival := 0.U - io_gpio.pins(8).i.ival := 0.U - - // Header row 3: A0-A5 (we don't support using them as analog inputs) - // just treat them as regular digital GPIOs - IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) - IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) - IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) - IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA - IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL - - // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty - // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active - IOBUF(th.led0_r, io_gpio.pins(1)) - IOBUF(th.led0_g, io_gpio.pins(2)) - IOBUF(th.led0_b, io_gpio.pins(3)) - - // Note that this is the one which is actually connected on the HiFive/Crazy88 - // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active - IOBUF(th.led1_r, io_gpio.pins(19)) - IOBUF(th.led1_g, io_gpio.pins(21)) - IOBUF(th.led1_b, io_gpio.pins(22)) - - // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active - IOBUF(th.led2_r, io_gpio.pins(11)) - IOBUF(th.led2_g, io_gpio.pins(12)) - IOBUF(th.led2_b, io_gpio.pins(13)) - - // Only 19 out of 20 shield pins connected to GPIO pins - // Shield pin A5 (pin 14) left unconnected - // The buttons are connected to some extra GPIO pins not connected on the - // HiFive1 board - IOBUF(th.btn_0, io_gpio.pins(15)) - IOBUF(th.btn_1, io_gpio.pins(30)) - IOBUF(th.btn_2, io_gpio.pins(31)) - - val iobuf_btn_3 = Module(new IOBUF()) - iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval - iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe - attach(th.btn_3, iobuf_btn_3.io.IO) - io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie - - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 - IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX - IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX - - // SPI2 pins mapped to 6 pin ICSP connector (standard on later - // arduinos) These are connected to some extra GPIO pins not connected - // on the HiFive1 board - IOBUF(th.ck_ss, io_gpio.pins(26)) - IOBUF(th.ck_mosi, io_gpio.pins(27)) - IOBUF(th.ck_miso, io_gpio.pins(28)) - IOBUF(th.ck_sck, io_gpio.pins(29)) - - // Use the LEDs for some more useful debugging things - IOBUF(th.led_0, th.ck_rst) - IOBUF(th.led_1, th.SRST_n) - IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) - IOBUF(th.led_3, io_gpio.pins(14)) - - //--------------------------------------------------------------------- - // Unconnected inputs - //--------------------------------------------------------------------- - - io_aon.erst_n.i.ival := ~th.reset_periph - io_aon.lfextclk.i.ival := slow_clock - io_aon.pmu.vddpaden.i.ival := 1.U - } - - Nil - } - } - - Seq((Nil, Nil, Some(harnessFn))) - } -}) - +//package chipyard.fpga.arty.e300 +// +//import chisel3._ +//import chisel3.experimental.{attach, IO} +// +//import freechips.rocketchip.util._ +//import freechips.rocketchip.devices.debug._ +//import freechips.rocketchip.subsystem.{NExtTopInterrupts} +// +//import sifive.blocks.devices.gpio._ +//import sifive.blocks.devices.uart._ +//import sifive.blocks.devices.spi._ +//import sifive.blocks.devices.pwm._ +//import sifive.blocks.devices.i2c._ +//import sifive.blocks.devices.mockaon._ +//import sifive.blocks.devices.jtag._ +//import sifive.blocks.devices.pinctrl._ +// +//import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} +//import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} +// +//import chipsalliance.rocketchip.config._ +// +//import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} +//import chipyard.{HasHarnessSignalReferences} +// +//class WithE300Connections extends OverrideIOBinder({ +// (system: HasPeripheryGPIOModuleImp +// with HasPeripheryUARTModuleImp +// with HasPeripherySPIModuleImp +// with HasPeripheryDebugModuleImp +// with HasPeripheryPWMModuleImp +// with HasPeripherySPIFlashModuleImp +// with HasPeripheryMockAONModuleImp +// with HasPeripheryI2CModuleImp) => { +// +// implicit val p: Parameters = GetSystemParameters(system) +// +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// // E300DigitalTop <-> ChipTop connections +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// +// object PinGen { +// def apply(): BasePin = { +// val pin = new BasePin() +// pin +// } +// } +// +// val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") +// val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") +// val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") +// val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") +// val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") +// val io_ndreset = IO(Output(Bool())).suggestName("ndreset") +// +// // This needs to be de-asserted synchronously to the coreClk. +// val async_corerst = system.aon.rsts.corerst +// // Add in debug-controlled reset. +// system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) +// Debug.connectDebugClockAndReset(system.debug, system.clock) +// +// //----------------------------------------------------------------------- +// // Check for unsupported rocket-chip connections +// //----------------------------------------------------------------------- +// +// require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); +// +// //----------------------------------------------------------------------- +// // Build GPIO Pin Mux +// //----------------------------------------------------------------------- +// // Pin Mux for UART, SPI, PWM +// // First convert the System outputs into "IOF" using the respective *GPIOPort +// // converters. +// +// val sys_uart = system.uart +// val sys_pwm = system.pwm +// val sys_spi = system.spi +// val sys_i2c = system.i2c +// +// val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} +// val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} +// val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} +// val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} +// +// (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} +// (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } +// (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} +// (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} +// +// //----------------------------------------------------------------------- +// // Default Pin connections before attaching pinmux +// +// for (iof_0 <- system.gpio(0).iof_0.get) { +// iof_0.default() +// } +// +// for (iof_1 <- system.gpio(0).iof_1.get) { +// iof_1.default() +// } +// +// //----------------------------------------------------------------------- +// +// val iof_0 = system.gpio(0).iof_0.get +// val iof_1 = system.gpio(0).iof_1.get +// +// // SPI1 (0 is the dedicated) +// BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) +// BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) +// BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) +// BasePinToIOF(spi_pins(0).sck, iof_0(5)) +// BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) +// BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) +// BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) +// BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) +// BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) +// +// // SPI2 +// BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) +// BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) +// BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) +// BasePinToIOF(spi_pins(1).sck, iof_0(29)) +// BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) +// BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) +// +// // I2C +// if (p(PeripheryI2CKey).length == 1) { +// BasePinToIOF(i2c_pins(0).sda, iof_0(12)) +// BasePinToIOF(i2c_pins(0).scl, iof_0(13)) +// } +// +// // UART0 +// BasePinToIOF(uart_pins(0).rxd, iof_0(16)) +// BasePinToIOF(uart_pins(0).txd, iof_0(17)) +// +// // UART1 +// BasePinToIOF(uart_pins(1).rxd, iof_0(24)) +// BasePinToIOF(uart_pins(1).txd, iof_0(25)) +// +// //PWM +// BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) +// BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) +// BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) +// BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) +// +// BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) +// BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) +// BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) +// BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) +// +// BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) +// BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) +// BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) +// BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) +// +// //----------------------------------------------------------------------- +// // Drive actual Pads +// //----------------------------------------------------------------------- +// +// // Result of Pin Mux +// GPIOPinsFromPort(io_gpio, system.gpio(0)) +// +// // Dedicated SPI Pads +// SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) +// +// // JTAG Debug Interface +// val sjtag = system.debug.get.systemjtag.get +// JTAGPinsFromPort(io_jtag, sjtag.jtag) +// sjtag.reset := io_jtag_reset +// sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) +// +// io_ndreset := system.debug.get.ndreset +// +// // AON Pads -- direct connection is OK because +// // EnhancedPin is hard-coded in MockAONPads +// // and thus there is no .fromPort method. +// io_aon <> system.aon.pins +// +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// // Harness Function (ArtyHarness <-> ChipTop) +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// val harnessFn = (baseTh: HasHarnessSignalReferences) => { +// baseTh match { case th: ArtyShell => +// +// //----------------------------------------------------------------------- +// // Clock divider +// //----------------------------------------------------------------------- +// val slow_clock = Wire(Bool()) +// +// // Divide clock by 256, used to generate 32.768 kHz clock for AON block +// withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { +// val clockToggleReg = RegInit(false.B) +// val (_, slowTick) = chisel3.util.Counter(true.B, 256) +// when (slowTick) {clockToggleReg := ~clockToggleReg} +// slow_clock := clockToggleReg +// } +// +// //----------------------------------------------------------------------- +// // DUT +// //----------------------------------------------------------------------- +// withClockAndReset(th.clock_32MHz, th.ck_rst) { +// +// //--------------------------------------------------------------------- +// // SPI flash IOBUFs +// //--------------------------------------------------------------------- +// +// IOBUF(th.qspi_sck, io_qspi.sck) +// IOBUF(th.qspi_cs, io_qspi.cs(0)) +// +// IOBUF(th.qspi_dq(0), io_qspi.dq(0)) +// IOBUF(th.qspi_dq(1), io_qspi.dq(1)) +// IOBUF(th.qspi_dq(2), io_qspi.dq(2)) +// IOBUF(th.qspi_dq(3), io_qspi.dq(3)) +// +// //--------------------------------------------------------------------- +// // JTAG IOBUFs +// //--------------------------------------------------------------------- +// +// io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt +// +// IOBUF(th.jd_5, io_jtag.TMS) +// PULLUP(th.jd_5) +// +// IOBUF(th.jd_4, io_jtag.TDI) +// PULLUP(th.jd_4) +// +// IOBUF(th.jd_0, io_jtag.TDO) +// +// // mimic putting a pullup on this line (part of reset vote) +// th.SRST_n := IOBUF(th.jd_6) +// PULLUP(th.jd_6) +// +// // jtag reset +// val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) +// io_jtag_reset := jtag_power_on_reset +// +// // debug reset +// th.dut_ndreset := io_ndreset +// +// //--------------------------------------------------------------------- +// // Assignment to package pins +// //--------------------------------------------------------------------- +// // Pins IO0-IO13 +// // +// // FTDI UART TX/RX are not connected to th.ck_io[0,1] +// // the way they are on Arduino boards. We copy outgoing +// // data to both places, switch 3 (sw[3]) determines whether +// // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) +// +// val iobuf_ck0 = Module(new IOBUF()) +// iobuf_ck0.io.I := io_gpio.pins(16).o.oval +// iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe +// attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX +// +// val iobuf_uart_txd = Module(new IOBUF()) +// iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval +// iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe +// attach(iobuf_uart_txd.io.IO, th.uart_txd_in) +// +// // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] +// val sw_3_in = IOBUF(th.sw_3) +// io_gpio.pins(16).i.ival := Mux(sw_3_in, +// iobuf_ck0.io.O & io_gpio.pins(16).o.ie, +// iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) +// +// IOBUF(th.uart_rxd_out, io_gpio.pins(17)) +// +// // Shield header row 0: PD2-PD7 +// IOBUF(th.ck_io(2), io_gpio.pins(18)) +// IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) +// IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) +// IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) +// IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) +// IOBUF(th.ck_io(7), io_gpio.pins(23)) +// +// // Header row 1: PB0-PB5 +// IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) +// IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) +// IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) +// IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) +// IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO +// IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK +// +// io_gpio.pins(6).i.ival := 0.U +// io_gpio.pins(7).i.ival := 0.U +// io_gpio.pins(8).i.ival := 0.U +// +// // Header row 3: A0-A5 (we don't support using them as analog inputs) +// // just treat them as regular digital GPIOs +// IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) +// IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) +// IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) +// IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA +// IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL +// +// // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty +// // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active +// IOBUF(th.led0_r, io_gpio.pins(1)) +// IOBUF(th.led0_g, io_gpio.pins(2)) +// IOBUF(th.led0_b, io_gpio.pins(3)) +// +// // Note that this is the one which is actually connected on the HiFive/Crazy88 +// // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active +// IOBUF(th.led1_r, io_gpio.pins(19)) +// IOBUF(th.led1_g, io_gpio.pins(21)) +// IOBUF(th.led1_b, io_gpio.pins(22)) +// +// // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active +// IOBUF(th.led2_r, io_gpio.pins(11)) +// IOBUF(th.led2_g, io_gpio.pins(12)) +// IOBUF(th.led2_b, io_gpio.pins(13)) +// +// // Only 19 out of 20 shield pins connected to GPIO pins +// // Shield pin A5 (pin 14) left unconnected +// // The buttons are connected to some extra GPIO pins not connected on the +// // HiFive1 board +// IOBUF(th.btn_0, io_gpio.pins(15)) +// IOBUF(th.btn_1, io_gpio.pins(30)) +// IOBUF(th.btn_2, io_gpio.pins(31)) +// +// val iobuf_btn_3 = Module(new IOBUF()) +// iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval +// iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe +// attach(th.btn_3, iobuf_btn_3.io.IO) +// io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie +// +// // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 +// IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX +// IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX +// +// // SPI2 pins mapped to 6 pin ICSP connector (standard on later +// // arduinos) These are connected to some extra GPIO pins not connected +// // on the HiFive1 board +// IOBUF(th.ck_ss, io_gpio.pins(26)) +// IOBUF(th.ck_mosi, io_gpio.pins(27)) +// IOBUF(th.ck_miso, io_gpio.pins(28)) +// IOBUF(th.ck_sck, io_gpio.pins(29)) +// +// // Use the LEDs for some more useful debugging things +// IOBUF(th.led_0, th.ck_rst) +// IOBUF(th.led_1, th.SRST_n) +// IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) +// IOBUF(th.led_3, io_gpio.pins(14)) +// +// //--------------------------------------------------------------------- +// // Unconnected inputs +// //--------------------------------------------------------------------- +// +// io_aon.erst_n.i.ival := ~th.reset_periph +// io_aon.lfextclk.i.ival := slow_clock +// io_aon.pmu.vddpaden.i.ival := 1.U +// } +// +// Nil +// } +// } +// +// Seq((Nil, Nil, Some(harnessFn))) +// } +//}) +// diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index ab087afa..feaa0484 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -23,20 +23,18 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} import chipyard.fpga.vcu118.bringup.{BringupGPIOs} -class WithChipyardBuildTop extends Config((site, here, up) => { - case DesignKey => {(p: Parameters) => new VCU118Platform()(p) } -}) +import chipyard.harness._ class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) - case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L)), - SPIParams(rAddress = BigInt(0x64004000L))) - case VCU118ShellPMOD => "SDIO" - case PeripheryI2CKey => List( - I2CParams(address = BigInt(0x64005000L))) +// case PeripherySPIKey => List( +// SPIParams(rAddress = BigInt(0x64001000L)), +// SPIParams(rAddress = BigInt(0x64004000L))) +// case VCU118ShellPMOD => "SDIO" +// case PeripheryI2CKey => List( +// I2CParams(address = BigInt(0x64005000L))) case PeripheryGPIOKey => { if (BringupGPIOs.width > 0) { require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) @@ -72,8 +70,18 @@ class SmallModifications extends Config((site, here, up) => { class FakeBringupConfig extends Config( + new WithBringupUART ++ + //new WithBringupSPI ++ + //new WithBringupI2C ++ + new WithBringupGPIO ++ + new chipyard.iobinders.WithUARTIOCells ++ + //new WithSPICells ++ + //new WithI2CCells ++ + new chipyard.iobinders.WithGPIOCells ++ + //new WithBringupDDR ++ new WithBringupPeripherals ++ - new WithChipyardBuildTop ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala deleted file mode 100644 index 342f7328..00000000 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ /dev/null @@ -1,81 +0,0 @@ -package chipyard.fpga.vcu118 - -import chisel3._ -import chisel3.experimental.{Analog, IO, DataMirror} - -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.tilelink.{TLBundle} - -import chipyard.{BuildSystem} - -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.gpio._ - -trait HasVCU118PlatformIO { - val io_uart: Seq[UARTPortIO] - val io_spi: Seq[SPIPortIO] - val io_i2c: Seq[I2CPort] - val io_gpio: Seq[GPIOPortIO] - val io_tl_mem: HeterogeneousBag[TLBundle] -} - -class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope with BindingScope { - - val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") - - // add MMC to the DTS - lazySystem match { case lsys: HasPeripherySPI => - val mmcDev = new MMCDevice(lsys.tlspi.head.device, 1) - ResourceBinding { - Resource(mmcDev, "reg").bind(ResourceAddress(0)) - } - } - - override lazy val module = new VCU118PlatformModule(this) -} - -class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) - with HasVCU118PlatformIO { - - val io_uart = _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => - val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex.map { case (p, i) => IO(new UARTPortIO(p)).suggestName(s"uart_$i") } - (io_uart_pins_temp zip sys.uart).map { case (io, sysio) => - io <> sysio - } - io_uart_pins_temp - } - - val io_spi = _outer.lazySystem.module match { case sys: HasPeripherySPIModuleImp => - val io_spi_pins_temp = p(PeripherySPIKey).zipWithIndex.map { case (p, i) => IO(new SPIPortIO(p)).suggestName(s"spi_$i") } - (io_spi_pins_temp zip sys.spi).map { case (io, sysio) => - io <> sysio - } - io_spi_pins_temp - } - - val io_i2c = _outer.lazySystem.module match { case sys: HasPeripheryI2CModuleImp => - val io_i2c_pins_temp = p(PeripheryI2CKey).zipWithIndex.map { case (p, i) => IO(new I2CPort).suggestName(s"i2c_$i") } - (io_i2c_pins_temp zip sys.i2c).map { case (io, sysio) => - io <> sysio - } - io_i2c_pins_temp - } - - val io_gpio = _outer.lazySystem.module match { case sys: HasPeripheryGPIOModuleImp => - val io_gpio_pins_temp = p(PeripheryGPIOKey).zipWithIndex.map { case (p, i) => IO(new GPIOPortIO(p)).suggestName(s"gpio_$i") } - (io_gpio_pins_temp zip sys.gpio).map { case (io, sysio) => - io <> sysio - } - io_gpio_pins_temp - } - - val io_tl_mem = _outer.lazySystem match { case sys: chipyard.CanHaveMasterTLMemPort => - val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](sys.mem_tl)).suggestName("tl_slave") - io_tl_mem_pins_temp <> sys.mem_tl - io_tl_mem_pins_temp - } -} diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 4275f68d..d371aced 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -19,10 +19,12 @@ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} +import chipyard.harness._ +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions} case object DUTFrequencyKey extends Field[Double](100.0) -class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell { +class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell with HasHarnessSignalReferences { def dp = designParameters @@ -58,122 +60,20 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends Chipyar } } - /*** UART ***/ - require(dp(PeripheryUARTKey).size == 2) + lazy val harnessClock = InModuleBody { + dutClock.in.head._1.clock + }.getWrappedValue + lazy val harnessReset = InModuleBody { + WireInit(dutClock.in.head._1.reset) + }.getWrappedValue + lazy val dutReset = harnessReset + lazy val success = InModuleBody { false.B }.getWrappedValue - // 1st UART goes to the VCU118 dedicated UART - - // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design - // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) - dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_uart_bb.bundle <> dutMod.io_uart.head + topDesign match { case d: HasTestHarnessFunctions => + InModuleBody { + d.harnessFunctions.foreach(_(this)) } + ApplyHarnessBinders(this, d.lazySystem, d.portMap.toMap) } - - // 2nd UART goes to the FMC UART - - val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) - - val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) - dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_uart_bb_2.bundle <> dutMod.io_uart.last - } - } - - /*** SPI ***/ - require(dp(PeripherySPIKey).size == 2) - - // 1st SPI goes to the VCU118 SDIO port - - val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) - val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_spi_bb.bundle <> dutMod.io_spi.head - } - } - - // TODO: No access to the TLSPI node... - //val mmcDev = new MMCDevice(sdio_placed.device, 1) - //ResourceBinding { - // Resource(mmcDev, "reg").bind(ResourceAddress(0)) - //} - - // 2nd SPI goes to the ADI port - - val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) - - val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) - val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_spi_bb_2.bundle <> dutMod.io_spi.last - } - } - - // TODO: No access to the TLSPI node... - //val adiDev = new chipyard.fpga.vcu118.bringup.ADISPIDevice(adi_placed.device, 1) - //ResourceBinding { - // Resource(adiDev, "reg").bind(ResourceAddress(0)) - //} - - /*** I2C ***/ - require(dp(PeripheryI2CKey).size == 1) - - val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) - - val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) - dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_i2c_bb.bundle <> dutMod.io_i2c.head - } - } - - /*** GPIO ***/ - val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { - val maxGPIOSupport = 32 - val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) - Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) - }) - - val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } - (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => - placer.place(GPIODesignInput(params, io_gpio_bb(i))) - } - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - (io_gpio_bb zip dutMod.io_gpio).map { case (bb_io, dut_io) => - bb_io.bundle <> dut_io - } - } - } - - /*** Experimental DDR ***/ - - val ddrWrangler = LazyModule(new ResetWrangler) - val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL)) - - // connect 1 mem. channel to the FPGA DDR - val inParams = topDesign match { case td: VCU118Platform => - td.lazySystem match { case lsys: chipyard.CanHaveMasterTLMemPort => - lsys.memTLNode.edges.in(0) - } - } - val ddrClient = TLClientNode(Seq(inParams.master)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - val bundles = ddrClient.out.map(_._1) - val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType))) - bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } - ddrClientBundle <> dutMod.io_tl_mem - } - } - ddrPlaced.overlayOutput.ddr := ddrClient } diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 1cef2180..b86b6b07 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -7,7 +7,7 @@ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope} import freechips.rocketchip.util.{ResetCatchAndSync} import chipyard.iobinders._ @@ -23,7 +23,7 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) * drive clock and reset generation */ -class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunctions { +class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunctions with BindingScope { // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) val iocells = ArrayBuffer.empty[IOCell] From 949d60597fb4d930e985cdc4c935683649fe11d4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 14 Oct 2020 14:50:38 -0700 Subject: [PATCH 030/157] Revert "Support evaluation of HarnessBinders in LazyModule context" This reverts commit 9c298eedfe539e05aa409d4b60595f5a0ab2ada1. --- .../src/main/scala/HarnessBinders.scala | 75 +++++++++---------- .../chipyard/src/main/scala/IOBinders.scala | 36 +++++---- .../chipyard/src/main/scala/TestHarness.scala | 2 +- .../src/main/scala/BridgeBinders.scala | 16 ++-- 4 files changed, 68 insertions(+), 61 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 6f7d2dd8..e5cfacfb 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -1,7 +1,7 @@ package chipyard.harness import chisel3._ -import chisel3.experimental.{Analog, BaseModule} +import chisel3.experimental.{Analog} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} @@ -33,41 +33,40 @@ case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalRefer object ApplyHarnessBinders { - def apply(th: HasHarnessSignalReferences, sys: LazyModule, portMap: Map[String, Seq[Data]])(implicit p: Parameters) = { + def apply(th: HasHarnessSignalReferences, sys: LazyModule, map: Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]], portMap: Map[String, Seq[Data]]) = { val pm = portMap.withDefaultValue(Nil) - p(HarnessBinders).map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } + map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) } } } -class HarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](composer: ((T, S, Seq[U]) => Seq[Any]) => (T, S, Seq[U]) => Seq[Any])(implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) extends Config((site, here, up) => { +class OverrideHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { - val pts = ports.collect({case p: U => p}) + val pts = ports.collect({case p: S => p}) require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") - val upfn = up(HarnessBinders, site)(tag.runtimeClass.toString) - th match { - case th: S => - t match { - case system: T => composer(upfn)(system, th, pts) - case _ => Nil - } + t match { + case system: T => fn(system, th, pts) case _ => Nil } }) ) }) -class OverrideHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) - (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) - extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => fn) - -class ComposeHarnessBinder[T, S <: HasHarnessSignalReferences, U <: Data](fn: => (T, S, Seq[U]) => Seq[Any]) - (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U]) - extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Seq[Any]) => (t, th, p) => upfn(t, th, p) ++ fn(t, th, p)) - +class ComposeHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T], ptag: ClassTag[S]) extends Config((site, here, up) => { + case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString -> + ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => { + val pts = ports.collect({case p: S => p}) + require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${ptag}") + t match { + case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, pts) ++ fn(system, th, pts) + case _ => Nil + } + }) + ) +}) class WithGPIOTiedOff extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Analog]) => { + (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Analog]) => { ports.foreach { _ <> AnalogConst(0) } Nil } @@ -75,7 +74,7 @@ class WithGPIOTiedOff extends OverrideHarnessBinder({ // DOC include start: WithUARTAdapter class WithUARTAdapter extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { UARTAdapter.connect(ports)(system.p) Nil } @@ -83,14 +82,14 @@ class WithUARTAdapter extends OverrideHarnessBinder({ // DOC include end: WithUARTAdapter class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({ - (system: HasPeripherySPIFlashModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { + (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => { SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p) Nil } }) class WithSimBlockDevice extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => SimBlockDevice.connect(b.clock, th.harnessReset.asBool, Some(b.bits)) } Nil @@ -98,7 +97,7 @@ class WithSimBlockDevice extends OverrideHarnessBinder({ }) class WithBlockDeviceModel extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => withClockAndReset(b.clock, th.harnessReset) { BlockDeviceModel.connect(Some(b.bits)) } } Nil @@ -106,7 +105,7 @@ class WithBlockDeviceModel extends OverrideHarnessBinder({ }) class WithLoopbackNIC extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => withClockAndReset(n.clock, th.harnessReset) { @@ -118,7 +117,7 @@ class WithLoopbackNIC extends OverrideHarnessBinder({ }) class WithSimNetwork extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.harnessReset.asBool) } Nil @@ -126,7 +125,7 @@ class WithSimNetwork extends OverrideHarnessBinder({ }) class WithSimAXIMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p)) @@ -140,7 +139,7 @@ class WithSimAXIMem extends OverrideHarnessBinder({ }) class WithBlackBoxSimMem extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val memSize = p(ExtMem).get.master.size @@ -155,7 +154,7 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ }) class WithSimAXIMMIO extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MMIOPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.mmioAXI4Node.edges.in).map { case (port, edge) => val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p)) @@ -169,21 +168,21 @@ class WithSimAXIMMIO extends OverrideHarnessBinder({ }) class WithTieOffInterrupts extends OverrideHarnessBinder({ - (system: HasExtInterruptsModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UInt]) => { + (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[UInt]) => { ports.foreach { _ := 0.U } Nil } }) class WithTieOffL2FBusAXI extends OverrideHarnessBinder({ - (system: CanHaveSlaveAXI4Port, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { ports.foreach({ p => p := DontCare; p.bits.tieoff() }) Nil } }) class WithSimDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { case d: ClockedDMIIO => val dtm_success = WireInit(false.B) @@ -199,7 +198,7 @@ class WithSimDebug extends OverrideHarnessBinder({ }) class WithTiedOffDebug extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { + (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => { ports.map { case j: JTAGIO => j.TCK := true.B.asClock @@ -225,7 +224,7 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -235,7 +234,7 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ }) class WithSimSerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -246,14 +245,14 @@ class WithSimSerial extends OverrideHarnessBinder({ }) class WithTraceGenSuccess extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Bool]) => { + (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { ports.map { p => when (p) { th.success := true.B } } Nil } }) class WithSimDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } Nil } diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 5259cbb1..4a31e2c0 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -72,33 +72,41 @@ object GetSystemParameters { } } -class IOBinder[T, S <: Data](composer: (Any => (Seq[Data], Seq[IOCell])) => T => (Seq[Data], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class IOBinder(f: (View, View, View) => PartialFunction[Any, Any]) extends Config(f) + +// This macro overrides previous matches on some Top mixin. This is useful for +// binders which drive IO, since those typically cannot be composed +class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((t: Any) => { - val upfn = up(IOBinders, site)(tag.runtimeClass.toString) t match { - case system: T => composer(upfn)(system) + case system: T => + val (ports, cells) = fn(system) + (ports, cells) case _ => (Nil, Nil) } }) ) }) - -// This macro overrides previous matches on some Top mixin. This is useful for -// binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder[T, S](upfn => fn) - - // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder[T, S](upfn => t => { - val r = upfn(t) - val h = fn(t) - (r._1 ++ h._1, r._2 ++ h._2) +class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { + case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> + ((t: Any) => { + t match { + case system: T => + val r = up(IOBinders, site)(tag.runtimeClass.toString)(system) + val h = fn(system) + val ports = r._1 ++ h._1 + val cells = r._2 ++ h._2 + (ports, cells) + case _ => (Nil, Nil) + } + }) + ) }) - object BoreHelper { def apply(name: String, source: Clock): Clock = { val clock_io = IO(Output(Clock())).suggestName(name) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 64b889e3..2faff565 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -44,7 +44,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, d.portMap.toMap) + ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) } } diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 2fa49fc3..444c7b33 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -66,7 +66,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { }) class WithSerialBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { port => implicit val p = GetSystemParameters(system) val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) @@ -77,7 +77,7 @@ class WithSerialBridge extends OverrideHarnessBinder({ }) class WithNICBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNIC, th: FireSim, ports: Seq[ClockedIO[NICIOvonly]]) => { + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { val p: Parameters = GetSystemParameters(system) ports.map { n => NICBridge(n.clock, n.bits)(p) } Nil @@ -85,12 +85,12 @@ class WithNICBridge extends OverrideHarnessBinder({ }) class WithUARTBridge extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) => + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDevice, th: FireSim, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { implicit val p: Parameters = GetSystemParameters(system) ports.map { b => BlockDevBridge(b.clock, b.bits, th.harnessReset.toBool) } Nil @@ -98,7 +98,7 @@ class WithBlockDeviceBridge extends OverrideHarnessBinder({ }) class WithFASEDBridge extends OverrideHarnessBinder({ - (system: CanHaveMasterAXI4MemPort, th: FireSim, ports: Seq[ClockedIO[AXI4Bundle]]) => { + (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => { implicit val p: Parameters = GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (axi4, edge) => val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth, @@ -118,20 +118,20 @@ class WithFASEDBridge extends OverrideHarnessBinder({ }) class WithTracerVBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => { + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => { ports.map { p => p.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p)) } Nil } }) class WithDromajoBridge extends ComposeHarnessBinder({ - (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => + (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => ports.map { p => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil }) class WithTraceGenBridge extends OverrideHarnessBinder({ - (system: TraceGenSystemModuleImp, th: FireSim, ports: Seq[Bool]) => + (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => ports.map { p => GroundTestBridge(th.harnessClock, p)(system.p) }; Nil }) From dcac9b79dfb222218023372a0a335647466ec310 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 14 Oct 2020 16:15:10 -0700 Subject: [PATCH 031/157] Basic working with UART --- fpga/Makefile | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 6 +- fpga/src/main/scala/vcu118/TestHarness.scala | 116 +++++++++++++++---- 3 files changed, 98 insertions(+), 26 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index f3f6308b..643e0c67 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -26,7 +26,7 @@ CONFIG := FakeBringupConfig CONFIG_PACKAGE := chipyard.fpga.vcu118 GENERATOR_PACKAGE := chipyard TB := none # unused -TOP := VCU118Platform +TOP := ChipTop # setup the board to use BOARD ?= arty diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index feaa0484..efb2c551 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -73,11 +73,11 @@ class FakeBringupConfig extends Config( new WithBringupUART ++ //new WithBringupSPI ++ //new WithBringupI2C ++ - new WithBringupGPIO ++ - new chipyard.iobinders.WithUARTIOCells ++ + //new WithBringupGPIO ++ + new WithUARTIOPassthrough ++ //new WithSPICells ++ //new WithI2CCells ++ - new chipyard.iobinders.WithGPIOCells ++ + //new chipyard.iobinders.WithGPIOCells ++ //new WithBringupDDR ++ new WithBringupPeripherals ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index d371aced..ea8d4b0c 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -20,14 +20,31 @@ import sifive.blocks.devices.gpio._ import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} import chipyard.harness._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop} case object DUTFrequencyKey extends Field[Double](100.0) -class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell with HasHarnessSignalReferences { +class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { def dp = designParameters + val pmod_is_sdio = p(VCU118ShellPMOD) == "SDIO" + val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52") + + // Order matters; ddr depends on sys_clock + val uart = Overlay(UARTOverlayKey, new UARTVCU118ShellPlacer(this, UARTShellInput())) + val sdio = if (pmod_is_sdio) Some(Overlay(SPIOverlayKey, new SDIOVCU118ShellPlacer(this, SPIShellInput()))) else None + val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVCU118ShellPlacer(this, JTAGDebugShellInput(location = jtag_location))) + val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVCU118ShellPlacer(this, cJTAGDebugShellInput())) + val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput())) + val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput())) + val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput())) + + val topDesign = LazyModule(p(BuildTop)(dp)) + + // place all clocks in the shell + dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } + /*** Connect/Generate clocks ***/ // connect to the PLL that will generate multiple clocks @@ -44,13 +61,13 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends Chipyar val dutGroup = ClockGroup() dutClock := dutWrangler.node := dutGroup := harnessSysPLL - InModuleBody { - topDesign.module match { case td: LazyModuleImp => { - td.clock := dutClock.in.head._1.clock - td.reset := dutClock.in.head._1.reset - } - } - } + //InModuleBody { + // topDesign.module match { case td: LazyModuleImp => { + // td.clock := dutClock.in.head._1.clock + // td.reset := dutClock.in.head._1.reset + // } + // } + //} // connect ref clock to dummy sink node ref_clock.get() match { @@ -60,20 +77,75 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends Chipyar } } - lazy val harnessClock = InModuleBody { - dutClock.in.head._1.clock - }.getWrappedValue - lazy val harnessReset = InModuleBody { - WireInit(dutClock.in.head._1.reset) - }.getWrappedValue - lazy val dutReset = harnessReset - lazy val success = InModuleBody { false.B }.getWrappedValue + // extra overlays - topDesign match { case d: HasTestHarnessFunctions => - InModuleBody { - d.harnessFunctions.foreach(_(this)) - } - ApplyHarnessBinders(this, d.lazySystem, d.portMap.toMap) + /*** UART ***/ + + // 1st UART goes to the VCU118 dedicated UART + + // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design + // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) + dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + + // 2nd UART goes to the FMC UART + + val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) + + val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) + dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + + /*** GPIO ***/ + + val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { + val maxGPIOSupport = 32 + val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) + Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) + }) + + val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } + (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => + placer.place(GPIODesignInput(params, io_gpio_bb(i))) } + + // module implementation + override lazy val module = new VCU118FPGATestHarnessImp(this) } +class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { + + val outer = _outer + + val reset = IO(Input(Bool())) + _outer.xdc.addPackagePin(reset, "L19") + _outer.xdc.addIOStandard(reset, "LVCMOS12") + + val reset_ibuf = Module(new IBUF) + reset_ibuf.io.I := reset + + val sysclk: Clock = _outer.sys_clock.get() match { + case Some(x: SysClockVCU118PlacedOverlay) => x.clock + } + + val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) + _outer.sdc.addAsyncPath(Seq(powerOnReset)) + + val ereset: Bool = _outer.chiplink.get() match { + case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n + case _ => false.B + } + + _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset) + + // cy stuff + val harnessClock = _outer.dutClock.in.head._1.clock + val harnessReset = WireInit(_outer.dutClock.in.head._1.reset) + val dutReset = harnessReset + val success = false.B + + // harness binders are non-lazy + _outer.topDesign match { case d: HasTestHarnessFunctions => + d.harnessFunctions.foreach(_(this)) + ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } +} From 7f387a254b25951f9038a93bfab10833bdb6c5ee Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 14 Oct 2020 23:09:49 -0700 Subject: [PATCH 032/157] Working up until the MMC attachment --- fpga/Makefile | 8 +- .../vcu118/{ => bringup}/BringupGPIOs.scala | 0 .../scala/vcu118/{ => bringup}/Configs.scala | 31 +++--- .../vcu118/{ => bringup}/CustomOverlays.scala | 0 .../scala/vcu118/bringup/HarnessBinders.scala | 94 +++++++++++++++++++ .../main/scala/vcu118/bringup/IOBinders.scala | 90 ++++++++++++++++++ .../vcu118/{ => bringup}/TestHarness.scala | 50 ++++++++-- 7 files changed, 248 insertions(+), 25 deletions(-) rename fpga/src/main/scala/vcu118/{ => bringup}/BringupGPIOs.scala (100%) rename fpga/src/main/scala/vcu118/{ => bringup}/Configs.scala (85%) rename fpga/src/main/scala/vcu118/{ => bringup}/CustomOverlays.scala (100%) create mode 100644 fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala create mode 100644 fpga/src/main/scala/vcu118/bringup/IOBinders.scala rename fpga/src/main/scala/vcu118/{ => bringup}/TestHarness.scala (74%) diff --git a/fpga/Makefile b/fpga/Makefile index 643e0c67..e6bc426a 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -19,11 +19,11 @@ include $(base_dir)/variables.mk # default variables to build the arty example SUB_PROJECT := fpga SBT_PROJECT := fpga_platforms -MODEL := VCU118FPGATestHarness -VLOG_MODEL := VCU118FPGATestHarness -MODEL_PACKAGE := chipyard.fpga.vcu118 +MODEL := BringupVCU118FPGATestHarness +VLOG_MODEL := BringupVCU118FPGATestHarness +MODEL_PACKAGE := chipyard.fpga.vcu118.bringup CONFIG := FakeBringupConfig -CONFIG_PACKAGE := chipyard.fpga.vcu118 +CONFIG_PACKAGE := chipyard.fpga.vcu118.bringup GENERATOR_PACKAGE := chipyard TB := none # unused TOP := ChipTop diff --git a/fpga/src/main/scala/vcu118/BringupGPIOs.scala b/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala similarity index 100% rename from fpga/src/main/scala/vcu118/BringupGPIOs.scala rename to fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala similarity index 85% rename from fpga/src/main/scala/vcu118/Configs.scala rename to fpga/src/main/scala/vcu118/bringup/Configs.scala index efb2c551..9a34b198 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -1,5 +1,4 @@ -// See LICENSE for license details. -package chipyard.fpga.vcu118 +package chipyard.fpga.vcu118.bringup import math.min @@ -29,12 +28,12 @@ class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) -// case PeripherySPIKey => List( -// SPIParams(rAddress = BigInt(0x64001000L)), -// SPIParams(rAddress = BigInt(0x64004000L))) -// case VCU118ShellPMOD => "SDIO" -// case PeripheryI2CKey => List( -// I2CParams(address = BigInt(0x64005000L))) + case PeripherySPIKey => List( + SPIParams(rAddress = BigInt(0x64001000L)), + SPIParams(rAddress = BigInt(0x64004000L))) + case VCU118ShellPMOD => "SDIO" + case PeripheryI2CKey => List( + I2CParams(address = BigInt(0x64005000L))) case PeripheryGPIOKey => { if (BringupGPIOs.width > 0) { require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) @@ -71,14 +70,16 @@ class SmallModifications extends Config((site, here, up) => { class FakeBringupConfig extends Config( new WithBringupUART ++ - //new WithBringupSPI ++ - //new WithBringupI2C ++ - //new WithBringupGPIO ++ + new WithBringupSPI ++ + new WithBringupI2C ++ + new WithBringupGPIO ++ + new WithBringupDDR ++ new WithUARTIOPassthrough ++ - //new WithSPICells ++ - //new WithI2CCells ++ - //new chipyard.iobinders.WithGPIOCells ++ - //new WithBringupDDR ++ + new WithSPIIOPassthrough ++ + //new WithMMCSPIDTS ++ + new WithI2CIOPassthrough ++ + new WithGPIOIOPassthrough ++ + new WithTLIOPassthrough ++ new WithBringupPeripherals ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala similarity index 100% rename from fpga/src/main/scala/vcu118/CustomOverlays.scala rename to fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala new file mode 100644 index 00000000..efe805cd --- /dev/null +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -0,0 +1,94 @@ +package chipyard.fpga.vcu118.bringup + +import chisel3._ +import chisel3.experimental.{Analog, IO} + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem} +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util._ + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.clocks._ + +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.gpio._ + +import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} +import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} +import chipyard.harness._ + +/*** UART ***/ +class WithBringupUART extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + require(ports.size == 2) + + vcu118th.outer.io_uart_bb.bundle <> ports.head + vcu118th.outer.io_uart_bb_2.bundle <> ports.last + } } + + Nil + } +}) + +/*** SPI ***/ +class WithBringupSPI extends OverrideHarnessBinder({ + (system: HasPeripherySPIModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + require(ports.size == 2) + + vcu118th.outer.io_spi_bb.bundle <> ports.head + vcu118th.outer.io_spi_bb_2.bundle <> ports.last + } } + + Nil + } +}) + +/*** I2C ***/ +class WithBringupI2C extends OverrideHarnessBinder({ + (system: HasPeripheryI2CModuleImp, th: HasHarnessSignalReferences, ports: Seq[I2CPort]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + require(ports.size == 1) + + vcu118th.outer.io_i2c_bb.bundle <> ports.head + } } + + Nil + } +}) + +/*** GPIO ***/ +class WithBringupGPIO extends OverrideHarnessBinder({ + (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + (vcu118th.outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) => + bb_io.bundle <> dut_io + } + } } + + Nil + } +}) + +/*** Experimental DDR ***/ +class WithBringupDDR extends OverrideHarnessBinder({ + (system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + require(ports.size == 1) + + val bundles = vcu118th.outer.ddrClient.out.map(_._1) + val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType))) + bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } + ddrClientBundle <> ports.head + } } + + Nil + } +}) diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala new file mode 100644 index 00000000..d10f5500 --- /dev/null +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -0,0 +1,90 @@ +package chipyard.fpga.vcu118.bringup + +import chisel3._ +import chisel3.util.experimental.{BoringUtils} +import chisel3.experimental.{Analog, IO, DataMirror} + +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress} +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.jtag.{JTAGIO} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system.{SimAXIMem} +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} +import freechips.rocketchip.util._ +import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} +import freechips.rocketchip.tilelink.{TLBundle} + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ +import tracegen.{TraceGenSystemModuleImp} + +import barstools.iocell.chisel._ + +import testchipip._ +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} + +import chipyard.{GlobalResetSchemeKey, CanHaveMasterTLMemPort} +import chipyard.iobinders.{OverrideIOBinder} + +class WithUARTIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryUARTModuleImp) => { + val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") } + (io_uart_pins_temp zip system.uart).map { case (io, sysio) => + io <> sysio + } + (io_uart_pins_temp, Nil) + } +}) + +class WithGPIOIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryGPIOModuleImp) => { + val io_gpio_pins_temp = system.gpio.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"gpio_$i") } + (io_gpio_pins_temp zip system.gpio).map { case (io, sysio) => + io <> sysio + } + (io_gpio_pins_temp, Nil) + } +}) + +class WithSPIIOPassthrough extends OverrideIOBinder({ + (system: HasPeripherySPIModuleImp) => { + val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } + (io_spi_pins_temp zip system.spi).map { case (io, sysio) => + io <> sysio + } + (io_spi_pins_temp, Nil) + } +}) + +//class WithMMCSPIDTS extends OverrideIOBinder({ +// (system: HasPeripherySPI) => { +// +// val mmcDev = new MMCDevice(system.tlspi.head.device, 1) +// ResourceBinding { +// Resource(mmcDev, "reg").bind(ResourceAddress(0)) +// } +// +// (Nil, Nil) +// } +//}) + +class WithI2CIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryI2CModuleImp) => { + val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } + (io_i2c_pins_temp zip system.i2c).map { case (io, sysio) => + io <> sysio + } + (io_i2c_pins_temp, Nil) + } +}) + +class WithTLIOPassthrough extends OverrideIOBinder({ + (system: CanHaveMasterTLMemPort) => { + val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") + io_tl_mem_pins_temp <> system.mem_tl + (Seq(io_tl_mem_pins_temp), Nil) + } +}) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala similarity index 74% rename from fpga/src/main/scala/vcu118/TestHarness.scala rename to fpga/src/main/scala/vcu118/bringup/TestHarness.scala index ea8d4b0c..28e42e3c 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.vcu118 +package chipyard.fpga.vcu118.bringup import chisel3._ import chisel3.experimental.{Analog, IO} @@ -18,13 +18,12 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} import chipyard.harness._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} case object DUTFrequencyKey extends Field[Double](100.0) -class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { +class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { def dp = designParameters @@ -81,6 +80,8 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S /*** UART ***/ + require(dp(PeripheryUARTKey).size == 2) + // 1st UART goes to the VCU118 dedicated UART // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design @@ -95,6 +96,29 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + /*** SPI ***/ + + require(dp(PeripherySPIKey).size == 2) + + // 1st SPI goes to the VCU118 SDIO port + + val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) + val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) + + // 2nd SPI goes to the ADI port + + val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) + + val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) + val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2)) + + /*** I2C ***/ + + val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) + + val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) + dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) + /*** GPIO ***/ val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { @@ -108,11 +132,25 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S placer.place(GPIODesignInput(params, io_gpio_bb(i))) } + /*** DDR ***/ + + val ddrWrangler = LazyModule(new ResetWrangler) + val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL)) + + // connect 1 mem. channel to the FPGA DDR + val inParams = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: CanHaveMasterTLMemPort => + lsys.memTLNode.edges.in(0) + } + } + val ddrClient = TLClientNode(Seq(inParams.master)) + ddrPlaced.overlayOutput.ddr := ddrClient + // module implementation - override lazy val module = new VCU118FPGATestHarnessImp(this) + override lazy val module = new BringupVCU118FPGATestHarnessImp(this) } -class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { +class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { val outer = _outer From 9ba4918cb863294844a3b16cddede8b4a7d752dd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 15 Oct 2020 11:46:42 -0700 Subject: [PATCH 033/157] Inject MMCDevice into TLSPI Node --- fpga/src/main/scala/vcu118/bringup/Configs.scala | 10 +++++++--- fpga/src/main/scala/vcu118/bringup/IOBinders.scala | 12 ------------ generators/sifive-blocks | 2 +- 3 files changed, 8 insertions(+), 16 deletions(-) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 9a34b198..f0dd91cc 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -6,7 +6,7 @@ import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ @@ -20,7 +20,6 @@ import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} -import chipyard.fpga.vcu118.bringup.{BringupGPIOs} import chipyard.harness._ @@ -29,7 +28,12 @@ class WithBringupPeripherals extends Config((site, here, up) => { UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L)), + SPIParams(rAddress = BigInt(0x64001000L), + injectFunc = Some((spi: TLSPI) => { + ResourceBinding { + Resource(new MMCDevice(spi.device, 1), "reg").bind(ResourceAddress(0)) + } + })), SPIParams(rAddress = BigInt(0x64004000L))) case VCU118ShellPMOD => "SDIO" case PeripheryI2CKey => List( diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index d10f5500..ece212bb 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -59,18 +59,6 @@ class WithSPIIOPassthrough extends OverrideIOBinder({ } }) -//class WithMMCSPIDTS extends OverrideIOBinder({ -// (system: HasPeripherySPI) => { -// -// val mmcDev = new MMCDevice(system.tlspi.head.device, 1) -// ResourceBinding { -// Resource(mmcDev, "reg").bind(ResourceAddress(0)) -// } -// -// (Nil, Nil) -// } -//}) - class WithI2CIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryI2CModuleImp) => { val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 413e0a88..ed9f63f9 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 413e0a88a4e48b1966b9444d613a7f3a776e65aa +Subproject commit ed9f63f9f5b9209c9e5ef2adfd063d6669691d79 From dd358f45ab7e3e85aab41cbef04710a056a89b3e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 19 Oct 2020 11:29:25 -0700 Subject: [PATCH 034/157] UART Working... Bumped to newer fpga-shells --- fpga/Makefile | 2 +- fpga/fpga-shells | 2 +- .../main/scala/vcu118/bringup/Configs.scala | 24 ++++++++++++------- .../scala/vcu118/bringup/CustomOverlays.scala | 3 +-- .../scala/vcu118/bringup/TestHarness.scala | 3 +++ generators/sifive-blocks | 2 +- 6 files changed, 23 insertions(+), 13 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index e6bc426a..b984431c 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -29,7 +29,7 @@ TB := none # unused TOP := ChipTop # setup the board to use -BOARD ?= arty +BOARD ?= vcu118 .PHONY: default default: $(mcs) diff --git a/fpga/fpga-shells b/fpga/fpga-shells index e8e7f8a3..89a5efec 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit e8e7f8a321ebde213ebc79db06422278d9aa477f +Subproject commit 89a5efec011ebc21b9455923501df70783161cb8 diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index f0dd91cc..8db731ed 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -1,6 +1,7 @@ package chipyard.fpga.vcu118.bringup import math.min +import sys.process._ import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -54,6 +55,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { }) class SmallModifications extends Config((site, here, up) => { + case DebugModuleKey => None // disable debug module case SystemBusKey => up(SystemBusKey).copy( errorDevice = Some(DevNullParams( Seq(AddressSet(0x3000, 0xfff)), @@ -61,18 +63,24 @@ class SmallModifications extends Config((site, here, up) => { maxTransfer=128, region = RegionType.TRACKED))) case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = - Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt), + Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt)) + case ControlBusKey => up(ControlBusKey, site).copy( errorDevice = None) case DTSTimebase => BigInt(1000000) - case JtagDTMKey => new JtagDTMConfig( - idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai). - idcodePartNum = 0x000, // Decided to simplify. - idcodeManufId = 0x489, // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses. - debugIdleCycles = 5) // Reasonable guess for synchronization }) +class WithBootROM extends Config((site, here, up) => { + case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => + // invoke makefile for sdboot + val freqMHz = site(DUTFrequencyKey).toInt * 1000000 + val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin" + require (make.! == 0, "Failed to build bootrom") + p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") + } +}) class FakeBringupConfig extends Config( + new SmallModifications ++ new WithBringupUART ++ new WithBringupSPI ++ new WithBringupI2C ++ @@ -80,14 +88,14 @@ class FakeBringupConfig extends Config( new WithBringupDDR ++ new WithUARTIOPassthrough ++ new WithSPIIOPassthrough ++ - //new WithMMCSPIDTS ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ new WithTLIOPassthrough ++ new WithBringupPeripherals ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ - new chipyard.config.WithBootROM ++ + new WithBootROM ++ // use local bootrom new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 2c438a34..fdbbb919 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -138,8 +138,7 @@ class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, io) => { shell.xdc.addPackagePin(io, pin) shell.xdc.addIOStandard(io, iostd) - // TODO: no drive strength found - //if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } + if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } } } } } } diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 28e42e3c..28c3ae14 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -181,6 +181,9 @@ class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) exte val dutReset = harnessReset val success = false.B + childClock := harnessClock + childReset := harnessReset + // harness binders are non-lazy _outer.topDesign match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) diff --git a/generators/sifive-blocks b/generators/sifive-blocks index ed9f63f9..c160544e 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit ed9f63f9f5b9209c9e5ef2adfd063d6669691d79 +Subproject commit c160544e74db4f33d51f23c8a41c07a1ec16b7b7 From db73cab164b063da299bfcabba6c6d99f91277fb Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 20 Oct 2020 21:20:11 -0700 Subject: [PATCH 035/157] Add BootROM | Fix ResetWrangler for DDR | Add scripts --- fpga/.gitignore | 4 +- fpga/Makefile | 10 + fpga/scripts/run_impl_bitstream.tcl | 45 ++++ fpga/scripts/write_mmi.tcl | 75 ++++++ .../main/resources/vcu118/sdboot/.gitignore | 1 + .../src/main/resources/vcu118/sdboot/Makefile | 39 +++ .../src/main/resources/vcu118/sdboot/common.h | 9 + fpga/src/main/resources/vcu118/sdboot/head.S | 20 ++ .../resources/vcu118/sdboot/include/bits.h | 36 +++ .../resources/vcu118/sdboot/include/const.h | 18 ++ .../vcu118/sdboot/include/devices/clint.h | 14 ++ .../vcu118/sdboot/include/devices/gpio.h | 24 ++ .../vcu118/sdboot/include/devices/plic.h | 31 +++ .../vcu118/sdboot/include/devices/spi.h | 79 ++++++ .../vcu118/sdboot/include/devices/uart.h | 28 +++ .../vcu118/sdboot/include/platform.h | 108 ++++++++ .../sdboot/include/riscv_test_defaults.h | 81 ++++++ .../vcu118/sdboot/include/sections.h | 17 ++ .../resources/vcu118/sdboot/include/smp.h | 142 +++++++++++ .../main/resources/vcu118/sdboot/kprintf.c | 75 ++++++ .../main/resources/vcu118/sdboot/kprintf.h | 49 ++++ .../resources/vcu118/sdboot/linker/memory.lds | 5 + .../vcu118/sdboot/linker/sdboot.elf.lds | 79 ++++++ fpga/src/main/resources/vcu118/sdboot/sd.c | 236 ++++++++++++++++++ .../scala/vcu118/bringup/TestHarness.scala | 3 +- 25 files changed, 1223 insertions(+), 5 deletions(-) create mode 100644 fpga/scripts/run_impl_bitstream.tcl create mode 100644 fpga/scripts/write_mmi.tcl create mode 100644 fpga/src/main/resources/vcu118/sdboot/.gitignore create mode 100644 fpga/src/main/resources/vcu118/sdboot/Makefile create mode 100644 fpga/src/main/resources/vcu118/sdboot/common.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/head.S create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/bits.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/const.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/platform.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/sections.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/include/smp.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/kprintf.c create mode 100644 fpga/src/main/resources/vcu118/sdboot/kprintf.h create mode 100644 fpga/src/main/resources/vcu118/sdboot/linker/memory.lds create mode 100644 fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds create mode 100644 fpga/src/main/resources/vcu118/sdboot/sd.c diff --git a/fpga/.gitignore b/fpga/.gitignore index a0991ff4..814384f3 100644 --- a/fpga/.gitignore +++ b/fpga/.gitignore @@ -1,3 +1 @@ -* -!.gitignore -!Makefile +generated-src diff --git a/fpga/Makefile b/fpga/Makefile index b984431c..748a5029 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -76,6 +76,16 @@ $(BIT_FILE): $(synth_list_f) .PHONY: bit bit: $(BIT_FILE) +.PHONY: debug-bitstream +debug-bitstream: $(build_dir)/obj/post_synth.dcp + cd $(build_dir); vivado \ + -nojournal -mode batch \ + -source $(sim_dir)/scripts/run_impl_bitstream.tcl \ + -tclargs \ + $(build_dir)/obj/post_synth.dcp \ + xcvu9p-flga2104-2l-e \ + $(build_dir)/obj/debug_output + # Build .mcs MCS_FILE := $(build_dir)/obj/$(MODEL).mcs $(MCS_FILE): $(BIT_FILE) diff --git a/fpga/scripts/run_impl_bitstream.tcl b/fpga/scripts/run_impl_bitstream.tcl new file mode 100644 index 00000000..ec3828e8 --- /dev/null +++ b/fpga/scripts/run_impl_bitstream.tcl @@ -0,0 +1,45 @@ +#### Command line arguments to this script +# argv[0] = absolute path to post_synth checkpoint file +# argv[1] = part +# argv[2] = output directory + +set synth_checkpoint_file [lindex $argv 0] +set part [lindex $argv 1] +set output_dir [lindex $argv 2] + +# Set the project part to the part passed into this script +set_part ${part} + +# Create output directory if it doesn't exist +file mkdir ${output_dir} +file mkdir ${output_dir}/reports +file mkdir ${output_dir}/outputs + +# Load synthesis checkpoint +open_checkpoint ${synth_checkpoint_file} + +# Run implementation and save reports as needed +opt_design +place_design +phys_opt_design +write_checkpoint -force ${output_dir}/outputs/post_place +report_timing_summary -file ${output_dir}/reports/post_place_timing_summary.rpt +report_drc -file ${output_dir}/reports/post_place_drc.rpt + +route_design +write_checkpoint -force ${output_dir}/outputs/post_route +report_timing_summary -file ${output_dir}/reports/post_route_timing_summary.rpt +report_timing -sort_by group -max_paths 100 -path_type summary -file ${output_dir}/reports/post_route_timing.rpt +report_clock_utilization -file ${output_dir}/reports/post_route_clock_utilization.rpt +report_utilization -file ${output_dir}/reports/post_route_utilization.rpt +report_drc -file ${output_dir}/reports/post_route_drc.rpt +report_cdc -details -file ${output_dir}/reports/post_route_cdc.rpt +report_clock_interaction -file ${output_dir}/reports/post_route_clock_interaction.rpt +report_bus_skew -file ${output_dir}/reports/post_route_bus_skew.rpt +report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file ${output_dir}/reports/post_route_timing_violations.rpt + +write_verilog -force ${output_dir}/outputs/post_route.v +write_xdc -no_fixed_only -force ${output_dir}/outputs/post_route.xdc + +write_bitstream -force ${output_dir}/outputs/top.bit +write_debug_probes -force ${output_dir}/outputs/debug_nets.ltx diff --git a/fpga/scripts/write_mmi.tcl b/fpga/scripts/write_mmi.tcl new file mode 100644 index 00000000..e577dd2b --- /dev/null +++ b/fpga/scripts/write_mmi.tcl @@ -0,0 +1,75 @@ +proc write_mmi {filepath inst} { + current_instance + current_instance $inst + set chn [open $filepath w] + puts $chn "" + puts $chn "" + puts $chn "\t" + set brams [dict create] + foreach cell [get_cells -hierarchical -filter { PRIMITIVE_GROUP =~ BLOCKRAM }] { + set name [get_property RTL_RAM_NAME $cell] + dict update brams $name name { + dict lappend name cells $cell + dict set name size [get_property RTL_RAM_BITS $cell] + } + } + proc compare {a b} { + set a_addr [get_property bram_addr_begin $a] + set b_addr [get_property bram_addr_begin $b] + if {$a_addr > $b_addr} { + return 1 + } elseif {$a_addr < $b_addr} { + return -1 + } + set a_slice [get_property bram_slice_begin $a] + set b_slice [get_property bram_slice_begin $b] + if {$a_slice > $b_slice} { + return 1 + } elseif {$a_slice < $b_slice} { + return -1 + } + return 0 + } + dict for {name desc} $brams { + dict with desc { + puts $chn "\t\t> 3]\">" + puts $chn "\t\t\t" + foreach cell [lsort -command compare $cells] { + set type [switch [get_property REF_NAME $cell] \ + RAMB36E2 {expr {"RAMB32"}} \ + RAMB36E1 {expr {"RAMB32"}}] + set loc [lindex [split [get_property LOC $cell] "_"] 1] + set lsb [get_property bram_slice_begin $cell] + set msb [get_property bram_slice_end $cell] + set addr_bgn [get_property bram_addr_begin $cell] + set addr_end [get_property bram_addr_end $cell] + puts $chn "\t\t\t\t" + puts $chn "\t\t\t\t\t" + puts $chn "\t\t\t\t\t" + puts $chn "\t\t\t\t\t" + puts $chn "\t\t\t\t" + } + puts $chn "\t\t\t" + puts $chn "\t\t" + } + } + puts $chn "\t" + puts $chn "\t" + puts $chn "\t\t" + puts $chn "" + close $chn + current_instance + +} + +if {$argc != 3} { + puts $argc + puts {Error: Invalid number of arguments} + puts {Usage: write_mmi.tcl checkpoint mmi_file instance} +} + +lassign $argv checkpoint mmi_file instance + +open_checkpoint $checkpoint +write_mmi $mmi_file $instance diff --git a/fpga/src/main/resources/vcu118/sdboot/.gitignore b/fpga/src/main/resources/vcu118/sdboot/.gitignore new file mode 100644 index 00000000..378eac25 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/.gitignore @@ -0,0 +1 @@ +build diff --git a/fpga/src/main/resources/vcu118/sdboot/Makefile b/fpga/src/main/resources/vcu118/sdboot/Makefile new file mode 100644 index 00000000..b9c21470 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/Makefile @@ -0,0 +1,39 @@ +# RISCV environment variable must be set +ROOT_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +BUILD_DIR := $(ROOT_DIR)/build + +CC=$(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy +OBJDUMP=$(RISCV)/bin/riscv64-unknown-elf-objdump +CFLAGS=-march=rv64ima -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles +CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 +CFLAGS+= -I $(ROOT_DIR)/include -I. +LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T sdboot.elf.lds + +#PBUS_CLK passed in +elf := $(BUILD_DIR)/sdboot.elf +$(elf): head.S kprintf.c sd.c + mkdir -p $(BUILD_DIR) + $(CC) $(CFLAGS) -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S sd.c kprintf.c + +.PHONY: elf +elf: $(elf) + +bin := $(BUILD_DIR)/sdboot.bin +$(bin): $(elf) + mkdir -p $(BUILD_DIR) + $(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@ + +.PHONY: bin +bin: $(bin) + +dump := $(BUILD_DIR)/sdboot.dump +$(dump): $(elf) + $(OBJDUMP) -D -S $< > $@ + +.PHONY: dump +dump: $(dump) + +.PHONY: clean +clean:: + rm -rf $(BUILD_DIR) diff --git a/fpga/src/main/resources/vcu118/sdboot/common.h b/fpga/src/main/resources/vcu118/sdboot/common.h new file mode 100644 index 00000000..4f71e103 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/common.h @@ -0,0 +1,9 @@ +#ifndef _SDBOOT_COMMON_H +#define _SDBOOT_COMMON_H + +#ifndef PAYLOAD_DEST + #define PAYLOAD_DEST MEMORY_MEM_ADDR +#endif + + +#endif diff --git a/fpga/src/main/resources/vcu118/sdboot/head.S b/fpga/src/main/resources/vcu118/sdboot/head.S new file mode 100644 index 00000000..662a6fd2 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/head.S @@ -0,0 +1,20 @@ +// See LICENSE for license details. +#include +#include +#include "common.h" + + .section .text.init + .option norvc + .globl _prog_start +_prog_start: + smp_pause(s1, s2) + li sp, (PAYLOAD_DEST + 0xffff000) + call main + smp_resume(s1, s2) + csrr a0, mhartid // hartid for next level bootloader + la a1, dtb // dtb address for next level bootloader + li s1, PAYLOAD_DEST + jr s1 + + .section .rodata +dtb: diff --git a/fpga/src/main/resources/vcu118/sdboot/include/bits.h b/fpga/src/main/resources/vcu118/sdboot/include/bits.h new file mode 100644 index 00000000..bfe656fe --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/bits.h @@ -0,0 +1,36 @@ +// See LICENSE for license details. +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/fpga/src/main/resources/vcu118/sdboot/include/const.h b/fpga/src/main/resources/vcu118/sdboot/include/const.h new file mode 100644 index 00000000..8dcffbb0 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/const.h @@ -0,0 +1,18 @@ +// See LICENSE for license details. +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h new file mode 100644 index 00000000..c2b05bae --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h new file mode 100644 index 00000000..f7f0acb4 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h new file mode 100644 index 00000000..4d5b2d8d --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h new file mode 100644 index 00000000..7118572a --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h @@ -0,0 +1,79 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + +#endif /* _SIFIVE_SPI_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h new file mode 100644 index 00000000..aecfd912 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h @@ -0,0 +1,28 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXNSTOP 0x2 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/platform.h b/fpga/src/main/resources/vcu118/sdboot/include/platform.h new file mode 100644 index 00000000..c240e0e5 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/platform.h @@ -0,0 +1,108 @@ +// See LICENSE for license details. + +#ifndef _EAGLE_PLATFORM_H +#define _EAGLE_PLATFORM_H + +#include "const.h" +#include "riscv_test_defaults.h" +#include "devices/clint.h" +#include "devices/gpio.h" +#include "devices/plic.h" +#include "devices/spi.h" +#include "devices/uart.h" + + // Some things missing from the official encoding.h +#if __riscv_xlen == 32 + #define MCAUSE_INT 0x80000000UL + #define MCAUSE_CAUSE 0x7FFFFFFFUL +#else + #define MCAUSE_INT 0x8000000000000000UL + #define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL +#endif + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// CPU info +#define NUM_CORES 1 +#define GLOBAL_INT_SIZE 38 +#define GLOBAL_INT_MAX_PRIORITY 7 + +// Memory map +#define CLINT_CTRL_ADDR _AC(0x2000000,UL) +#define CLINT_CTRL_SIZE _AC(0x10000,UL) +#define DEBUG_CTRL_ADDR _AC(0x0,UL) +#define DEBUG_CTRL_SIZE _AC(0x1000,UL) +#define ERROR_MEM_ADDR _AC(0x3000,UL) +#define ERROR_MEM_SIZE _AC(0x1000,UL) +#define GPIO_CTRL_ADDR _AC(0x64002000,UL) +#define GPIO_CTRL_SIZE _AC(0x1000,UL) +#define MASKROM_MEM_ADDR _AC(0x10000,UL) +#define MASKROM_MEM_SIZE _AC(0x10000,UL) +#define MEMORY_MEM_ADDR _AC(0x80000000,UL) +#define MEMORY_MEM_SIZE _AC(0x10000000,UL) +#define PLIC_CTRL_ADDR _AC(0xc000000,UL) +#define PLIC_CTRL_SIZE _AC(0x4000000,UL) +#define SPI_CTRL_ADDR _AC(0x64001000,UL) +#define SPI_CTRL_SIZE _AC(0x1000,UL) +#define SPI1_CTRL_ADDR _AC(0x64004000,UL) +#define SPI1_CTRL_SIZE _AC(0x1000,UL) +#define TEST_CTRL_ADDR _AC(0x4000,UL) +#define TEST_CTRL_SIZE _AC(0x1000,UL) +#define UART_CTRL_ADDR _AC(0x64000000,UL) +#define UART_CTRL_SIZE _AC(0x1000,UL) +#define UART1_CTRL_ADDR _AC(0x64003000,UL) +#define UART1_CTRL_SIZE _AC(0x1000,UL) +#define I2C_CTRL_ADDR _AC(0x64005000,UL) +#define I2C_CTRL_SIZE _AC(0x1000,UL) + +// IOF masks + + +// Interrupt numbers +#define UART_INT_BASE 1 +#define UART1_INT_BASE 2 +#define I2C_INT_BASE 3 +#define GPIO_INT_BASE 4 +#define SPI_INT_BASE 36 +#define SPI1_INT_BASE 37 + +// Helper functions +#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i))) +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) +#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i))) +// Bulk set bits in `reg` to either 0 or 1. +// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7 +// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7 +#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); } +#define AXI_PCIE_HOST_1_00_A_REG(offset) _REG32(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define DEBUG_REG(offset) _REG32(DEBUG_CTRL_ADDR, offset) +#define ERROR_REG(offset) _REG32(ERROR_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define MASKROM_REG(offset) _REG32(MASKROM_CTRL_ADDR, offset) +#define MEMORY_REG(offset) _REG32(MEMORY_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define SPI_REG(offset) _REG32(SPI_CTRL_ADDR, offset) +#define TEST_REG(offset) _REG32(TEST_CTRL_ADDR, offset) +#define UART_REG(offset) _REG32(UART_CTRL_ADDR, offset) +#define AXI_PCIE_HOST_1_00_A_REG64(offset) _REG64(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset) +#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset) +#define DEBUG_REG64(offset) _REG64(DEBUG_CTRL_ADDR, offset) +#define ERROR_REG64(offset) _REG64(ERROR_CTRL_ADDR, offset) +#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset) +#define MASKROM_REG64(offset) _REG64(MASKROM_CTRL_ADDR, offset) +#define MEMORY_REG64(offset) _REG64(MEMORY_CTRL_ADDR, offset) +#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset) +#define SPI_REG64(offset) _REG64(SPI_CTRL_ADDR, offset) +#define SPI1_REG64(offset) _REG64(SPI1_CTRL_ADDR, offset) +#define TEST_REG64(offset) _REG64(TEST_CTRL_ADDR, offset) +#define UART_REG64(offset) _REG64(UART_CTRL_ADDR, offset) +#define UART1_REG64(offset) _REG64(UART1_CTRL_ADDR, offset) +#define I2C_REG64(offset) _REG64(I2C_CTRL_ADDR, offset) + +// Misc + + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h b/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h new file mode 100644 index 00000000..a2dea3d4 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h @@ -0,0 +1,81 @@ +// See LICENSE for license details. +#ifndef _RISCV_TEST_DEFAULTS_H +#define _RISCV_TEST_DEFAULTS_H + +#define TESTNUM x28 +#define TESTBASE 0x4000 + +#define RVTEST_RV32U \ + .macro init; \ + .endm + +#define RVTEST_RV64U \ + .macro init; \ + .endm + +#define RVTEST_RV32UF \ + .macro init; \ + /* If FPU exists, initialize FCSR. */ \ + csrr t0, misa; \ + andi t0, t0, 1 << ('F' - 'A'); \ + beqz t0, 1f; \ + /* Enable FPU if it exists. */ \ + li t0, MSTATUS_FS; \ + csrs mstatus, t0; \ + fssr x0; \ +1: ; \ + .endm + +#define RVTEST_RV64UF \ + .macro init; \ + /* If FPU exists, initialize FCSR. */ \ + csrr t0, misa; \ + andi t0, t0, 1 << ('F' - 'A'); \ + beqz t0, 1f; \ + /* Enable FPU if it exists. */ \ + li t0, MSTATUS_FS; \ + csrs mstatus, t0; \ + fssr x0; \ +1: ; \ + .endm + +#define RVTEST_CODE_BEGIN \ + .section .text.init; \ + .globl _prog_start; \ +_prog_start: \ + init; + +#define RVTEST_CODE_END \ + unimp + +#define RVTEST_PASS \ + fence; \ + li t0, TESTBASE; \ + li t1, 0x5555; \ + sw t1, 0(t0); \ +1: \ + j 1b; + +#define RVTEST_FAIL \ + li t0, TESTBASE; \ + li t1, 0x3333; \ + slli a0, a0, 16; \ + add a0, a0, t1; \ + sw a0, 0(t0); \ +1: \ + j 1b; + +#define EXTRA_DATA + +#define RVTEST_DATA_BEGIN \ + EXTRA_DATA \ + .align 4; .global begin_signature; begin_signature: + +#define RVTEST_DATA_END \ + _msg_init: .asciz "RUN\r\n"; \ + _msg_pass: .asciz "PASS"; \ + _msg_fail: .asciz "FAIL "; \ + _msg_end: .asciz "\r\n"; \ + .align 4; .global end_signature; end_signature: + +#endif /* _RISCV_TEST_DEFAULTS_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/sections.h b/fpga/src/main/resources/vcu118/sdboot/include/sections.h new file mode 100644 index 00000000..6e1f0518 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/sections.h @@ -0,0 +1,17 @@ +// See LICENSE for license details. +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/smp.h b/fpga/src/main/resources/vcu118/sdboot/include/smp.h new file mode 100644 index 00000000..145ceb37 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/include/smp.h @@ -0,0 +1,142 @@ +#ifndef SIFIVE_SMP +#define SIFIVE_SMP +#include "platform.h" + +// The maximum number of HARTs this code supports +#ifndef MAX_HARTS +#define MAX_HARTS 32 +#endif +#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4) +#define CLINT1_END_HART_IPI CLINT1_CTRL_ADDR + (MAX_HARTS*4) + +// The hart that non-SMP tests should run on +#ifndef NONSMP_HART +#define NONSMP_HART 0 +#endif + +/* If your test cannot handle multiple-threads, use this: + * smp_disable(reg1) + */ +#define smp_disable(reg1, reg2) \ + csrr reg1, mhartid ;\ + li reg2, NONSMP_HART ;\ + beq reg1, reg2, hart0_entry ;\ +42: ;\ + wfi ;\ + j 42b ;\ +hart0_entry: + +/* If your test needs to temporarily block multiple-threads, do this: + * smp_pause(reg1, reg2) + * ... single-threaded work ... + * smp_resume(reg1, reg2) + * ... multi-threaded work ... + */ + +#define smp_pause(reg1, reg2) \ + li reg2, 0x8 ;\ + csrw mie, reg2 ;\ + li reg1, NONSMP_HART ;\ + csrr reg2, mhartid ;\ + bne reg1, reg2, 42f + +#ifdef CLINT1_CTRL_ADDR +// If a second CLINT exists, then make sure we: +// 1) Trigger a software interrupt on all harts of both CLINTs. +// 2) Locate your own hart's software interrupt pending register and clear it. +// 3) Wait for all harts on both CLINTs to clear their software interrupt +// pending register. +// WARNING: This code makes these assumptions, which are only true for Fadu as +// of now: +// 1) hart0 uses CLINT0 at offset 0 +// 2) hart2 uses CLINT1 at offset 0 +// 3) hart3 uses CLINT1 at offset 1 +// 4) There are no other harts or CLINTs in the system. +#define smp_resume(reg1, reg2) \ + /* Trigger software interrupt on CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ + /* Trigger software interrupt on CLINT1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT1_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ + /* Wait to receive software interrupt */ \ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + /* Clear own software interrupt bit */ \ + csrr reg2, mhartid ;\ + bnez reg2, 41f; \ + /* hart0 case: Use CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ + j 42f; \ +41: \ + /* hart 2, 3 case: Use CLINT1 and remap hart IDs to 0 and 1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ + addi reg2, reg2, -2; \ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ; \ +42: \ + /* Wait for all software interrupt bits to be cleared on CLINT0 */ \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b; \ + /* Wait for all software interrupt bits to be cleared on CLINT1 */ \ + li reg1, CLINT1_CTRL_ADDR ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT1_END_HART_IPI ;\ + blt reg1, reg2, 41b; \ + /* End smp_resume() */ + +#else + +#define smp_resume(reg1, reg2) \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + li reg1, CLINT_CTRL_ADDR ;\ + csrr reg2, mhartid ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b + +#endif /* ifdef CLINT1_CTRL_ADDR */ + +#endif diff --git a/fpga/src/main/resources/vcu118/sdboot/kprintf.c b/fpga/src/main/resources/vcu118/sdboot/kprintf.c new file mode 100644 index 00000000..57627011 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/kprintf.c @@ -0,0 +1,75 @@ +// See LICENSE for license details. +#include +#include +#include + +#include "kprintf.h" + +static inline void _kputs(const char *s) +{ + char c; + for (; (c = *s) != '\0'; s++) + kputc(c); +} + +void kputs(const char *s) +{ + _kputs(s); + kputc('\r'); + kputc('\n'); +} + +void kprintf(const char *fmt, ...) +{ + va_list vl; + bool is_format, is_long, is_char; + char c; + + va_start(vl, fmt); + is_format = false; + is_long = false; + is_char = false; + while ((c = *fmt++) != '\0') { + if (is_format) { + switch (c) { + case 'l': + is_long = true; + continue; + case 'h': + is_char = true; + continue; + case 'x': { + unsigned long n; + long i; + if (is_long) { + n = va_arg(vl, unsigned long); + i = (sizeof(unsigned long) << 3) - 4; + } else { + n = va_arg(vl, unsigned int); + i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4; + } + for (; i >= 0; i -= 4) { + long d; + d = (n >> i) & 0xF; + kputc(d < 10 ? '0' + d : 'a' + d - 10); + } + break; + } + case 's': + _kputs(va_arg(vl, const char *)); + break; + case 'c': + kputc(va_arg(vl, int)); + break; + } + is_format = false; + is_long = false; + is_char = false; + } else if (c == '%') { + is_format = true; + } else { + kputc(c); + } + } + va_end(vl); +} diff --git a/fpga/src/main/resources/vcu118/sdboot/kprintf.h b/fpga/src/main/resources/vcu118/sdboot/kprintf.h new file mode 100644 index 00000000..26cc8055 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/kprintf.h @@ -0,0 +1,49 @@ +// See LICENSE for license details. +#ifndef _SDBOOT_KPRINTF_H +#define _SDBOOT_KPRINTF_H + +#include +#include + +#define REG32(p, i) ((p)[(i) >> 2]) + +#ifndef UART_CTRL_ADDR + #ifndef UART_NUM + #define UART_NUM 0 + #endif + + #define _CONCAT3(A, B, C) A ## B ## C + #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR) + #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM) +#endif +static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR); + +static inline void kputc(char c) +{ + volatile uint32_t *tx = ®32(uart, UART_REG_TXFIFO); +#ifdef __riscv_atomic + int32_t r; + do { + __asm__ __volatile__ ( + "amoor.w %0, %2, %1\n" + : "=r" (r), "+A" (*tx) + : "r" (c)); + } while (r < 0); +#else + while ((int32_t)(*tx) < 0); + *tx = c; +#endif +} + +extern void kputs(const char *); +extern void kprintf(const char *, ...); + +#ifdef DEBUG +#define dprintf(s, ...) kprintf((s), ##__VA_ARGS__) +#define dputs(s) kputs((s)) +#else +#define dprintf(s, ...) do { } while (0) +#define dputs(s) do { } while (0) +#endif + +#endif /* _SDBOOT_KPRINTF_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/linker/memory.lds b/fpga/src/main/resources/vcu118/sdboot/linker/memory.lds new file mode 100644 index 00000000..997de4d3 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/linker/memory.lds @@ -0,0 +1,5 @@ +MEMORY +{ + bootrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x2000 + memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x40000000 +} diff --git a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds new file mode 100644 index 00000000..34610c94 --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds @@ -0,0 +1,79 @@ +OUTPUT_ARCH("riscv") +ENTRY(_prog_start) + +INCLUDE memory.lds + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + PROVIDE(_ram = ORIGIN(memory_mem)); + PROVIDE(_ram_end = _ram + LENGTH(memory_mem)); + + .text ALIGN((ORIGIN(bootrom_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(bootrom_mem) + 0x0), 8)) { + PROVIDE(_ftext = .); + *(.text.init) + *(.text.unlikely .text.unlikely.*) + *(.text .text.* .gnu.linkonce.t.*) + PROVIDE(_etext = .); + . += 0x40; /* to create a gap between .text and .data b/c ifetch can fetch ahead from .data */ + } >bootrom_mem :text + + .eh_frame ALIGN((ADDR(.text) + SIZEOF(.text)), 8) : AT(ALIGN((LOADADDR(.text) + SIZEOF(.text)), 8)) { + *(.eh_frame) + } >bootrom_mem :text + + .srodata ALIGN((ADDR(.eh_frame) + SIZEOF(.eh_frame)), 8) : AT(ALIGN((LOADADDR(.eh_frame) + SIZEOF(.eh_frame)), 8)) ALIGN_WITH_INPUT { + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata.*) + } >bootrom_mem :data + + .data ALIGN((ADDR(.srodata) + SIZEOF(.srodata)), 8) : AT(ALIGN((LOADADDR(.srodata) + SIZEOF(.srodata)), 8)) ALIGN_WITH_INPUT { + *(.data .data.* .gnu.linkonce.d.*) + *(.tohost) /* TODO: Support sections that aren't explicitly listed in this linker script */ + } >bootrom_mem :data + + .sdata ALIGN((ADDR(.data) + SIZEOF(.data)), 8) : AT(ALIGN((LOADADDR(.data) + SIZEOF(.data)), 8)) ALIGN_WITH_INPUT { + *(.sdata .sdata.* .gnu.linkonce.s.*) + } >bootrom_mem :data + + .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } >bootrom_mem :data + + PROVIDE(_data = ADDR(.rodata)); + PROVIDE(_data_lma = LOADADDR(.rodata)); + PROVIDE(_edata = .); + + .bss ALIGN((ORIGIN(memory_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(memory_mem) + 0x0), 8)) ALIGN(8) { + PROVIDE(_fbss = .); + PROVIDE(__global_pointer$ = . + 0x7C0); + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(8); + PROVIDE(_ebss = .); + } >memory_mem :bss + + PROVIDE(_end = .); + + /* + * heap_stack_region_usable_end: (ORIGIN(memory_mem) + LENGTH(memory_mem)) + * heap_stack_min_size: 4096 + * heap_stack_max_size: 1048576 + */ + PROVIDE(_sp = ALIGN(MIN((ORIGIN(memory_mem) + LENGTH(memory_mem)), _ebss + 1048576) - 7, 8)); + PROVIDE(_heap_end = _sp - 2048); + + /* This section is a noop and is only used for the ASSERT */ + .stack : { + ASSERT(_sp >= (_ebss + 4096), "Error: No room left for the heap and stack"); + } +} diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c new file mode 100644 index 00000000..bdd9d62a --- /dev/null +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -0,0 +1,236 @@ +// See LICENSE for license details. +#include + +#include + +#include "common.h" + +#define DEBUG +#include "kprintf.h" + +#define MAX_CORES 8 + +// A sector is 512 bytes, so ((1 << 11) * 512) = 1 MiB +#define PAYLOAD_SIZE (16 << 11) + +// The sector at which the BBL partition starts +#define BBL_PARTITION_START_SECTOR 34 + +#ifndef TL_CLK +#error Must define TL_CLK +#endif + +#define F_CLK TL_CLK + +static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR); + +static inline uint8_t spi_xfer(uint8_t d) +{ + int32_t r; + + REG32(spi, SPI_REG_TXFIFO) = d; + do { + r = REG32(spi, SPI_REG_RXFIFO); + } while (r < 0); + return r; +} + +static inline uint8_t sd_dummy(void) +{ + return spi_xfer(0xFF); +} + +static uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) +{ + unsigned long n; + uint8_t r; + + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_HOLD; + sd_dummy(); + spi_xfer(cmd); + spi_xfer(arg >> 24); + spi_xfer(arg >> 16); + spi_xfer(arg >> 8); + spi_xfer(arg); + spi_xfer(crc); + + n = 1000; + do { + r = sd_dummy(); + if (!(r & 0x80)) { +// dprintf("sd:cmd: %hx\r\n", r); + goto done; + } + } while (--n > 0); + kputs("sd_cmd: timeout"); +done: + return r; +} + +static inline void sd_cmd_end(void) +{ + sd_dummy(); + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO; +} + + +static void sd_poweron(void) +{ + long i; + REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL); + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF; + for (i = 10; i > 0; i--) { + sd_dummy(); + } + REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO; +} + +static int sd_cmd0(void) +{ + int rc; + dputs("CMD0"); + rc = (sd_cmd(0x40, 0, 0x95) != 0x01); + sd_cmd_end(); + return rc; +} + +static int sd_cmd8(void) +{ + int rc; + dputs("CMD8"); + rc = (sd_cmd(0x48, 0x000001AA, 0x87) != 0x01); + sd_dummy(); /* command version; reserved */ + sd_dummy(); /* reserved */ + rc |= ((sd_dummy() & 0xF) != 0x1); /* voltage */ + rc |= (sd_dummy() != 0xAA); /* check pattern */ + sd_cmd_end(); + return rc; +} + +static void sd_cmd55(void) +{ + sd_cmd(0x77, 0, 0x65); + sd_cmd_end(); +} + +static int sd_acmd41(void) +{ + uint8_t r; + dputs("ACMD41"); + do { + sd_cmd55(); + r = sd_cmd(0x69, 0x40000000, 0x77); /* HCS = 1 */ + } while (r == 0x01); + return (r != 0x00); +} + +static int sd_cmd58(void) +{ + int rc; + dputs("CMD58"); + rc = (sd_cmd(0x7A, 0, 0xFD) != 0x00); + rc |= ((sd_dummy() & 0x80) != 0x80); /* Power up status */ + sd_dummy(); + sd_dummy(); + sd_dummy(); + sd_cmd_end(); + return rc; +} + +static int sd_cmd16(void) +{ + int rc; + dputs("CMD16"); + rc = (sd_cmd(0x50, 0x200, 0x15) != 0x00); + sd_cmd_end(); + return rc; +} + +static uint16_t crc16_round(uint16_t crc, uint8_t data) { + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= data; + crc ^= (uint8_t)(crc >> 4) & 0xf; + crc ^= crc << 12; + crc ^= (crc & 0xff) << 5; + return crc; +} + +#define SPIN_SHIFT 6 +#define SPIN_UPDATE(i) (!((i) & ((1 << SPIN_SHIFT)-1))) +#define SPIN_INDEX(i) (((i) >> SPIN_SHIFT) & 0x3) + +static const char spinner[] = { '-', '/', '|', '\\' }; + +static int copy(void) +{ + volatile uint8_t *p = (void *)(PAYLOAD_DEST); + long i = PAYLOAD_SIZE; + int rc = 0; + + dputs("CMD18"); + kprintf("LOADING "); + + // John: Let's go slow until we get this working + //REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL); + REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); + if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) { + sd_cmd_end(); + return 1; + } + do { + uint16_t crc, crc_exp; + long n; + + crc = 0; + n = 512; + while (sd_dummy() != 0xFE); + do { + uint8_t x = sd_dummy(); + *p++ = x; + crc = crc16_round(crc, x); + } while (--n > 0); + + crc_exp = ((uint16_t)sd_dummy() << 8); + crc_exp |= sd_dummy(); + + if (crc != crc_exp) { + kputs("\b- CRC mismatch "); + rc = 1; + break; + } + + if (SPIN_UPDATE(i)) { + kputc('\b'); + kputc(spinner[SPIN_INDEX(i)]); + } + } while (--i > 0); + sd_cmd_end(); + + sd_cmd(0x4C, 0, 0x01); + sd_cmd_end(); + kputs("\b "); + return rc; +} + +int main(void) +{ + REG32(uart, UART_REG_TXCTRL) = UART_TXEN; + + kputs("INIT"); + sd_poweron(); + if (sd_cmd0() || + sd_cmd8() || + sd_acmd41() || + sd_cmd58() || + sd_cmd16() || + copy()) { + kputs("ERROR"); + return 1; + } + + kputs("BOOT"); + + __asm__ __volatile__ ("fence.i" : : : "memory"); + + return 0; +} diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 28c3ae14..4eaea05b 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -134,8 +134,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends /*** DDR ***/ - val ddrWrangler = LazyModule(new ResetWrangler) - val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL)) + val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) // connect 1 mem. channel to the FPGA DDR val inParams = topDesign match { case td: ChipTop => From 3c42e2cae7a903d4d3e914d90405274e247cbbb1 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 26 Oct 2020 18:15:58 -0700 Subject: [PATCH 036/157] Fixed BootROM | Updated HarnessBinders --- fpga/src/main/resources/vcu118/sdboot/head.S | 3 ++- .../vcu118/sdboot/linker/sdboot.elf.lds | 1 + .../main/scala/vcu118/bringup/Configs.scala | 19 +++++++------- .../scala/vcu118/bringup/HarnessBinders.scala | 13 +++++----- .../main/scala/vcu118/bringup/IOBinders.scala | 25 +++++++++++++------ .../scala/vcu118/bringup/TestHarness.scala | 5 +++- .../chipyard/src/main/scala/ChipTop.scala | 4 +-- generators/sifive-blocks | 2 +- 8 files changed, 43 insertions(+), 29 deletions(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/head.S b/fpga/src/main/resources/vcu118/sdboot/head.S index 662a6fd2..d871b824 100644 --- a/fpga/src/main/resources/vcu118/sdboot/head.S +++ b/fpga/src/main/resources/vcu118/sdboot/head.S @@ -16,5 +16,6 @@ _prog_start: li s1, PAYLOAD_DEST jr s1 - .section .rodata + .section .dtb + .align 3 dtb: diff --git a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds index 34610c94..7a0a42fe 100644 --- a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds +++ b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds @@ -47,6 +47,7 @@ SECTIONS .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT { *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.dtb) } >bootrom_mem :data PROVIDE(_data = ADDR(.rodata)); diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 8db731ed..79dbf6db 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -18,7 +18,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import sifive.fpgashells.shell.{DesignKey} -import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} +import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import chipyard.{BuildTop} @@ -29,12 +29,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L), - injectFunc = Some((spi: TLSPI) => { - ResourceBinding { - Resource(new MMCDevice(spi.device, 1), "reg").bind(ResourceAddress(0)) - } - })), + SPIParams(rAddress = BigInt(0x64001000L)), SPIParams(rAddress = BigInt(0x64004000L))) case VCU118ShellPMOD => "SDIO" case PeripheryI2CKey => List( @@ -56,6 +51,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { class SmallModifications extends Config((site, here, up) => { case DebugModuleKey => None // disable debug module + case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS case SystemBusKey => up(SystemBusKey).copy( errorDevice = Some(DevNullParams( Seq(AddressSet(0x3000, 0xfff)), @@ -79,6 +75,10 @@ class WithBootROM extends Config((site, here, up) => { } }) +class WithExtMemSetToDDR extends Config((site, here, up) => { + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) +}) + class FakeBringupConfig extends Config( new SmallModifications ++ new WithBringupUART ++ @@ -92,6 +92,7 @@ class FakeBringupConfig extends Config( new WithGPIOIOPassthrough ++ new WithTLIOPassthrough ++ new WithBringupPeripherals ++ + new WithExtMemSetToDDR ++ // set the external mem port size properly new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ @@ -100,8 +101,8 @@ class FakeBringupConfig extends Config( new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ + //new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new chipyard.WithMulticlockCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index efe805cd..79f602dc 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -1,7 +1,7 @@ package chipyard.fpga.vcu118.bringup import chisel3._ -import chisel3.experimental.{Analog, IO} +import chisel3.experimental.{Analog, IO, BaseModule} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters, Field} @@ -19,13 +19,12 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} import chipyard.harness._ /*** UART ***/ class WithBringupUART extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 2) @@ -39,7 +38,7 @@ class WithBringupUART extends OverrideHarnessBinder({ /*** SPI ***/ class WithBringupSPI extends OverrideHarnessBinder({ - (system: HasPeripherySPIModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { + (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 2) @@ -53,7 +52,7 @@ class WithBringupSPI extends OverrideHarnessBinder({ /*** I2C ***/ class WithBringupI2C extends OverrideHarnessBinder({ - (system: HasPeripheryI2CModuleImp, th: HasHarnessSignalReferences, ports: Seq[I2CPort]) => { + (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 1) @@ -66,7 +65,7 @@ class WithBringupI2C extends OverrideHarnessBinder({ /*** GPIO ***/ class WithBringupGPIO extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { + (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { (vcu118th.outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) => bb_io.bundle <> dut_io @@ -79,7 +78,7 @@ class WithBringupGPIO extends OverrideHarnessBinder({ /*** Experimental DDR ***/ class WithBringupDDR extends OverrideHarnessBinder({ - (system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { + (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 1) diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index ece212bb..558b074f 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -5,7 +5,7 @@ import chisel3.util.experimental.{BoringUtils} import chisel3.experimental.{Analog, IO, DataMirror} import freechips.rocketchip.config._ -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress, InModuleBody} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem._ @@ -27,7 +27,7 @@ import testchipip._ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.{GlobalResetSchemeKey, CanHaveMasterTLMemPort} -import chipyard.iobinders.{OverrideIOBinder} +import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} class WithUARTIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryUARTModuleImp) => { @@ -49,13 +49,22 @@ class WithGPIOIOPassthrough extends OverrideIOBinder({ } }) -class WithSPIIOPassthrough extends OverrideIOBinder({ - (system: HasPeripherySPIModuleImp) => { - val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } - (io_spi_pins_temp zip system.spi).map { case (io, sysio) => - io <> sysio +class WithSPIIOPassthrough extends OverrideLazyIOBinder({ + (system: HasPeripherySPI) => { + // attach resource to 1st SPI + ResourceBinding { + Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) + } + + InModuleBody { + system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => { + val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } + (io_spi_pins_temp zip system.spi).map { case (io, sysio) => + io <> sysio + } + (io_spi_pins_temp, Nil) + } } } - (io_spi_pins_temp, Nil) } }) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 4eaea05b..9f51d2aa 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -20,6 +20,7 @@ import sifive.blocks.devices.gpio._ import chipyard.harness._ import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} +import chipyard.iobinders.{HasIOBinders} case object DUTFrequencyKey extends Field[Double](100.0) @@ -186,6 +187,8 @@ class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) exte // harness binders are non-lazy _outer.topDesign match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } + _outer.topDesign match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) } } diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index bf07bcee..61a043b6 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -23,8 +23,8 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) * drive clock and reset generation */ -class ChipTop(implicit p: Parameters) extends LazyModule - with HasTestHarnessFunctions with HasIOBinders with BindingScope { +class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope + with HasTestHarnessFunctions with HasIOBinders { // The system module specified by BuildSystem lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") diff --git a/generators/sifive-blocks b/generators/sifive-blocks index c160544e..25eae85e 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit c160544e74db4f33d51f23c8a41c07a1ec16b7b7 +Subproject commit 25eae85e711d650a305eb1cd923421a2872fcc56 From 0eca51ba4dce419b803945ad888b27ba7981a455 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 27 Oct 2020 12:57:34 -0700 Subject: [PATCH 037/157] Reorganize into bringup/simple | Bump sifive-blocks --- fpga/Makefile | 54 +++++-- fpga/src/main/scala/vcu118/Configs.scala | 85 +++++++++++ .../main/scala/vcu118/HarnessBinders.scala | 51 +++++++ fpga/src/main/scala/vcu118/IOBinders.scala | 52 +++++++ fpga/src/main/scala/vcu118/TestHarness.scala | 144 ++++++++++++++++++ .../main/scala/vcu118/bringup/Configs.scala | 92 +++-------- .../scala/vcu118/bringup/CustomOverlays.scala | 4 - .../scala/vcu118/bringup/HarnessBinders.scala | 53 ++----- .../main/scala/vcu118/bringup/IOBinders.scala | 66 +------- .../scala/vcu118/bringup/TestHarness.scala | 144 ++---------------- generators/sifive-blocks | 2 +- 11 files changed, 420 insertions(+), 327 deletions(-) create mode 100644 fpga/src/main/scala/vcu118/Configs.scala create mode 100644 fpga/src/main/scala/vcu118/HarnessBinders.scala create mode 100644 fpga/src/main/scala/vcu118/IOBinders.scala create mode 100644 fpga/src/main/scala/vcu118/TestHarness.scala diff --git a/fpga/Makefile b/fpga/Makefile index 748a5029..74af21e9 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -14,22 +14,52 @@ sim_name := none ######################################################################################### # include shared variables ######################################################################################### +SUB_PROJECT ?= vcu118 + +ifeq ($(SUB_PROJECT),vcu118) + SBT_PROJECT ?= fpga_platforms + MODEL ?= VCU118FPGATestHarness + VLOG_MODEL ?= VCU118FPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.vcu118 + CONFIG ?= RocketVCU118Config + CONFIG_PACKAGE ?= chipyard.fpga.vcu118 + GENERATOR_PACKAGE ?= chipyard + TB ?= none # unused + TOP ?= ChipTop + BOARD ?= vcu118 +endif + +ifeq ($(SUB_PROJECT),bringup) + SBT_PROJECT ?= fpga_platforms + MODEL ?= BringupVCU118FPGATestHarness + VLOG_MODEL ?= BringupVCU118FPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup + CONFIG ?= RocketBringupConfig + CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup + GENERATOR_PACKAGE ?= chipyard + TB ?= none # unused + TOP ?= ChipTop + BOARD ?= vcu118 +endif + +ifeq ($(SUB_PROJECT),arty) + # TODO: Fix with Arty + SBT_PROJECT ?= fpga_platforms + MODEL ?= BringupVCU118FPGATestHarness + VLOG_MODEL ?= BringupVCU118FPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup + CONFIG ?= RocketBringupConfig + CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup + GENERATOR_PACKAGE ?= chipyard + TB ?= none # unused + TOP ?= ChipTop + BOARD ?= arty +endif + include $(base_dir)/variables.mk # default variables to build the arty example -SUB_PROJECT := fpga -SBT_PROJECT := fpga_platforms -MODEL := BringupVCU118FPGATestHarness -VLOG_MODEL := BringupVCU118FPGATestHarness -MODEL_PACKAGE := chipyard.fpga.vcu118.bringup -CONFIG := FakeBringupConfig -CONFIG_PACKAGE := chipyard.fpga.vcu118.bringup -GENERATOR_PACKAGE := chipyard -TB := none # unused -TOP := ChipTop - # setup the board to use -BOARD ?= vcu118 .PHONY: default default: $(mcs) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala new file mode 100644 index 00000000..f7b0df10 --- /dev/null +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -0,0 +1,85 @@ +package chipyard.fpga.vcu118 + +import sys.process._ + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} +import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} +import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.tile.{XLen} + +import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} +import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} + +import sifive.fpgashells.shell.{DesignKey} +import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} + +class WithDefaultPeripherals extends Config((site, here, up) => { + case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) + case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L))) + case VCU118ShellPMOD => "SDIO" +}) + +class WithSystemModifications extends Config((site, here, up) => { + case DebugModuleKey => None // disable debug module + case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS + case SystemBusKey => up(SystemBusKey).copy( + errorDevice = Some(DevNullParams( + Seq(AddressSet(0x3000, 0xfff)), + maxAtomic=site(XLen)/8, + maxTransfer=128, + region = RegionType.TRACKED))) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = + Some(BigDecimal(site(FPGAFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt)) + case ControlBusKey => up(ControlBusKey, site).copy( + errorDevice = None) + case DTSTimebase => BigInt(1000000) + case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => + // invoke makefile for sdboot + val freqMHz = site(FPGAFrequencyKey).toInt * 1000000 + val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin" + require (make.! == 0, "Failed to build bootrom") + p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") + } + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) +}) + +class AbstractVCU118Config extends Config( + new WithUART ++ + new WithSPISDCard ++ + new WithDDRMem ++ + new WithUARTIOPassthrough ++ + new WithSPIIOPassthrough ++ + new WithTLIOPassthrough ++ + new WithDefaultPeripherals ++ + new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new chipyard.WithMulticlockCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class RocketVCU118Config extends Config( + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new AbstractVCU118Config) + +class BoomVCU118Config extends Config( + new WithFPGAFrequency(75) ++ + new boom.common.WithNLargeBooms(1) ++ + new AbstractVCU118Config) + +class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => { + case FPGAFrequencyKey => MHz +}) + +class WithFPGAFreq25MHz extends WithFPGAFrequency(25) +class WithFPGAFreq50MHz extends WithFPGAFrequency(50) +class WithFPGAFreq75MHz extends WithFPGAFrequency(75) +class WithFPGAFreq100MHz extends WithFPGAFrequency(100) diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala new file mode 100644 index 00000000..ae2462a2 --- /dev/null +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -0,0 +1,51 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{BaseModule} + +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + +import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} +import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} + +import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} +import chipyard.harness.{OverrideHarnessBinder} + +/*** UART ***/ +class WithUART extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + th match { case vcu118th: VCU118FPGATestHarnessImp => { + vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head + } } + + Nil + } +}) + +/*** SPI ***/ +class WithSPISDCard extends OverrideHarnessBinder({ + (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { + th match { case vcu118th: VCU118FPGATestHarnessImp => { + vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head + } } + + Nil + } +}) + +/*** Experimental DDR ***/ +class WithDDRMem extends OverrideHarnessBinder({ + (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { + th match { case vcu118th: VCU118FPGATestHarnessImp => { + require(ports.size == 1) + + val bundles = vcu118th.vcu118Outer.ddrClient.out.map(_._1) + val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType))) + bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } + ddrClientBundle <> ports.head + } } + + Nil + } +}) diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala new file mode 100644 index 00000000..a1f67bcd --- /dev/null +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -0,0 +1,52 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{IO, DataMirror} + +import freechips.rocketchip.diplomacy.{ResourceBinding, Resource, ResourceAddress, InModuleBody} +import freechips.rocketchip.subsystem.{BaseSubsystem} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + +import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} +import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} + +import chipyard.{CanHaveMasterTLMemPort} +import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} + +class WithUARTIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryUARTModuleImp) => { + val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") } + (io_uart_pins_temp zip system.uart).map { case (io, sysio) => + io <> sysio + } + (io_uart_pins_temp, Nil) + } +}) + +class WithSPIIOPassthrough extends OverrideLazyIOBinder({ + (system: HasPeripherySPI) => { + // attach resource to 1st SPI + ResourceBinding { + Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) + } + + InModuleBody { + system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => { + val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } + (io_spi_pins_temp zip system.spi).map { case (io, sysio) => + io <> sysio + } + (io_spi_pins_temp, Nil) + } } + } + } +}) + +class WithTLIOPassthrough extends OverrideIOBinder({ + (system: CanHaveMasterTLMemPort) => { + val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") + io_tl_mem_pins_temp <> system.mem_tl + (Seq(io_tl_mem_pins_temp), Nil) + } +}) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala new file mode 100644 index 00000000..4748c528 --- /dev/null +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -0,0 +1,144 @@ +package chipyard.fpga.vcu118 + +import chisel3._ +import chisel3.experimental.{IO} + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tilelink._ + +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.clocks._ + +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.gpio._ + +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} +import chipyard.iobinders.{HasIOBinders} +import chipyard.harness.{ApplyHarnessBinders} + +case object FPGAFrequencyKey extends Field[Double](100.0) + +class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { + + def dp = designParameters + + val pmod_is_sdio = p(VCU118ShellPMOD) == "SDIO" + val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52") + + // Order matters; ddr depends on sys_clock + val uart = Overlay(UARTOverlayKey, new UARTVCU118ShellPlacer(this, UARTShellInput())) + val sdio = if (pmod_is_sdio) Some(Overlay(SPIOverlayKey, new SDIOVCU118ShellPlacer(this, SPIShellInput()))) else None + val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVCU118ShellPlacer(this, JTAGDebugShellInput(location = jtag_location))) + val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVCU118ShellPlacer(this, cJTAGDebugShellInput())) + val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput())) + val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput())) + val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput())) + + val topDesign = LazyModule(p(BuildTop)(dp)) + + // place all clocks in the shell + dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } + + /*** Connect/Generate clocks ***/ + + // connect to the PLL that will generate multiple clocks + val harnessSysPLL = dp(PLLFactoryKey)() + sys_clock.get() match { + case Some(x : SysClockVCU118PlacedOverlay) => { + harnessSysPLL := x.node + } + } + + // create and connect to the dutClock + val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + val dutWrangler = LazyModule(new ResetWrangler) + val dutGroup = ClockGroup() + dutClock := dutWrangler.node := dutGroup := harnessSysPLL + + // connect ref clock to dummy sink node + ref_clock.get() match { + case Some(x : RefClockVCU118PlacedOverlay) => { + val sink = ClockSinkNode(Seq(ClockSinkParameters())) + sink := x.node + } + } + + /*** UART ***/ + + // 1st UART goes to the VCU118 dedicated UART + + val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) + dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) + + /*** SPI ***/ + + // 1st SPI goes to the VCU118 SDIO port + + val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) + dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) + + /*** DDR ***/ + + val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) + + // connect 1 mem. channel to the FPGA DDR + val inParams = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: CanHaveMasterTLMemPort => + lsys.memTLNode.edges.in(0) + } + } + val ddrClient = TLClientNode(Seq(inParams.master)) + ddrPlaced.overlayOutput.ddr := ddrClient + + // module implementation + override lazy val module = new VCU118FPGATestHarnessImp(this) +} + +class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { + + val vcu118Outer = _outer + + val reset = IO(Input(Bool())) + _outer.xdc.addPackagePin(reset, "L19") + _outer.xdc.addIOStandard(reset, "LVCMOS12") + + val reset_ibuf = Module(new IBUF) + reset_ibuf.io.I := reset + + val sysclk: Clock = _outer.sys_clock.get() match { + case Some(x: SysClockVCU118PlacedOverlay) => x.clock + } + + val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) + _outer.sdc.addAsyncPath(Seq(powerOnReset)) + + val ereset: Bool = _outer.chiplink.get() match { + case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n + case _ => false.B + } + + _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset) + + // cy stuff + val harnessClock = _outer.dutClock.in.head._1.clock + val harnessReset = WireInit(_outer.dutClock.in.head._1.reset) + val dutReset = harnessReset + val success = false.B + + childClock := harnessClock + childReset := harnessReset + + // harness binders are non-lazy + _outer.topDesign match { case d: HasTestHarnessFunctions => + d.harnessFunctions.foreach(_(this)) + } + _outer.topDesign match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) + } +} diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 79dbf6db..0e5602e5 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -1,39 +1,24 @@ package chipyard.fpga.vcu118.bringup import math.min -import sys.process._ -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.config.{Config} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} -import freechips.rocketchip.system._ -import freechips.rocketchip.tile._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} +import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} +import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} +import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} -import chipyard.{BuildTop} - -import chipyard.harness._ +import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config} class WithBringupPeripherals extends Config((site, here, up) => { - case PeripheryUARTKey => List( - UARTParams(address = BigInt(0x64000000L)), - UARTParams(address = BigInt(0x64003000L))) - case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L)), - SPIParams(rAddress = BigInt(0x64004000L))) - case VCU118ShellPMOD => "SDIO" - case PeripheryI2CKey => List( - I2CParams(address = BigInt(0x64005000L))) + case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) + case PeripherySPIKey => up(PeripherySPIKey, site) ++ List(SPIParams(rAddress = BigInt(0x64004000L))) + case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L))) case PeripheryGPIOKey => { if (BringupGPIOs.width > 0) { require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) @@ -49,60 +34,19 @@ class WithBringupPeripherals extends Config((site, here, up) => { } }) -class SmallModifications extends Config((site, here, up) => { - case DebugModuleKey => None // disable debug module - case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS - case SystemBusKey => up(SystemBusKey).copy( - errorDevice = Some(DevNullParams( - Seq(AddressSet(0x3000, 0xfff)), - maxAtomic=site(XLen)/8, - maxTransfer=128, - region = RegionType.TRACKED))) - case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = - Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt)) - case ControlBusKey => up(ControlBusKey, site).copy( - errorDevice = None) - case DTSTimebase => BigInt(1000000) -}) - -class WithBootROM extends Config((site, here, up) => { - case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => - // invoke makefile for sdboot - val freqMHz = site(DUTFrequencyKey).toInt * 1000000 - val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin" - require (make.! == 0, "Failed to build bootrom") - p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") - } -}) - -class WithExtMemSetToDDR extends Config((site, here, up) => { - case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) -}) - -class FakeBringupConfig extends Config( - new SmallModifications ++ +class WithBringupAdditions extends Config( new WithBringupUART ++ new WithBringupSPI ++ new WithBringupI2C ++ new WithBringupGPIO ++ - new WithBringupDDR ++ - new WithUARTIOPassthrough ++ - new WithSPIIOPassthrough ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ - new WithTLIOPassthrough ++ + new WithBringupPeripherals) + +class RocketBringupConfig extends Config( new WithBringupPeripherals ++ - new WithExtMemSetToDDR ++ // set the external mem port size properly - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ - new WithBootROM ++ // use local bootrom - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - //new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new chipyard.WithMulticlockCoherentBusTopology ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + new RocketVCU118Config) + +class BoomBringupConfig extends Config( + new WithBringupPeripherals ++ + new BoomVCU118Config) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index fdbbb919..c0a96d3c 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -4,15 +4,11 @@ import chisel3._ import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ -import chipsalliance.rocketchip.config.{Parameters, Field} import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell.xilinx._ -import sifive.blocks.devices.gpio._ - - import chipyard.fpga.vcu118.{FMCPMap} /* Connect the I2C to certain FMC pins */ diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index 79f602dc..b6693036 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -3,33 +3,21 @@ package chipyard.fpga.vcu118.bringup import chisel3._ import chisel3.experimental.{Analog, IO, BaseModule} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util._ +import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} +import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} +import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.ip.xilinx._ -import sifive.fpgashells.shell._ -import sifive.fpgashells.clocks._ - -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.gpio._ - -import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} -import chipyard.harness._ +import chipyard.{HasHarnessSignalReferences} +import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} /*** UART ***/ -class WithBringupUART extends OverrideHarnessBinder({ +class WithBringupUART extends ComposeHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 2) - vcu118th.outer.io_uart_bb.bundle <> ports.head - vcu118th.outer.io_uart_bb_2.bundle <> ports.last + vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last } } Nil @@ -37,13 +25,12 @@ class WithBringupUART extends OverrideHarnessBinder({ }) /*** SPI ***/ -class WithBringupSPI extends OverrideHarnessBinder({ +class WithBringupSPI extends ComposeHarnessBinder({ (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 2) - vcu118th.outer.io_spi_bb.bundle <> ports.head - vcu118th.outer.io_spi_bb_2.bundle <> ports.last + vcu118th.bringupOuter.io_adi_spi_bb.bundle <> ports.last } } Nil @@ -56,7 +43,7 @@ class WithBringupI2C extends OverrideHarnessBinder({ th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 1) - vcu118th.outer.io_i2c_bb.bundle <> ports.head + vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head } } Nil @@ -67,7 +54,7 @@ class WithBringupI2C extends OverrideHarnessBinder({ class WithBringupGPIO extends OverrideHarnessBinder({ (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { - (vcu118th.outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) => + (vcu118th.bringupOuter.io_gpio_bb zip ports).map { case (bb_io, dut_io) => bb_io.bundle <> dut_io } } } @@ -75,19 +62,3 @@ class WithBringupGPIO extends OverrideHarnessBinder({ Nil } }) - -/*** Experimental DDR ***/ -class WithBringupDDR extends OverrideHarnessBinder({ - (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { - th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { - require(ports.size == 1) - - val bundles = vcu118th.outer.ddrClient.out.map(_._1) - val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType))) - bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } - ddrClientBundle <> ports.head - } } - - Nil - } -}) diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index 558b074f..168933f7 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -1,43 +1,12 @@ package chipyard.fpga.vcu118.bringup import chisel3._ -import chisel3.util.experimental.{BoringUtils} -import chisel3.experimental.{Analog, IO, DataMirror} +import chisel3.experimental.{IO, DataMirror} -import freechips.rocketchip.config._ -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress, InModuleBody} -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.jtag.{JTAGIO} -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system.{SimAXIMem} -import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} -import freechips.rocketchip.util._ -import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} -import freechips.rocketchip.tilelink.{TLBundle} +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} +import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ -import tracegen.{TraceGenSystemModuleImp} - -import barstools.iocell.chisel._ - -import testchipip._ -import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} - -import chipyard.{GlobalResetSchemeKey, CanHaveMasterTLMemPort} -import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} - -class WithUARTIOPassthrough extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => { - val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") } - (io_uart_pins_temp zip system.uart).map { case (io, sysio) => - io <> sysio - } - (io_uart_pins_temp, Nil) - } -}) +import chipyard.iobinders.{OverrideIOBinder} class WithGPIOIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryGPIOModuleImp) => { @@ -49,25 +18,6 @@ class WithGPIOIOPassthrough extends OverrideIOBinder({ } }) -class WithSPIIOPassthrough extends OverrideLazyIOBinder({ - (system: HasPeripherySPI) => { - // attach resource to 1st SPI - ResourceBinding { - Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) - } - - InModuleBody { - system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => { - val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } - (io_spi_pins_temp zip system.spi).map { case (io, sysio) => - io <> sysio - } - (io_spi_pins_temp, Nil) - } } - } - } -}) - class WithI2CIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryI2CModuleImp) => { val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } @@ -77,11 +27,3 @@ class WithI2CIOPassthrough extends OverrideIOBinder({ (io_i2c_pins_temp, Nil) } }) - -class WithTLIOPassthrough extends OverrideIOBinder({ - (system: CanHaveMasterTLMemPort) => { - val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") - io_tl_mem_pins_temp <> system.mem_tl - (Seq(io_tl_mem_pins_temp), Nil) - } -}) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 9f51d2aa..080f6189 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -1,11 +1,10 @@ package chipyard.fpga.vcu118.bringup import chisel3._ -import chisel3.experimental.{Analog, IO} import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem} +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import sifive.fpgashells.shell.xilinx._ @@ -18,100 +17,31 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.harness._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} -import chipyard.iobinders.{HasIOBinders} +import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp} -case object DUTFrequencyKey extends Field[Double](100.0) - -class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { - - def dp = designParameters - - val pmod_is_sdio = p(VCU118ShellPMOD) == "SDIO" - val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52") - - // Order matters; ddr depends on sys_clock - val uart = Overlay(UARTOverlayKey, new UARTVCU118ShellPlacer(this, UARTShellInput())) - val sdio = if (pmod_is_sdio) Some(Overlay(SPIOverlayKey, new SDIOVCU118ShellPlacer(this, SPIShellInput()))) else None - val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVCU118ShellPlacer(this, JTAGDebugShellInput(location = jtag_location))) - val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVCU118ShellPlacer(this, cJTAGDebugShellInput())) - val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput())) - val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput())) - val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput())) - - val topDesign = LazyModule(p(BuildTop)(dp)) - - // place all clocks in the shell - dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } - - /*** Connect/Generate clocks ***/ - - // connect to the PLL that will generate multiple clocks - val harnessSysPLL = dp(PLLFactoryKey)() - sys_clock.get() match { - case Some(x : SysClockVCU118PlacedOverlay) => { - harnessSysPLL := x.node - } - } - - // create and connect to the dutClock - val dutClock = ClockSinkNode(freqMHz = dp(DUTFrequencyKey)) - val dutWrangler = LazyModule(new ResetWrangler) - val dutGroup = ClockGroup() - dutClock := dutWrangler.node := dutGroup := harnessSysPLL - - //InModuleBody { - // topDesign.module match { case td: LazyModuleImp => { - // td.clock := dutClock.in.head._1.clock - // td.reset := dutClock.in.head._1.reset - // } - // } - //} - - // connect ref clock to dummy sink node - ref_clock.get() match { - case Some(x : RefClockVCU118PlacedOverlay) => { - val sink = ClockSinkNode(Seq(ClockSinkParameters())) - sink := x.node - } - } - - // extra overlays +class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness { /*** UART ***/ require(dp(PeripheryUARTKey).size == 2) - // 1st UART goes to the VCU118 dedicated UART - - // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design - // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) - dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) - // 2nd UART goes to the FMC UART val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) - val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) - dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) + val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) + dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb)) /*** SPI ***/ require(dp(PeripherySPIKey).size == 2) - // 1st SPI goes to the VCU118 SDIO port - - val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) - val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) - // 2nd SPI goes to the ADI port val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) - val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) - val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2)) + val io_adi_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) + dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_adi_spi_bb)) /*** I2C ***/ @@ -123,7 +53,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends /*** GPIO ***/ val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { - val maxGPIOSupport = 32 + val maxGPIOSupport = 32 // max gpio per gpio chip val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) }) @@ -133,62 +63,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends placer.place(GPIODesignInput(params, io_gpio_bb(i))) } - /*** DDR ***/ - - val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) - - // connect 1 mem. channel to the FPGA DDR - val inParams = topDesign match { case td: ChipTop => - td.lazySystem match { case lsys: CanHaveMasterTLMemPort => - lsys.memTLNode.edges.in(0) - } - } - val ddrClient = TLClientNode(Seq(inParams.master)) - ddrPlaced.overlayOutput.ddr := ddrClient - // module implementation override lazy val module = new BringupVCU118FPGATestHarnessImp(this) } -class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences { - - val outer = _outer - - val reset = IO(Input(Bool())) - _outer.xdc.addPackagePin(reset, "L19") - _outer.xdc.addIOStandard(reset, "LVCMOS12") - - val reset_ibuf = Module(new IBUF) - reset_ibuf.io.I := reset - - val sysclk: Clock = _outer.sys_clock.get() match { - case Some(x: SysClockVCU118PlacedOverlay) => x.clock - } - - val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) - _outer.sdc.addAsyncPath(Seq(powerOnReset)) - - val ereset: Bool = _outer.chiplink.get() match { - case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n - case _ => false.B - } - - _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset) - - // cy stuff - val harnessClock = _outer.dutClock.in.head._1.clock - val harnessReset = WireInit(_outer.dutClock.in.head._1.reset) - val dutReset = harnessReset - val success = false.B - - childClock := harnessClock - childReset := harnessReset - - // harness binders are non-lazy - _outer.topDesign match { case d: HasTestHarnessFunctions => - d.harnessFunctions.foreach(_(this)) - } - _outer.topDesign match { case d: HasIOBinders => - ApplyHarnessBinders(this, d.lazySystem, d.portMap) - } +class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) { + val bringupOuter = _outer } diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 25eae85e..7e2121ee 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 25eae85e711d650a305eb1cd923421a2872fcc56 +Subproject commit 7e2121ee26e614f2144a9e4c67c440773aa7544d From 356fa70c3c9a334f8ead280c61afd4d619f7a01d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 11:16:17 -0800 Subject: [PATCH 038/157] Update fpga-shells submodule | Fix Arty Makefile lines --- fpga/Makefile | 10 +++++----- scripts/init-submodules-no-riscv-tools-nolog.sh | 2 -- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index 74af21e9..fa1f8e08 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -45,11 +45,11 @@ endif ifeq ($(SUB_PROJECT),arty) # TODO: Fix with Arty SBT_PROJECT ?= fpga_platforms - MODEL ?= BringupVCU118FPGATestHarness - VLOG_MODEL ?= BringupVCU118FPGATestHarness - MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup - CONFIG ?= RocketBringupConfig - CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup + MODEL ?= ArtyFPGATestHarness + VLOG_MODEL ?= ArtyFPGATestHarness + MODEL_PACKAGE ?= chipyard.fpga.arty + CONFIG ?= E300ArtyDevKitConfig + CONFIG_PACKAGE ?= chipyard.fpga.arty GENERATOR_PACKAGE ?= chipyard TB ?= none # unused TOP ?= ChipTop diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index db16d125..c861658d 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -39,8 +39,6 @@ git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none git config submodule.software/firemarshal.update none -# Disable updates to the local FPGA tools -git config submodule.fpga/fpga-shells.update none git submodule update --init --recursive #--jobs 8 # Un-ignore toolchain submodules From a7ab0dab593771678498dcff2ac108f7c13f1caf Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 13:59:10 -0800 Subject: [PATCH 039/157] Updated VCU118 | Bumped naming on Arty --- fpga/src/main/scala/arty/HarnessBinders.scala | 2 - fpga/src/main/scala/arty/TestHarness.scala | 14 +++-- fpga/src/main/scala/vcu118/Configs.scala | 5 +- fpga/src/main/scala/vcu118/DigitalTop.scala | 62 +++++++++++++++++++ .../main/scala/vcu118/HarnessBinders.scala | 8 +-- fpga/src/main/scala/vcu118/IOBinders.scala | 1 - fpga/src/main/scala/vcu118/TestHarness.scala | 12 ++-- .../main/scala/vcu118/bringup/Configs.scala | 11 +++- .../scala/vcu118/bringup/DigitalTop.scala | 25 ++++++++ .../scala/vcu118/bringup/HarnessBinders.scala | 8 --- .../chipyard/src/main/scala/DigitalTop.scala | 40 ------------ 11 files changed, 117 insertions(+), 71 deletions(-) create mode 100644 fpga/src/main/scala/vcu118/DigitalTop.scala create mode 100644 fpga/src/main/scala/vcu118/bringup/DigitalTop.scala diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 89105d78..a7ce4465 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -58,7 +58,6 @@ class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ // IOBUF(th.jd_1, j.TRSTn) // PULLUP(th.jd_1) // } - Nil } }) @@ -68,6 +67,5 @@ class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ // UARTAdapter.connect(ports)(system.p) // IOBUF(th.ck_io(2), ports.txd) // IOBUF(th.ck_io(3), ports.rxd) - Nil } }) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 856f903f..ff16327e 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -7,11 +7,12 @@ import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} +import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { - val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") + val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") // turn IO clock into Reset type val hReset = Wire(Reset()) @@ -19,17 +20,20 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell // default to 32MHz clock withClockAndReset(clock_32MHz, hReset) { - val dut = Module(ldut.module) + val dut = Module(lazyDut.module) } val harnessClock = clock_32MHz val harnessReset = hReset val success = false.B + val dutReset = reset_core - // must be after HasHarnessSignalReferences assignments - ldut match { case d: HasTestHarnessFunctions => + lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) } + lazyDut match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) + } + } diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index f7b0df10..f55c9520 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -2,7 +2,7 @@ package chipyard.fpga.vcu118 import sys.process._ -import freechips.rocketchip.config.{Config} +import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} @@ -15,6 +15,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import chipyard.{BuildSystem} + class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L))) @@ -22,6 +24,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => { }) class WithSystemModifications extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top case DebugModuleKey => None // disable debug module case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS case SystemBusKey => up(SystemBusKey).copy( diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala new file mode 100644 index 00000000..4a176fca --- /dev/null +++ b/fpga/src/main/scala/vcu118/DigitalTop.scala @@ -0,0 +1,62 @@ +package chipyard.fpga.vcu118 + +import chisel3._ + +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ + +import chipyard.{DigitalTop, DigitalTopModule} + +// ------------------------------------ +// VCU118 DigitalTop +// ------------------------------------ + +class VCU118DigitalTop(implicit p: Parameters) extends DigitalTop + with sifive.blocks.devices.spi.HasPeripherySPI + with CanHaveMasterTLMemPort +{ + override lazy val module = new VCU118DigitalTopModule(this) +} + +class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends DigitalTopModule(l) + with sifive.blocks.devices.spi.HasPeripherySPIModuleImp + +/** Adds a TileLink port to the system intended to master an MMIO device bus */ +trait CanHaveMasterTLMemPort { this: BaseSubsystem => + private val memPortParamsOpt = p(ExtMem) + private val portName = "tl_mem" + private val device = new MemoryDevice + private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) + + val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => + Seq.tabulate(nMemoryChannels) { channel => + val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) + val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) + + TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = base.flatMap(_.intersect(filter)), + resources = device.reg, + regionType = RegionType.UNCACHED, // cacheable + executable = true, + supportsGet = TransferSizes(1, mbus.blockBytes), + supportsPutFull = TransferSizes(1, mbus.blockBytes), + supportsPutPartial = TransferSizes(1, mbus.blockBytes))), + beatBytes = memPortParams.beatBytes) + } + }).toList.flatten) + + mbus.coupleTo(s"memory_controller_port_named_$portName") { + (memTLNode + :*= TLBuffer() + :*= TLSourceShrinker(1 << idBits) + :*= TLWidthWidget(mbus.beatBytes) + :*= _) + } + + val mem_tl = InModuleBody { memTLNode.makeIOs() } +} diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index ae2462a2..6ba53642 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} +import chipyard.{HasHarnessSignalReferences} import chipyard.harness.{OverrideHarnessBinder} /*** UART ***/ @@ -18,8 +18,6 @@ class WithUART extends OverrideHarnessBinder({ th match { case vcu118th: VCU118FPGATestHarnessImp => { vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head } } - - Nil } }) @@ -29,8 +27,6 @@ class WithSPISDCard extends OverrideHarnessBinder({ th match { case vcu118th: VCU118FPGATestHarnessImp => { vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head } } - - Nil } }) @@ -45,7 +41,5 @@ class WithDDRMem extends OverrideHarnessBinder({ bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } ddrClientBundle <> ports.head } } - - Nil } }) diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala index a1f67bcd..4c5bb357 100644 --- a/fpga/src/main/scala/vcu118/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -11,7 +11,6 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} -import chipyard.{CanHaveMasterTLMemPort} import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} class WithUARTIOPassthrough extends OverrideIOBinder({ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 4748c528..d5a5481e 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -15,10 +15,9 @@ import sifive.fpgashells.clocks._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop} import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} @@ -125,10 +124,13 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset) - // cy stuff + // reset setup + val hReset = Wire(Reset()) + hReset := _outer.dutClock.in.head._1.reset + val harnessClock = _outer.dutClock.in.head._1.clock - val harnessReset = WireInit(_outer.dutClock.in.head._1.reset) - val dutReset = harnessReset + val harnessReset = WireInit(hReset) + val dutReset = hReset.asAsyncReset val success = false.B childClock := harnessClock diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 0e5602e5..fc5df5a1 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -2,7 +2,7 @@ package chipyard.fpga.vcu118.bringup import math.min -import freechips.rocketchip.config.{Config} +import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} @@ -13,6 +13,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import chipyard.{BuildSystem} + import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config} class WithBringupPeripherals extends Config((site, here, up) => { @@ -34,6 +36,10 @@ class WithBringupPeripherals extends Config((site, here, up) => { } }) +class WithBringupVCU118System extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => new BringupVCU118DigitalTop()(p) // use the VCU118-extended bringup digital top +}) + class WithBringupAdditions extends Config( new WithBringupUART ++ new WithBringupSPI ++ @@ -41,7 +47,8 @@ class WithBringupAdditions extends Config( new WithBringupGPIO ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ - new WithBringupPeripherals) + new WithBringupPeripherals ++ + new WithBringupVCU118System) class RocketBringupConfig extends Config( new WithBringupPeripherals ++ diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala new file mode 100644 index 00000000..ddcfe163 --- /dev/null +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -0,0 +1,25 @@ +package chipyard.fpga.vcu118.bringup + +import chisel3._ + +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ + +import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} + +// ------------------------------------ +// BringupVCU118 DigitalTop +// ------------------------------------ + +class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop + with sifive.blocks.devices.i2c.HasPeripheryI2C +{ + override lazy val module = new BringupVCU118DigitalTopModule(this) +} + +class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l) + with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index b6693036..531b3c8d 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -19,8 +19,6 @@ class WithBringupUART extends ComposeHarnessBinder({ vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last } } - - Nil } }) @@ -32,8 +30,6 @@ class WithBringupSPI extends ComposeHarnessBinder({ vcu118th.bringupOuter.io_adi_spi_bb.bundle <> ports.last } } - - Nil } }) @@ -45,8 +41,6 @@ class WithBringupI2C extends OverrideHarnessBinder({ vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head } } - - Nil } }) @@ -58,7 +52,5 @@ class WithBringupGPIO extends OverrideHarnessBinder({ bb_io.bundle <> dut_io } } } - - Nil } }) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 46904a37..c0ac1ff7 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -26,7 +26,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA - with CanHaveMasterTLMemPort { override lazy val module = new DigitalTopModule(this) } @@ -39,42 +38,3 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop - -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - -/** Adds a TileLink port to the system intended to master an MMIO device bus */ -trait CanHaveMasterTLMemPort { this: BaseSubsystem => - private val memPortParamsOpt = p(ExtMem) - private val portName = "tl_mem" - private val device = new MemoryDevice - private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) - - val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => - Seq.tabulate(nMemoryChannels) { channel => - val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) - val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) - - TLSlavePortParameters.v1( - managers = Seq(TLSlaveParameters.v1( - address = base.flatMap(_.intersect(filter)), - resources = device.reg, - regionType = RegionType.UNCACHED, // cacheable - executable = true, - supportsGet = TransferSizes(1, mbus.blockBytes), - supportsPutFull = TransferSizes(1, mbus.blockBytes), - supportsPutPartial = TransferSizes(1, mbus.blockBytes))), - beatBytes = memPortParams.beatBytes) - } - }).toList.flatten) - - mbus.coupleTo(s"memory_controller_port_named_$portName") { - (memTLNode - :*= TLBuffer() - :*= TLSourceShrinker(1 << idBits) - :*= TLWidthWidget(mbus.beatBytes) - :*= _) - } - - val mem_tl = InModuleBody { memTLNode.makeIOs() } -} From a281869041fbe7c38d91268756626d5d1d891f51 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 15:04:44 -0800 Subject: [PATCH 040/157] Fix Arty merge and errors from CY bump --- fpga/Makefile | 2 +- fpga/src/main/scala/arty/Configs.scala | 39 ++------ fpga/src/main/scala/arty/DigitalTop.scala | 21 ----- fpga/src/main/scala/arty/HarnessBinders.scala | 90 +++++++++---------- fpga/src/main/scala/arty/IOBinders.scala | 24 +++++ fpga/src/main/scala/arty/TestHarness.scala | 19 ++-- 6 files changed, 89 insertions(+), 106 deletions(-) delete mode 100644 fpga/src/main/scala/arty/DigitalTop.scala create mode 100644 fpga/src/main/scala/arty/IOBinders.scala diff --git a/fpga/Makefile b/fpga/Makefile index fa1f8e08..fa6847ef 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -48,7 +48,7 @@ ifeq ($(SUB_PROJECT),arty) MODEL ?= ArtyFPGATestHarness VLOG_MODEL ?= ArtyFPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.arty - CONFIG ?= E300ArtyDevKitConfig + CONFIG ?= TinyRocketArtyConfig CONFIG_PACKAGE ?= chipyard.fpga.arty GENERATOR_PACKAGE ?= chipyard TB ?= none # unused diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index e96bcd9c..11cf0260 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -9,35 +9,13 @@ import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ import chipyard.{BuildSystem} -import chipyard.iobinders -class E300DevKitExtra extends Config((site, here, up) => { - case PeripheryGPIOKey => List( - GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) - case PeripheryPWMKey => List( - PWMParams(address = 0x10015000, cmpWidth = 8), - PWMParams(address = 0x10025000, cmpWidth = 16), - PWMParams(address = 0x10035000, cmpWidth = 16)) - case PeripherySPIKey => List( - SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3), - SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3)) - case PeripherySPIFlashKey => List( - SPIFlashParams( - fAddress = 0x20000000, - rAddress = 0x10014000, - defaultSampleDel = 3)) +class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( - UARTParams(address = 0x10013000), - UARTParams(address = 0x10023000)) - case PeripheryI2CKey => List( - I2CParams(address = 0x10016000)) + UARTParams(address = 0x10013000)) case DTSTimebase => BigInt(32768) case JtagDTMKey => new JtagDTMConfig ( idcodeVersion = 2, @@ -46,17 +24,16 @@ class E300DevKitExtra extends Config((site, here, up) => { debugIdleCycles = 5) }) -class WithE300System extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) -}) - -class E300ArtyDevKitConfig extends Config( - new WithE300System ++ +class TinyRocketArtyConfig extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ + new WithArtyResetHarnessBinder ++ new chipyard.iobinders.WithDebugIOCells ++ new chipyard.iobinders.WithUARTIOCells ++ - new E300DevKitExtra ++ + new WithResetPassthrough ++ + new WithDefaultPeripherals ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.With1TinyCore ++ diff --git a/fpga/src/main/scala/arty/DigitalTop.scala b/fpga/src/main/scala/arty/DigitalTop.scala deleted file mode 100644 index 858b6215..00000000 --- a/fpga/src/main/scala/arty/DigitalTop.scala +++ /dev/null @@ -1,21 +0,0 @@ -package chipyard.fpga.arty - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ - -import chipyard.{DigitalTop, DigitalTopModule} - -// ------------------------------------ -// E300 DigitalTop -// ------------------------------------ - -class E300DigitalTop(implicit p: Parameters) extends DigitalTop -{ - override lazy val module = new E300DigitalTopModule(this) -} - -class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index a7ce4465..408d2b7d 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -1,71 +1,69 @@ package chipyard.fpga.arty import chisel3._ -import chisel3.experimental.{Analog} -import freechips.rocketchip.config.{Field, Config, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} -import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} -import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.subsystem._ -import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ - -import barstools.iocell.chisel._ - -import testchipip._ - -import chipyard.harness.OverrideHarnessBinder -import chipyard.HasHarnessSignalReferences -import chipyard.iobinders.GetSystemParameters - -import tracegen.{TraceGenSystemModuleImp} -import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} - -import scala.reflect.{ClassTag} +import sifive.blocks.devices.jtag._ +import sifive.blocks.devices.pinctrl._ import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} -class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => { - // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { - // ports.map { - // case d: ClockedDMIIO => - // // Want to error here. - // case j: JTAGIO => - // //val dtm_success = WireInit(false.B) - // //when (dtm_success) { th.success := true.B } - // //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) +import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} - // j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt +class WithArtyResetHarnessBinder extends ComposeHarnessBinder({ + (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => { + withClockAndReset(th.clock_32MHz, th.ck_rst) { + // Debug module reset + th.dut_ndreset := ports(0) - // IOBUF(th.jd_5, j.TMS) - // PULLUP(th.jd_5) + // JTAG reset + ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz) + } + } +}) - // IOBUF(th.jd_4, j.TDI) - // PULLUP(th.jd_4) +class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ + (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => { + ports.map { + case j: JTAGIO => + withClockAndReset(th.harnessClock, th.hReset) { + val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag") - // IOBUF(th.jd_0, j.TDO) + JTAGPinsFromPort(io_jtag, j) - // // mimic putting a pullup on this line (part of reset vote) - // th.SRST_n := IOBUF(th.jd_6) - // PULLUP(th.jd_6) + io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool - // IOBUF(th.jd_1, j.TRSTn) - // PULLUP(th.jd_1) - // } + IOBUF(th.jd_5, io_jtag.TMS) + PULLUP(th.jd_5) + + IOBUF(th.jd_4, io_jtag.TDI) + PULLUP(th.jd_4) + + IOBUF(th.jd_0, io_jtag.TDO) + + // mimic putting a pullup on this line (part of reset vote) + th.SRST_n := IOBUF(th.jd_6) + PULLUP(th.jd_6) + + // ignore the po input + io_jtag.TCK.i.po.map(_ := DontCare) + io_jtag.TDI.i.po.map(_ := DontCare) + io_jtag.TMS.i.po.map(_ := DontCare) + io_jtag.TDO.i.po.map(_ := DontCare) + } + } } }) class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { - // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { - // UARTAdapter.connect(ports)(system.p) - // IOBUF(th.ck_io(2), ports.txd) - // IOBUF(th.ck_io(3), ports.rxd) + withClockAndReset(th.clock_32MHz, th.ck_rst) { + IOBUF(th.uart_txd_in, ports.head.txd) + ports.head.rxd := IOBUF(th.uart_rxd_out) + } } }) diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala new file mode 100644 index 00000000..205f8fcc --- /dev/null +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -0,0 +1,24 @@ +package chipyard.fpga.arty + +import chisel3._ +import chisel3.experimental.{IO} + +import freechips.rocketchip.util._ +import freechips.rocketchip.devices.debug._ + +import chipyard.iobinders.{ComposeIOBinder} + +class WithResetPassthrough extends ComposeIOBinder({ + (system: HasPeripheryDebugModuleImp) => { + // Debug module reset + val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset") + io_ndreset := system.debug.get.ndreset + + // JTAG reset + val sjtag = system.debug.get.systemjtag.get + val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset") + sjtag.reset := io_sjtag_reset + + (Seq(io_ndreset, io_sjtag_reset), Nil) + } +}) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index ff16327e..503d2de6 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -1,23 +1,27 @@ package chipyard.fpga.arty import chisel3._ -import chisel3.experimental.{Analog} -import scala.collection.mutable.{ArrayBuffer} + import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.config.{Parameters} + import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} + import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} +import chipyard.harness.{ApplyHarnessBinders} import chipyard.iobinders.{HasIOBinders} -import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") - // turn IO clock into Reset type + // Convert harness resets from Bool to Reset type. val hReset = Wire(Reset()) hReset := ck_rst + val dReset = Wire(AsyncReset()) + dReset := reset_core.asAsyncReset + // default to 32MHz clock withClockAndReset(clock_32MHz, hReset) { val dut = Module(lazyDut.module) @@ -27,13 +31,14 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell val harnessReset = hReset val success = false.B - val dutReset = reset_core + val dutReset = dReset + // must be after HasHarnessSignalReferences assignments lazyDut match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) } lazyDut match { case d: HasIOBinders => ApplyHarnessBinders(this, d.lazySystem, d.portMap) } - } + From 43e64ded93ce22fa2c578cd1e283c8336f5a497d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 15:13:09 -0800 Subject: [PATCH 041/157] Readd ignore fpga-shells in main submodule setup --- scripts/init-submodules-no-riscv-tools-nolog.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index c861658d..e3272f86 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -39,6 +39,8 @@ git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none git config submodule.software/firemarshal.update none +# Disable update to fpga-shells +git config submodule.fpga/fpga-shells.update none git submodule update --init --recursive #--jobs 8 # Un-ignore toolchain submodules From 083f34ab23f91a910edfbbc70d35e56fe4331448 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 15:44:54 -0800 Subject: [PATCH 042/157] Revert Chipyard system | Create new VCU118 Chipyard system --- fpga/src/main/scala/vcu118/DigitalTop.scala | 54 +++++++++++++++++-- .../chipyard/src/main/scala/System.scala | 1 + 2 files changed, 50 insertions(+), 5 deletions(-) diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala index 4a176fca..9fe42bc8 100644 --- a/fpga/src/main/scala/vcu118/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/DigitalTop.scala @@ -8,22 +8,66 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.{DontTouch} -import chipyard.{DigitalTop, DigitalTopModule} +import chipyard.{DigitalTop, DigitalTopModule, ChipyardSubsystem, ChipyardSubsystemModuleImp} // ------------------------------------ // VCU118 DigitalTop // ------------------------------------ -class VCU118DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.spi.HasPeripherySPI - with CanHaveMasterTLMemPort +class VCU118DigitalTop(implicit p: Parameters) extends VCU118ChipyardSystem + with testchipip.CanHaveTraceIO // Enables optionally adding trace IO + with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad + with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device + with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter + with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART + with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs + with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller + with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port + with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim + with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget + with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget + with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget + with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget + with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { override lazy val module = new VCU118DigitalTopModule(this) } -class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends DigitalTopModule(l) +class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends VCU118ChipyardSystemModule(l) + with testchipip.CanHaveTraceIOModuleImp + with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp + with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp with sifive.blocks.devices.spi.HasPeripherySPIModuleImp + with chipyard.example.CanHavePeripheryGCDModuleImp + with freechips.rocketchip.util.DontTouch + +// ------------------------------------ +// VCU118 Chipyard System +// ------------------------------------ + +class VCU118ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem + with HasAsyncExtInterrupts + with CanHaveMasterTLMemPort // expose a TL port for outer memory (replaces AXI outer port) + with CanHaveMasterAXI4MMIOPort + with CanHaveSlaveAXI4Port +{ + + val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } + val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } + override lazy val module = new VCU118ChipyardSystemModule(this) +} + +class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer) + with HasRTCModuleImp + with HasExtInterruptsModuleImp + with DontTouch + +// ------------------------------------ +// VCU118 Mem Port Mixin +// ------------------------------------ /** Adds a TileLink port to the system intended to master an MMIO device bus */ trait CanHaveMasterTLMemPort { this: BaseSubsystem => diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index f8906e04..bd20ddc7 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -23,6 +23,7 @@ import freechips.rocketchip.util.{DontTouch} */ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem with HasAsyncExtInterrupts + with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort with CanHaveSlaveAXI4Port { From 255e88fe8f8a0ee5e2b648403d0d6b872d75e1d1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 17:06:34 -0800 Subject: [PATCH 043/157] Initial outline of FPGA prototyping docs --- docs/Chipyard-Basics/Chipyard-Components.rst | 11 ++- docs/Simulation/FPGA-Prototyping.rst | 87 ++++++++++++++++++++ docs/Simulation/index.rst | 11 ++- fpga/src/main/scala/vcu118/Configs.scala | 2 + fpga/src/main/scala/vcu118/TestHarness.scala | 2 + 5 files changed, 107 insertions(+), 6 deletions(-) create mode 100644 docs/Simulation/FPGA-Prototyping.rst diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index c24f81ed..1d19a65f 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -106,12 +106,12 @@ Software Sims ------------------------------------------- -**verilator (Verilator wrapper)** +**Verilator** Verilator is an open source Verilog simulator. The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). See :ref:`Verilator (Open-Source)` for more information. -**vcs (VCS wrapper)** +**VCS** VCS is a proprietary Verilog simulator. Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). See :ref:`Synopsys VCS (License Required)` for more information. @@ -124,6 +124,13 @@ Sims In order to use FireSim, the repository must be cloned and executed on AWS instances. See :ref:`FireSim` for more information. +**FPGA Prototyping** + FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``. + Some examples of FPGA's supported are Arty and VCU118. + For more accurate and deterministic simulation results, please consider using the :ref:`FireSim` platform. + See :ref:`FPGA Prototyping` for more information. + + VLSI ------------------------------------------- diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst new file mode 100644 index 00000000..eab33d35 --- /dev/null +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -0,0 +1,87 @@ +FPGA Prototyping +============================== + +FPGA Prototyping +----------------------- + +Chipyard supports FPGA prototyping for local FPGAs supported under ``fpga-shells`` . +This include popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. +FPGA prototyping allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times. + +Setup +----- + +All FPGA related collateral is located in the ``fpga`` top-level Chipyard folder. +To initialize the ``fpga-shells`` repository, run the included submodule script: + +.. code-block:: shell + + # in the chipyard top level folder + ./scripts/init-fpga.sh + +Making a Bitstream +------------------ + +Making a bitstream for any FPGA is similar to building RTL for a software RTL simulation. +Similar to the :ref:`Simulating A Custom Project` section in the :ref:`Software RTL Simulation` section you can run the following command in the ``fpga`` directory. + +.. code-block:: shell + + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... bit + + # or + + make SUB_PROJECT= bit + +By default a couple of ``SUB_PROJECT``'s are already defined for use, including ``vcu118`` and ``arty``. +These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more. +In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to. +For example, building the BOOM configuration on the VCU118: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config + +Running a Design on Arty +------------------------ + +Running a Design on VCU118 +-------------------------- + +Basic Design +~~~~~~~~~~~~ + +The default VCU118 design is setup to run RISC-V Linux from an SDCard while piping the terminal over UART. +To change the design, you can create your own configuration and add the ``AbstractVCU118Config`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. +Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory. +Notice that the majority of config. fragments in ``AbstractVCU118Config`` are shared with a normal Chipyard config. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala + :language: scala + :start-after: DOC include start: AbstractVCU118 and Rocket + :end-before: DOC include end: AbstractVCU118 and Rocket + +fpga-shells / Overlays / HarnessBinders +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To make meaningful VCU118 changes (adding new IOs, connecting to different VCU118 ports, etc), the ``VCU118TestHarness`` must change. +The ``VCU118TestHarness`` uses ``fpga-shells`` to add ``Overlays`` that connect to the VCU118 external IOs. +``fpga/src/main/scala/vcu118/TestHarness.scala`` shows an example of using these ``Overlays``. +First ``Overlays`` must be "placed" which adds them to the design. +For example, the following shows a UART overlay being placed into the design. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala + :language: scala + :start-after: DOC include start: UartOverlay + :end-before: DOC include end: UartOverlay + +Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART. +The ``UARTDesignInput`` is used to pass in the UART signals used to connect to the external UART IO. +This is similar to all the other ``Overlays``. +They must be "placed" and given a set of inputs (IOs, parameters). + +Once you add the wanted ``Overlays`` and place them into a new ``TestHarness``, you can add a new set of harness/io binders to connect to them. +This is shown in ``fpga/src/main/scala/vcu118/HarnessBinders.scala``. +For more information on harness and IO binders, refer to :ref:`IOBinders and HarnessBinders`. + +An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index c15283d3..24099bfb 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,16 +1,18 @@ Simulation ======================= -Chipyard supports two classes of simulation: +Chipyard supports three classes of simulation: -#. Software RTL simulation using commercial or open-source (Verilator) RTL simulators +#. Software RTL simulation using commercial or open-source (Verilator) RTL simulators #. FPGA-accelerated full-system simulation using FireSim +#. FPGA prototyping on ``fpga-shells`` platforms Software RTL simulators of Chipyard designs run at O(1 KHz), but compile -quickly and provide full waveforms. Conversly, FPGA-accelerated simulators run +quickly and provide full waveforms. Conversely, FPGA-accelerated simulators and FPGA prototyping run at O(100 MHz), making them appropriate for booting an operating system and running a complete workload, but have multi-hour compile times and poorer debug -visability. +visibility. However, FPGA-accelerated simulators differ from FPGA prototyping by providing deterministic +cycle-accurate results. Click next to see how to run a simulation. @@ -20,4 +22,5 @@ Click next to see how to run a simulation. Software-RTL-Simulation FPGA-Accelerated-Simulation + FPGA-Prototyping diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index f55c9520..6822b251 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -48,6 +48,7 @@ class WithSystemModifications extends Config((site, here, up) => { case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) }) +// DOC include start: AbstractVCU118 and Rocket class AbstractVCU118Config extends Config( new WithUART ++ new WithSPISDCard ++ @@ -72,6 +73,7 @@ class AbstractVCU118Config extends Config( class RocketVCU118Config extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new AbstractVCU118Config) +// DOC include end: AbstractVCU118 and Rocket class BoomVCU118Config extends Config( new WithFPGAFrequency(75) ++ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index d5a5481e..05e1e59d 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -70,10 +70,12 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S /*** UART ***/ +// DOC include start: UartOverlay // 1st UART goes to the VCU118 dedicated UART val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) +// DOC include end: UartOverlay /*** SPI ***/ From 9a5b67bf8c3a65e67cacd24616730f3c406c2ba1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 20:30:49 -0800 Subject: [PATCH 044/157] Use Chipyard configs as a base (VCU118) --- fpga/src/main/scala/vcu118/Configs.scala | 28 ++++++++----------- .../main/scala/vcu118/bringup/Configs.scala | 13 +++++---- .../scala/vcu118/bringup/TestHarness.scala | 2 +- .../main/scala/config/AbstractConfig.scala | 2 +- 4 files changed, 21 insertions(+), 24 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index f55c9520..aee3c489 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -15,6 +15,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import testchipip.{SerialTLKey} + import chipyard.{BuildSystem} class WithDefaultPeripherals extends Config((site, here, up) => { @@ -45,10 +47,11 @@ class WithSystemModifications extends Config((site, here, up) => { require (make.! == 0, "Failed to build bootrom") p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") } - case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size + case SerialTLKey => None // remove serialized tl port }) -class AbstractVCU118Config extends Config( +class WithVCU118Tweaks extends Config( new WithUART ++ new WithSPISDCard ++ new WithDDRMem ++ @@ -56,27 +59,18 @@ class AbstractVCU118Config extends Config( new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size + new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new chipyard.WithMulticlockCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) class RocketVCU118Config extends Config( - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new AbstractVCU118Config) + new WithVCU118Tweaks ++ + new chipyard.RocketConfig) class BoomVCU118Config extends Config( new WithFPGAFrequency(75) ++ - new boom.common.WithNLargeBooms(1) ++ - new AbstractVCU118Config) + new WithVCU118Tweaks ++ + new chipyard.MegaBoomConfig) class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => { case FPGAFrequencyKey => MHz diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index fc5df5a1..133d2ae2 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -15,7 +15,7 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import chipyard.{BuildSystem} -import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config} +import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency} class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) @@ -51,9 +51,12 @@ class WithBringupAdditions extends Config( new WithBringupVCU118System) class RocketBringupConfig extends Config( - new WithBringupPeripherals ++ - new RocketVCU118Config) + new WithBringupAdditions ++ + new WithVCU118Tweaks ++ + new chipyard.RocketConfig) class BoomBringupConfig extends Config( - new WithBringupPeripherals ++ - new BoomVCU118Config) + new WithFPGAFrequency(75) ++ + new WithBringupAdditions ++ + new WithVCU118Tweaks ++ + new chipyard.MegaBoomConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 080f6189..8a4ae8fc 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -68,5 +68,5 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends } class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) { - val bringupOuter = _outer + lazy val bringupOuter = _outer } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 301c03d7..b1e873d1 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -49,6 +49,6 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system From b0fc0457aa63073b10b86d4cccb21e45d428fc8c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 20:44:48 -0800 Subject: [PATCH 045/157] Use Chipyard configs as base (Arty) --- fpga/src/main/scala/arty/Configs.scala | 29 +++++++------------ fpga/src/main/scala/arty/HarnessBinders.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 4 +++ 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 11cf0260..bc62bcf9 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -11,6 +11,8 @@ import freechips.rocketchip.tile._ import sifive.blocks.devices.uart._ +import testchipip.{SerialTLKey} + import chipyard.{BuildSystem} class WithDefaultPeripherals extends Config((site, here, up) => { @@ -22,29 +24,20 @@ class WithDefaultPeripherals extends Config((site, here, up) => { idcodePartNum = 0x000, idcodeManufId = 0x489, debugIdleCycles = 5) + case SerialTLKey => None // remove serialized tl port }) -class TinyRocketArtyConfig extends Config( +class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ new WithArtyResetHarnessBinder ++ - new chipyard.iobinders.WithDebugIOCells ++ - new chipyard.iobinders.WithUARTIOCells ++ new WithResetPassthrough ++ new WithDefaultPeripherals ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.With1TinyCore ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithIncoherentBusTopology) + +class TinyRocketArtyConfig extends Config( + new WithArtyTweaks ++ + new chipyard.TinyRocketConfig) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 408d2b7d..464d054a 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -59,7 +59,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ } }) -class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ +class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { withClockAndReset(th.clock_32MHz, th.ck_rst) { IOBUF(th.uart_txd_in, ports.head.txd) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index d413cc12..626700a5 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -10,6 +10,10 @@ class RocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) +class TinyRocketConfig extends Config( + new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core + new chipyard.config.AbstractConfig) + class HwachaRocketConfig extends Config( new chipyard.config.WithHwachaTest ++ new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator From 84508bee6e075db9181ed4ad2b3bc76a43852e91 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 21:51:25 -0800 Subject: [PATCH 046/157] More FPGA prototyping docs --- docs/Simulation/FPGA-Prototyping.rst | 74 +++++++++++++------- fpga/src/main/scala/vcu118/TestHarness.scala | 2 + 2 files changed, 51 insertions(+), 25 deletions(-) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index eab33d35..0594b132 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -2,16 +2,21 @@ FPGA Prototyping ============================== FPGA Prototyping ------------------------ +---------------- -Chipyard supports FPGA prototyping for local FPGAs supported under ``fpga-shells`` . -This include popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. +Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. +This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. FPGA prototyping allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times. -Setup ------ +.. Note:: While ``fpga-shells`` also supports Xilinx VC707 and some MicroSemi PolarFire boards, currently only the VCU118 and Arty boards are explicitly supported in Chipyard. + However, using the VCU118/Arty examples would be useful to see how to implement VC707/PolarFire support. -All FPGA related collateral is located in the ``fpga`` top-level Chipyard folder. +Sources and Submodule Setup +--------------------------- + +All FPGA related collateral and sources are located in the ``fpga`` top-level Chipyard folder. +This includes ``fpga-shells`` and the ``src`` folders that hold both Scala, TCL and other collateral. +However, the ``fpga-shells`` repository is not initialized by default. To initialize the ``fpga-shells`` repository, run the included submodule script: .. code-block:: shell @@ -22,8 +27,8 @@ To initialize the ``fpga-shells`` repository, run the included submodule script: Making a Bitstream ------------------ -Making a bitstream for any FPGA is similar to building RTL for a software RTL simulation. -Similar to the :ref:`Simulating A Custom Project` section in the :ref:`Software RTL Simulation` section you can run the following command in the ``fpga`` directory. +Making a bitstream for any FPGA target is similar to building RTL for a software RTL simulation. +Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream: .. code-block:: shell @@ -35,12 +40,16 @@ Similar to the :ref:`Simulating A Custom Project` section in the :ref:`Software By default a couple of ``SUB_PROJECT``'s are already defined for use, including ``vcu118`` and ``arty``. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more. +Like a software RTL simulation make invocation, all of the make variables can be overridden with user specific values (i.e. include the ``SUB_PROJECT`` with a ``CONFIG`` and ``CONFIG_PACKAGE`` override). In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to. For example, building the BOOM configuration on the VCU118: .. code-block:: shell - make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bit + +That command will build the RTL and generate a bitstream using Vivado. +However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL. Running a Design on Arty ------------------------ @@ -51,24 +60,24 @@ Running a Design on VCU118 Basic Design ~~~~~~~~~~~~ -The default VCU118 design is setup to run RISC-V Linux from an SDCard while piping the terminal over UART. -To change the design, you can create your own configuration and add the ``AbstractVCU118Config`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. -Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory. -Notice that the majority of config. fragments in ``AbstractVCU118Config`` are shared with a normal Chipyard config. +The default VCU118 FPGA target design is setup to have UART, a SPI SDCard, and DDR backing memory. +This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). +To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. +Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. .. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala :language: scala :start-after: DOC include start: AbstractVCU118 and Rocket :end-before: DOC include end: AbstractVCU118 and Rocket -fpga-shells / Overlays / HarnessBinders -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Brief Implementation Description + More Complicated Designs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -To make meaningful VCU118 changes (adding new IOs, connecting to different VCU118 ports, etc), the ``VCU118TestHarness`` must change. -The ``VCU118TestHarness`` uses ``fpga-shells`` to add ``Overlays`` that connect to the VCU118 external IOs. -``fpga/src/main/scala/vcu118/TestHarness.scala`` shows an example of using these ``Overlays``. -First ``Overlays`` must be "placed" which adds them to the design. -For example, the following shows a UART overlay being placed into the design. +The basis for a VCU118 design revolves around creating a special test harness to connect the external IOs to your Chipyard design. +This is done with the ``VCU118TestHarness`` in the basic default VCU118 FPGA target. +The ``VCU118TestHarness`` (located in ``fpga/src/main/scala/vcu118/TestHarness.scala``) uses ``Overlays`` that connect to the VCU118 external IOs. +Generally, the ``Overlays`` take an IO from the ``ChipTop`` (labeled as ``topDesign`` in the file) when "placed" and connect it to the external IO and generate necessary Vivado collateral. +For example, the following shows a UART ``Overlay`` being "placed" into the design with a IO input called ``io_uart_bb``. .. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala :language: scala @@ -76,12 +85,27 @@ For example, the following shows a UART overlay being placed into the design. :end-before: DOC include end: UartOverlay Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART. -The ``UARTDesignInput`` is used to pass in the UART signals used to connect to the external UART IO. -This is similar to all the other ``Overlays``. +The ``UARTDesignInput`` is used to pass in the UART IO from the ``ChipTop``/``topDesign`` to the ``Overlay``. +Note that the ``BundleBridgeSource`` can be viewed as a glorified wire (that is defined in the ``LazyModule`` scope). +This pattern is similar for all other ``Overlays`` in the test harness. They must be "placed" and given a set of inputs (IOs, parameters). +The main exception to this pattern is the ``Overlay`` used to generate the clock(s) for the FPGA. -Once you add the wanted ``Overlays`` and place them into a new ``TestHarness``, you can add a new set of harness/io binders to connect to them. -This is shown in ``fpga/src/main/scala/vcu118/HarnessBinders.scala``. -For more information on harness and IO binders, refer to :ref:`IOBinders and HarnessBinders`. +.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala + :language: scala + :start-after: DOC include start: ClockOverlay + :end-before: DOC include end: ClockOverlay + +Without going into too much detail, the clocks overlay is placed in the harness and a PLL node (``harnessSysPLL``) generates the necessary clocks specified by ``ClockSinkNodes``. +For ease of use, you can change the ``FPGAFrequencyKey`` to change the default clock frequency of the FPGA design. + +After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs. +This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). +For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`. An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. +This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. + +.. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. + For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. + See :ref:`Making a Bitstream` for information on the various make variables. diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 05e1e59d..ed4ba221 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -41,6 +41,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val topDesign = LazyModule(p(BuildTop)(dp)) +// DOC include start: ClockOverlay // place all clocks in the shell dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } @@ -59,6 +60,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val dutWrangler = LazyModule(new ResetWrangler) val dutGroup = ClockGroup() dutClock := dutWrangler.node := dutGroup := harnessSysPLL +// DOC include end: ClockOverlay // connect ref clock to dummy sink node ref_clock.get() match { From c721d897f3397506d120efa6c00fa530e34aa584 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 10:18:10 -0800 Subject: [PATCH 047/157] Point to SiFive license | Add require on Arty --- LICENSE.SiFive | 202 ++++++++++++++++++ .../src/main/resources/vcu118/sdboot/common.h | 1 + fpga/src/main/resources/vcu118/sdboot/head.S | 2 +- .../resources/vcu118/sdboot/include/bits.h | 2 +- .../resources/vcu118/sdboot/include/const.h | 2 +- .../vcu118/sdboot/include/devices/clint.h | 4 +- .../vcu118/sdboot/include/devices/gpio.h | 2 +- .../vcu118/sdboot/include/devices/plic.h | 2 +- .../vcu118/sdboot/include/devices/spi.h | 2 +- .../vcu118/sdboot/include/devices/uart.h | 2 +- .../sdboot/include/riscv_test_defaults.h | 2 +- .../vcu118/sdboot/include/sections.h | 2 +- .../resources/vcu118/sdboot/include/smp.h | 3 +- .../main/resources/vcu118/sdboot/kprintf.c | 2 +- .../main/resources/vcu118/sdboot/kprintf.h | 2 +- fpga/src/main/resources/vcu118/sdboot/sd.c | 2 +- fpga/src/main/scala/arty/HarnessBinders.scala | 2 + 17 files changed, 221 insertions(+), 15 deletions(-) create mode 100644 LICENSE.SiFive diff --git a/LICENSE.SiFive b/LICENSE.SiFive new file mode 100644 index 00000000..7e709337 --- /dev/null +++ b/LICENSE.SiFive @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright 2016-2017 SiFive, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/fpga/src/main/resources/vcu118/sdboot/common.h b/fpga/src/main/resources/vcu118/sdboot/common.h index 4f71e103..ccb9cd3b 100644 --- a/fpga/src/main/resources/vcu118/sdboot/common.h +++ b/fpga/src/main/resources/vcu118/sdboot/common.h @@ -1,3 +1,4 @@ +// See LICENSE.Sifive for license details. #ifndef _SDBOOT_COMMON_H #define _SDBOOT_COMMON_H diff --git a/fpga/src/main/resources/vcu118/sdboot/head.S b/fpga/src/main/resources/vcu118/sdboot/head.S index d871b824..c6653f7c 100644 --- a/fpga/src/main/resources/vcu118/sdboot/head.S +++ b/fpga/src/main/resources/vcu118/sdboot/head.S @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #include #include #include "common.h" diff --git a/fpga/src/main/resources/vcu118/sdboot/include/bits.h b/fpga/src/main/resources/vcu118/sdboot/include/bits.h index bfe656fe..216b698c 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/bits.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/bits.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _RISCV_BITS_H #define _RISCV_BITS_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/const.h b/fpga/src/main/resources/vcu118/sdboot/include/const.h index 8dcffbb0..8507e168 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/const.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/const.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. /* Derived from */ #ifndef _SIFIVE_CONST_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h index c2b05bae..08092cd4 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/clint.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SIFIVE_CLINT_H #define _SIFIVE_CLINT_H @@ -11,4 +11,4 @@ #define CLINT_MTIME 0xBFF8 #define CLINT_MTIME_size 0x8 -#endif /* _SIFIVE_CLINT_H */ +#endif /* _SIFIVE_CLINT_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h index f7f0acb4..76dcb9f0 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SIFIVE_GPIO_H #define _SIFIVE_GPIO_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h index 4d5b2d8d..eddcae98 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef PLIC_H #define PLIC_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h index 7118572a..85c10994 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SIFIVE_SPI_H #define _SIFIVE_SPI_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h b/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h index aecfd912..c3f6a532 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SIFIVE_UART_H #define _SIFIVE_UART_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h b/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h index a2dea3d4..c9212737 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _RISCV_TEST_DEFAULTS_H #define _RISCV_TEST_DEFAULTS_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/sections.h b/fpga/src/main/resources/vcu118/sdboot/include/sections.h index 6e1f0518..4ec1ef7e 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/sections.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/sections.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SECTIONS_H #define _SECTIONS_H diff --git a/fpga/src/main/resources/vcu118/sdboot/include/smp.h b/fpga/src/main/resources/vcu118/sdboot/include/smp.h index 145ceb37..d93e64b2 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/smp.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/smp.h @@ -1,3 +1,4 @@ +// See LICENSE.Sifive for license details. #ifndef SIFIVE_SMP #define SIFIVE_SMP #include "platform.h" @@ -14,7 +15,7 @@ #define NONSMP_HART 0 #endif -/* If your test cannot handle multiple-threads, use this: +/* If your test cannot handle multiple-threads, use this: * smp_disable(reg1) */ #define smp_disable(reg1, reg2) \ diff --git a/fpga/src/main/resources/vcu118/sdboot/kprintf.c b/fpga/src/main/resources/vcu118/sdboot/kprintf.c index 57627011..3e3f2185 100644 --- a/fpga/src/main/resources/vcu118/sdboot/kprintf.c +++ b/fpga/src/main/resources/vcu118/sdboot/kprintf.c @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #include #include #include diff --git a/fpga/src/main/resources/vcu118/sdboot/kprintf.h b/fpga/src/main/resources/vcu118/sdboot/kprintf.h index 26cc8055..a7a94866 100644 --- a/fpga/src/main/resources/vcu118/sdboot/kprintf.h +++ b/fpga/src/main/resources/vcu118/sdboot/kprintf.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #ifndef _SDBOOT_KPRINTF_H #define _SDBOOT_KPRINTF_H diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index bdd9d62a..47c87d5f 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -1,4 +1,4 @@ -// See LICENSE for license details. +// See LICENSE.Sifive for license details. #include #include diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 464d054a..ef7b1805 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -16,6 +16,8 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} class WithArtyResetHarnessBinder extends ComposeHarnessBinder({ (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => { + require(ports.size == 2) + withClockAndReset(th.clock_32MHz, th.ck_rst) { // Debug module reset th.dut_ndreset := ports(0) From b0eed5075f804990deb8346e33db6ab87aebed55 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Fri, 6 Nov 2020 10:57:55 -0800 Subject: [PATCH 048/157] [temp] start integrating tsi host widget --- .../main/scala/vcu118/bringup/Configs.scala | 29 ++++++++++ .../scala/vcu118/bringup/CustomOverlays.scala | 56 ++++++++++++++++++- .../scala/vcu118/bringup/DigitalTop.scala | 2 + .../main/scala/vcu118/bringup/IOBinders.scala | 14 +++++ generators/testchipip | 2 +- 5 files changed, 101 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 133d2ae2..4c6cd5ad 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -4,6 +4,8 @@ import math.min import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.diplomacy._ import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} @@ -13,6 +15,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} + import chipyard.{BuildSystem} import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency} @@ -34,6 +38,30 @@ class WithBringupPeripherals extends Config((site, here, up) => { List.empty[GPIOParams] } } + case PeripheryTSIHostKey => List( + TSIHostParams( + serialIfWidth = 4, + mmioBaseAddress = BigInt(0x64006000), + mmioSourceId = 1 << 13, // manager source + serdesParams = TSIHostSerdesParams( + clientPortParams = TLMasterPortParameters.v1( + clients = Seq(TLMasterParameters.v1( + name = "tl-tsi-host-serdes", + sourceId = IdRange(0, (1 << 13))))), + managerPortParams = TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), + regionType = RegionType.UNCACHED, + executable = true, + supportsGet = TransferSizes(1, 64), + supportsPutFull = TransferSizes(1, 64), + supportsPutPartial = TransferSizes(1, 64), + supportsAcquireT = TransferSizes(1, 64), + supportsAcquireB = TransferSizes(1, 64), + supportsArithmetic = TransferSizes(1, 64), + supportsLogical = TransferSizes(1, 64))), + endSinkId = 1 << 6, // manager sink + beatBytes = 8)))) }) class WithBringupVCU118System extends Config((site, here, up) => { @@ -45,6 +73,7 @@ class WithBringupAdditions extends Config( new WithBringupSPI ++ new WithBringupI2C ++ new WithBringupGPIO ++ + new WithTSITLIOPassthrough ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ new WithBringupPeripherals ++ diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index c0a96d3c..30a25afe 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -144,4 +144,58 @@ class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) } - +//case class TSIShellInput() +//case class TSIDesignInput( +// +// )( +// implicit val p: Parameters)extends DDRDesignInput +// +//abstract class TSIOverlay(val params: TSIOverlayParams) +// extends IOOverlay[TLTSIWithDDRIO, TLTSIHostWidget] +//{ +// implicit val p = params.p +// +// // instantiate the tsi host widget and setup necessary connections +// val (tlTsiHost, tlTsiMemNode) = TLTSIHostWidget.attach(TSIHostWidgetAttachParams(params.tsiHostParams, params.controlBus)) +// val tlTsiHostIONodeSink = tlTsiHost.ioNode.makeSink +// +// // instantiate the DDR +// val size = p(TSIMigDDRSize) +// val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(params.tsiHostParams.targetBaseAddress, size)) +// val mig = LazyModule(new XilinxVCU118MIG(migParams)) +// val tsiIONode = BundleBridgeSource(() => new TSIHostWidgetIO(params.tsiHostParams.serialIfWidth)) +// val topTSIIONode = shell { tsiIONode.makeSink() } +// val ddrIONode = BundleBridgeSource(() => mig.module.io.cloneType) +// val topDDRIONode = shell { ddrIONode.makeSink() } +// val ddrUI = shell { ClockSourceNode(freqMHz = 200) } +// val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } +// areset := params.ddrParams.wrangler := ddrUI +// val asyncSink = LazyModule(new TLAsyncCrossingSink) +// val migClockReset = BundleBridgeSource(() => new Bundle { +// val clock = Output(Clock()) +// val reset = Output(Bool()) +// }) +// val migClockResetTop = shell { migClockReset.makeSink() } +// +// // connect them +// (mig.node := TLFragmenter(32,64,holdFirstDeny=true) := TLCacheCork() := TLSinkSetter(1 << 1) := TLSourceShrinker(1 << 4) := tlTsiMemNode) +// +// def designOutput = tlTsiHost +// def ioFactory = new TLTSIWithDDRIO(params.tsiHostParams.serialIfWidth, size) // top level io of the shell +// +// InModuleBody { +// val (t, _) = tsiIONode.out(0) +// val tsi = tlTsiHostIONodeSink.bundle +// tsi.serial_clock := t.serial_clock +// tsi.serial.in.bits := t.serial.in.bits +// tsi.serial.in.valid := t.serial.in.valid +// tsi.serial.out.ready := t.serial.out.ready +// t.serial.out.bits := tsi.serial.out.bits +// t.serial.out.valid := tsi.serial.out.valid +// t.serial.in.ready := tsi.serial.in.ready +// ddrIONode.bundle <> mig.module.io +// asyncSink.module.clock := migClockReset.bundle.clock +// asyncSink.module.reset := migClockReset.bundle.reset +// } +//} +// diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index ddcfe163..a9105e26 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -17,9 +17,11 @@ import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop with sifive.blocks.devices.i2c.HasPeripheryI2C + with testchipip.HasPeripheryTSIHostWidget { override lazy val module = new BringupVCU118DigitalTopModule(this) } class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l) with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp + with testchipip.HasPeripheryTSIHostWidgetModuleImp diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index 168933f7..32badd2a 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -3,9 +3,14 @@ package chipyard.fpga.vcu118.bringup import chisel3._ import chisel3.experimental.{IO, DataMirror} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} +import testchipip.{HasPeripheryTSIHostWidget} + import chipyard.iobinders.{OverrideIOBinder} class WithGPIOIOPassthrough extends OverrideIOBinder({ @@ -27,3 +32,12 @@ class WithI2CIOPassthrough extends OverrideIOBinder({ (io_i2c_pins_temp, Nil) } }) + +class WithTSITLIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryTSIHostWidget) => { + require(system.tsiMem.size == 1) + val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiMem.head)).suggestName("tsi_tl_slave") + io_tsi_tl_mem_pins_temp <> system.tsiMem.head + (Seq(io_tsi_tl_mem_pins_temp), Nil) + } +}) diff --git a/generators/testchipip b/generators/testchipip index 03af7aa5..5dae68ef 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 03af7aa53988dd96dffd613d1d50a5c6661e0a82 +Subproject commit 5dae68efbc925d09c6a8758064e88f6a3661baa2 From b7ef84860583bca6948f14d1518235077454de71 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 11:13:27 -0800 Subject: [PATCH 049/157] Add some docs on debugging --- docs/Simulation/FPGA-Prototyping.rst | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index 0594b132..ba53a0b7 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -109,3 +109,19 @@ This example extends the default test harness and creates new ``Overlays`` to co .. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. See :ref:`Making a Bitstream` for information on the various make variables. + +Debugging with ILAs +~~~~~~~~~~~~~~~~~~~ + +Adding an ILA can be added to the design for debugging relevant signals. +First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). +Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). +After the changes are made, save the checkpoint and run the make invocation with the ``debug-bitstream`` target: +be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. +For example, running the bitstream build for an added ILA for a BOOM config.: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream + +For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. From 6aae66c54fe3653a3aeb294fa4bdd8843becd673 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 15:50:28 -0800 Subject: [PATCH 050/157] Add TSI Host Widget --- .../main/scala/vcu118/bringup/Configs.scala | 1 + .../scala/vcu118/bringup/CustomOverlays.scala | 208 +++++++++++++----- .../scala/vcu118/bringup/DigitalTop.scala | 2 - .../scala/vcu118/bringup/HarnessBinders.scala | 27 +++ .../main/scala/vcu118/bringup/IOBinders.scala | 14 +- .../scala/vcu118/bringup/TestHarness.scala | 26 +++ generators/testchipip | 2 +- 7 files changed, 217 insertions(+), 63 deletions(-) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 4c6cd5ad..f6e4880c 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -73,6 +73,7 @@ class WithBringupAdditions extends Config( new WithBringupSPI ++ new WithBringupI2C ++ new WithBringupGPIO ++ + new WithBringupTSIHost ++ new WithTSITLIOPassthrough ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 30a25afe..b138038d 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -4,10 +4,16 @@ import chisel3._ import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.tilelink.{TLInwardNode} import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.clocks._ +import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} + +import testchipip.{TSIHostParams, TSIHostWidgetIO} import chipyard.fpga.vcu118.{FMCPMap} @@ -144,58 +150,150 @@ class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) } -//case class TSIShellInput() -//case class TSIDesignInput( -// -// )( -// implicit val p: Parameters)extends DDRDesignInput -// -//abstract class TSIOverlay(val params: TSIOverlayParams) -// extends IOOverlay[TLTSIWithDDRIO, TLTSIHostWidget] -//{ -// implicit val p = params.p -// -// // instantiate the tsi host widget and setup necessary connections -// val (tlTsiHost, tlTsiMemNode) = TLTSIHostWidget.attach(TSIHostWidgetAttachParams(params.tsiHostParams, params.controlBus)) -// val tlTsiHostIONodeSink = tlTsiHost.ioNode.makeSink -// -// // instantiate the DDR -// val size = p(TSIMigDDRSize) -// val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(params.tsiHostParams.targetBaseAddress, size)) -// val mig = LazyModule(new XilinxVCU118MIG(migParams)) -// val tsiIONode = BundleBridgeSource(() => new TSIHostWidgetIO(params.tsiHostParams.serialIfWidth)) -// val topTSIIONode = shell { tsiIONode.makeSink() } -// val ddrIONode = BundleBridgeSource(() => mig.module.io.cloneType) -// val topDDRIONode = shell { ddrIONode.makeSink() } -// val ddrUI = shell { ClockSourceNode(freqMHz = 200) } -// val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } -// areset := params.ddrParams.wrangler := ddrUI -// val asyncSink = LazyModule(new TLAsyncCrossingSink) -// val migClockReset = BundleBridgeSource(() => new Bundle { -// val clock = Output(Clock()) -// val reset = Output(Bool()) -// }) -// val migClockResetTop = shell { migClockReset.makeSink() } -// -// // connect them -// (mig.node := TLFragmenter(32,64,holdFirstDeny=true) := TLCacheCork() := TLSinkSetter(1 << 1) := TLSourceShrinker(1 << 4) := tlTsiMemNode) -// -// def designOutput = tlTsiHost -// def ioFactory = new TLTSIWithDDRIO(params.tsiHostParams.serialIfWidth, size) // top level io of the shell -// -// InModuleBody { -// val (t, _) = tsiIONode.out(0) -// val tsi = tlTsiHostIONodeSink.bundle -// tsi.serial_clock := t.serial_clock -// tsi.serial.in.bits := t.serial.in.bits -// tsi.serial.in.valid := t.serial.in.valid -// tsi.serial.out.ready := t.serial.out.ready -// t.serial.out.bits := tsi.serial.out.bits -// t.serial.out.valid := tsi.serial.out.valid -// t.serial.in.ready := tsi.serial.in.ready -// ddrIONode.bundle <> mig.module.io -// asyncSink.module.clock := migClockReset.bundle.clock -// asyncSink.module.reset := migClockReset.bundle.reset -// } -//} -// +case class TSIHostShellInput() +case class TSIHostDesignInput( + wrangler: ClockAdapterNode, + corePLL: PLLNode, + tsiHostParams: TSIHostParams, + node: BundleBridgeSource[TSIHostWidgetIO], + vc7074gbdimm: Boolean = false + )( + implicit val p: Parameters) +case class TSIHostOverlayOutput(ddr: TLInwardNode) +trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] + +class TSIHostWithDDRIO(val w: Int, val size: BigInt) extends Bundle { + val tsi = new TSIHostWidgetIO(w) + val ddr = new XilinxVCU118MIGPads(size) +} + +case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil) + +abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput) + extends IOPlacedOverlay[IO, TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] +{ + implicit val p = di.p +} + +case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB +class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) + extends TSIHostPlacedOverlay[TSIHostWithDDRIO](name, designInput, shellInput) +{ + val size = p(TSIHostVCU118DDRSize) + + // connect the DDR + val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(di.tsiHostParams.targetBaseAddress, size)) + val mig = LazyModule(new XilinxVCU118MIG(migParams)) + val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) + val topIONode = shell { ioNode.makeSink() } + val ddrUI = shell { ClockSourceNode(freqMHz = 200) } + val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } + areset := designInput.wrangler := ddrUI + + // connect the TSI serial + val tlTsiSerialSink = di.node.makeSink() + val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.tsiHostParams.serialIfWidth)) + val topTSIIONode = shell { tsiIoNode.makeSink() } + + def overlayOutput = TSIHostOverlayOutput(ddr = mig.node) + def ioFactory = new TSIHostWithDDRIO(di.tsiHostParams.serialIfWidth, size) + + InModuleBody { + // connect MIG + ioNode.bundle <> mig.module.io + + // connect TSI serial + val tsiSourcePort = tsiIoNode.bundle + val tsiSinkPort = tlTsiSerialSink.bundle + tsiSinkPort.serial_clock := tsiSourcePort.serial_clock + tsiSourcePort.serial.out.bits := tsiSinkPort.serial.out.bits + tsiSourcePort.serial.out.valid := tsiSinkPort.serial.out.valid + tsiSinkPort.serial.out.ready := tsiSourcePort.serial.out.ready + tsiSinkPort.serial.in.bits := tsiSourcePort.serial.in.bits + tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid + tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready + } + + // connect the DDR port + shell { InModuleBody { + require (shell.sys_clock.get.isDefined, "Use of DDRVCU118Overlay depends on SysClockVCU118Overlay") + val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) + val (ui, _) = ddrUI.out(0) + val (ar, _) = areset.in(0) + val ddrPort = topIONode.bundle.port + io.ddr <> ddrPort + ui.clock := ddrPort.c0_ddr4_ui_clk + ui.reset := /*!ddrPort.mmcm_locked ||*/ ddrPort.c0_ddr4_ui_clk_sync_rst + ddrPort.c0_sys_clk_i := sys.clock.asUInt + ddrPort.sys_rst := sys.reset // pllReset + ddrPort.c0_ddr4_aresetn := !ar.reset + + // This was just copied from the SiFive example, but it's hard to follow. + // The pins are emitted in the following order: + // adr[0->13], we_n, cas_n, ras_n, bg, ba[0->1], reset_n, act_n, ck_c, ck_t, cke, cs_n, odt, dq[0->63], dqs_c[0->7], dqs_t[0->7], dm_dbi_n[0->7] + val allddrpins = Seq( + "AM27", "AL27", "AP26", "AP25", "AN28", "AM28", "AP28", "AP27", "AN26", "AM26", "AR28", "AR27", "AV25", "AT25", // adr[0->13] + "AV28", "AU26", "AV26", "AU27", // we_n, cas_n, ras_n, bg + "AR25", "AU28", // ba[0->1] + "BD35", "AN25", "AT27", "AT26", "AW28", "AY29", "BB29", // reset_n, act_n, ck_c, ck_t, cke, cs_n, odt + "BD30", "BE30", "BD32", "BE33", "BC33", "BD33", "BC31", "BD31", "BA32", "BB33", "BA30", "BA31", "AW31", "AW32", "AY32", "AY33", // dq[0->15] + "AV30", "AW30", "AU33", "AU34", "AT31", "AU32", "AU31", "AV31", "AR33", "AT34", "AT29", "AT30", "AP30", "AR30", "AN30", "AN31", // dq[16->31] + "BE34", "BF34", "BC35", "BC36", "BD36", "BE37", "BF36", "BF37", "BD37", "BE38", "BC39", "BD40", "BB38", "BB39", "BC38", "BD38", // dq[32->47] + "BB36", "BB37", "BA39", "BA40", "AW40", "AY40", "AY38", "AY39", "AW35", "AW36", "AU40", "AV40", "AU38", "AU39", "AV38", "AV39", // dq[48->63] + "BF31", "BA34", "AV29", "AP32", "BF35", "BF39", "BA36", "AW38", // dqs_c[0->7] + "BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7] + "BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7] + + (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + } } + + shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk)) +} + +class BringupTSIHostVCU118PlacedOverlay(override val shell: VCU118ShellBasicOverlays, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) + extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) +{ + // connect the TSI port + shell { InModuleBody { + // connect TSI signals + val tsiPort = topTSIIONode.bundle + io.tsi <> tsiPort + + require(di.tsiHostParams.serialIfWidth == 4) + + val clkIo = IOPin(io.tsi.serial_clock) + val packagePinsWithPackageIOs = Seq( + (FMCPMap("D8"), clkIo), + (FMCPMap("D17"), IOPin(io.tsi.serial.out.ready)), + (FMCPMap("D18"), IOPin(io.tsi.serial.out.valid)), + (FMCPMap("D11"), IOPin(io.tsi.serial.out.bits, 0)), + (FMCPMap("D12"), IOPin(io.tsi.serial.out.bits, 1)), + (FMCPMap("D14"), IOPin(io.tsi.serial.out.bits, 2)), + (FMCPMap("D15"), IOPin(io.tsi.serial.out.bits, 3)), + (FMCPMap("D26"), IOPin(io.tsi.serial.in.ready)), + (FMCPMap("D27"), IOPin(io.tsi.serial.in.valid)), + (FMCPMap("D20"), IOPin(io.tsi.serial.in.bits, 0)), + (FMCPMap("D21"), IOPin(io.tsi.serial.in.bits, 1)), + (FMCPMap("D23"), IOPin(io.tsi.serial.in.bits, 2)), + (FMCPMap("D24"), IOPin(io.tsi.serial.in.bits, 3))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + } } + + // Don't add an IOB to the clock + (packagePinsWithPackageIOs take 1) foreach { case (pin, io) => { + shell.xdc.addIOB(io) + } } + + shell.sdc.addClock("TSI_CLK", clkIo, 50) + shell.sdc.addGroup(pins = Seq(clkIo)) + shell.xdc.clockDedicatedRouteFalse(clkIo) + } } +} + +class BringupTSIHostVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: TSIHostShellInput)(implicit val valName: ValName) + extends TSIHostShellPlacer[VCU118ShellBasicOverlays] { + def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index a9105e26..42ea7af2 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -10,7 +10,6 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} - // ------------------------------------ // BringupVCU118 DigitalTop // ------------------------------------ @@ -24,4 +23,3 @@ class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l) with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp - with testchipip.HasPeripheryTSIHostWidgetModuleImp diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index 531b3c8d..02b821b4 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -3,11 +3,16 @@ package chipyard.fpga.vcu118.bringup import chisel3._ import chisel3.experimental.{Analog, IO, BaseModule} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} +import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} + import chipyard.{HasHarnessSignalReferences} import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} @@ -54,3 +59,25 @@ class WithBringupGPIO extends OverrideHarnessBinder({ } } } }) + +/*** TSI Host Widget ***/ +class WithBringupTSIHost extends OverrideHarnessBinder({ + (system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => { + th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { + require(ports.size == 2) // 1st goes to the TL mem, 2nd goes to the serial link + + ports.head match { case tlPort: HeterogeneousBag[TLBundle] => + val tsiBundles = vcu118th.bringupOuter.tsiDdrClient.out.map(_._1) + val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType))) + tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io } + tsiDdrClientBundle <> tlPort + } + + ports.last match { case serialPort: TSIHostWidgetIO => + vcu118th.bringupOuter.io_tsi_serial_bb.bundle <> serialPort + } + } } + } +}) + + diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index 32badd2a..87763cde 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} -import testchipip.{HasPeripheryTSIHostWidget} +import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} import chipyard.iobinders.{OverrideIOBinder} @@ -35,9 +35,13 @@ class WithI2CIOPassthrough extends OverrideIOBinder({ class WithTSITLIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryTSIHostWidget) => { - require(system.tsiMem.size == 1) - val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiMem.head)).suggestName("tsi_tl_slave") - io_tsi_tl_mem_pins_temp <> system.tsiMem.head - (Seq(io_tsi_tl_mem_pins_temp), Nil) + require(system.tsiTLMem.size == 1) + val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiTLMem.head)).suggestName("tsi_tl_slave") + io_tsi_tl_mem_pins_temp <> system.tsiTLMem.head + + require(system.tsiSerial.size == 1) + val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial") + io_tsi_serial_pins_temp <> system.tsiSerial.head + (Seq(io_tsi_tl_mem_pins_temp, io_tsi_serial_pins_temp), Nil) } }) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 8a4ae8fc..e3b4c137 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -17,8 +17,12 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ +import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter} + import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp} +import chipyard.{ChipTop} + class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness { /*** UART ***/ @@ -63,6 +67,28 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends placer.place(GPIODesignInput(params, io_gpio_bb(i))) } + /*** TSI Host Widget ***/ + require(dp(PeripheryTSIHostKey).size == 1) + + val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) + + val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) + val tsiDdrPlaced = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dutWrangler.node, harnessSysPLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)) + + // connect 1 mem. channel to the FPGA DDR + val inTsiParams = topDesign match { case td: ChipTop => + td.lazySystem match { case lsys: HasPeripheryTSIHostWidget => + lsys.tsiMemTLNodes.head.edges.in(0) + } + } + val tsiDdrClient = TLClientNode(Seq(inTsiParams.master)) + (tsiDdrPlaced.overlayOutput.ddr + := TLFragmenter(8,64,holdFirstDeny=true) + := TLCacheCork() + := TLAtomicAutomata(passthrough=false) + := TLSinkSetter(64) + := tsiDdrClient) + // module implementation override lazy val module = new BringupVCU118FPGATestHarnessImp(this) } diff --git a/generators/testchipip b/generators/testchipip index 5dae68ef..e956a60c 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 5dae68efbc925d09c6a8758064e88f6a3661baa2 +Subproject commit e956a60cbfd848c31bd849ffe0140eb0f9af2524 From 7baa1341ee221f8d3aa7feb1638508e9eed46575 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 16:34:45 -0800 Subject: [PATCH 051/157] Use 2nd system clock for TSI DDR | Small cleanups --- fpga/src/main/scala/vcu118/TestHarness.scala | 21 ++------ .../scala/vcu118/bringup/CustomOverlays.scala | 49 ++++++++++++++++--- .../scala/vcu118/bringup/TestHarness.scala | 14 +++++- 3 files changed, 59 insertions(+), 25 deletions(-) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index d5a5481e..39f389f8 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -42,17 +42,14 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val topDesign = LazyModule(p(BuildTop)(dp)) // place all clocks in the shell - dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } + require(dp(ClockInputOverlayKey).size >= 1) + val sys_clk_placed = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()) /*** Connect/Generate clocks ***/ // connect to the PLL that will generate multiple clocks val harnessSysPLL = dp(PLLFactoryKey)() - sys_clock.get() match { - case Some(x : SysClockVCU118PlacedOverlay) => { - harnessSysPLL := x.node - } - } + harnessSysPLL := sys_clk_placed.overlayOutput.node // create and connect to the dutClock val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) @@ -60,14 +57,6 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val dutGroup = ClockGroup() dutClock := dutWrangler.node := dutGroup := harnessSysPLL - // connect ref clock to dummy sink node - ref_clock.get() match { - case Some(x : RefClockVCU118PlacedOverlay) => { - val sink = ClockSinkNode(Seq(ClockSinkParameters())) - sink := x.node - } - } - /*** UART ***/ // 1st UART goes to the VCU118 dedicated UART @@ -110,9 +99,7 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod val reset_ibuf = Module(new IBUF) reset_ibuf.io.I := reset - val sysclk: Clock = _outer.sys_clock.get() match { - case Some(x: SysClockVCU118PlacedOverlay) => x.clock - } + val sysclk: Clock = _outer.sys_clk_placed.overlayOutput.node.out.head._1.clock val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) _outer.sdc.addAsyncPath(Seq(powerOnReset)) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index b138038d..23ed9f11 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -5,7 +5,7 @@ import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.tilelink.{TLInwardNode} +import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ @@ -176,7 +176,7 @@ abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHos } case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB -class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) +class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) extends TSIHostPlacedOverlay[TSIHostWithDDRIO](name, designInput, shellInput) { val size = p(TSIHostVCU118DDRSize) @@ -190,6 +190,14 @@ class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: Stri val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } areset := designInput.wrangler := ddrUI + // since this uses a separate clk/rst need to put an async crossing + val asyncSink = LazyModule(new TLAsyncCrossingSink()) + val migClkRstNode = BundleBridgeSource(() => new Bundle { + val clock = Output(Clock()) + val reset = Output(Bool()) + }) + val topMigClkRstIONode = shell { migClkRstNode.makeSink() } + // connect the TSI serial val tlTsiSerialSink = di.node.makeSink() val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.tsiHostParams.serialIfWidth)) @@ -202,6 +210,10 @@ class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: Stri // connect MIG ioNode.bundle <> mig.module.io + // setup async crossing + asyncSink.module.clock := migClkRstNode.bundle.clock + asyncSink.module.reset := migClkRstNode.bundle.reset + // connect TSI serial val tsiSourcePort = tsiIoNode.bundle val tsiSinkPort = tlTsiSerialSink.bundle @@ -216,10 +228,15 @@ class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: Stri // connect the DDR port shell { InModuleBody { - require (shell.sys_clock.get.isDefined, "Use of DDRVCU118Overlay depends on SysClockVCU118Overlay") - val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) + require (shell.sys_clock2.get.isDefined, "Use of TSIHostVCU118Overlay depends on SysClock2VCU118Overlay") + val (sys, _) = shell.sys_clock2.get.get.overlayOutput.node.out(0) val (ui, _) = ddrUI.out(0) val (ar, _) = areset.in(0) + + // connect the async fifo sink to sys_clock2 + topMigClkRstIONode.bundle.clock := sys.clock + topMigClkRstIONode.bundle.reset := sys.reset + val ddrPort = topIONode.bundle.port io.ddr <> ddrPort ui.clock := ddrPort.c0_ddr4_ui_clk @@ -250,7 +267,7 @@ class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: Stri shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk)) } -class BringupTSIHostVCU118PlacedOverlay(override val shell: VCU118ShellBasicOverlays, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) +class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) { // connect the TSI port @@ -293,7 +310,25 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: VCU118ShellBasicOver } } } -class BringupTSIHostVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: TSIHostShellInput)(implicit val valName: ValName) - extends TSIHostShellPlacer[VCU118ShellBasicOverlays] { +class BringupTSIHostVCU118ShellPlacer(shell: BringupVCU118FPGATestHarness, val shellInput: TSIHostShellInput)(implicit val valName: ValName) + extends TSIHostShellPlacer[BringupVCU118FPGATestHarness] { def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } + +class SysClock2VCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) + extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) +{ + val node = shell { ClockSourceNode(freqMHz = 250, jitterPS = 50)(ValName(name)) } + + shell { InModuleBody { + shell.xdc.addPackagePin(io.p, "AW26") + shell.xdc.addPackagePin(io.n, "AW27") + shell.xdc.addIOStandard(io.p, "DIFF_SSTL12") + shell.xdc.addIOStandard(io.n, "DIFF_SSTL12") + } } +} +class SysClock2VCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName) + extends ClockInputShellPlacer[VCU118ShellBasicOverlays] +{ + def place(designInput: ClockInputDesignInput) = new SysClock2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index e3b4c137..0fd51108 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -70,10 +70,22 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends /*** TSI Host Widget ***/ require(dp(PeripheryTSIHostKey).size == 1) + // use the 2nd system clock for the 2nd DDR + val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput())) + val sys_clk2_placed = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()) + + val ddr2PLL = dp(PLLFactoryKey)() + ddr2PLL := sys_clk2_placed.overlayOutput.node + + val ddrClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + val ddrWrangler = LazyModule(new ResetWrangler) + val ddrGroup = ClockGroup() + ddrClock := ddrWrangler.node := ddrGroup := ddr2PLL + val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) - val tsiDdrPlaced = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dutWrangler.node, harnessSysPLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)) + val tsiDdrPlaced = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)) // connect 1 mem. channel to the FPGA DDR val inTsiParams = topDesign match { case td: ChipTop => From 98fcea7b572e2c0456a9f74096cea3b2482997c9 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 6 Nov 2020 17:25:05 -0800 Subject: [PATCH 052/157] Adding initial Arty documentation; will be expanded further. --- docs/Simulation/FPGA-Prototyping.rst | 15 +++++++++++++++ fpga/src/main/scala/arty/Configs.scala | 3 ++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index ba53a0b7..ed07a7f4 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -54,6 +54,21 @@ However, like a software RTL simulation, you can also run the intermediate make Running a Design on Arty ------------------------ +Basic Design +~~~~~~~~~~~~ + +The default Arty FPGA target design is setup to have JTAG, UART, SPI, and I2C available over the board's GPIO pins. The pin mappings of these interfaces are identical to those described in the `SiFive Freedom E310 Arty Getting Started Guide `__. +The JTAG interface allows a user to connect to the core over OpenOCD, run bare-metal applications, and debug using gdb. +To extend this design, you can create your own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. +Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2C interfaces to your Chipyard design/config. + +.. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala + :language: scala + :start-after: DOC include start: AbstractArty and Rocket + :end-before: DOC include end: AbstractArty and Rocket + +Future peripherals to be supported include the Arty's SPI Flash EEPROM. + Running a Design on VCU118 -------------------------- diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index bc62bcf9..61a6234c 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -26,7 +26,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => { debugIdleCycles = 5) case SerialTLKey => None // remove serialized tl port }) - +// DOC include start: AbstractArty and Rocket class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ @@ -41,3 +41,4 @@ class WithArtyTweaks extends Config( class TinyRocketArtyConfig extends Config( new WithArtyTweaks ++ new chipyard.TinyRocketConfig) +// DOC include start: AbstractArty and Rocket From e20311da84d85178ad0a2b16fd0a642feb2bc4a5 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 6 Nov 2020 19:58:52 -0800 Subject: [PATCH 053/157] Adding implementation details for the Arty. --- docs/Simulation/FPGA-Prototyping.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index ed07a7f4..eacf3982 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -69,6 +69,12 @@ Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2 Future peripherals to be supported include the Arty's SPI Flash EEPROM. +Brief Implementation Description for Less Complicated Designs (Such as Arty), and Guidance for Adding/Changing Xilinx Collateral +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Like the VCU118, the basis for the Arty design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design. +This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlay``s, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlay``s, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinder``s and ssIOBinder``s. + Running a Design on VCU118 -------------------------- From 8fb76dda7babad128f76d121bfd77c5155fbfa24 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 6 Nov 2020 20:00:29 -0800 Subject: [PATCH 054/157] Fixed syntax. --- docs/Simulation/FPGA-Prototyping.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index eacf3982..6f82446e 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -73,7 +73,7 @@ Brief Implementation Description for Less Complicated Designs (Such as Arty), an ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Like the VCU118, the basis for the Arty design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design. -This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlay``s, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlay``s, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinder``s and ssIOBinder``s. +This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinders`` and ``IOBinders``. Running a Design on VCU118 -------------------------- From 9144e3c70640b6be54759a76768bbe3469d01c22 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Fri, 6 Nov 2020 20:51:11 -0800 Subject: [PATCH 055/157] Fix pin mappings for TSI DDR --- fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 23ed9f11..1881d821 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -261,7 +261,7 @@ class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: "BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7] "BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7] - (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + (IOPin.of(io.ddr) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } } } shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk)) From c5e8fecb5c88f762969ef8755cb3e8c708b360e5 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 21:00:18 -0800 Subject: [PATCH 056/157] Small renaming and cleanup --- fpga/src/main/scala/vcu118/TestHarness.scala | 16 ++++++++-------- .../main/scala/vcu118/bringup/TestHarness.scala | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 39f389f8..8b91c3ea 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -43,13 +43,13 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S // place all clocks in the shell require(dp(ClockInputOverlayKey).size >= 1) - val sys_clk_placed = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()) + val sysClkNode = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()).overlayOutput.node /*** Connect/Generate clocks ***/ // connect to the PLL that will generate multiple clocks val harnessSysPLL = dp(PLLFactoryKey)() - harnessSysPLL := sys_clk_placed.overlayOutput.node + harnessSysPLL := sysClkNode // create and connect to the dutClock val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) @@ -73,7 +73,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S /*** DDR ***/ - val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)) + val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr // connect 1 mem. channel to the FPGA DDR val inParams = topDesign match { case td: ChipTop => @@ -82,7 +82,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } } val ddrClient = TLClientNode(Seq(inParams.master)) - ddrPlaced.overlayOutput.ddr := ddrClient + ddrNode := ddrClient // module implementation override lazy val module = new VCU118FPGATestHarnessImp(this) @@ -96,10 +96,10 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod _outer.xdc.addPackagePin(reset, "L19") _outer.xdc.addIOStandard(reset, "LVCMOS12") - val reset_ibuf = Module(new IBUF) - reset_ibuf.io.I := reset + val resetIBUF = Module(new IBUF) + resetIBUF.io.I := reset - val sysclk: Clock = _outer.sys_clk_placed.overlayOutput.node.out.head._1.clock + val sysclk: Clock = _outer.sysClkNode.out.head._1.clock val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) _outer.sdc.addAsyncPath(Seq(powerOnReset)) @@ -109,7 +109,7 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod case _ => false.B } - _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset) + _outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset) // reset setup val hReset = Wire(Reset()) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 0fd51108..95025dc7 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -72,10 +72,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends // use the 2nd system clock for the 2nd DDR val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput())) - val sys_clk2_placed = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()) + val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node val ddr2PLL = dp(PLLFactoryKey)() - ddr2PLL := sys_clk2_placed.overlayOutput.node + ddr2PLL := sysClk2Node val ddrClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) val ddrWrangler = LazyModule(new ResetWrangler) @@ -85,7 +85,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) - val tsiDdrPlaced = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)) + val tsiDdrNode = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)).overlayOutput.ddr // connect 1 mem. channel to the FPGA DDR val inTsiParams = topDesign match { case td: ChipTop => @@ -94,7 +94,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends } } val tsiDdrClient = TLClientNode(Seq(inTsiParams.master)) - (tsiDdrPlaced.overlayOutput.ddr + (tsiDdrNode := TLFragmenter(8,64,holdFirstDeny=true) := TLCacheCork() := TLAtomicAutomata(passthrough=false) From 9c12ce08b7f309fa19d8196d688d5dd70f82c71b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 7 Nov 2020 17:05:39 -0800 Subject: [PATCH 057/157] Create new prototyping section | Address some comments | Small clarifications --- docs/Chipyard-Basics/Chipyard-Components.rst | 10 +- docs/Prototyping/Arty.rst | 28 ++++ docs/Prototyping/General.rst | 68 +++++++++ docs/Prototyping/VCU118.rst | 55 +++++++ docs/Prototyping/index.rst | 17 +++ docs/Simulation/FPGA-Prototyping.rst | 148 ------------------- docs/Simulation/index.rst | 10 +- docs/index.rst | 2 + 8 files changed, 179 insertions(+), 159 deletions(-) create mode 100644 docs/Prototyping/Arty.rst create mode 100644 docs/Prototyping/General.rst create mode 100644 docs/Prototyping/VCU118.rst create mode 100644 docs/Prototyping/index.rst delete mode 100644 docs/Simulation/FPGA-Prototyping.rst diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 1d19a65f..3e45f99f 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -124,12 +124,14 @@ Sims In order to use FireSim, the repository must be cloned and executed on AWS instances. See :ref:`FireSim` for more information. +Prototyping +------------------------------------------- + **FPGA Prototyping** FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``. - Some examples of FPGA's supported are Arty and VCU118. - For more accurate and deterministic simulation results, please consider using the :ref:`FireSim` platform. - See :ref:`FPGA Prototyping` for more information. - + Some examples of FPGAs supported are the Arty and VCU118 boards. + To instead do an fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform. + See :ref:`Prototyping Flow` for more information on FPGA prototypes. VLSI ------------------------------------------- diff --git a/docs/Prototyping/Arty.rst b/docs/Prototyping/Arty.rst new file mode 100644 index 00000000..fe36a4ef --- /dev/null +++ b/docs/Prototyping/Arty.rst @@ -0,0 +1,28 @@ +Running a Design on Arty +======================== + +Basic Design +------------ + +The default Arty FPGA target design is setup to have JTAG, UART, SPI, and I2C available over the board's GPIO pins. +The pin mappings of these interfaces are identical to those described in the `SiFive Freedom E310 Arty Getting Started Guide `__. +The JTAG interface allows a user to connect to the core over OpenOCD, run bare-metal applications, and debug using gdb. +To extend this design, you can create your own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. +Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2C interfaces to your Chipyard design/config. + +.. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala + :language: scala + :start-after: DOC include start: AbstractArty and Rocket + :end-before: DOC include end: AbstractArty and Rocket + +Future peripherals to be supported include the Arty's SPI Flash EEPROM. + +Brief Implementation Description and Guidance for Adding/Changing Xilinx Collateral +----------------------------------------------------------------------------------- + +The basis for the Arty design is the creation of a special test harness that connects the external FPGA IO (which exist as Xilinx IP blackboxes) to the Chipyard design. +This is done with the ``ArtyTestHarness`` in the basic default Arty target. +However, unlike the more complicated ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects ``ChipTop`` IO to the ports of the external FPGA IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. +Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. +If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. +The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the ``ChipTop`` using ``HarnessBinders`` and ``IOBinders``. diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst new file mode 100644 index 00000000..d27cd66a --- /dev/null +++ b/docs/Prototyping/General.rst @@ -0,0 +1,68 @@ +General Setup and Usage +============================== + +Sources and Submodule Setup +--------------------------- + +All FPGA related collateral and sources are located in the ``fpga`` top-level Chipyard directory. +This includes the ``fpga-shells`` submodule and the ``src`` directory that hold both Scala, TCL and other collateral. +However, the ``fpga-shells`` submodule repository is not initialized by default. +To initialize the ``fpga-shells`` submodule repository, run the included initialization script from the Chipyard top-level directory: + +.. code-block:: shell + + # in the chipyard top level folder + ./scripts/init-fpga.sh + +Generating a Bitstream +------------------ + +Generating a bitstream for any FPGA target using Vivado is similar to building RTL for a software RTL simulation. +Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado: + +.. code-block:: shell + + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... bit + + # or + + make SUB_PROJECT= bit + +The ``SUB_PROJECT`` make variable is a way to meta make variable that sets all of the other make variables to a specific default. +For example: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 bit + + # converts to + + make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 bit + +Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``. +These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system. +Like a software RTL simulation make invocation, all of the make variables can be overridden with user specific values (ex. include the ``SUB_PROJECT`` with a ``CONFIG`` and ``CONFIG_PACKAGE`` override). +In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to. +For example, building the BOOM configuration on the VCU118: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bit + +That command will build the RTL and generate a bitstream using Vivado. +However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL. + +Debugging with ILAs on Supported FPGAs +-------------------------------------- + +Adding an ILA (integrated logic analyzer) can be added to certain designs for debugging relevant signals. +First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). +Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). +This can be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. +For example, running the bitstream build for an added ILA for a BOOM config.: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream + +For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst new file mode 100644 index 00000000..a23b487e --- /dev/null +++ b/docs/Prototyping/VCU118.rst @@ -0,0 +1,55 @@ +Running a Design on VCU118 +========================== + +Basic Design +------------ + +The default VCU118 FPGA target design is setup to have UART, a SPI SDCard, and DDR backing memory. +This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). +To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. +Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala + :language: scala + :start-after: DOC include start: AbstractVCU118 and Rocket + :end-before: DOC include end: AbstractVCU118 and Rocket + +Brief Implementation Description + More Complicated Designs +----------------------------------------------------------- + +The basis for a VCU118 design revolves around creating a special test harness to connect the external IOs to your Chipyard design. +This is done with the ``VCU118TestHarness`` in the basic default VCU118 FPGA target. +The ``VCU118TestHarness`` (located in ``fpga/src/main/scala/vcu118/TestHarness.scala``) uses ``Overlays`` that connect to the VCU118 external IOs. +Generally, the ``Overlays`` take an IO from the ``ChipTop`` (labeled as ``topDesign`` in the file) when "placed" and connect it to the external IO and generate necessary Vivado collateral. +For example, the following shows a UART ``Overlay`` being "placed" into the design with a IO input called ``io_uart_bb``. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala + :language: scala + :start-after: DOC include start: UartOverlay + :end-before: DOC include end: UartOverlay + +Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART. +The ``UARTDesignInput`` is used to pass in the UART IO from the ``ChipTop``/``topDesign`` to the ``Overlay``. +Note that the ``BundleBridgeSource`` can be viewed as a glorified wire (that is defined in the ``LazyModule`` scope). +This pattern is similar for all other ``Overlays`` in the test harness. +They must be "placed" and given a set of inputs (IOs, parameters). +The main exception to this pattern is the ``Overlay`` used to generate the clock(s) for the FPGA. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala + :language: scala + :start-after: DOC include start: ClockOverlay + :end-before: DOC include end: ClockOverlay + +Without going into too much detail, the clocks overlay is placed in the harness and a PLL node (``harnessSysPLL``) generates the necessary clocks specified by ``ClockSinkNodes``. +For ease of use, you can change the ``FPGAFrequencyKey`` to change the default clock frequency of the FPGA design. + +After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs. +This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). +For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`. + +An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. +This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. + +.. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. + For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. + See :ref:`Making a Bitstream` for information on the various make variables. diff --git a/docs/Prototyping/index.rst b/docs/Prototyping/index.rst new file mode 100644 index 00000000..695c588f --- /dev/null +++ b/docs/Prototyping/index.rst @@ -0,0 +1,17 @@ +Prototyping Flow +================ + +Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. +This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. +FPGA prototyping allows for orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times and less design introspection. + +.. Note:: While ``fpga-shells`` also supports Xilinx VC707 and some MicroSemi PolarFire boards, currently only the VCU118 and Arty boards are explicitly supported in Chipyard. + However, using the VCU118/Arty examples would be useful to see how to implement VC707/PolarFire support. + +.. toctree:: + :maxdepth: 2 + :caption: Prototyping Flow: + + General + VCU118 + Arty diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst deleted file mode 100644 index 6f82446e..00000000 --- a/docs/Simulation/FPGA-Prototyping.rst +++ /dev/null @@ -1,148 +0,0 @@ -FPGA Prototyping -============================== - -FPGA Prototyping ----------------- - -Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. -This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. -FPGA prototyping allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times. - -.. Note:: While ``fpga-shells`` also supports Xilinx VC707 and some MicroSemi PolarFire boards, currently only the VCU118 and Arty boards are explicitly supported in Chipyard. - However, using the VCU118/Arty examples would be useful to see how to implement VC707/PolarFire support. - -Sources and Submodule Setup ---------------------------- - -All FPGA related collateral and sources are located in the ``fpga`` top-level Chipyard folder. -This includes ``fpga-shells`` and the ``src`` folders that hold both Scala, TCL and other collateral. -However, the ``fpga-shells`` repository is not initialized by default. -To initialize the ``fpga-shells`` repository, run the included submodule script: - -.. code-block:: shell - - # in the chipyard top level folder - ./scripts/init-fpga.sh - -Making a Bitstream ------------------- - -Making a bitstream for any FPGA target is similar to building RTL for a software RTL simulation. -Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream: - -.. code-block:: shell - - make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... bit - - # or - - make SUB_PROJECT= bit - -By default a couple of ``SUB_PROJECT``'s are already defined for use, including ``vcu118`` and ``arty``. -These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more. -Like a software RTL simulation make invocation, all of the make variables can be overridden with user specific values (i.e. include the ``SUB_PROJECT`` with a ``CONFIG`` and ``CONFIG_PACKAGE`` override). -In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to. -For example, building the BOOM configuration on the VCU118: - -.. code-block:: shell - - make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bit - -That command will build the RTL and generate a bitstream using Vivado. -However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL. - -Running a Design on Arty ------------------------- - -Basic Design -~~~~~~~~~~~~ - -The default Arty FPGA target design is setup to have JTAG, UART, SPI, and I2C available over the board's GPIO pins. The pin mappings of these interfaces are identical to those described in the `SiFive Freedom E310 Arty Getting Started Guide `__. -The JTAG interface allows a user to connect to the core over OpenOCD, run bare-metal applications, and debug using gdb. -To extend this design, you can create your own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. -Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2C interfaces to your Chipyard design/config. - -.. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala - :language: scala - :start-after: DOC include start: AbstractArty and Rocket - :end-before: DOC include end: AbstractArty and Rocket - -Future peripherals to be supported include the Arty's SPI Flash EEPROM. - -Brief Implementation Description for Less Complicated Designs (Such as Arty), and Guidance for Adding/Changing Xilinx Collateral -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Like the VCU118, the basis for the Arty design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design. -This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinders`` and ``IOBinders``. - -Running a Design on VCU118 --------------------------- - -Basic Design -~~~~~~~~~~~~ - -The default VCU118 FPGA target design is setup to have UART, a SPI SDCard, and DDR backing memory. -This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). -To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. -Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. - -.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala - :language: scala - :start-after: DOC include start: AbstractVCU118 and Rocket - :end-before: DOC include end: AbstractVCU118 and Rocket - -Brief Implementation Description + More Complicated Designs -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The basis for a VCU118 design revolves around creating a special test harness to connect the external IOs to your Chipyard design. -This is done with the ``VCU118TestHarness`` in the basic default VCU118 FPGA target. -The ``VCU118TestHarness`` (located in ``fpga/src/main/scala/vcu118/TestHarness.scala``) uses ``Overlays`` that connect to the VCU118 external IOs. -Generally, the ``Overlays`` take an IO from the ``ChipTop`` (labeled as ``topDesign`` in the file) when "placed" and connect it to the external IO and generate necessary Vivado collateral. -For example, the following shows a UART ``Overlay`` being "placed" into the design with a IO input called ``io_uart_bb``. - -.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala - :language: scala - :start-after: DOC include start: UartOverlay - :end-before: DOC include end: UartOverlay - -Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART. -The ``UARTDesignInput`` is used to pass in the UART IO from the ``ChipTop``/``topDesign`` to the ``Overlay``. -Note that the ``BundleBridgeSource`` can be viewed as a glorified wire (that is defined in the ``LazyModule`` scope). -This pattern is similar for all other ``Overlays`` in the test harness. -They must be "placed" and given a set of inputs (IOs, parameters). -The main exception to this pattern is the ``Overlay`` used to generate the clock(s) for the FPGA. - -.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala - :language: scala - :start-after: DOC include start: ClockOverlay - :end-before: DOC include end: ClockOverlay - -Without going into too much detail, the clocks overlay is placed in the harness and a PLL node (``harnessSysPLL``) generates the necessary clocks specified by ``ClockSinkNodes``. -For ease of use, you can change the ``FPGAFrequencyKey`` to change the default clock frequency of the FPGA design. - -After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs. -This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). -For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`. - -An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. -This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. - -.. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. - For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. - See :ref:`Making a Bitstream` for information on the various make variables. - -Debugging with ILAs -~~~~~~~~~~~~~~~~~~~ - -Adding an ILA can be added to the design for debugging relevant signals. -First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). -Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). -After the changes are made, save the checkpoint and run the make invocation with the ``debug-bitstream`` target: -be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. -For example, running the bitstream build for an added ILA for a BOOM config.: - -.. code-block:: shell - - make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream - -For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index 24099bfb..9be1b2c9 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,18 +1,16 @@ Simulation ======================= -Chipyard supports three classes of simulation: +Chipyard supports two classes of simulation: #. Software RTL simulation using commercial or open-source (Verilator) RTL simulators #. FPGA-accelerated full-system simulation using FireSim -#. FPGA prototyping on ``fpga-shells`` platforms Software RTL simulators of Chipyard designs run at O(1 KHz), but compile -quickly and provide full waveforms. Conversely, FPGA-accelerated simulators and FPGA prototyping run +quickly and provide full waveforms. Conversely, FPGA-accelerated simulators run at O(100 MHz), making them appropriate for booting an operating system and running a complete workload, but have multi-hour compile times and poorer debug -visibility. However, FPGA-accelerated simulators differ from FPGA prototyping by providing deterministic -cycle-accurate results. +visibility. Click next to see how to run a simulation. @@ -22,5 +20,3 @@ Click next to see how to run a simulation. Software-RTL-Simulation FPGA-Accelerated-Simulation - FPGA-Prototyping - diff --git a/docs/index.rst b/docs/index.rst index d776b353..5efa417a 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -45,6 +45,8 @@ Table of Contents TileLink-Diplomacy-Reference/index + Prototyping/index + Indices and tables ================== From 38a6bae872fa99428e00bcc051614b16bba9bd26 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 7 Nov 2020 17:27:19 -0800 Subject: [PATCH 058/157] Add CI for Arty/VCU118 (just verilog) --- .circleci/README.md | 18 ++++++++---- .circleci/check-commit.sh | 9 ++++++ .circleci/config.yml | 10 +++++++ .circleci/defaults.sh | 5 ++++ .circleci/do-fpga-rtl-build.sh | 52 ++++++++++++++++++++++++++++++++++ 5 files changed, 89 insertions(+), 5 deletions(-) create mode 100755 .circleci/do-fpga-rtl-build.sh diff --git a/.circleci/README.md b/.circleci/README.md index a50fc44a..0c53405d 100644 --- a/.circleci/README.md +++ b/.circleci/README.md @@ -34,11 +34,19 @@ Here the key is built from a string where the `checksum` portion converts the fi This directory contains all the collateral for the Chipyard CI to work. The following is included: - `build-toolchains.sh` # build either riscv-tools or esp-tools - `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work - `do-rtl-build.sh` # use verilator to build a sim executable (remotely) - `config.yml` # main circleci config script to enumerate jobs/workflows - `defaults.sh` # default variables used + `build-toolchains.sh` # build either riscv-tools or esp-tools + `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work + `do-rtl-build.sh` # use verilator to build a sim executable (remotely) + `config.yml` # main circleci config script to enumerate jobs/workflows + `defaults.sh` # default variables used + `check-commit.sh` # check that submodule commits are valid + `build-extra-tests.sh` # build default chipyard tests located in tests/ + `clean-old-files.sh` # clean up build server files + `do-fpga-rtl-build.sh` # similar to `do-rtl-build` but using fpga/ + `install-verilator.sh` # install verilator on build server + `run-firesim-scala-tests.sh` # run firesim scala tests + `run-tests.sh # run tests for a specific set of designs + `images/` # docker image used in CI How things are setup for Chipyard --------------------------------- diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 68cc975c..51e56449 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -120,6 +120,15 @@ dir="vlsi" branches=("master") search +submodules=("fpga-shells") +dir="fpga" +if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +then + branches=("master") +else + branches=("master" "dev") +fi +search # turn off verbose printing to make this easier to read set +x diff --git a/.circleci/config.yml b/.circleci/config.yml index 4ee84ced..f5130930 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -361,6 +361,12 @@ jobs: project-key: "firesim-multiclock" run-script: "run-firesim-scala-tests.sh" timeout: "20m" + prepare-chipyard-fpga: + executor: main-env + steps: + - prepare-rtl: + group-key: "group-fpga" + build-script: "do-fpga-rtl-build.sh" # Order and dependencies of jobs to run workflows: @@ -500,4 +506,8 @@ workflows: - install-verilator - build-extra-tests + # Prepare the fpga builds (just Verilog) + - prepare-chipyard-fpga: + requires: + - install-riscv-toolchain diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e628de7b..0b6b6fc9 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -33,6 +33,7 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim +REMOTE_FPGA_DIR=$REMOTE_CHIPYARD_DIR/fpga # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install @@ -52,6 +53,7 @@ grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spifl grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" grouping["group-other"]="icenet testchipip" +grouping["group-fpga"]="arty vcu118" # key value store to get the build strings declare -A mapping @@ -81,3 +83,6 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" + +mapping["arty"]="SUB_PROJECT=arty verilog" +mapping["vcu118"]="SUB_PROJECT=vcu118 verilog" diff --git a/.circleci/do-fpga-rtl-build.sh b/.circleci/do-fpga-rtl-build.sh new file mode 100755 index 00000000..29a5dac2 --- /dev/null +++ b/.circleci/do-fpga-rtl-build.sh @@ -0,0 +1,52 @@ +#!/bin/bash + +# create the different verilator builds +# argument is the make command string + +# turn echo on and error on earliest command +set -ex + +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + +# call clean on exit +trap clean EXIT + +cd $LOCAL_CHIPYARD_DIR +./scripts/init-submodules-no-riscv-tools.sh + +# set stricthostkeychecking to no (must happen before rsync) +run "echo \"Ping $SERVER\"" + +clean + +# copy over riscv/esp-tools, and chipyard to remote +run "mkdir -p $REMOTE_CHIPYARD_DIR" +copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR + +run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" +run "cp -r ~/.sbt $REMOTE_WORK_DIR" + +TOOLS_DIR=$REMOTE_RISCV_DIR +LD_LIB_DIR=$REMOTE_RISCV_DIR/lib + +run "mkdir -p $REMOTE_RISCV_DIR" +copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR + +# enter the verilator directory and build the specific config on remote server +run "export RISCV=\"$TOOLS_DIR\"; \ + make -C $REMOTE_FPGA_DIR clean;" + +read -a keys <<< ${grouping[$1]} + +for key in "${keys[@]}" +do + run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ + make -j$REMOTE_MAKE_NPROC -C $REMOTE_FPGA_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" +done + +run "rm -rf $REMOTE_CHIPYARD_DIR/project" From 244205e2b40aee6029627f1864b96ae427946f26 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 8 Nov 2020 17:49:32 -0800 Subject: [PATCH 059/157] Separate new sys_clk and ddr2 from TSI --- fpga/src/main/scala/vcu118/TestHarness.scala | 2 + .../main/scala/vcu118/bringup/Configs.scala | 5 +- .../scala/vcu118/bringup/CustomOverlays.scala | 142 +++--------------- .../scala/vcu118/bringup/TestHarness.scala | 17 ++- 4 files changed, 39 insertions(+), 127 deletions(-) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 3d1d438e..ae019e21 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -38,6 +38,8 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput())) val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput())) val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput())) + val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput())) + val ddr2 = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput())) val topDesign = LazyModule(p(BuildTop)(dp)) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index f6e4880c..913a4fc2 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -19,7 +19,7 @@ import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} import chipyard.{BuildSystem} -import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency} +import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size} class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) @@ -38,6 +38,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { List.empty[GPIOParams] } } + case TSIClockMaxFrequency => 100 case PeripheryTSIHostKey => List( TSIHostParams( serialIfWidth = 4, @@ -50,7 +51,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { sourceId = IdRange(0, (1 << 13))))), managerPortParams = TLSlavePortParameters.v1( managers = Seq(TLSlaveParameters.v1( - address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), + address = Seq(AddressSet(0, site(VCU118DDR2Size) - 1)), regionType = RegionType.UNCACHED, executable = true, supportsGet = TransferSizes(1, 64), diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 1881d821..ef25cea3 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.clocks._ import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} -import testchipip.{TSIHostParams, TSIHostWidgetIO} +import testchipip.{TSIHostWidgetIO} import chipyard.fpga.vcu118.{FMCPMap} @@ -152,21 +152,13 @@ class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp case class TSIHostShellInput() case class TSIHostDesignInput( - wrangler: ClockAdapterNode, - corePLL: PLLNode, - tsiHostParams: TSIHostParams, - node: BundleBridgeSource[TSIHostWidgetIO], - vc7074gbdimm: Boolean = false + serialIfWidth: Int, + node: BundleBridgeSource[TSIHostWidgetIO] )( implicit val p: Parameters) -case class TSIHostOverlayOutput(ddr: TLInwardNode) +case class TSIHostOverlayOutput() trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] -class TSIHostWithDDRIO(val w: Int, val size: BigInt) extends Bundle { - val tsi = new TSIHostWidgetIO(w) - val ddr = new XilinxVCU118MIGPads(size) -} - case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil) abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput) @@ -177,43 +169,16 @@ abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHos case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) - extends TSIHostPlacedOverlay[TSIHostWithDDRIO](name, designInput, shellInput) + extends TSIHostPlacedOverlay[TSIHostWidgetIO](name, designInput, shellInput) { - val size = p(TSIHostVCU118DDRSize) - - // connect the DDR - val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(di.tsiHostParams.targetBaseAddress, size)) - val mig = LazyModule(new XilinxVCU118MIG(migParams)) - val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) - val topIONode = shell { ioNode.makeSink() } - val ddrUI = shell { ClockSourceNode(freqMHz = 200) } - val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } - areset := designInput.wrangler := ddrUI - - // since this uses a separate clk/rst need to put an async crossing - val asyncSink = LazyModule(new TLAsyncCrossingSink()) - val migClkRstNode = BundleBridgeSource(() => new Bundle { - val clock = Output(Clock()) - val reset = Output(Bool()) - }) - val topMigClkRstIONode = shell { migClkRstNode.makeSink() } - - // connect the TSI serial val tlTsiSerialSink = di.node.makeSink() - val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.tsiHostParams.serialIfWidth)) + val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.serialIfWidth)) val topTSIIONode = shell { tsiIoNode.makeSink() } - def overlayOutput = TSIHostOverlayOutput(ddr = mig.node) - def ioFactory = new TSIHostWithDDRIO(di.tsiHostParams.serialIfWidth, size) + def overlayOutput = TSIHostOverlayOutput() + def ioFactory = new TSIHostWidgetIO(di.serialIfWidth) InModuleBody { - // connect MIG - ioNode.bundle <> mig.module.io - - // setup async crossing - asyncSink.module.clock := migClkRstNode.bundle.clock - asyncSink.module.reset := migClkRstNode.bundle.reset - // connect TSI serial val tsiSourcePort = tsiIoNode.bundle val tsiSinkPort = tlTsiSerialSink.bundle @@ -225,48 +190,9 @@ class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready } - - // connect the DDR port - shell { InModuleBody { - require (shell.sys_clock2.get.isDefined, "Use of TSIHostVCU118Overlay depends on SysClock2VCU118Overlay") - val (sys, _) = shell.sys_clock2.get.get.overlayOutput.node.out(0) - val (ui, _) = ddrUI.out(0) - val (ar, _) = areset.in(0) - - // connect the async fifo sink to sys_clock2 - topMigClkRstIONode.bundle.clock := sys.clock - topMigClkRstIONode.bundle.reset := sys.reset - - val ddrPort = topIONode.bundle.port - io.ddr <> ddrPort - ui.clock := ddrPort.c0_ddr4_ui_clk - ui.reset := /*!ddrPort.mmcm_locked ||*/ ddrPort.c0_ddr4_ui_clk_sync_rst - ddrPort.c0_sys_clk_i := sys.clock.asUInt - ddrPort.sys_rst := sys.reset // pllReset - ddrPort.c0_ddr4_aresetn := !ar.reset - - // This was just copied from the SiFive example, but it's hard to follow. - // The pins are emitted in the following order: - // adr[0->13], we_n, cas_n, ras_n, bg, ba[0->1], reset_n, act_n, ck_c, ck_t, cke, cs_n, odt, dq[0->63], dqs_c[0->7], dqs_t[0->7], dm_dbi_n[0->7] - val allddrpins = Seq( - "AM27", "AL27", "AP26", "AP25", "AN28", "AM28", "AP28", "AP27", "AN26", "AM26", "AR28", "AR27", "AV25", "AT25", // adr[0->13] - "AV28", "AU26", "AV26", "AU27", // we_n, cas_n, ras_n, bg - "AR25", "AU28", // ba[0->1] - "BD35", "AN25", "AT27", "AT26", "AW28", "AY29", "BB29", // reset_n, act_n, ck_c, ck_t, cke, cs_n, odt - "BD30", "BE30", "BD32", "BE33", "BC33", "BD33", "BC31", "BD31", "BA32", "BB33", "BA30", "BA31", "AW31", "AW32", "AY32", "AY33", // dq[0->15] - "AV30", "AW30", "AU33", "AU34", "AT31", "AU32", "AU31", "AV31", "AR33", "AT34", "AT29", "AT30", "AP30", "AR30", "AN30", "AN31", // dq[16->31] - "BE34", "BF34", "BC35", "BC36", "BD36", "BE37", "BF36", "BF37", "BD37", "BE38", "BC39", "BD40", "BB38", "BB39", "BC38", "BD38", // dq[32->47] - "BB36", "BB37", "BA39", "BA40", "AW40", "AY40", "AY38", "AY39", "AW35", "AW36", "AU40", "AV40", "AU38", "AU39", "AV38", "AV39", // dq[48->63] - "BF31", "BA34", "AV29", "AP32", "BF35", "BF39", "BA36", "AW38", // dqs_c[0->7] - "BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7] - "BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7] - - (IOPin.of(io.ddr) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } - } } - - shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk)) } +case object TSIClockMaxFrequency extends Field[Int](50) // in MHz class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) { @@ -274,25 +200,25 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATes shell { InModuleBody { // connect TSI signals val tsiPort = topTSIIONode.bundle - io.tsi <> tsiPort + io <> tsiPort - require(di.tsiHostParams.serialIfWidth == 4) + require(di.serialIfWidth == 4) - val clkIo = IOPin(io.tsi.serial_clock) + val clkIo = IOPin(io.serial_clock) val packagePinsWithPackageIOs = Seq( (FMCPMap("D8"), clkIo), - (FMCPMap("D17"), IOPin(io.tsi.serial.out.ready)), - (FMCPMap("D18"), IOPin(io.tsi.serial.out.valid)), - (FMCPMap("D11"), IOPin(io.tsi.serial.out.bits, 0)), - (FMCPMap("D12"), IOPin(io.tsi.serial.out.bits, 1)), - (FMCPMap("D14"), IOPin(io.tsi.serial.out.bits, 2)), - (FMCPMap("D15"), IOPin(io.tsi.serial.out.bits, 3)), - (FMCPMap("D26"), IOPin(io.tsi.serial.in.ready)), - (FMCPMap("D27"), IOPin(io.tsi.serial.in.valid)), - (FMCPMap("D20"), IOPin(io.tsi.serial.in.bits, 0)), - (FMCPMap("D21"), IOPin(io.tsi.serial.in.bits, 1)), - (FMCPMap("D23"), IOPin(io.tsi.serial.in.bits, 2)), - (FMCPMap("D24"), IOPin(io.tsi.serial.in.bits, 3))) + (FMCPMap("D17"), IOPin(io.serial.out.ready)), + (FMCPMap("D18"), IOPin(io.serial.out.valid)), + (FMCPMap("D11"), IOPin(io.serial.out.bits, 0)), + (FMCPMap("D12"), IOPin(io.serial.out.bits, 1)), + (FMCPMap("D14"), IOPin(io.serial.out.bits, 2)), + (FMCPMap("D15"), IOPin(io.serial.out.bits, 3)), + (FMCPMap("D26"), IOPin(io.serial.in.ready)), + (FMCPMap("D27"), IOPin(io.serial.in.valid)), + (FMCPMap("D20"), IOPin(io.serial.in.bits, 0)), + (FMCPMap("D21"), IOPin(io.serial.in.bits, 1)), + (FMCPMap("D23"), IOPin(io.serial.in.bits, 2)), + (FMCPMap("D24"), IOPin(io.serial.in.bits, 3))) packagePinsWithPackageIOs foreach { case (pin, io) => { shell.xdc.addPackagePin(io, pin) @@ -304,7 +230,7 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATes shell.xdc.addIOB(io) } } - shell.sdc.addClock("TSI_CLK", clkIo, 50) + shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequency)) shell.sdc.addGroup(pins = Seq(clkIo)) shell.xdc.clockDedicatedRouteFalse(clkIo) } } @@ -314,21 +240,3 @@ class BringupTSIHostVCU118ShellPlacer(shell: BringupVCU118FPGATestHarness, val s extends TSIHostShellPlacer[BringupVCU118FPGATestHarness] { def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } - -class SysClock2VCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) - extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) -{ - val node = shell { ClockSourceNode(freqMHz = 250, jitterPS = 50)(ValName(name)) } - - shell { InModuleBody { - shell.xdc.addPackagePin(io.p, "AW26") - shell.xdc.addPackagePin(io.n, "AW27") - shell.xdc.addIOStandard(io.p, "DIFF_SSTL12") - shell.xdc.addIOStandard(io.n, "DIFF_SSTL12") - } } -} -class SysClock2VCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName) - extends ClockInputShellPlacer[VCU118ShellBasicOverlays] -{ - def place(designInput: ClockInputDesignInput) = new SysClock2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 95025dc7..6a4c8e2d 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -19,7 +19,7 @@ import sifive.blocks.devices.gpio._ import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter} -import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp} +import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer} import chipyard.{ChipTop} @@ -71,21 +71,22 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends require(dp(PeripheryTSIHostKey).size == 1) // use the 2nd system clock for the 2nd DDR - val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput())) val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node val ddr2PLL = dp(PLLFactoryKey)() ddr2PLL := sysClk2Node - val ddrClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) - val ddrWrangler = LazyModule(new ResetWrangler) - val ddrGroup = ClockGroup() - ddrClock := ddrWrangler.node := ddrGroup := ddr2PLL + val ddr2Clock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) + val ddr2Wrangler = LazyModule(new ResetWrangler) + val ddr2Group = ClockGroup() + ddr2Clock := ddr2Wrangler.node := ddr2Group := ddr2PLL val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) + val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetBaseAddress, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr + val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) - val tsiDdrNode = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)).overlayOutput.ddr + dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.serialIfWidth, io_tsi_serial_bb)) // connect 1 mem. channel to the FPGA DDR val inTsiParams = topDesign match { case td: ChipTop => @@ -94,7 +95,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends } } val tsiDdrClient = TLClientNode(Seq(inTsiParams.master)) - (tsiDdrNode + (ddr2Node := TLFragmenter(8,64,holdFirstDeny=true) := TLCacheCork() := TLAtomicAutomata(passthrough=false) From 082b2304520a48c78f2a0dd1f8a98857c53df140 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 8 Nov 2020 17:51:21 -0800 Subject: [PATCH 060/157] Add missing file --- .../main/scala/vcu118/CustomOverlays.scala | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 fpga/src/main/scala/vcu118/CustomOverlays.scala diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala new file mode 100644 index 00000000..a58fb424 --- /dev/null +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -0,0 +1,110 @@ +package chipyard.fpga.vcu118 + +import chisel3._ + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} + +import sifive.fpgashells.shell._ +import sifive.fpgashells.ip.xilinx._ +import sifive.fpgashells.shell.xilinx._ +import sifive.fpgashells.clocks._ +import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} + +class SysClock2VCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) + extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) +{ + val node = shell { ClockSourceNode(freqMHz = 250, jitterPS = 50)(ValName(name)) } + + shell { InModuleBody { + shell.xdc.addPackagePin(io.p, "AW26") + shell.xdc.addPackagePin(io.n, "AW27") + shell.xdc.addIOStandard(io.p, "DIFF_SSTL12") + shell.xdc.addIOStandard(io.n, "DIFF_SSTL12") + } } +} +class SysClock2VCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName) + extends ClockInputShellPlacer[VCU118ShellBasicOverlays] +{ + def place(designInput: ClockInputDesignInput) = new SysClock2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +case object VCU118DDR2Size extends Field[BigInt](0x40000000L * 2) // 2GB +class DDR2VCU118PlacedOverlay(val shell: VCU118FPGATestHarness, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) + extends DDRPlacedOverlay[XilinxVCU118MIGPads](name, designInput, shellInput) +{ + val size = p(VCU118DDRSize) + + val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(di.baseAddress, size)) + val mig = LazyModule(new XilinxVCU118MIG(migParams)) + val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) + val topIONode = shell { ioNode.makeSink() } + val ddrUI = shell { ClockSourceNode(freqMHz = 200) } + val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } + areset := designInput.wrangler := ddrUI + + // since this uses a separate clk/rst need to put an async crossing + val asyncSink = LazyModule(new TLAsyncCrossingSink()) + val migClkRstNode = BundleBridgeSource(() => new Bundle { + val clock = Output(Clock()) + val reset = Output(Bool()) + }) + val topMigClkRstIONode = shell { migClkRstNode.makeSink() } + + def overlayOutput = DDROverlayOutput(ddr = mig.node) + def ioFactory = new XilinxVCU118MIGPads(size) + + InModuleBody { + ioNode.bundle <> mig.module.io + + // setup async crossing + asyncSink.module.clock := migClkRstNode.bundle.clock + asyncSink.module.reset := migClkRstNode.bundle.reset + } + + shell { InModuleBody { + require (shell.sys_clock2.get.isDefined, "Use of DDRVCU118Overlay depends on SysClock2VCU118Overlay") + val (sys, _) = shell.sys_clock2.get.get.overlayOutput.node.out(0) + val (ui, _) = ddrUI.out(0) + val (ar, _) = areset.in(0) + + // connect the async fifo sync to sys_clock2 + topMigClkRstIONode.bundle.clock := sys.clock + topMigClkRstIONode.bundle.reset := sys.reset + + val port = topIONode.bundle.port + io <> port + ui.clock := port.c0_ddr4_ui_clk + ui.reset := /*!port.mmcm_locked ||*/ port.c0_ddr4_ui_clk_sync_rst + port.c0_sys_clk_i := sys.clock.asUInt + port.sys_rst := sys.reset // pllReset + port.c0_ddr4_aresetn := !ar.reset + + // This was just copied from the SiFive example, but it's hard to follow. + // The pins are emitted in the following order: + // adr[0->13], we_n, cas_n, ras_n, bg, ba[0->1], reset_n, act_n, ck_c, ck_t, cke, cs_n, odt, dq[0->63], dqs_c[0->7], dqs_t[0->7], dm_dbi_n[0->7] + val allddrpins = Seq( + "AM27", "AL27", "AP26", "AP25", "AN28", "AM28", "AP28", "AP27", "AN26", "AM26", "AR28", "AR27", "AV25", "AT25", // adr[0->13] + "AV28", "AU26", "AV26", "AU27", // we_n, cas_n, ras_n, bg + "AR25", "AU28", // ba[0->1] + "BD35", "AN25", "AT27", "AT26", "AW28", "AY29", "BB29", // reset_n, act_n, ck_c, ck_t, cke, cs_n, odt + "BD30", "BE30", "BD32", "BE33", "BC33", "BD33", "BC31", "BD31", "BA32", "BB33", "BA30", "BA31", "AW31", "AW32", "AY32", "AY33", // dq[0->15] + "AV30", "AW30", "AU33", "AU34", "AT31", "AU32", "AU31", "AV31", "AR33", "AT34", "AT29", "AT30", "AP30", "AR30", "AN30", "AN31", // dq[16->31] + "BE34", "BF34", "BC35", "BC36", "BD36", "BE37", "BF36", "BF37", "BD37", "BE38", "BC39", "BD40", "BB38", "BB39", "BC38", "BD38", // dq[32->47] + "BB36", "BB37", "BA39", "BA40", "AW40", "AY40", "AY38", "AY39", "AW35", "AW36", "AU40", "AV40", "AU38", "AU39", "AV38", "AV39", // dq[48->63] + "BF31", "BA34", "AV29", "AP32", "BF35", "BF39", "BA36", "AW38", // dqs_c[0->7] + "BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7] + "BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7] + + (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + } } + + shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk)) +} + +class DDR2VCU118ShellPlacer(shell: VCU118FPGATestHarness, val shellInput: DDRShellInput)(implicit val valName: ValName) + extends DDRShellPlacer[VCU118FPGATestHarness] { + def place(designInput: DDRDesignInput) = new DDR2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput) +} + From 714fb56423e612c49f82ba9badc2a026b12f681c Mon Sep 17 00:00:00 2001 From: dunn Date: Mon, 9 Nov 2020 14:56:54 -0800 Subject: [PATCH 061/157] Addressing PR comments in docs. --- docs/Chipyard-Basics/Chipyard-Components.rst | 2 +- docs/Prototyping/Arty.rst | 22 +++++++++----------- docs/Prototyping/index.rst | 6 +++--- 3 files changed, 14 insertions(+), 16 deletions(-) diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 3e45f99f..ba6a8774 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -129,7 +129,7 @@ Prototyping **FPGA Prototyping** FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``. - Some examples of FPGAs supported are the Arty and VCU118 boards. + Some examples of FPGAs supported are the Xilinx Arty 35T and VCU118 boards. To instead do an fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform. See :ref:`Prototyping Flow` for more information on FPGA prototypes. diff --git a/docs/Prototyping/Arty.rst b/docs/Prototyping/Arty.rst index fe36a4ef..d01cc5c2 100644 --- a/docs/Prototyping/Arty.rst +++ b/docs/Prototyping/Arty.rst @@ -4,25 +4,23 @@ Running a Design on Arty Basic Design ------------ -The default Arty FPGA target design is setup to have JTAG, UART, SPI, and I2C available over the board's GPIO pins. -The pin mappings of these interfaces are identical to those described in the `SiFive Freedom E310 Arty Getting Started Guide `__. -The JTAG interface allows a user to connect to the core over OpenOCD, run bare-metal applications, and debug using gdb. -To extend this design, you can create your own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. -Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2C interfaces to your Chipyard design/config. +The default Xilinx Arty 35T harness is setup to have JTAG available over the board's PMOD pins, and UART available over its FTDI serial USB adapter. The pin mappings for JTAG signals are identical to those described in the `SiFive Freedom E310 Arty 35T Getting Started Guide `__. +The JTAG interface allows a user to connect to the core via OpenOCD, run bare-metal applications, and debug these applications with gdb. UART allows a user to communicate with the core over a USB connection and serial console running on a PC. +To extend this design, a user may create their own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. +Adding this config. fragment will enable and connect the JTAG and UART interfaces to your Chipyard design. .. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala :language: scala :start-after: DOC include start: AbstractArty and Rocket :end-before: DOC include end: AbstractArty and Rocket -Future peripherals to be supported include the Arty's SPI Flash EEPROM. +Future peripherals to be supported include the Arty 35T SPI Flash EEPROM, and I2C/PWM/SPI over the Arty 35T GPIO pins. These peripherals are available as part of sifive-blocks. Brief Implementation Description and Guidance for Adding/Changing Xilinx Collateral ----------------------------------------------------------------------------------- -The basis for the Arty design is the creation of a special test harness that connects the external FPGA IO (which exist as Xilinx IP blackboxes) to the Chipyard design. -This is done with the ``ArtyTestHarness`` in the basic default Arty target. -However, unlike the more complicated ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects ``ChipTop`` IO to the ports of the external FPGA IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. -Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. -If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. -The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the ``ChipTop`` using ``HarnessBinders`` and ``IOBinders``. +Like the VCU118, the basis for the Arty 35T design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design. +This is done with the ``ArtyTestHarness`` in the basic default Arty 35T target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. +Unlike the VCU118 and other more complicated test harnesses, the Arty 35T Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. +If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinders`` and ``IOBinders``. +Examples of a simple ``IOBinder`` and ``HarnessBinder`` for routing signals (in this case the debug and JTAG resets) from the core to the test harness are the ``WithResetPassthrough`` and ``WithArtyResetHarnessBinder``. diff --git a/docs/Prototyping/index.rst b/docs/Prototyping/index.rst index 695c588f..118ce745 100644 --- a/docs/Prototyping/index.rst +++ b/docs/Prototyping/index.rst @@ -2,11 +2,11 @@ Prototyping Flow ================ Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. -This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. +This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty 35T board. FPGA prototyping allows for orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times and less design introspection. -.. Note:: While ``fpga-shells`` also supports Xilinx VC707 and some MicroSemi PolarFire boards, currently only the VCU118 and Arty boards are explicitly supported in Chipyard. - However, using the VCU118/Arty examples would be useful to see how to implement VC707/PolarFire support. +.. Note:: While ``fpga-shells`` provides harnesses for other FPGA development boards such as the Xilinx VC707 and some MicroSemi PolarFire, only harnesses for the Xilinx VCU118 and Xilinx Arty 35T boards are currently supported in Chipyard. + However, the VCU118 and Arty 35T examples demonstrate how a user may implement support for other harnesses provided by fpga-shells. .. toctree:: :maxdepth: 2 From 1110dd702cd02510f47e5a8cfd7bdbc88181a164 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Wed, 11 Nov 2020 18:57:16 +0000 Subject: [PATCH 062/157] Bump RC, firesim and barstools for chisel3.4 updates Note: firesim and barstools point to commits in the sifive forks of those repos I didn't update the URL in .gitmodules because I'm not sure how that works in a PR (because you wouldn't really want to merge sync'ing to the sifive repo). Requires: ucb-bar/barstools#92 and firesim/firesim#658 The version of rocket-chip, chisel3 and firrtl is chosen here because it is the latest known to pass my tests. You will likely want to bump further. --- generators/rocket-chip | 2 +- sims/firesim | 2 +- tools/barstools | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index 6eb1a3de..577994e3 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 6eb1a3de082e27c752d9e4c1ae971c693cc192eb +Subproject commit 577994e38e3115cafa3a232b0fc60584aacb996e diff --git a/sims/firesim b/sims/firesim index 37fe89a6..f89d746a 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 37fe89a65f1c1ccd8d2cc0d1efd0c06308d0224d +Subproject commit f89d746aa3c0c35c78a883c22c58679aeb9e2030 diff --git a/tools/barstools b/tools/barstools index 4a5c75fc..20d370be 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 4a5c75fcf85f03af858f1d7db04303d4b0733de7 +Subproject commit 20d370be496d3f9e873e5e63bf8d220727701dff diff --git a/tools/chisel3 b/tools/chisel3 index cc2971fe..d379dca4 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit cc2971feb15d4bc8cb4a8138b5a095ccbc92dcc3 +Subproject commit d379dca4413d4cb08b02165a493faff01f3ddbb9 diff --git a/tools/firrtl b/tools/firrtl index c07da8a5..05d047a9 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit c07da8a581789b88f7e6ffc98c8e810565034ad9 +Subproject commit 05d047a9befda3877f5d8a0a9e1076ffd520ddf9 From 7ca3be236cd5c3e1ab3f8b4b3b733727a60f54fd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 11:47:16 -0800 Subject: [PATCH 063/157] Bump bringup VCU118 | Ignore HTIF if no-debug module --- .gitmodules | 2 +- fpga/fpga-shells | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 1 - .../main/scala/vcu118/bringup/Configs.scala | 10 ++--- .../scala/vcu118/bringup/CustomOverlays.scala | 45 ++----------------- .../scala/vcu118/bringup/DigitalTop.scala | 3 +- .../scala/vcu118/bringup/HarnessBinders.scala | 13 ------ .../scala/vcu118/bringup/TestHarness.scala | 11 ----- .../chipyard/src/main/scala/Subsystem.scala | 4 +- generators/testchipip | 2 +- 10 files changed, 14 insertions(+), 79 deletions(-) diff --git a/.gitmodules b/.gitmodules index 8756fbc9..04c01f12 100644 --- a/.gitmodules +++ b/.gitmodules @@ -133,4 +133,4 @@ url = https://github.com/ucb-bar/riscv-sodor.git [submodule "fpga/fpga-shells"] path = fpga/fpga-shells - url = git@github.com:sifive/fpga-shells.git + url = git@github.com:abejgonzalez/fpga-shells.git diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 89a5efec..fcfadb4c 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 89a5efec011ebc21b9455923501df70783161cb8 +Subproject commit fcfadb4cf36dfbcd7cfee525404b56bf661793b9 diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index a08ce0f2..77f03acf 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -28,7 +28,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => { class WithSystemModifications extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top case DebugModuleKey => None // disable debug module - case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS case SystemBusKey => up(SystemBusKey).copy( errorDevice = Some(DevNullParams( Seq(AddressSet(0x3000, 0xfff)), diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 913a4fc2..5e19cc5c 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -9,7 +9,6 @@ import freechips.rocketchip.diplomacy._ import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} -import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} @@ -23,7 +22,6 @@ import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) - case PeripherySPIKey => up(PeripherySPIKey, site) ++ List(SPIParams(rAddress = BigInt(0x64004000L))) case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L))) case PeripheryGPIOKey => { if (BringupGPIOs.width > 0) { @@ -38,12 +36,13 @@ class WithBringupPeripherals extends Config((site, here, up) => { List.empty[GPIOParams] } } - case TSIClockMaxFrequency => 100 + case TSIClockMaxFrequencyKey => 100 case PeripheryTSIHostKey => List( TSIHostParams( serialIfWidth = 4, mmioBaseAddress = BigInt(0x64006000), mmioSourceId = 1 << 13, // manager source + targetSize = site(VCU118DDR2Size), serdesParams = TSIHostSerdesParams( clientPortParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( @@ -51,7 +50,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { sourceId = IdRange(0, (1 << 13))))), managerPortParams = TLSlavePortParameters.v1( managers = Seq(TLSlaveParameters.v1( - address = Seq(AddressSet(0, site(VCU118DDR2Size) - 1)), + address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), // access everything on chip regionType = RegionType.UNCACHED, executable = true, supportsGet = TransferSizes(1, 64), @@ -71,7 +70,6 @@ class WithBringupVCU118System extends Config((site, here, up) => { class WithBringupAdditions extends Config( new WithBringupUART ++ - new WithBringupSPI ++ new WithBringupI2C ++ new WithBringupGPIO ++ new WithBringupTSIHost ++ @@ -87,7 +85,7 @@ class RocketBringupConfig extends Config( new chipyard.RocketConfig) class BoomBringupConfig extends Config( - new WithFPGAFrequency(75) ++ + new WithFPGAFrequency(70) ++ new WithBringupAdditions ++ new WithVCU118Tweaks ++ new chipyard.MegaBoomConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index ef25cea3..a47a6a3b 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -69,46 +69,7 @@ class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) } -/* Connect SPI to ADI device */ -class BringupSPIVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: SPIDesignInput, val shellInput: SPIShellInput) - extends SDIOXilinxPlacedOverlay(name, designInput, shellInput) -{ - shell { InModuleBody { - val packagePinsWithPackageIOs = Seq((FMCPMap("H37"), IOPin(io.spi_clk)), - (FMCPMap("H19"), IOPin(io.spi_cs)), - (FMCPMap("H17"), IOPin(io.spi_dat(0))), - (FMCPMap("H28"), IOPin(io.spi_dat(1))), - (FMCPMap("H29"), IOPin(io.spi_dat(2))), - (FMCPMap("H16"), IOPin(io.spi_dat(3)))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - } } - packagePinsWithPackageIOs drop 1 foreach { case (pin, io) => { - shell.xdc.addPullup(io) - shell.xdc.addIOB(io) - } } - } } -} - -class BringupSPIVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: SPIShellInput)(implicit val valName: ValName) - extends SPIShellPlacer[VCU118ShellBasicOverlays] { - def place(designInput: SPIDesignInput) = new BringupSPIVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} - -// TODO: Move this to a different location -// SPI device description for ADI part -class ADISPIDevice(spi: Device, maxMHz: Double = 1) extends SimpleDevice("clkgen", Seq("analog,adi9516-4")) { - override def parent = Some(spi) - override def describe(resources: ResourceBindings): Description = { - val Description(name, mapping) = super.describe(resources) - val extra = Map("spi-max-frequency" -> Seq(ResourceInt(maxMHz * 1000000))) - Description(name, mapping ++ extra) - } -} - -/* Connect GPIOs to FMC */ +/* Connect GPIOs to FPGA I/Os */ abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput) extends GPIOPlacedOverlay(name, di, si) { @@ -192,7 +153,7 @@ class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: } } -case object TSIClockMaxFrequency extends Field[Int](50) // in MHz +case object TSIClockMaxFrequencyKey extends Field[Int](50) // in MHz class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) { @@ -230,7 +191,7 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATes shell.xdc.addIOB(io) } } - shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequency)) + shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequencyKey)) shell.sdc.addGroup(pins = Seq(clkIo)) shell.xdc.clockDedicatedRouteFalse(clkIo) } } diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index 42ea7af2..251ea8e9 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -10,8 +10,9 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} + // ------------------------------------ -// BringupVCU118 DigitalTop +// Bringup VCU118 DigitalTop // ------------------------------------ class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index 02b821b4..27689ca8 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -27,17 +27,6 @@ class WithBringupUART extends ComposeHarnessBinder({ } }) -/*** SPI ***/ -class WithBringupSPI extends ComposeHarnessBinder({ - (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { - th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { - require(ports.size == 2) - - vcu118th.bringupOuter.io_adi_spi_bb.bundle <> ports.last - } } - } -}) - /*** I2C ***/ class WithBringupI2C extends OverrideHarnessBinder({ (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => { @@ -79,5 +68,3 @@ class WithBringupTSIHost extends OverrideHarnessBinder({ } } } }) - - diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 6a4c8e2d..2e86e646 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -36,17 +36,6 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb)) - /*** SPI ***/ - - require(dp(PeripherySPIKey).size == 2) - - // 2nd SPI goes to the ADI port - - val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) - - val io_adi_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) - dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_adi_spi_bb)) - /*** I2C ***/ val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 5dd6ac18..20529ab5 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -11,7 +11,7 @@ import chisel3.internal.sourceinfo.{SourceInfo} import freechips.rocketchip.prci._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} @@ -31,7 +31,7 @@ trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true - case _: HasPeripheryDebug if p(ExportDebug).dmi => true + case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true case _ => false }) { ResourceBinding { diff --git a/generators/testchipip b/generators/testchipip index e956a60c..9c0163ab 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit e956a60cbfd848c31bd849ffe0140eb0f9af2524 +Subproject commit 9c0163ab9399cda10ed6da49bf959f5fefc3daaa From d5a0fd1a8e3ae47aa40ca3f522565b5d55083356 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 15:30:43 -0800 Subject: [PATCH 064/157] Address CircleCI --- .circleci/check-commit.sh | 7 +---- .circleci/config.yml | 7 +++-- .circleci/do-fpga-rtl-build.sh | 52 ---------------------------------- .circleci/do-rtl-build.sh | 29 +++++++++++++++---- 4 files changed, 29 insertions(+), 66 deletions(-) delete mode 100755 .circleci/do-fpga-rtl-build.sh diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 51e56449..ae05eb56 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -122,12 +122,7 @@ search submodules=("fpga-shells") dir="fpga" -if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] -then - branches=("master") -else - branches=("master" "dev") -fi +branches=("master") search # turn off verbose printing to make this easier to read diff --git a/.circleci/config.yml b/.circleci/config.yml index f5130930..25de2322 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -81,12 +81,15 @@ commands: build-script: type: string default: "do-rtl-build.sh" + build-type: + type: string + default: "sim" steps: - setup-tools: tools-version: "<< parameters.tools-version >>" - run: name: Building << parameters.group-key >> subproject using Verilator - command: .circleci/<< parameters.build-script >> << parameters.group-key >> + command: .circleci/<< parameters.build-script >> << parameters.group-key >> << parameters.build-type >> no_output_timeout: << parameters.timeout >> - save_cache: key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }} @@ -366,7 +369,7 @@ jobs: steps: - prepare-rtl: group-key: "group-fpga" - build-script: "do-fpga-rtl-build.sh" + build-type: "fpga" # Order and dependencies of jobs to run workflows: diff --git a/.circleci/do-fpga-rtl-build.sh b/.circleci/do-fpga-rtl-build.sh deleted file mode 100755 index 29a5dac2..00000000 --- a/.circleci/do-fpga-rtl-build.sh +++ /dev/null @@ -1,52 +0,0 @@ -#!/bin/bash - -# create the different verilator builds -# argument is the make command string - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -# call clean on exit -trap clean EXIT - -cd $LOCAL_CHIPYARD_DIR -./scripts/init-submodules-no-riscv-tools.sh - -# set stricthostkeychecking to no (must happen before rsync) -run "echo \"Ping $SERVER\"" - -clean - -# copy over riscv/esp-tools, and chipyard to remote -run "mkdir -p $REMOTE_CHIPYARD_DIR" -copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR - -run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" -run "cp -r ~/.sbt $REMOTE_WORK_DIR" - -TOOLS_DIR=$REMOTE_RISCV_DIR -LD_LIB_DIR=$REMOTE_RISCV_DIR/lib - -run "mkdir -p $REMOTE_RISCV_DIR" -copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR - -# enter the verilator directory and build the specific config on remote server -run "export RISCV=\"$TOOLS_DIR\"; \ - make -C $REMOTE_FPGA_DIR clean;" - -read -a keys <<< ${grouping[$1]} - -for key in "${keys[@]}" -do - run "export RISCV=\"$TOOLS_DIR\"; \ - export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ - export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_FPGA_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" -done - -run "rm -rf $REMOTE_CHIPYARD_DIR/project" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 784dbc04..9780f64b 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -1,7 +1,11 @@ #!/bin/bash # create the different verilator builds -# argument is the make command string +# usage: +# do-rtl-build.sh sim +# run rtl build for simulations and copy back results +# do-rtl-build.sh fpga +# run rtl build for fpga and don't copy back results # turn echo on and error on earliest command set -ex @@ -50,9 +54,19 @@ else copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR fi +# choose what make dir to use +case $2 in + "sim") + REMOTE_MAKE_DIR=$REMOTE_SIM_DIR + ;; + "fpga") + REMOTE_MAKE_DIR=$REMOTE_FPGA_DIR + ;; +esac + # enter the verilator directory and build the specific config on remote server run "export RISCV=\"$TOOLS_DIR\"; \ - make -C $REMOTE_SIM_DIR clean;" + make -C $REMOTE_MAKE_DIR clean;" read -a keys <<< ${grouping[$1]} @@ -63,11 +77,14 @@ do export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" + make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" done run "rm -rf $REMOTE_CHIPYARD_DIR/project" -# copy back the final build -mkdir -p $LOCAL_CHIPYARD_DIR -copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR +# choose to copy back results +if [ $2 = "sim" ]; then + # copy back the final build + mkdir -p $LOCAL_CHIPYARD_DIR + copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR +fi From 999ae05bfe0dcf3cb3744a6f7171e21f1a7b792a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 15:31:34 -0800 Subject: [PATCH 065/157] Address some docs, build.sbt, .gitmodules --- .gitmodules | 2 +- build.sbt | 2 +- docs/Chipyard-Basics/Chipyard-Components.rst | 2 +- docs/Prototyping/General.rst | 18 ++++++++++-------- docs/Prototyping/VCU118.rst | 8 ++++---- docs/Prototyping/index.rst | 1 - 6 files changed, 17 insertions(+), 16 deletions(-) diff --git a/.gitmodules b/.gitmodules index 04c01f12..17025437 100644 --- a/.gitmodules +++ b/.gitmodules @@ -133,4 +133,4 @@ url = https://github.com/ucb-bar/riscv-sodor.git [submodule "fpga/fpga-shells"] path = fpga/fpga-shells - url = git@github.com:abejgonzalez/fpga-shells.git + url = https://github.com/abejgonzalez/fpga-shells.git diff --git a/build.sbt b/build.sbt index 0de63b3a..f7b8aabe 100644 --- a/build.sbt +++ b/build.sbt @@ -222,7 +222,7 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) testOptions in Test += Tests.Argument("-oF") ) lazy val fpga_shells = (project in file("./fpga/fpga-shells")) - .dependsOn(rocketchip, sifive_blocks, chipyard) + .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) lazy val fpga_platforms = (project in file("./fpga")) diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index ba6a8774..f0d170f2 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -130,7 +130,7 @@ Prototyping **FPGA Prototyping** FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``. Some examples of FPGAs supported are the Xilinx Arty 35T and VCU118 boards. - To instead do an fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform. + For a fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform. See :ref:`Prototyping Flow` for more information on FPGA prototypes. VLSI diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index d27cd66a..b9fc5da3 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -4,7 +4,7 @@ General Setup and Usage Sources and Submodule Setup --------------------------- -All FPGA related collateral and sources are located in the ``fpga`` top-level Chipyard directory. +All FPGA prototyping-related collateral and sources are located in the ``fpga`` top-level Chipyard directory. This includes the ``fpga-shells`` submodule and the ``src`` directory that hold both Scala, TCL and other collateral. However, the ``fpga-shells`` submodule repository is not initialized by default. To initialize the ``fpga-shells`` submodule repository, run the included initialization script from the Chipyard top-level directory: @@ -22,22 +22,22 @@ Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you c .. code-block:: shell - make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... bit + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... bitstream # or - make SUB_PROJECT= bit + make SUB_PROJECT= bitstream The ``SUB_PROJECT`` make variable is a way to meta make variable that sets all of the other make variables to a specific default. For example: .. code-block:: shell - make SUB_PROJECT=vcu118 bit + make SUB_PROJECT=vcu118 bitstream # converts to - make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 bit + make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 bitstream Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system. @@ -47,22 +47,24 @@ For example, building the BOOM configuration on the VCU118: .. code-block:: shell - make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bit + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bitstream That command will build the RTL and generate a bitstream using Vivado. +The generated bitstream will be located in your designs specific build folder (``generated-src//obj``). However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL. Debugging with ILAs on Supported FPGAs -------------------------------------- -Adding an ILA (integrated logic analyzer) can be added to certain designs for debugging relevant signals. +ILA (integrated logic analyzers) can be added to certain designs for debugging relevant signals. First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). This can be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. +This will create a new bitstream called ``debug_output`` in the same location as the normal bitstream (``generated-src//obj``). For example, running the bitstream build for an added ILA for a BOOM config.: .. code-block:: shell make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream -For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. +.. IMPORTANT:: For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index a23b487e..9deb8739 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -4,10 +4,10 @@ Running a Design on VCU118 Basic Design ------------ -The default VCU118 FPGA target design is setup to have UART, a SPI SDCard, and DDR backing memory. +The default Xilinx VCU118 harness is setup to have UART, a SPI SDCard, and DDR backing memory. This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. -Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. +Adding this config fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. .. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala :language: scala @@ -50,6 +50,6 @@ For more information on harness binders and io binders, refer to :ref:`IOBinders An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. -.. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. - For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. +.. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation. + For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. See :ref:`Making a Bitstream` for information on the various make variables. diff --git a/docs/Prototyping/index.rst b/docs/Prototyping/index.rst index 118ce745..ba0dff49 100644 --- a/docs/Prototyping/index.rst +++ b/docs/Prototyping/index.rst @@ -3,7 +3,6 @@ Prototyping Flow Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty 35T board. -FPGA prototyping allows for orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times and less design introspection. .. Note:: While ``fpga-shells`` provides harnesses for other FPGA development boards such as the Xilinx VC707 and some MicroSemi PolarFire, only harnesses for the Xilinx VCU118 and Xilinx Arty 35T boards are currently supported in Chipyard. However, the VCU118 and Arty 35T examples demonstrate how a user may implement support for other harnesses provided by fpga-shells. From 55f19f79d3372f118c7cb784bbf081790c2e77e9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 15:39:29 -0800 Subject: [PATCH 066/157] Address fpga srcs --- .../src/main/resources/vcu118/sdboot/Makefile | 5 +- .../vcu118/sdboot/include/platform.h | 7 +- .../sdboot/include/riscv_test_defaults.h | 81 ------------------- .../vcu118/sdboot/linker/sdboot.elf.lds | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 11 +-- fpga/src/main/scala/vcu118/TestHarness.scala | 2 +- 6 files changed, 10 insertions(+), 98 deletions(-) delete mode 100644 fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h diff --git a/fpga/src/main/resources/vcu118/sdboot/Makefile b/fpga/src/main/resources/vcu118/sdboot/Makefile index b9c21470..e4636129 100644 --- a/fpga/src/main/resources/vcu118/sdboot/Makefile +++ b/fpga/src/main/resources/vcu118/sdboot/Makefile @@ -10,7 +10,10 @@ CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 CFLAGS+= -I $(ROOT_DIR)/include -I. LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T sdboot.elf.lds -#PBUS_CLK passed in +PBUS_CLK ?= 1000000 # default to 1MHz but really should be overridden + +default: elf bin dump + elf := $(BUILD_DIR)/sdboot.elf $(elf): head.S kprintf.c sd.c mkdir -p $(BUILD_DIR) diff --git a/fpga/src/main/resources/vcu118/sdboot/include/platform.h b/fpga/src/main/resources/vcu118/sdboot/include/platform.h index c240e0e5..21ebb0b3 100644 --- a/fpga/src/main/resources/vcu118/sdboot/include/platform.h +++ b/fpga/src/main/resources/vcu118/sdboot/include/platform.h @@ -1,10 +1,9 @@ // See LICENSE for license details. -#ifndef _EAGLE_PLATFORM_H -#define _EAGLE_PLATFORM_H +#ifndef _CHIPYARD_PLATFORM_H +#define _CHIPYARD_PLATFORM_H #include "const.h" -#include "riscv_test_defaults.h" #include "devices/clint.h" #include "devices/gpio.h" #include "devices/plic.h" @@ -105,4 +104,4 @@ // Misc -#endif /* _SIFIVE_PLATFORM_H */ +#endif /* _CHIPYARD_PLATFORM_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h b/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h deleted file mode 100644 index c9212737..00000000 --- a/fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h +++ /dev/null @@ -1,81 +0,0 @@ -// See LICENSE.Sifive for license details. -#ifndef _RISCV_TEST_DEFAULTS_H -#define _RISCV_TEST_DEFAULTS_H - -#define TESTNUM x28 -#define TESTBASE 0x4000 - -#define RVTEST_RV32U \ - .macro init; \ - .endm - -#define RVTEST_RV64U \ - .macro init; \ - .endm - -#define RVTEST_RV32UF \ - .macro init; \ - /* If FPU exists, initialize FCSR. */ \ - csrr t0, misa; \ - andi t0, t0, 1 << ('F' - 'A'); \ - beqz t0, 1f; \ - /* Enable FPU if it exists. */ \ - li t0, MSTATUS_FS; \ - csrs mstatus, t0; \ - fssr x0; \ -1: ; \ - .endm - -#define RVTEST_RV64UF \ - .macro init; \ - /* If FPU exists, initialize FCSR. */ \ - csrr t0, misa; \ - andi t0, t0, 1 << ('F' - 'A'); \ - beqz t0, 1f; \ - /* Enable FPU if it exists. */ \ - li t0, MSTATUS_FS; \ - csrs mstatus, t0; \ - fssr x0; \ -1: ; \ - .endm - -#define RVTEST_CODE_BEGIN \ - .section .text.init; \ - .globl _prog_start; \ -_prog_start: \ - init; - -#define RVTEST_CODE_END \ - unimp - -#define RVTEST_PASS \ - fence; \ - li t0, TESTBASE; \ - li t1, 0x5555; \ - sw t1, 0(t0); \ -1: \ - j 1b; - -#define RVTEST_FAIL \ - li t0, TESTBASE; \ - li t1, 0x3333; \ - slli a0, a0, 16; \ - add a0, a0, t1; \ - sw a0, 0(t0); \ -1: \ - j 1b; - -#define EXTRA_DATA - -#define RVTEST_DATA_BEGIN \ - EXTRA_DATA \ - .align 4; .global begin_signature; begin_signature: - -#define RVTEST_DATA_END \ - _msg_init: .asciz "RUN\r\n"; \ - _msg_pass: .asciz "PASS"; \ - _msg_fail: .asciz "FAIL "; \ - _msg_end: .asciz "\r\n"; \ - .align 4; .global end_signature; end_signature: - -#endif /* _RISCV_TEST_DEFAULTS_H */ diff --git a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds index 7a0a42fe..6843436f 100644 --- a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds +++ b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds @@ -47,7 +47,7 @@ SECTIONS .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT { *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.dtb) + *(.dtb) /* Must be last if this code is added to RC's BootROM */ } >bootrom_mem :data PROVIDE(_data = ADDR(.rodata)); diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 77f03acf..07eefd19 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -28,16 +28,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => { class WithSystemModifications extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top case DebugModuleKey => None // disable debug module - case SystemBusKey => up(SystemBusKey).copy( - errorDevice = Some(DevNullParams( - Seq(AddressSet(0x3000, 0xfff)), - maxAtomic=site(XLen)/8, - maxTransfer=128, - region = RegionType.TRACKED))) - case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = - Some(BigDecimal(site(FPGAFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt)) - case ControlBusKey => up(ControlBusKey, site).copy( - errorDevice = None) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => // invoke makefile for sdboot diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index ae019e21..cd88ff8e 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -41,7 +41,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput())) val ddr2 = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput())) - val topDesign = LazyModule(p(BuildTop)(dp)) + val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") // DOC include start: ClockOverlay // place all clocks in the shell From 63b3d4290fae5388ecec17f787ad9a127ac4ff91 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 15:39:47 -0800 Subject: [PATCH 067/157] Change NotSimulator to NoSimulator --- generators/utilities/src/main/scala/Simulator.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index 45939343..d7f4d007 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -11,7 +11,7 @@ case class GenerateSimConfig( sealed trait Simulator object VerilatorSimulator extends Simulator object VCSSimulator extends Simulator -object NotSimulator extends Simulator +object NoSimulator extends Simulator trait HasGenerateSimConfig { val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { @@ -23,7 +23,7 @@ trait HasGenerateSimConfig { .action((x, c) => x match { case "verilator" => c.copy(simulator = VerilatorSimulator) case "vcs" => c.copy(simulator = VCSSimulator) - case "none" => c.copy(simulator = NotSimulator) + case "none" => c.copy(simulator = NoSimulator) case _ => throw new Exception(s"Unrecognized simulator $x") }) .text("Name of simulator to generate files for (verilator, vcs, none)") @@ -52,7 +52,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { case VerilatorSimulator => s"-FI ${fname}" // vcs pulls headers in with +incdir, doesn't have anything like verilator.h case VCSSimulator => "" - case _ => "" + case NoSimulator => "" } } else { // do nothing otherwise fname @@ -99,7 +99,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { "/csrc/remote_bitbang.cc", "/vsrc/EICG_wrapper.v", ) ++ (sim match { - case NotSimulator => Seq() + case NoSimulator => Seq() case _ => Seq( "/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/SimDRAM.cc", @@ -120,7 +120,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { case VCSSimulator => Seq( "/vsrc/TestDriver.v", ) - case _ => Seq() + case NoSimulator => Seq() }) def writeBootrom(): Unit = { From d4d989ce0f38c22557074de7775156cf3389aa7f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 15:41:05 -0800 Subject: [PATCH 068/157] Rename make target to bitstream | Delete unused make stuff / tcl --- fpga/Makefile | 12 +----- fpga/scripts/write_mmi.tcl | 75 -------------------------------------- 2 files changed, 2 insertions(+), 85 deletions(-) delete mode 100644 fpga/scripts/write_mmi.tcl diff --git a/fpga/Makefile b/fpga/Makefile index fa6847ef..12bfd754 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -103,8 +103,8 @@ $(BIT_FILE): $(synth_list_f) -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ -board "$(BOARD)" -.PHONY: bit -bit: $(BIT_FILE) +.PHONY: bitstream +bitstream: $(BIT_FILE) .PHONY: debug-bitstream debug-bitstream: $(build_dir)/obj/post_synth.dcp @@ -116,14 +116,6 @@ debug-bitstream: $(build_dir)/obj/post_synth.dcp xcvu9p-flga2104-2l-e \ $(build_dir)/obj/debug_output -# Build .mcs -MCS_FILE := $(build_dir)/obj/$(MODEL).mcs -$(MCS_FILE): $(BIT_FILE) - cd $(build_dir); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< - -.PHONY: mcs -mcs: $(MCS_FILE) - ######################################################################################### # general cleanup rules ######################################################################################### diff --git a/fpga/scripts/write_mmi.tcl b/fpga/scripts/write_mmi.tcl deleted file mode 100644 index e577dd2b..00000000 --- a/fpga/scripts/write_mmi.tcl +++ /dev/null @@ -1,75 +0,0 @@ -proc write_mmi {filepath inst} { - current_instance - current_instance $inst - set chn [open $filepath w] - puts $chn "" - puts $chn "" - puts $chn "\t" - set brams [dict create] - foreach cell [get_cells -hierarchical -filter { PRIMITIVE_GROUP =~ BLOCKRAM }] { - set name [get_property RTL_RAM_NAME $cell] - dict update brams $name name { - dict lappend name cells $cell - dict set name size [get_property RTL_RAM_BITS $cell] - } - } - proc compare {a b} { - set a_addr [get_property bram_addr_begin $a] - set b_addr [get_property bram_addr_begin $b] - if {$a_addr > $b_addr} { - return 1 - } elseif {$a_addr < $b_addr} { - return -1 - } - set a_slice [get_property bram_slice_begin $a] - set b_slice [get_property bram_slice_begin $b] - if {$a_slice > $b_slice} { - return 1 - } elseif {$a_slice < $b_slice} { - return -1 - } - return 0 - } - dict for {name desc} $brams { - dict with desc { - puts $chn "\t\t> 3]\">" - puts $chn "\t\t\t" - foreach cell [lsort -command compare $cells] { - set type [switch [get_property REF_NAME $cell] \ - RAMB36E2 {expr {"RAMB32"}} \ - RAMB36E1 {expr {"RAMB32"}}] - set loc [lindex [split [get_property LOC $cell] "_"] 1] - set lsb [get_property bram_slice_begin $cell] - set msb [get_property bram_slice_end $cell] - set addr_bgn [get_property bram_addr_begin $cell] - set addr_end [get_property bram_addr_end $cell] - puts $chn "\t\t\t\t" - puts $chn "\t\t\t\t\t" - puts $chn "\t\t\t\t\t" - puts $chn "\t\t\t\t\t" - puts $chn "\t\t\t\t" - } - puts $chn "\t\t\t" - puts $chn "\t\t" - } - } - puts $chn "\t" - puts $chn "\t" - puts $chn "\t\t" - puts $chn "" - close $chn - current_instance - -} - -if {$argc != 3} { - puts $argc - puts {Error: Invalid number of arguments} - puts {Usage: write_mmi.tcl checkpoint mmi_file instance} -} - -lassign $argv checkpoint mmi_file instance - -open_checkpoint $checkpoint -write_mmi $mmi_file $instance From 1b4826ad82552375ca50d42542fb336fbfc0c5e9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 16:20:22 -0800 Subject: [PATCH 069/157] Generalize debug-bitstream --- docs/Prototyping/General.rst | 2 +- fpga/Makefile | 20 +++++---- fpga/scripts/run_impl_bitstream.tcl | 69 ++++++++++++++++++----------- 3 files changed, 55 insertions(+), 36 deletions(-) diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index b9fc5da3..a9a02af9 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -60,7 +60,7 @@ ILA (integrated logic analyzers) can be added to certain designs for debugging r First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). This can be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. -This will create a new bitstream called ``debug_output`` in the same location as the normal bitstream (``generated-src//obj``). +This will create a new bitstream called ``top.bit`` in a folder named ``generated-src//debug_obj/``. For example, running the bitstream build for an added ILA for a BOOM config.: .. code-block:: shell diff --git a/fpga/Makefile b/fpga/Makefile index 12bfd754..1437d8bc 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -27,6 +27,7 @@ ifeq ($(SUB_PROJECT),vcu118) TB ?= none # unused TOP ?= ChipTop BOARD ?= vcu118 + FPGA_BRAND ?= xilinx endif ifeq ($(SUB_PROJECT),bringup) @@ -40,6 +41,7 @@ ifeq ($(SUB_PROJECT),bringup) TB ?= none # unused TOP ?= ChipTop BOARD ?= vcu118 + FPGA_BRAND ?= xilinx endif ifeq ($(SUB_PROJECT),arty) @@ -54,6 +56,7 @@ ifeq ($(SUB_PROJECT),arty) TB ?= none # unused TOP ?= ChipTop BOARD ?= arty + FPGA_BRAND ?= xilinx endif include $(base_dir)/variables.mk @@ -67,7 +70,7 @@ default: $(mcs) ######################################################################################### # misc. directories ######################################################################################### -fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx +fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND) fpga_common_script_dir := $(fpga_dir)/common/tcl ######################################################################################### @@ -98,10 +101,10 @@ $(BIT_FILE): $(synth_list_f) -nojournal -mode batch \ -source $(fpga_common_script_dir)/vivado.tcl \ -tclargs \ - -top-module "$(MODEL)" \ - -F "$(synth_list_f)" \ - -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ - -board "$(BOARD)" + -top-module "$(MODEL)" \ + -F "$(synth_list_f)" \ + -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ + -board "$(BOARD)" .PHONY: bitstream bitstream: $(BIT_FILE) @@ -112,9 +115,10 @@ debug-bitstream: $(build_dir)/obj/post_synth.dcp -nojournal -mode batch \ -source $(sim_dir)/scripts/run_impl_bitstream.tcl \ -tclargs \ - $(build_dir)/obj/post_synth.dcp \ - xcvu9p-flga2104-2l-e \ - $(build_dir)/obj/debug_output + $(build_dir)/obj/post_synth.dcp \ + $(BOARD) \ + $(build_dir)/debug_obj \ + $(fpga_common_script_dir) ######################################################################################### # general cleanup rules diff --git a/fpga/scripts/run_impl_bitstream.tcl b/fpga/scripts/run_impl_bitstream.tcl index ec3828e8..31175904 100644 --- a/fpga/scripts/run_impl_bitstream.tcl +++ b/fpga/scripts/run_impl_bitstream.tcl @@ -2,44 +2,59 @@ # argv[0] = absolute path to post_synth checkpoint file # argv[1] = part # argv[2] = output directory +# argv[3] = common fpga brand tcl set synth_checkpoint_file [lindex $argv 0] -set part [lindex $argv 1] -set output_dir [lindex $argv 2] +set board [lindex $argv 1] +set wrkdir [lindex $argv 2] + +set scriptdir [lindex $argv 3] + +# Set the variable for all the common files +set commondir [file dirname $scriptdir] + +# Set the variable that points to board specific files +set boarddir [file join [file dirname $commondir] $board] +source [file join $boarddir tcl board.tcl] # Set the project part to the part passed into this script -set_part ${part} +set_part $part_fpga -# Create output directory if it doesn't exist -file mkdir ${output_dir} -file mkdir ${output_dir}/reports -file mkdir ${output_dir}/outputs +# Create output directories if they doesn't exist +file mkdir $wrkdir +set rptdir [file join $wrkdir report] +file mkdir $rptdir # Load synthesis checkpoint -open_checkpoint ${synth_checkpoint_file} +open_checkpoint $synth_checkpoint_file -# Run implementation and save reports as needed +# opt opt_design +write_checkpoint -force [file join $wrkdir post_opt] + +# place place_design phys_opt_design -write_checkpoint -force ${output_dir}/outputs/post_place -report_timing_summary -file ${output_dir}/reports/post_place_timing_summary.rpt -report_drc -file ${output_dir}/reports/post_place_drc.rpt +write_checkpoint -force [file join $wrkdir post_place] +report_timing_summary -file [file join $rptdir post_place_timing_summary.rpt] +report_drc -file [file join $rptdir post_place_drc.rpt] + +# route route_design -write_checkpoint -force ${output_dir}/outputs/post_route -report_timing_summary -file ${output_dir}/reports/post_route_timing_summary.rpt -report_timing -sort_by group -max_paths 100 -path_type summary -file ${output_dir}/reports/post_route_timing.rpt -report_clock_utilization -file ${output_dir}/reports/post_route_clock_utilization.rpt -report_utilization -file ${output_dir}/reports/post_route_utilization.rpt -report_drc -file ${output_dir}/reports/post_route_drc.rpt -report_cdc -details -file ${output_dir}/reports/post_route_cdc.rpt -report_clock_interaction -file ${output_dir}/reports/post_route_clock_interaction.rpt -report_bus_skew -file ${output_dir}/reports/post_route_bus_skew.rpt -report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file ${output_dir}/reports/post_route_timing_violations.rpt +write_checkpoint -force [filel join $wrkdir post_route] +report_timing_summary -file [file join $rptdir post_route_timing_summary.rpt] +report_timing -sort_by group -max_paths 100 -path_type summary -file [file join $rptdir post_route_timing.rpt] +report_clock_utilization -file [file join $rptdir post_route_clock_utilization.rpt] +report_utilization -file [file join $rptdir post_route_utilization.rpt] +report_drc -file [file join $rptdir post_route_drc.rpt] +report_cdc -details -file [file join $rptdir post_route_cdc.rpt] +report_clock_interaction -file [file join $rptdir post_route_clock_interaction.rpt] +report_bus_skew -file [file join $rptdir post_route_bus_skew.rpt] +report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file [file join $rptdir post_route_timing_violations.rpt] -write_verilog -force ${output_dir}/outputs/post_route.v -write_xdc -no_fixed_only -force ${output_dir}/outputs/post_route.xdc - -write_bitstream -force ${output_dir}/outputs/top.bit -write_debug_probes -force ${output_dir}/outputs/debug_nets.ltx +# bitstream +write_verilog -force [file join $wrkdir post_route.v] +write_xdc -no_fixed_only -force [file join $wrkdir post_route.xdc] +write_bitstream -force [file join $wrkdir top.bit] +write_debug_probes -force [file join $wrkdir debug_nets.ltx] From 61e1730c90f46ac9dcb3c91de36c95161ecfbe61 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 16:23:05 -0800 Subject: [PATCH 070/157] Small fix to docs --- docs/Prototyping/General.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index a9a02af9..a653f20a 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -22,7 +22,7 @@ Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you c .. code-block:: shell - make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... bitstream + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... FPGA_BRAND=... bitstream # or @@ -37,7 +37,7 @@ For example: # converts to - make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 bitstream + make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system. From f8bd8eaa2799a446dbc8eb7593952f1152d6e04b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 12 Nov 2020 16:24:10 -0800 Subject: [PATCH 071/157] Small fix to run_impl_bitstream --- fpga/scripts/run_impl_bitstream.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/scripts/run_impl_bitstream.tcl b/fpga/scripts/run_impl_bitstream.tcl index 31175904..8d9960c7 100644 --- a/fpga/scripts/run_impl_bitstream.tcl +++ b/fpga/scripts/run_impl_bitstream.tcl @@ -42,7 +42,7 @@ report_drc -file [file join $rptdir post_place_drc.rpt] # route route_design -write_checkpoint -force [filel join $wrkdir post_route] +write_checkpoint -force [file join $wrkdir post_route] report_timing_summary -file [file join $rptdir post_route_timing_summary.rpt] report_timing -sort_by group -max_paths 100 -path_type summary -file [file join $rptdir post_route_timing.rpt] report_clock_utilization -file [file join $rptdir post_route_clock_utilization.rpt] From c8add488ad0050b82eb55554cd44d5ec1937ffed Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 15 Nov 2020 14:31:14 -0800 Subject: [PATCH 072/157] Reduce BOOM default freq. (play it safe) --- fpga/src/main/scala/vcu118/Configs.scala | 2 +- fpga/src/main/scala/vcu118/bringup/Configs.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 07eefd19..3c52f249 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -60,7 +60,7 @@ class RocketVCU118Config extends Config( // DOC include end: AbstractVCU118 and Rocket class BoomVCU118Config extends Config( - new WithFPGAFrequency(75) ++ + new WithFPGAFrequency(50) ++ new WithVCU118Tweaks ++ new chipyard.MegaBoomConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 5e19cc5c..ec1ea1e3 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -85,7 +85,7 @@ class RocketBringupConfig extends Config( new chipyard.RocketConfig) class BoomBringupConfig extends Config( - new WithFPGAFrequency(70) ++ + new WithFPGAFrequency(50) ++ new WithBringupAdditions ++ new WithVCU118Tweaks ++ new chipyard.MegaBoomConfig) From d94a8efd4368763d141e6ee342c509a1fe19759d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 15 Nov 2020 15:44:38 -0800 Subject: [PATCH 073/157] Fix TLMemPort comment | Use Option instead of NoSimulator --- fpga/src/main/scala/vcu118/DigitalTop.scala | 2 +- .../utilities/src/main/scala/Simulator.scala | 25 +++++++++---------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala index 9fe42bc8..d5c747fa 100644 --- a/fpga/src/main/scala/vcu118/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/DigitalTop.scala @@ -69,7 +69,7 @@ class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends // VCU118 Mem Port Mixin // ------------------------------------ -/** Adds a TileLink port to the system intended to master an MMIO device bus */ +/** Adds a port to the system intended to master an TL DRAM controller. */ trait CanHaveMasterTLMemPort { this: BaseSubsystem => private val memPortParamsOpt = p(ExtMem) private val portName = "tl_mem" diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index d7f4d007..fa157a36 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -5,13 +5,12 @@ import java.io.File case class GenerateSimConfig( targetDir: String = ".", dotFName: String = "sim_files.f", - simulator: Simulator = VerilatorSimulator, + simulator: Option[Simulator] = Some(VerilatorSimulator) ) sealed trait Simulator object VerilatorSimulator extends Simulator object VCSSimulator extends Simulator -object NoSimulator extends Simulator trait HasGenerateSimConfig { val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { @@ -21,9 +20,9 @@ trait HasGenerateSimConfig { .abbr("sim") .valueName("") .action((x, c) => x match { - case "verilator" => c.copy(simulator = VerilatorSimulator) - case "vcs" => c.copy(simulator = VCSSimulator) - case "none" => c.copy(simulator = NoSimulator) + case "verilator" => c.copy(simulator = Some(VerilatorSimulator)) + case "vcs" => c.copy(simulator = Some(VCSSimulator)) + case "none" => c.copy(simulator = None) case _ => throw new Exception(s"Unrecognized simulator $x") }) .text("Name of simulator to generate files for (verilator, vcs, none)") @@ -49,10 +48,10 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { if (fname.takeRight(2) == ".h") { cfg.simulator match { // verilator needs to explicitly include verilator.h, so use the -FI option - case VerilatorSimulator => s"-FI ${fname}" + case Some(VerilatorSimulator) => s"-FI ${fname}" // vcs pulls headers in with +incdir, doesn't have anything like verilator.h - case VCSSimulator => "" - case NoSimulator => "" + case Some(VCSSimulator) => "" + case None => "" } } else { // do nothing otherwise fname @@ -84,7 +83,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { out.write(text) out.close() } - def resources(sim: Simulator): Seq[String] = Seq( + def resources(sim: Option[Simulator]): Seq[String] = Seq( "/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/testchip_tsi.cc", "/testchipip/csrc/testchip_tsi.h", @@ -99,7 +98,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { "/csrc/remote_bitbang.cc", "/vsrc/EICG_wrapper.v", ) ++ (sim match { - case NoSimulator => Seq() + case None => Seq() case _ => Seq( "/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/SimDRAM.cc", @@ -113,14 +112,14 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { "/csrc/remote_bitbang.cc", ) }) ++ (sim match { // simulator specific files to include - case VerilatorSimulator => Seq( + case Some(VerilatorSimulator) => Seq( "/csrc/emulator.cc", "/csrc/verilator.h", ) - case VCSSimulator => Seq( + case Some(VCSSimulator) => Seq( "/vsrc/TestDriver.v", ) - case NoSimulator => Seq() + case None => Seq() }) def writeBootrom(): Unit = { From ba59d0318fe8552d0b9018d9305ba0433ae1c40e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 15 Nov 2020 16:14:38 -0800 Subject: [PATCH 074/157] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 20d370be..8e5757b5 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 20d370be496d3f9e873e5e63bf8d220727701dff +Subproject commit 8e5757b5ceb8a2c0246e3368baa5bc347dd6f99b From 70d43210d880a1257f864141d87fa5a4d6c6fe58 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 15 Nov 2020 18:18:04 -0800 Subject: [PATCH 075/157] [temp] Unable to build/get past chisel-testers --- .sbtopts | 2 ++ build.sbt | 8 ++------ common.mk | 20 +------------------- generators/boom | 2 +- generators/cva6 | 2 +- generators/hwacha | 2 +- generators/riscv-sodor | 2 +- generators/sifive-blocks | 2 +- generators/sifive-cache | 2 +- project/build.properties | 2 +- project/plugins.sbt | 6 ++++-- tools/chisel-testers | 2 +- tools/firrtl-interpreter | 2 +- tools/treadle | 2 +- variables.mk | 8 +++++++- 15 files changed, 26 insertions(+), 38 deletions(-) create mode 100644 .sbtopts diff --git a/.sbtopts b/.sbtopts new file mode 100644 index 00000000..e6cc0650 --- /dev/null +++ b/.sbtopts @@ -0,0 +1,2 @@ +-Dsbt.sourcemode=true +-Dsbt.workspace=$PWD diff --git a/build.sbt b/build.sbt index bbf7964f..e6320076 100644 --- a/build.sbt +++ b/build.sbt @@ -14,7 +14,7 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.8" % "test", + libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.0" % "test", libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", @@ -77,11 +77,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => } toSeq // Subproject definitions begin -// -// FIRRTL is handled as an unmanaged dependency. Make will build the firrtl jar -// before launching sbt if any of the firrtl source files has been updated -// The jar is dropped in chipyard's lib/ directory, which is used as the unmanagedBase -// for all subprojects + lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) diff --git a/common.mk b/common.mk index ca34ffce..d0b11fe3 100644 --- a/common.mk +++ b/common.mk @@ -65,24 +65,6 @@ VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt -######################################################################################### -# jar creation variables and rules -######################################################################################### -FIRRTL_JAR := $(base_dir)/lib/firrtl.jar -FIRRTL_TEST_JAR := $(base_dir)/test_lib/firrtl-test.jar - -$(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) - $(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala - mkdir -p $(@D) - cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@ - touch $@ - -$(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) - cd $(CHIPYARD_FIRRTL_DIR) && $(SBT) "test:assembly" - mkdir -p $(@D) - cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@ - touch $@ - ######################################################################################### # Bloop Project Definitions ######################################################################################### @@ -93,7 +75,7 @@ $(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES) ######################################################################################### # create list of simulation file inputs ######################################################################################### -$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS) +$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(SCALA_BUILDTOOL_DEPS) $(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name)) ######################################################################################### diff --git a/generators/boom b/generators/boom index dc22cacf..2dfec3d0 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit dc22cacf71fe88b95f3393d622f53648bf0440bd +Subproject commit 2dfec3d012e61ff07108af6034a86e60979deecd diff --git a/generators/cva6 b/generators/cva6 index 8a11e2c9..c2b9fc41 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 8a11e2c97627459d0449853447bfc7ca64608b82 +Subproject commit c2b9fc412179a386fb4b662d13e588a9613f41d5 diff --git a/generators/hwacha b/generators/hwacha index e29b65db..c1b7306f 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit e29b65db86e4486ebdfd4f39d1265df83a2d7d9d +Subproject commit c1b7306f319aef6ea9ff0fd88d11d10244ee9e87 diff --git a/generators/riscv-sodor b/generators/riscv-sodor index d92a8476..cca8a7aa 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit d92a8476e4afbae189381d708136aef7d3970952 +Subproject commit cca8a7aa5743b9f9bf25779b87b464187c5c3fbc diff --git a/generators/sifive-blocks b/generators/sifive-blocks index c240e629..612ed01d 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit c240e629e2fc111cbb12e4fe707be898b5204984 +Subproject commit 612ed01df3be83ad0198fb9bd7e367ea43df3d56 diff --git a/generators/sifive-cache b/generators/sifive-cache index 4ebefa3e..d4db623f 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 4ebefa3e30ec44bd2f4ff82747025fb7b362b954 +Subproject commit d4db623ff534f775ffc49f59c4a9ef24d5d759d0 diff --git a/project/build.properties b/project/build.properties index 8522443d..0837f7a1 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.3.2 +sbt.version=1.3.13 diff --git a/project/plugins.sbt b/project/plugins.sbt index 3fe776fa..8c0937ed 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -5,16 +5,18 @@ resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven" addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") -addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0") +addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.10.0") addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3") addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1") addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") -addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6") +addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") +addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") +addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" diff --git a/tools/chisel-testers b/tools/chisel-testers index 1aa906fe..c5b99a45 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit 1aa906fe168eb5ddca705ec955b27cf5c8856e4d +Subproject commit c5b99a452f84af3f581d34e9c51c6c65b6c2a63c diff --git a/tools/firrtl-interpreter b/tools/firrtl-interpreter index a881c07d..5ab0cfe7 160000 --- a/tools/firrtl-interpreter +++ b/tools/firrtl-interpreter @@ -1 +1 @@ -Subproject commit a881c07df6bceea462dbbd9a28e25721a1e88567 +Subproject commit 5ab0cfe7020ca17804078c85d020730764ee176f diff --git a/tools/treadle b/tools/treadle index 1c67bc84..925687ad 160000 --- a/tools/treadle +++ b/tools/treadle @@ -1 +1 @@ -Subproject commit 1c67bc846aafc3bdd707f76ead8cefd5f93e0376 +Subproject commit 925687ad22c42dd2c8b4dc127c0476f9902b3163 diff --git a/variables.mk b/variables.mk index b187a23d..2828366c 100644 --- a/variables.mk +++ b/variables.mk @@ -154,6 +154,12 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M SCALA_VERSION=2.12.10 SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar +# Running with sbt-launch.jar doesn't read .sbtopts by default +# # Set if the file exists (if it exists, we're building chisel3 and firrtl from source) +sbtopts_file := $(base_dir)/.sbtopts +ifneq (,$(wildcard $(sbtopts_file))) + SBT_OPTS ?= $(shell cat $(sbtopts_file)) +endif BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop @@ -176,7 +182,7 @@ define run_scala_main endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) $(SBT_OPTS) "project $(1)" "runMain $(2) $(3)" endef endif From 9d9813fe0abf8146aaade002ef06203b8065c491 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 16 Nov 2020 22:24:18 -0800 Subject: [PATCH 076/157] [temp] Following RC's way to build Chisel from source or Maven [ci skip] --- .sbtopts | 2 +- build.sbt | 25 ++++++++++++++++++++----- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/.sbtopts b/.sbtopts index e6cc0650..2358d787 100644 --- a/.sbtopts +++ b/.sbtopts @@ -1,2 +1,2 @@ -Dsbt.sourcemode=true --Dsbt.workspace=$PWD +-Dsbt.workspace=$PWD/tools diff --git a/build.sbt b/build.sbt index e6320076..cffc235d 100644 --- a/build.sbt +++ b/build.sbt @@ -78,7 +78,15 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin -lazy val chisel = (project in file("tools/chisel3")) +// This needs to stay in sync with the chisel3 and firrtl git submodules +val chiselVersion = "3.4.0" + +lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") +lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion +// While not built from source, *must* be in sync with the chisel3 git submodule +// Building from source requires extending sbt-sriracha or a similar plugin and +// keeping scalaVersion in sync with chisel3 to the minor version +lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .settings(commonSettings) @@ -87,7 +95,9 @@ lazy val treadle = (project in file("tools/treadle")) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .dependsOn(chisel, firrtl_interpreter, treadle) + .sourceDependency(chiselRef, chiselLib) + .dependsOn(firrtl_interpreter, treadle) + .settings(addCompilerPlugin(chiselPluginLib)) .settings( commonSettings, libraryDependencies ++= Seq( @@ -113,15 +123,18 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) + .sourceDependency(chiselRef, chiselLib) + .dependsOn(hardfloat, rocketMacros, rocketConfig) + .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) - .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig) lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) lazy val iocell = (project in file("./tools/barstools/iocell/")) - .dependsOn(chisel) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) @@ -184,7 +197,9 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) - .dependsOn(chisel, chisel_testers) + .sourceDependency(chiselRef, chiselLib) + .dependsOn(chisel_testers) + .settings(addCompilerPlugin(chiselPluginLib)) .settings( commonSettings, libraryDependencies ++= Seq( From a0d479f3ea996524c9a57a65dff4128b2da5604f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 16 Nov 2020 22:55:04 -0800 Subject: [PATCH 077/157] Working FIRRTL/RC/Chisel3 build | chisel-testers still broken --- build.sbt | 27 +++++++++------------------ project/plugins.sbt | 2 +- 2 files changed, 10 insertions(+), 19 deletions(-) diff --git a/build.sbt b/build.sbt index cffc235d..27b08a3b 100644 --- a/build.sbt +++ b/build.sbt @@ -79,14 +79,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin // This needs to stay in sync with the chisel3 and firrtl git submodules -val chiselVersion = "3.4.0" - -lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") -lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion -// While not built from source, *must* be in sync with the chisel3 git submodule -// Building from source requires extending sbt-sriracha or a similar plugin and -// keeping scalaVersion in sync with chisel3 to the minor version -lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full +lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .settings(commonSettings) @@ -95,9 +88,7 @@ lazy val treadle = (project in file("tools/treadle")) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .sourceDependency(chiselRef, chiselLib) - .dependsOn(firrtl_interpreter, treadle) - .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(firrtl_interpreter, treadle, chisel) .settings( commonSettings, libraryDependencies ++= Seq( @@ -123,18 +114,20 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .sourceDependency(chiselRef, chiselLib) - .dependsOn(hardfloat, rocketMacros, rocketConfig) - .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(hardfloat, rocketMacros, rocketConfig, chisel) .settings(commonSettings) + .settings( // Settings for scalafix + semanticdbEnabled := true, + semanticdbVersion := scalafixSemanticdb.revision, + scalacOptions += "-Ywarn-unused-import" + ) lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) lazy val iocell = (project in file("./tools/barstools/iocell/")) - .sourceDependency(chiselRef, chiselLib) - .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(chisel) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) @@ -197,9 +190,7 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) - .sourceDependency(chiselRef, chiselLib) .dependsOn(chisel_testers) - .settings(addCompilerPlugin(chiselPluginLib)) .settings( commonSettings, libraryDependencies ++= Seq( diff --git a/project/plugins.sbt b/project/plugins.sbt index 8c0937ed..b6fe132a 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -13,7 +13,7 @@ addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") -addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") +addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") From 1b00d540f0a964dfbe86449df6491eda7910d639 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 17 Nov 2020 15:14:30 -0800 Subject: [PATCH 078/157] Add config fragment for replacing L2 with broadcastManager --- generators/chipyard/src/main/scala/ConfigFragments.scala | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 479120ba..c5c85e47 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -151,6 +151,11 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { } }) +// Replaces the L2 with a broadcast manager for maintaining coherence +class WithBroadcastManager extends Config((site, here, up) => { + case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) +}) + class WithHwachaTest extends Config((site, here, up) => { case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => { up(TestSuitesKey).apply(tileParams, suiteHelper, p) From 95e83651051e9ee49c5fed2e67cfb90e42f6b458 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Wed, 18 Nov 2020 16:53:37 -0800 Subject: [PATCH 079/157] Small change to Arty reset binder name, per Jerry's PR comment. --- fpga/src/main/scala/arty/IOBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala index 205f8fcc..78a1f0ee 100644 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -8,7 +8,7 @@ import freechips.rocketchip.devices.debug._ import chipyard.iobinders.{ComposeIOBinder} -class WithResetPassthrough extends ComposeIOBinder({ +class WithDebugResetPassthrough extends ComposeIOBinder({ (system: HasPeripheryDebugModuleImp) => { // Debug module reset val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset") From 5b1b4b3efe65299360a0de838bcc2c7025880b38 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 19 Nov 2020 15:28:24 -0800 Subject: [PATCH 080/157] Bump Gemmini/Hwacha/Sha3 --- generators/gemmini | 2 +- generators/hwacha | 2 +- generators/sha3 | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/gemmini b/generators/gemmini index caaf781e..371bc330 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit caaf781ec9d69e45443e496046bc6ab439e3e54f +Subproject commit 371bc33038e633779f52e26eaa0031f2820c2f0d diff --git a/generators/hwacha b/generators/hwacha index c1b7306f..e0109674 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit c1b7306f319aef6ea9ff0fd88d11d10244ee9e87 +Subproject commit e0109674572f4b40641a89db9e0429e51b5cb73a diff --git a/generators/sha3 b/generators/sha3 index 762d9d08..a4ea9602 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 762d9d08f8ccd96ba7ab12ead6d38a6b57fa8710 +Subproject commit a4ea960248fdf8267b515723d472b018b09ac24f From 222580a290ec243d8cc97154b61d5e1467b35c69 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 19 Nov 2020 16:13:58 -0800 Subject: [PATCH 081/157] Bump dsptools --- tools/dsptools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/dsptools b/tools/dsptools index e32ab8a0..ce6d87b2 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit e32ab8a0c77d419b52376064534090ff2583929d +Subproject commit ce6d87b2f23bf87085e4913e8324513147f43488 From 571e7517eb57deb10ad32e0e8e2d0ec1aaec036f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 19 Nov 2020 20:06:28 -0800 Subject: [PATCH 082/157] Bump barstools, chisel-testers, dsptools | Split build.sbt dependencies between projects | Bump CY collateral --- .gitmodules | 2 +- build.sbt | 78 ++++++++++++------- .../scala/clocking/ResetSynchronizer.scala | 30 ------- .../src/main/scala/example/NodeTypes.scala | 8 +- .../src/main/scala/example/TutorialTile.scala | 2 + tools/barstools | 2 +- tools/chisel-testers | 2 +- tools/dsptools | 2 +- 8 files changed, 60 insertions(+), 66 deletions(-) delete mode 100644 generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala diff --git a/.gitmodules b/.gitmodules index 7054c14f..55b4be56 100644 --- a/.gitmodules +++ b/.gitmodules @@ -76,7 +76,7 @@ url = https://github.com/ucb-bar/dsptools.git [submodule "tools/chisel-testers"] path = tools/chisel-testers - url = https://github.com/freechipsproject/chisel-testers.git + url = https://github.com/abejgonzalez/chisel-testers.git [submodule "tools/treadle"] path = tools/treadle url = https://github.com/freechipsproject/treadle.git diff --git a/build.sbt b/build.sbt index 27b08a3b..77a0962a 100644 --- a/build.sbt +++ b/build.sbt @@ -14,14 +14,11 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.0" % "test", - libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1", + libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.2" % "test", + libraryDependencies += "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", + libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.10", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, - libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", - libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", - libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", - libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), @@ -72,9 +69,9 @@ def freshProject(name: String, dir: File): Project = { // Fork each scala test for now, to work around persistent mutable state // in Rocket-Chip based generators def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => - val options = ForkOptions() - new Group(test.name, Seq(test), SubProcess(options)) - } toSeq + val options = ForkOptions() + new Group(test.name, Seq(test), SubProcess(options)) +} toSeq // Subproject definitions begin @@ -82,22 +79,32 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "org.scala-lang.modules" % "scala-jline" % "2.12.1", + )) lazy val treadle = (project in file("tools/treadle")) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "org.scala-lang.modules" % "scala-jline" % "2.12.1", + "com.github.scopt" %% "scopt" % "3.7.1", + "org.json4s" %% "json4s-native" % "3.6.10" + )) lazy val chisel_testers = (project in file("tools/chisel-testers")) .dependsOn(firrtl_interpreter, treadle, chisel) .settings( - commonSettings, - libraryDependencies ++= Seq( - "junit" % "junit" % "4.12", - "org.scalatest" %% "scalatest" % "3.0.5", - "org.scalacheck" %% "scalacheck" % "1.14.0", - "com.github.scopt" %% "scopt" % "3.7.0" - ) - ) + commonSettings, + libraryDependencies ++= Seq( + "junit" % "junit" % "4.13", + "org.scalatest" %% "scalatest" % "3.2.2", + "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1", + "org.scalacheck" %% "scalacheck" % "1.14.3", + "com.github.scopt" %% "scopt" % "3.7.1" + )) // Contains annotations & firrtl passes you may wish to use in rocket-chip without // introducing a circular dependency between RC and MIDAS @@ -170,7 +177,11 @@ lazy val sha3 = (project in file("generators/sha3")) lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "org.scalanlp" %% "breeze" % "0.13.2" + )) lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) @@ -182,26 +193,37 @@ lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeo .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "com.typesafe.play" %% "play-json" % "2.6.10" + )) lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .dependsOn(firrtl_interpreter, mdf, rocketchip) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) +val dsptoolsDependencies = Seq( + "org.scalanlp" %% "breeze" % "1.0", + "junit" % "junit" % "4.13" % "test", + "org.scalatest" %% "scalatest" % "3.2.2", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" +) + lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel_testers) .settings( - commonSettings, - libraryDependencies ++= Seq( - "junit" % "junit" % "4.13" % "test", - "org.scalatest" %% "scalatest" % "3.0.8", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" - )) + commonSettings, + libraryDependencies ++= dsptoolsDependencies + ) lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= dsptoolsDependencies + ) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) diff --git a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala deleted file mode 100644 index 2ba8e855..00000000 --- a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala +++ /dev/null @@ -1,30 +0,0 @@ - -package chipyard.clocking - -import chisel3._ - -import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.prci._ -import freechips.rocketchip.util.{ResetCatchAndSync} - -/** - * Instantiates a reset synchronizer on all clock-reset pairs in a clock group - */ -class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { - val node = ClockGroupAdapterNode() - lazy val module = new LazyRawModuleImp(this) { - (node.out zip node.in).map { case ((oG, _), (iG, _)) => - (oG.member.data zip iG.member.data).foreach { case (o, i) => - o.clock := i.clock - o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) - } - } - } -} - -object ClockGroupResetSynchronizer { - def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node -} - - diff --git a/generators/chipyard/src/main/scala/example/NodeTypes.scala b/generators/chipyard/src/main/scala/example/NodeTypes.scala index 0e2b6565..914e5ba5 100644 --- a/generators/chipyard/src/main/scala/example/NodeTypes.scala +++ b/generators/chipyard/src/main/scala/example/NodeTypes.scala @@ -11,7 +11,7 @@ import testchipip.TLHelper // DOC include start: MyClient class MyClient(implicit p: Parameters) extends LazyModule { - val node = TLHelper.makeClientNode(TLClientParameters( + val node = TLHelper.makeClientNode(TLMasterParameters.v1( name = "my-client", sourceId = IdRange(0, 4), requestFifo = true, @@ -29,7 +29,7 @@ class MyClient(implicit p: Parameters) extends LazyModule { class MyManager(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("my-device", Seq("tutorial,my-device0")) val beatBytes = 8 - val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( + val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1( address = Seq(AddressSet(0x20000, 0xfff)), resources = device.reg, regionType = RegionType.UNCACHED, @@ -83,7 +83,7 @@ class MyClientGroup(implicit p: Parameters) extends LazyModule { // DOC include start: MyManagerGroup class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule { - val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( + val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1( address = Seq(AddressSet(0x0, 0xfff)))) lazy val module = new LazyModuleImp(this) { @@ -92,7 +92,7 @@ class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule { } class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule { - val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( + val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1( address = Seq(AddressSet(0x1000, 0xfff)))) lazy val module = new LazyModuleImp(this) { diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 9af2cb54..23b05f76 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -43,6 +43,8 @@ case class MyCoreParams( val pmpGranularity: Int = 4 // copied from Rocket val nBreakpoints: Int = 0 // TODO: Check val useBPWatch: Boolean = false + val mcontextWidth: Int = 0 + val scontextWidth: Int = 0 val nPerfCounters: Int = 29 val haveBasicCounters: Boolean = true val haveFSDirty: Boolean = false diff --git a/tools/barstools b/tools/barstools index 8e5757b5..845af06b 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 8e5757b5ceb8a2c0246e3368baa5bc347dd6f99b +Subproject commit 845af06b1515c69b1d788726134e92b808bf45e4 diff --git a/tools/chisel-testers b/tools/chisel-testers index c5b99a45..5b9cc56d 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit c5b99a452f84af3f581d34e9c51c6c65b6c2a63c +Subproject commit 5b9cc56dd80c8d3bce67d54385d769037e2481d8 diff --git a/tools/dsptools b/tools/dsptools index ce6d87b2..74612fd7 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit ce6d87b2f23bf87085e4913e8324513147f43488 +Subproject commit 74612fd76645bfcfcc1c711ed43025cb8105e539 From 11ab0d73461f7322ce906f9beb0133a01fa4116c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 10:48:44 -0800 Subject: [PATCH 083/157] Put libdeps back into commonSettings in build.sbt --- build.sbt | 56 ++++++++++++++++++------------------------------------- 1 file changed, 18 insertions(+), 38 deletions(-) diff --git a/build.sbt b/build.sbt index 77a0962a..e58e7d60 100644 --- a/build.sbt +++ b/build.sbt @@ -18,7 +18,13 @@ lazy val commonSettings = Seq( libraryDependencies += "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.10", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, + libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.1", + libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", + libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", + libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", + libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.10", + libraryDependencies += "junit" % "junit" % "4.13", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), @@ -75,27 +81,16 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin -// This needs to stay in sync with the chisel3 and firrtl git submodules lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scala-lang.modules" % "scala-jline" % "2.12.1", - )) + .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scala-lang.modules" % "scala-jline" % "2.12.1", - "com.github.scopt" %% "scopt" % "3.7.1", - "org.json4s" %% "json4s-native" % "3.6.10" - )) + .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .dependsOn(firrtl_interpreter, treadle, chisel) + .dependsOn(chisel, firrtl_interpreter, treadle) .settings( commonSettings, libraryDependencies ++= Seq( @@ -121,7 +116,7 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .dependsOn(hardfloat, rocketMacros, rocketConfig, chisel) + .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig) .settings(commonSettings) .settings( // Settings for scalafix semanticdbEnabled := true, @@ -177,11 +172,7 @@ lazy val sha3 = (project in file("generators/sha3")) lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scalanlp" %% "breeze" % "0.13.2" - )) + .settings(commonSettings) lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) @@ -193,37 +184,26 @@ lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeo .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "com.typesafe.play" %% "play-json" % "2.6.10" - )) + .settings(commonSettings) lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .dependsOn(firrtl_interpreter, mdf, rocketchip) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) -val dsptoolsDependencies = Seq( - "org.scalanlp" %% "breeze" % "1.0", - "junit" % "junit" % "4.13" % "test", - "org.scalatest" %% "scalatest" % "3.2.2", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" -) - lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel_testers) .settings( commonSettings, - libraryDependencies ++= dsptoolsDependencies - ) + libraryDependencies ++= Seq( + "junit" % "junit" % "4.13" % "test", + "org.scalatest" %% "scalatest" % "3.2.2", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" + )) lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) - .settings( - commonSettings, - libraryDependencies ++= dsptoolsDependencies - ) + .settings(commonSettings) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) From 2b4fb555af8dc06c8f6fe19c32d1002afebc0f09 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 12:15:19 -0800 Subject: [PATCH 084/157] Use ProjectRef for FIRRTL and use it for firrtl-interpreter --- build.sbt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index e58e7d60..51172677 100644 --- a/build.sbt +++ b/build.sbt @@ -81,9 +81,12 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin -lazy val chisel = (project in file("tools/chisel3")) +lazy val chisel = (project in file("tools/chisel3")) + +lazy val firrtl = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) + .dependsOn(firrtl) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) @@ -107,7 +110,8 @@ lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") // Rocket-chip dependencies (subsumes making RC a RootProject) lazy val hardfloat = (project in rocketChipDir / "hardfloat") - .settings(commonSettings).dependsOn(midasTargetUtils) + .dependsOn(midasTargetUtils) + .settings(commonSettings) lazy val rocketMacros = (project in rocketChipDir / "macros") .settings(commonSettings) From 51b254f6b34f4f2535c260d4ba71030992f9f113 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 13:52:38 -0800 Subject: [PATCH 085/157] Small build.sbt cleanup --- build.sbt | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/build.sbt b/build.sbt index 51172677..ba0fea4e 100644 --- a/build.sbt +++ b/build.sbt @@ -1,12 +1,12 @@ import Tests._ -// This gives us a nicer handle to the root project instead of using the +// This gives us a nicer handle to the root project instead of using the // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) lazy val commonSettings = Seq( organization := "edu.berkeley.cs", - version := "1.0", + version := "1.3", scalaVersion := "2.12.10", traceLevel := 15, test in assembly := {}, @@ -14,17 +14,19 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.2" % "test", - libraryDependencies += "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", - libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.10", - libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, - libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.1", - libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", - libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", - libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", - libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", - libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.10", - libraryDependencies += "junit" % "junit" % "4.13", + libraryDependencies ++= Seq( + "org.scalatest" %% "scalatest" % "3.2.2" % "test", + "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", + "org.json4s" %% "json4s-jackson" % "3.6.10", + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "com.github.scopt" %% "scopt" % "3.7.1", + "org.scala-lang.modules" % "scala-jline" % "2.12.1", + "com.typesafe.play" %% "play-json" % "2.6.10", + "org.typelevel" %% "spire" % "0.16.2", + "org.scalanlp" %% "breeze" % "1.0", + "org.json4s" %% "json4s-native" % "3.6.10", + "junit" % "junit" % "4.13" + ), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), From c6e49e0716ba21e34f83447c6f2156d0d3946fa9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 15:05:00 -0800 Subject: [PATCH 086/157] Follow RC's SBT sriracha use | Bump FIRRTL plugin --- build.sbt | 21 ++++++++++++++++----- project/plugins.sbt | 2 +- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/build.sbt b/build.sbt index ba0fea4e..6ac4c85e 100644 --- a/build.sbt +++ b/build.sbt @@ -83,19 +83,27 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin +val chiselVersion = "3.4.0" lazy val chisel = (project in file("tools/chisel3")) +lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion +// While not built from source, *must* be in sync with the chisel3 git submodule +// Building from source requires extending sbt-sriracha or a similar plugin and +// keeping scalaVersion in sync with chisel3 to the minor version +lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -lazy val firrtl = ProjectRef(workspaceDirectory / "firrtl", "firrtl") +lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .dependsOn(firrtl) + .dependsOn(firrtlRef) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .dependsOn(chisel, firrtl_interpreter, treadle) + .sourceDependency(chisel, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(firrtl_interpreter, treadle) .settings( commonSettings, libraryDependencies ++= Seq( @@ -122,7 +130,9 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig) + .sourceDependency(chisel, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(hardfloat, rocketMacros, rocketConfig) .settings(commonSettings) .settings( // Settings for scalafix semanticdbEnabled := true, @@ -135,7 +145,8 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val iocell = (project in file("./tools/barstools/iocell/")) - .dependsOn(chisel) + .sourceDependency(chisel, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) diff --git a/project/plugins.sbt b/project/plugins.sbt index b6fe132a..496deb8d 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -19,4 +19,4 @@ addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) -libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" +libraryDependencies += "com.github.os72" % "protoc-jar" % "3.11.4" From 6f827456c8403e2809e0ae1d28ed4342cbb0102b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 16:09:07 -0800 Subject: [PATCH 087/157] Helper make target to launch SBT | Move SBT_OPTS to SBT variable --- common.mk | 8 ++++++++ variables.mk | 9 +++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/common.mk b/common.mk index d0b11fe3..80565a37 100644 --- a/common.mk +++ b/common.mk @@ -218,6 +218,14 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) +####################################### +# Helper to run SBT # +####################################### + +.PHONY: launch-sbt +launch-sbt: + cd $(base_dir) && $(SBT) + ######################################################################################### # print help text ######################################################################################### diff --git a/variables.mk b/variables.mk index 2828366c..42dc48c5 100644 --- a/variables.mk +++ b/variables.mk @@ -151,9 +151,6 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M ######################################################################################### # default sbt launch command ######################################################################################### -SCALA_VERSION=2.12.10 -SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) -SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar # Running with sbt-launch.jar doesn't read .sbtopts by default # # Set if the file exists (if it exists, we're building chisel3 and firrtl from source) sbtopts_file := $(base_dir)/.sbtopts @@ -161,6 +158,10 @@ ifneq (,$(wildcard $(sbtopts_file))) SBT_OPTS ?= $(shell cat $(sbtopts_file)) endif +SCALA_VERSION=2.12.10 +SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) +SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) + BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop # This mirrors the bloop default. Set to a system-unique port in a multi-user environment @@ -182,7 +183,7 @@ define run_scala_main endef else define run_scala_main - cd $(base_dir) && $(SBT) $(SBT_OPTS) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" endef endif From 3dfc03c31de01ec99f3b36d50c74ed4ba397f0e0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 17:02:59 -0800 Subject: [PATCH 088/157] Add more plugins and libdeps --- build.sbt | 7 +++++-- project/plugins.sbt | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index 6ac4c85e..00605b69 100644 --- a/build.sbt +++ b/build.sbt @@ -25,7 +25,9 @@ lazy val commonSettings = Seq( "org.typelevel" %% "spire" % "0.16.2", "org.scalanlp" %% "breeze" % "1.0", "org.json4s" %% "json4s-native" % "3.6.10", - "junit" % "junit" % "4.13" + "junit" % "junit" % "4.13", + "org.apache.commons" % "commons-text" % "1.8", + "net.jcazevedo" %% "moultingyaml" % "0.4.2" ), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, @@ -98,12 +100,13 @@ lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) + .dependsOn(firrtlRef) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) .sourceDependency(chisel, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) - .dependsOn(firrtl_interpreter, treadle) + .dependsOn(firrtl_interpreter, treadle, firrtlRef) .settings( commonSettings, libraryDependencies ++= Seq( diff --git a/project/plugins.sbt b/project/plugins.sbt index 496deb8d..61e69a3d 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -11,7 +11,7 @@ addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1") addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") -addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") +addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") From 9545abb65de6490b8a6e9ee760b21d131916f4cc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 21 Nov 2020 10:40:11 -0800 Subject: [PATCH 089/157] Working elaboration (breaks during barstools FIRRTL) --- build.sbt | 45 ++++++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/build.sbt b/build.sbt index 00605b69..968b22cd 100644 --- a/build.sbt +++ b/build.sbt @@ -27,7 +27,8 @@ lazy val commonSettings = Seq( "org.json4s" %% "json4s-native" % "3.6.10", "junit" % "junit" % "4.13", "org.apache.commons" % "commons-text" % "1.8", - "net.jcazevedo" %% "moultingyaml" % "0.4.2" + "net.jcazevedo" %% "moultingyaml" % "0.4.2", + "org.antlr" % "antlr4-runtime" % "4.7.1" ), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, @@ -47,19 +48,6 @@ lazy val firesimDir = if (firesimAsLibrary) { file("../../sim") } -// Checks for -DROCKET_USE_MAVEN. -// If it's there, use a maven dependency. -// Else, depend on subprojects in git submodules. -def conditionalDependsOn(prj: Project): Project = { - if (sys.props.contains("ROCKET_USE_MAVEN")) { - prj.settings(Seq( - libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT", - )) - } else { - prj.dependsOn(testchipip) - } -} - /** * It has been a struggle for us to override settings in subprojects. * An example would be adding a dependency to rocketchip on midas's targetutils library, @@ -93,20 +81,21 @@ lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") +lazy val firrtlRef = ProjectRef(file("tools/firrtl"), "firrtl") +lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % "1.4-SNAPSHOT" lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .dependsOn(firrtlRef) + .sourceDependency(firrtlRef, firrtlLib) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) - .dependsOn(firrtlRef) + .sourceDependency(firrtlRef, firrtlLib) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) .sourceDependency(chisel, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) - .dependsOn(firrtl_interpreter, treadle, firrtlRef) + .dependsOn(firrtl_interpreter, treadle) .settings( commonSettings, libraryDependencies ++= Seq( @@ -146,24 +135,28 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir) lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) +lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT" lazy val iocell = (project in file("./tools/barstools/iocell/")) .sourceDependency(chisel, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) -lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) +lazy val chipyard = (project in file("generators/chipyard")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) .settings(commonSettings) -lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) +lazy val tracegen = (project in file("generators/tracegen")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip, sifive_cache, boom, utilities) .settings(commonSettings) -lazy val utilities = conditionalDependsOn(project in file("generators/utilities")) +lazy val utilities = (project in file("generators/utilities")) + .sourceDependency(testchipip, testchipipLib) .settings(commonSettings) lazy val icenet = (project in file("generators/icenet")) @@ -174,7 +167,8 @@ lazy val hwacha = (project in file("generators/hwacha")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val boom = conditionalDependsOn(project in file("generators/boom")) +lazy val boom = (project in file("generators/boom")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip) .settings(commonSettings) @@ -198,8 +192,8 @@ lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) - .dependsOn(chisel_testers, chipyard) +lazy val tapeout = (project in file("./tools/barstools/tapeout/")) + .dependsOn(chisel_testers, chipyard) // must depend on chipyard to get scala resources .settings(commonSettings) .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) @@ -238,7 +232,8 @@ lazy val sifive_cache = (project in file("generators/sifive-cache")).settings( lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") -lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) +lazy val firechip = (project in file("generators/firechip")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, From 94c85c70bbe173077d1665190ccf1e3863bfeb4e Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 16 Nov 2020 10:37:23 -0800 Subject: [PATCH 090/157] bump IceNet for input/output tap and checksum fixes --- generators/icenet | 2 +- software/firemarshal | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/icenet b/generators/icenet index 277a9080..c14e5a02 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 +Subproject commit c14e5a02a7e4fee4d59b6cb0c1087976aba3fe14 diff --git a/software/firemarshal b/software/firemarshal index 45aebace..199f23ed 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 45aebace86d3a46c357337a19d4c8e894a5d0ed4 +Subproject commit 199f23ed74f723313b3bf225a9b4cfed8b6f6399 From 661a7701a70d5d776a85b7f7621df23afeeec8f2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 23 Nov 2020 15:46:03 -0800 Subject: [PATCH 091/157] Share DigitalTop/ChipyardSystem | Fix small naming compile error --- fpga/src/main/scala/arty/Configs.scala | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 9 +- fpga/src/main/scala/vcu118/DigitalTop.scala | 106 ------------------ .../main/scala/vcu118/HarnessBinders.scala | 2 +- fpga/src/main/scala/vcu118/IOBinders.scala | 1 + fpga/src/main/scala/vcu118/TestHarness.scala | 4 +- .../scala/vcu118/bringup/DigitalTop.scala | 6 +- .../chipyard/src/main/scala/DigitalTop.scala | 2 + .../chipyard/src/main/scala/System.scala | 48 +++++++- 9 files changed, 63 insertions(+), 117 deletions(-) delete mode 100644 fpga/src/main/scala/vcu118/DigitalTop.scala diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 61a6234c..2a78a54c 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -31,7 +31,7 @@ class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ new WithArtyResetHarnessBinder ++ - new WithResetPassthrough ++ + new WithDebugResetPassthrough ++ new WithDefaultPeripherals ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 3c52f249..44913ba2 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -17,7 +17,7 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem} +import chipyard.{BuildSystem, ExtTLMem} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) @@ -26,7 +26,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => { }) class WithSystemModifications extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top case DebugModuleKey => None // disable debug module case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) @@ -41,6 +40,11 @@ class WithSystemModifications extends Config((site, here, up) => { case SerialTLKey => None // remove serialized tl port }) +class WithTLBackingMemory extends Config((site, here, up) => { + case ExtMem => None // disable AXI backing memory + case ExtTLMem => up(ExtMem, site) // enable TL backing memory +}) + // DOC include start: AbstractVCU118 and Rocket class WithVCU118Tweaks extends Config( new WithUART ++ @@ -50,6 +54,7 @@ class WithVCU118Tweaks extends Config( new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ + new WithTLBackingMemory ++ // use TL backing memory new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala deleted file mode 100644 index d5c747fa..00000000 --- a/fpga/src/main/scala/vcu118/DigitalTop.scala +++ /dev/null @@ -1,106 +0,0 @@ -package chipyard.fpga.vcu118 - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util.{DontTouch} - -import chipyard.{DigitalTop, DigitalTopModule, ChipyardSubsystem, ChipyardSubsystemModuleImp} - -// ------------------------------------ -// VCU118 DigitalTop -// ------------------------------------ - -class VCU118DigitalTop(implicit p: Parameters) extends VCU118ChipyardSystem - with testchipip.CanHaveTraceIO // Enables optionally adding trace IO - with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad - with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device - with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter - with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART - with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs - with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller - with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port - with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim - with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget - with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget - with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget - with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA -{ - override lazy val module = new VCU118DigitalTopModule(this) -} - -class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends VCU118ChipyardSystemModule(l) - with testchipip.CanHaveTraceIOModuleImp - with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp - with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIModuleImp - with chipyard.example.CanHavePeripheryGCDModuleImp - with freechips.rocketchip.util.DontTouch - -// ------------------------------------ -// VCU118 Chipyard System -// ------------------------------------ - -class VCU118ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem - with HasAsyncExtInterrupts - with CanHaveMasterTLMemPort // expose a TL port for outer memory (replaces AXI outer port) - with CanHaveMasterAXI4MMIOPort - with CanHaveSlaveAXI4Port -{ - - val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } - val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } - override lazy val module = new VCU118ChipyardSystemModule(this) -} - -class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer) - with HasRTCModuleImp - with HasExtInterruptsModuleImp - with DontTouch - -// ------------------------------------ -// VCU118 Mem Port Mixin -// ------------------------------------ - -/** Adds a port to the system intended to master an TL DRAM controller. */ -trait CanHaveMasterTLMemPort { this: BaseSubsystem => - private val memPortParamsOpt = p(ExtMem) - private val portName = "tl_mem" - private val device = new MemoryDevice - private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) - - val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => - Seq.tabulate(nMemoryChannels) { channel => - val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) - val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) - - TLSlavePortParameters.v1( - managers = Seq(TLSlaveParameters.v1( - address = base.flatMap(_.intersect(filter)), - resources = device.reg, - regionType = RegionType.UNCACHED, // cacheable - executable = true, - supportsGet = TransferSizes(1, mbus.blockBytes), - supportsPutFull = TransferSizes(1, mbus.blockBytes), - supportsPutPartial = TransferSizes(1, mbus.blockBytes))), - beatBytes = memPortParams.beatBytes) - } - }).toList.flatten) - - mbus.coupleTo(s"memory_controller_port_named_$portName") { - (memTLNode - :*= TLBuffer() - :*= TLSourceShrinker(1 << idBits) - :*= TLWidthWidget(mbus.beatBytes) - :*= _) - } - - val mem_tl = InModuleBody { memTLNode.makeIOs() } -} diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index 6ba53642..d60af21a 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import chipyard.{HasHarnessSignalReferences} +import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} import chipyard.harness.{OverrideHarnessBinder} /*** UART ***/ diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala index 4c5bb357..a1f67bcd 100644 --- a/fpga/src/main/scala/vcu118/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/IOBinders.scala @@ -11,6 +11,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp} import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice} +import chipyard.{CanHaveMasterTLMemPort} import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} class WithUARTIOPassthrough extends OverrideIOBinder({ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index cd88ff8e..5002817f 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -17,7 +17,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.gpio._ -import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop} +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort} import chipyard.iobinders.{HasIOBinders} import chipyard.harness.{ApplyHarnessBinders} @@ -79,7 +79,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S /*** DDR ***/ - val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr + val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr // connect 1 mem. channel to the FPGA DDR val inParams = topDesign match { case td: ChipTop => diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index 251ea8e9..5b554f5b 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -9,18 +9,18 @@ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ -import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} +import chipyard.{DigitalTop, DigitalTopModule} // ------------------------------------ // Bringup VCU118 DigitalTop // ------------------------------------ -class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop +class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop with sifive.blocks.devices.i2c.HasPeripheryI2C with testchipip.HasPeripheryTSIHostWidget { override lazy val module = new BringupVCU118DigitalTopModule(this) } -class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l) +class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends DigitalTopModule(l) with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index c0ac1ff7..7fd682d2 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -20,6 +20,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller + with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget @@ -35,6 +36,7 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index bd20ddc7..4ab0da3e 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -7,7 +7,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ @@ -23,7 +23,8 @@ import freechips.rocketchip.util.{DontTouch} */ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem with HasAsyncExtInterrupts - with CanHaveMasterAXI4MemPort + with CanHaveMasterTLMemPort // export TL port for outer memory + with CanHaveMasterAXI4MemPort // expose AXI port for outer mem with CanHaveMasterAXI4MMIOPort with CanHaveSlaveAXI4Port { @@ -40,3 +41,46 @@ class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubs with HasRTCModuleImp with HasExtInterruptsModuleImp with DontTouch + +// ------------------------------------ +// TL Mem Port Mixin +// ------------------------------------ + +// Similar to ExtMem but instantiates a TL mem port +case object ExtTLMem extends Field[Option[MemoryPortParams]](None) + +/** Adds a port to the system intended to master an TL DRAM controller. */ +trait CanHaveMasterTLMemPort { this: BaseSubsystem => + private val memPortParamsOpt = p(ExtTLMem) + private val portName = "tl_mem" + private val device = new MemoryDevice + private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) + + val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) => + Seq.tabulate(nMemoryChannels) { channel => + val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) + val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) + + TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = base.flatMap(_.intersect(filter)), + resources = device.reg, + regionType = RegionType.UNCACHED, // cacheable + executable = true, + supportsGet = TransferSizes(1, mbus.blockBytes), + supportsPutFull = TransferSizes(1, mbus.blockBytes), + supportsPutPartial = TransferSizes(1, mbus.blockBytes))), + beatBytes = memPortParams.beatBytes) + } + }).toList.flatten) + + mbus.coupleTo(s"memory_controller_port_named_$portName") { + (memTLNode + :*= TLBuffer() + :*= TLSourceShrinker(1 << idBits) + :*= TLWidthWidget(mbus.beatBytes) + :*= _) + } + + val mem_tl = InModuleBody { memTLNode.makeIOs() } +} From 8f6de22e72c52de67fbaa5f317173f884ea6cd95 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 23 Nov 2020 16:30:39 -0800 Subject: [PATCH 092/157] Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs --- fpga/src/main/scala/arty/Configs.scala | 5 +---- fpga/src/main/scala/vcu118/Configs.scala | 4 ++-- generators/chipyard/src/main/scala/ConfigFragments.scala | 4 ++++ .../chipyard/src/main/scala/config/RocketConfigs.scala | 8 +++++++- 4 files changed, 14 insertions(+), 7 deletions(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 2a78a54c..fa9a47e0 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -33,10 +33,7 @@ class WithArtyTweaks extends Config( new WithArtyResetHarnessBinder ++ new WithDebugResetPassthrough ++ new WithDefaultPeripherals ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ - new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory - new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ - new freechips.rocketchip.subsystem.WithIncoherentBusTopology) + new freechips.rocketchip.subsystem.WithNBreakpoints(2)) class TinyRocketArtyConfig extends Config( new WithArtyTweaks ++ diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 44913ba2..5bd21245 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -26,7 +26,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => { }) class WithSystemModifications extends Config((site, here, up) => { - case DebugModuleKey => None // disable debug module case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000)) case DTSTimebase => BigInt(1000000) case BootROMLocated(x) => up(BootROMLocated(x), site).map { p => @@ -55,7 +54,8 @@ class WithVCU118Tweaks extends Config( new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ new WithTLBackingMemory ++ // use TL backing memory - new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top + new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size + new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 68c41724..4bc0b9a2 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -177,6 +177,10 @@ class WithNoDebug extends Config((site, here, up) => { case DebugModuleKey => None }) +class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => { + case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere) +}) + class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 626700a5..40511eef 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -11,7 +11,13 @@ class RocketConfig extends Config( new chipyard.config.AbstractConfig) class TinyRocketConfig extends Config( - new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core + new chipyard.config.WithTLSerialLocation( + freechips.rocketchip.subsystem.FBUS, + freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses + new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology + new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory + new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core new chipyard.config.AbstractConfig) class HwachaRocketConfig extends Config( From f1fdab5bd337cc72563100296d54648393049882 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 23 Nov 2020 16:58:34 -0800 Subject: [PATCH 093/157] Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem --- fpga/src/main/scala/vcu118/Configs.scala | 7 +------ generators/chipyard/src/main/scala/ConfigFragments.scala | 5 +++++ generators/chipyard/src/main/scala/System.scala | 4 ++++ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 5bd21245..8b17aa98 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -39,11 +39,6 @@ class WithSystemModifications extends Config((site, here, up) => { case SerialTLKey => None // remove serialized tl port }) -class WithTLBackingMemory extends Config((site, here, up) => { - case ExtMem => None // disable AXI backing memory - case ExtTLMem => up(ExtMem, site) // enable TL backing memory -}) - // DOC include start: AbstractVCU118 and Rocket class WithVCU118Tweaks extends Config( new WithUART ++ @@ -53,7 +48,7 @@ class WithVCU118Tweaks extends Config( new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - new WithTLBackingMemory ++ // use TL backing memory + new chipyard.config.WithTLBackingMemory ++ // use TL backing memory new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 4bc0b9a2..749c75bb 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -181,6 +181,11 @@ class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusW case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere) }) +class WithTLBackingMemory extends Config((site, here, up) => { + case ExtMem => None // disable AXI backing memory + case ExtTLMem => up(ExtMem, site) // enable TL backing memory +}) + class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 4ab0da3e..31bedae7 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -51,6 +51,10 @@ case object ExtTLMem extends Field[Option[MemoryPortParams]](None) /** Adds a port to the system intended to master an TL DRAM controller. */ trait CanHaveMasterTLMemPort { this: BaseSubsystem => + + require(!(p(ExtTLMem).nonEmpty && p(ExtMem).nonEmpty), + "Can only have 1 backing memory port. Use ExtTLMem for a TL memory port or ExtMem for an AXI memory port.") + private val memPortParamsOpt = p(ExtTLMem) private val portName = "tl_mem" private val device = new MemoryDevice From 71a3ea8abcacd9907b3a1bcc4e2588b6905526fa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 24 Nov 2020 16:44:20 -0800 Subject: [PATCH 094/157] Allow custom verilator optimization flags --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 65e64179..2b250ee9 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -84,7 +84,7 @@ TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) #---------------------------------------------------------------------------------------- # we initially had --noassert for performance, but several modules use # assertions, including dramsim, so we enable --assert by default -VERILATOR_OPT_FLAGS := \ +VERILATOR_OPT_FLAGS ?= \ -O3 \ --x-assign fast \ --x-initial fast \ From c223f18f73f932f26ccba5782a470a09ad94032e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 25 Nov 2020 20:57:17 -0800 Subject: [PATCH 095/157] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 845af06b..9be550e2 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 845af06b1515c69b1d788726134e92b808bf45e4 +Subproject commit 9be550e23d2f6a2968f35719ba55edb8aefaf138 From 8a46d4a1ea7032bf0442d743b77d8e553419c1b7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 27 Nov 2020 17:34:48 -0800 Subject: [PATCH 096/157] Bump BOOM and Barstools --- generators/boom | 2 +- tools/barstools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index 2dfec3d0..f3a30168 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 2dfec3d012e61ff07108af6034a86e60979deecd +Subproject commit f3a301689e8ceee54f247a6c0913d28454bd376a diff --git a/tools/barstools b/tools/barstools index 9be550e2..fa699af0 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 9be550e23d2f6a2968f35719ba55edb8aefaf138 +Subproject commit fa699af02635681c8af90f2169a6705fe5e3e37a From 60e834c812b40c2317715f0a4cd6135436c2b448 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 28 Nov 2020 16:01:35 -0800 Subject: [PATCH 097/157] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index f89d746a..5e64d783 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f89d746aa3c0c35c78a883c22c58679aeb9e2030 +Subproject commit 5e64d78300a2e5316878af862447c84cee9f6c12 From b7ed614b1968de05c49f3c258867211cfe20b3a6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 30 Nov 2020 21:22:55 -0800 Subject: [PATCH 098/157] Attempt at "fixing" build.sbt | Bump sub-projects --- build.sbt | 202 +++++++++++++++++++++++++++++------------- generators/boom | 2 +- generators/cva6 | 2 +- generators/gemmini | 2 +- generators/sha3 | 2 +- generators/testchipip | 2 +- project/plugins.sbt | 6 -- sims/firesim | 2 +- tools/barstools | 2 +- tools/dsptools | 2 +- 10 files changed, 147 insertions(+), 77 deletions(-) diff --git a/build.sbt b/build.sbt index 968b22cd..01655abc 100644 --- a/build.sbt +++ b/build.sbt @@ -14,25 +14,22 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies ++= Seq( - "org.scalatest" %% "scalatest" % "3.2.2" % "test", - "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", - "org.json4s" %% "json4s-jackson" % "3.6.10", - "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "com.github.scopt" %% "scopt" % "3.7.1", - "org.scala-lang.modules" % "scala-jline" % "2.12.1", - "com.typesafe.play" %% "play-json" % "2.6.10", - "org.typelevel" %% "spire" % "0.16.2", - "org.scalanlp" %% "breeze" % "1.0", - "org.json4s" %% "json4s-native" % "3.6.10", - "junit" % "junit" % "4.13", - "org.apache.commons" % "commons-text" % "1.8", - "net.jcazevedo" %% "moultingyaml" % "0.4.2", - "org.antlr" % "antlr4-runtime" % "4.7.1" - ), - addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), + addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), // TODO: Needed for just Rocket? unmanagedBase := (chipyardRoot / unmanagedBase).value, - allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), + allDependencies := { + // drop dependencies (org, name) + val dropDeps = Seq( + ("edu.berkeley.cs", "firrtl"), + ("edu.berkeley.cs", "chisel3"), + ("edu.berkeley.cs", "rocketchip"), + ("edu.berkeley.cs", "chisel-iotesters"), + ("edu.berkeley.cs", "treadle"), + ("edu.berkeley.cs", "firrtl-interpreter")) + + allDependencies.value.filterNot { dep => + dropDeps.contains((dep.organization, dep.name)) + } + }, exportJars := true, resolvers ++= Seq( Resolver.sonatypeRepo("snapshots"), @@ -73,86 +70,135 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin +// -- Rocket Chip -- + val chiselVersion = "3.4.0" -lazy val chisel = (project in file("tools/chisel3")) +lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion +lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) // While not built from source, *must* be in sync with the chisel3 git submodule // Building from source requires extending sbt-sriracha or a similar plugin and // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -lazy val firrtlRef = ProjectRef(file("tools/firrtl"), "firrtl") -lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % "1.4-SNAPSHOT" - -lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .sourceDependency(firrtlRef, firrtlLib) - .settings(commonSettings) - -lazy val treadle = (project in file("tools/treadle")) - .sourceDependency(firrtlRef, firrtlLib) - .settings(commonSettings) - -lazy val chisel_testers = (project in file("tools/chisel-testers")) - .sourceDependency(chisel, chiselLib) - .settings(addCompilerPlugin(chiselPluginLib)) - .dependsOn(firrtl_interpreter, treadle) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "junit" % "junit" % "4.13", - "org.scalatest" %% "scalatest" % "3.2.2", - "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1", - "org.scalacheck" %% "scalacheck" % "1.14.3", - "com.github.scopt" %% "scopt" % "3.7.1" - )) - -// Contains annotations & firrtl passes you may wish to use in rocket-chip without -// introducing a circular dependency between RC and MIDAS -lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") +val firrtlVersion = "1.4-SNAPSHOT" +lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") +lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion +//lazy val firrtlLibDeps = (firrtlRef / Keys.libraryDependencies) // TODO: Won't work because of antlr plugin +lazy val firrtlLibDeps = Seq( + "org.scalatest" %% "scalatest" % "3.2.0" % "test", + "org.scalatestplus" %% "scalacheck-1-14" % "3.1.3.0" % "test", + "com.github.scopt" %% "scopt" % "3.7.1", + "net.jcazevedo" %% "moultingyaml" % "0.4.2", + "org.json4s" %% "json4s-native" % "3.6.9", + "org.apache.commons" % "commons-text" % "1.8", + "org.antlr" % "antlr4-runtime" % "4.7.1" +) // Rocket-chip dependencies (subsumes making RC a RootProject) lazy val hardfloat = (project in rocketChipDir / "hardfloat") + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) .dependsOn(midasTargetUtils) .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) lazy val rocketMacros = (project in rocketChipDir / "macros") .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt") .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .sourceDependency(chisel, chiselLib) + .sourceDependency(chiselRef, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) .dependsOn(hardfloat, rocketMacros, rocketConfig) .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) .settings( // Settings for scalafix semanticdbEnabled := true, semanticdbVersion := scalafixSemanticdb.revision, scalacOptions += "-Ywarn-unused-import" ) +lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) + +// -- "Problematic" Projects -- + +lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) + .sourceDependency(firrtlRef, firrtlLib) + .settings(libraryDependencies ++= firrtlLibDeps) + .settings(commonSettings) +lazy val firrtlInterpreterLibDeps = (firrtl_interpreter / Keys.libraryDependencies) + +lazy val treadle = (project in file("tools/treadle")) + .sourceDependency(firrtlRef, firrtlLib) + .settings(libraryDependencies ++= firrtlLibDeps) + .settings(commonSettings) +lazy val treadleLibDeps = (treadle / Keys.libraryDependencies) + +lazy val chisel_testers = (project in file("tools/chisel-testers")) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) + .dependsOn(firrtl_interpreter, treadle) + .settings(libraryDependencies ++= firrtlInterpreterLibDeps.value) + .settings(libraryDependencies ++= treadleLibDeps.value) + .settings(commonSettings) +lazy val chiselTestersLibDeps = (chisel_testers / Keys.libraryDependencies) + +// -- UCB-controlled Projects -- + +// Contains annotations & firrtl passes you may wish to use in rocket-chip without +// introducing a circular dependency between RC and MIDAS +lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT" -lazy val iocell = (project in file("./tools/barstools/iocell/")) - .sourceDependency(chisel, chiselLib) - .settings(addCompilerPlugin(chiselPluginLib)) - .settings(commonSettings) - lazy val chipyard = (project in file("generators/chipyard")) .sourceDependency(testchipip, testchipipLib) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, + .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val tracegen = (project in file("generators/tracegen")) .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip, sifive_cache, boom, utilities) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val utilities = (project in file("generators/utilities")) @@ -160,73 +206,103 @@ lazy val utilities = (project in file("generators/utilities")) .settings(commonSettings) lazy val icenet = (project in file("generators/icenet")) - .dependsOn(rocketchip, testchipip) + .sourceDependency(testchipip, testchipipLib) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val hwacha = (project in file("generators/hwacha")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val cva6 = (project in file("generators/cva6")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val sodor = (project in file("generators/riscv-sodor")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val sha3 = (project in file("generators/sha3")) .dependsOn(rocketchip, chisel_testers, midasTargetUtils) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(rocketchip, chisel_testers, testchipip) + .sourceDependency(testchipip, testchipipLib) + .dependsOn(rocketchip, chisel_testers) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings(commonSettings) lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + +lazy val iocell = (project in file("./tools/barstools/iocell/")) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) .settings(commonSettings) lazy val tapeout = (project in file("./tools/barstools/tapeout/")) .dependsOn(chisel_testers, chipyard) // must depend on chipyard to get scala resources + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings(commonSettings) - .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) .settings(commonSettings) lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) - .dependsOn(firrtl_interpreter, mdf, rocketchip) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) + .dependsOn(firrtl_interpreter, mdf, chisel_testers) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) + .settings(libraryDependencies ++= firrtlInterpreterLibDeps.value) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel_testers) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings( commonSettings, libraryDependencies ++= Seq( + "org.typelevel" %% "spire" % "0.16.2", + "org.scalanlp" %% "breeze" % "1.1", "junit" % "junit" % "4.13" % "test", - "org.scalatest" %% "scalatest" % "3.2.2", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" + "org.scalatest" %% "scalatest" % "3.0.+" % "test", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test", )) lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val sifive_cache = (project in file("generators/sifive-cache")).settings( +lazy val sifive_cache = (project in file("generators/sifive-cache")) + .settings( commonSettings, - scalaSource in Compile := baseDirectory.value / "design/craft" - ).dependsOn(rocketchip) + scalaSource in Compile := baseDirectory.value / "design/craft") + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) // Library components of FireSim lazy val midas = ProjectRef(firesimDir, "midas") diff --git a/generators/boom b/generators/boom index f3a30168..6198e335 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit f3a301689e8ceee54f247a6c0913d28454bd376a +Subproject commit 6198e33545f2ec2c70a6ac9afba78c7023e9605b diff --git a/generators/cva6 b/generators/cva6 index c2b9fc41..d40a8f5c 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit c2b9fc412179a386fb4b662d13e588a9613f41d5 +Subproject commit d40a8f5c844f4169c8e74d3fa05f36286f9e4bb6 diff --git a/generators/gemmini b/generators/gemmini index 371bc330..eb719930 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 371bc33038e633779f52e26eaa0031f2820c2f0d +Subproject commit eb7199307d3adf994c78b02a54859f3e37ac7012 diff --git a/generators/sha3 b/generators/sha3 index a4ea9602..74e41f57 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit a4ea960248fdf8267b515723d472b018b09ac24f +Subproject commit 74e41f579213549501ccf292d101f9db73ee2347 diff --git a/generators/testchipip b/generators/testchipip index 03af7aa5..6fbb1b77 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 03af7aa53988dd96dffd613d1d50a5c6661e0a82 +Subproject commit 6fbb1b77b90da5e88bfde8e504595a332cca0e0b diff --git a/project/plugins.sbt b/project/plugins.sbt index 61e69a3d..fa2a1a57 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,7 +1,3 @@ -resolvers += Resolver.url("scalasbt", new URL("https://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) -resolvers += Classpaths.sbtPluginReleases -resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven" - addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") @@ -18,5 +14,3 @@ addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) - -libraryDependencies += "com.github.os72" % "protoc-jar" % "3.11.4" diff --git a/sims/firesim b/sims/firesim index 5e64d783..4752009e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 5e64d78300a2e5316878af862447c84cee9f6c12 +Subproject commit 4752009e98fdd0b1848c6a3cde21fee331885939 diff --git a/tools/barstools b/tools/barstools index fa699af0..3a29f535 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit fa699af02635681c8af90f2169a6705fe5e3e37a +Subproject commit 3a29f535726a191d09164470eb1ce1a1ddd5bf9a diff --git a/tools/dsptools b/tools/dsptools index 74612fd7..27304bde 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 74612fd76645bfcfcc1c711ed43025cb8105e539 +Subproject commit 27304bdeae3e4fb969c7cac1e0bda358be7cdb12 From 5bc7e6cd685428d50a8bd28ee1e97dfda730577c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 1 Dec 2020 22:28:23 -0800 Subject: [PATCH 099/157] Support SBT thin client | Rename JAVA_ARGS -> OPTS | Support env. SBT_OPTS --- .gitignore | 1 + .sbtopts | 2 -- build.sbt | 2 +- common.mk | 14 +++++++++----- project/build.properties | 2 +- variables.mk | 21 +++++++++++---------- 6 files changed, 23 insertions(+), 19 deletions(-) delete mode 100644 .sbtopts diff --git a/.gitignore b/.gitignore index a85d0dd2..153e7275 100644 --- a/.gitignore +++ b/.gitignore @@ -20,3 +20,4 @@ tags env-riscv-tools.sh env-esp-tools.sh .bloop/ +.bsp/ diff --git a/.sbtopts b/.sbtopts deleted file mode 100644 index 2358d787..00000000 --- a/.sbtopts +++ /dev/null @@ -1,2 +0,0 @@ --Dsbt.sourcemode=true --Dsbt.workspace=$PWD/tools diff --git a/build.sbt b/build.sbt index 01655abc..1132dde1 100644 --- a/build.sbt +++ b/build.sbt @@ -81,7 +81,7 @@ lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -val firrtlVersion = "1.4-SNAPSHOT" +val firrtlVersion = "1.4.+" lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion //lazy val firrtlLibDeps = (firrtlRef / Keys.libraryDependencies) // TODO: Won't work because of antlr plugin diff --git a/common.mk b/common.mk index 80565a37..4f632a26 100644 --- a/common.mk +++ b/common.mk @@ -63,7 +63,7 @@ SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) -SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt +SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties ######################################################################################### # Bloop Project Definitions @@ -209,7 +209,7 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) endif ####################################### -# Rules for building DRAMSim2 library # +# Rules for building DRAMSim2 library ####################################### dramsim_dir = $(base_dir)/tools/DRAMSim2 @@ -218,14 +218,18 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) -####################################### -# Helper to run SBT # -####################################### +################################################ +# Helper to run SBT or shutdown the SBT server +################################################ .PHONY: launch-sbt launch-sbt: cd $(base_dir) && $(SBT) +.PHONY: launch-sbt +shutdown-sbt: + cd $(base_dir) && $(SBT) shutdown + ######################################################################################### # print help text ######################################################################################### diff --git a/project/build.properties b/project/build.properties index 0837f7a1..7de0a938 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.3.13 +sbt.version=1.4.4 diff --git a/variables.mk b/variables.mk index 42dc48c5..73918376 100644 --- a/variables.mk +++ b/variables.mk @@ -146,21 +146,22 @@ sim_common_files ?= $(build_dir)/sim_files.common.f # java arguments used in sbt ######################################################################################### JAVA_HEAP_SIZE ?= 8G -JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M +JAVA_OPTS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M ######################################################################################### # default sbt launch command ######################################################################################### -# Running with sbt-launch.jar doesn't read .sbtopts by default -# # Set if the file exists (if it exists, we're building chisel3 and firrtl from source) -sbtopts_file := $(base_dir)/.sbtopts -ifneq (,$(wildcard $(sbtopts_file))) - SBT_OPTS ?= $(shell cat $(sbtopts_file)) +# by default build chisel3/firrtl and other subprojects from source +override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools + +ifdef ENABLE_SBT_THIN_CLIENT +# enabling speeds up sbt loading +# however if build.sbt changes are done you need to +# "shutdown" the server (shutdown-sbt target) to reload build.sbt changes +SBT_CLIENT_FLAG = --client endif -SCALA_VERSION=2.12.10 -SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) -SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) +SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG) BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop @@ -183,7 +184,7 @@ define run_scala_main endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" endef endif From 4e53dc1e663560131f5b12fb0dcd7079a0dd0bdc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 12:18:12 -0800 Subject: [PATCH 100/157] Cleanly reload proj. defs. with thin client support --- .gitignore | 1 + common.mk | 18 +++++++++++++++--- variables.mk | 7 +++++-- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/.gitignore b/.gitignore index 153e7275..77b9eb6c 100644 --- a/.gitignore +++ b/.gitignore @@ -21,3 +21,4 @@ env-riscv-tools.sh env-esp-tools.sh .bloop/ .bsp/ +*_TIMESTAMP diff --git a/common.mk b/common.mk index 4f632a26..f149d1ae 100644 --- a/common.mk +++ b/common.mk @@ -69,9 +69,20 @@ SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $ # Bloop Project Definitions ######################################################################################### $(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES) - cd $(base_dir) && $(SBT) "project chipyardRoot" "bloopInstall" + cd $(base_dir) && $(SBT) ";project chipyardRoot; bloopInstall" touch $@ +######################################################################################### +# SBT Server Setup (needed to rebuild project correctly) +######################################################################################### +$(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES) +ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP))) + cd $(base_dir) && $(SBT) "reload" + touch $@ +else + touch $@ +endif + ######################################################################################### # create list of simulation file inputs ######################################################################################### @@ -226,9 +237,10 @@ $(dramsim_lib): launch-sbt: cd $(base_dir) && $(SBT) -.PHONY: launch-sbt +.PHONY: shutdown-sbt shutdown-sbt: - cd $(base_dir) && $(SBT) shutdown + cd $(base_dir) && $(SBT) "shutdown" + rm -rf $(SBT_THIN_CLIENT_TIMESTAMP) ######################################################################################### # print help text diff --git a/variables.mk b/variables.mk index 73918376..731b7e1e 100644 --- a/variables.mk +++ b/variables.mk @@ -154,7 +154,12 @@ JAVA_OPTS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M # by default build chisel3/firrtl and other subprojects from source override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools +SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) + +SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/SBT_TIMESTAMP + ifdef ENABLE_SBT_THIN_CLIENT +override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP) # enabling speeds up sbt loading # however if build.sbt changes are done you need to # "shutdown" the server (shutdown-sbt target) to reload build.sbt changes @@ -168,8 +173,6 @@ BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop # This mirrors the bloop default. Set to a system-unique port in a multi-user environment BLOOP_NAILGUN_PORT ?= 8212 -SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) - ifdef ENABLE_BLOOP override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP # Two notes about the bloop invocation: From a0e2dcfc4ecddeaa79c3cb8904b6b2de4e397435 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 14:46:46 -0800 Subject: [PATCH 101/157] Remove support for bloop --- .gitignore | 1 - common.mk | 7 ------- project/plugins.sbt | 1 - variables.mk | 19 ------------------- 4 files changed, 28 deletions(-) diff --git a/.gitignore b/.gitignore index 77b9eb6c..a80f88ab 100644 --- a/.gitignore +++ b/.gitignore @@ -19,6 +19,5 @@ tags *~ env-riscv-tools.sh env-esp-tools.sh -.bloop/ .bsp/ *_TIMESTAMP diff --git a/common.mk b/common.mk index f149d1ae..159e7ea6 100644 --- a/common.mk +++ b/common.mk @@ -65,13 +65,6 @@ VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties -######################################################################################### -# Bloop Project Definitions -######################################################################################### -$(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES) - cd $(base_dir) && $(SBT) ";project chipyardRoot; bloopInstall" - touch $@ - ######################################################################################### # SBT Server Setup (needed to rebuild project correctly) ######################################################################################### diff --git a/project/plugins.sbt b/project/plugins.sbt index fa2a1a57..7e6f3aa8 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -11,6 +11,5 @@ addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") -addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) diff --git a/variables.mk b/variables.mk index 731b7e1e..6cc87bfc 100644 --- a/variables.mk +++ b/variables.mk @@ -168,28 +168,9 @@ endif SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG) -BLOOP ?= bloop -BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop -# This mirrors the bloop default. Set to a system-unique port in a multi-user environment -BLOOP_NAILGUN_PORT ?= 8212 - -ifdef ENABLE_BLOOP -override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP -# Two notes about the bloop invocation: -# 1) the sed removes a leading {file:} that sometimes needs to be -# provided to SBT when a project but not for bloop. -# 2) Generally, one could could pass '--' to indicate all remaining arguments are -# destined for the scala Main, however a bug in Bloop's argument parsing causes the -# --nailgun-port argument to be lost in this case. Workaround this by prefixing -# every main-destined argument with "--args" -define run_scala_main - cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) -endef -else define run_scala_main cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" endef -endif FIRRTL_LOGLEVEL ?= error From 08f3dbc1d07580af3c94bb1f59290a866abb1fc0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 14:51:49 -0800 Subject: [PATCH 102/157] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 4752009e..bf05870d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4752009e98fdd0b1848c6a3cde21fee331885939 +Subproject commit bf05870d225564772c44cf5505a40b1a742aa5f7 From 145885390f4a6cdbe9a5cf76bc35aa92c1458d71 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 15:08:06 -0800 Subject: [PATCH 103/157] Bump Hwacha --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index e0109674..b67d8ed0 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit e0109674572f4b40641a89db9e0429e51b5cb73a +Subproject commit b67d8ed06172c2ecd76807d3ef2bd5c79903f182 From 3bc1bdb841b55b4d97ebba8fc6abd588c7ddab47 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 15:49:35 -0800 Subject: [PATCH 104/157] Bump BOOM | Split JAVA/SBT options in CI --- .circleci/defaults.sh | 3 ++- .circleci/do-rtl-build.sh | 2 +- .circleci/run-firesim-scala-tests.sh | 2 +- generators/boom | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e9ccdfb5..02558101 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -33,8 +33,9 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim +REMOTE_JAVA_OPTS="-Xmx9G -Xss8M" # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI -REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" +REMOTE_SBT_ARGS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 784dbc04..1e065437 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -63,7 +63,7 @@ do export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" + make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$key]}" done run "rm -rf $REMOTE_CHIPYARD_DIR/project" diff --git a/.circleci/run-firesim-scala-tests.sh b/.circleci/run-firesim-scala-tests.sh index 8080a484..a2525297 100755 --- a/.circleci/run-firesim-scala-tests.sh +++ b/.circleci/run-firesim-scala-tests.sh @@ -49,4 +49,4 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" testOnly ${mapping[$1]}" + make -C $REMOTE_FIRESIM_DIR JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" testOnly ${mapping[$1]}" diff --git a/generators/boom b/generators/boom index 6198e335..a53372fc 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 6198e33545f2ec2c70a6ac9afba78c7023e9605b +Subproject commit a53372fcff4c1095a513eb8bb6e8a2b9cdb971a0 From eee0d58b5d6a8b368457873bd0fbc8b8f4b63d72 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 15:53:11 -0800 Subject: [PATCH 105/157] Cleanup comment --- variables.mk | 2 -- 1 file changed, 2 deletions(-) diff --git a/variables.mk b/variables.mk index 6cc87bfc..c8f72b3f 100644 --- a/variables.mk +++ b/variables.mk @@ -161,8 +161,6 @@ SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/SBT_TIMESTAMP ifdef ENABLE_SBT_THIN_CLIENT override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP) # enabling speeds up sbt loading -# however if build.sbt changes are done you need to -# "shutdown" the server (shutdown-sbt target) to reload build.sbt changes SBT_CLIENT_FLAG = --client endif From 41c710b6c8c4391381caffdea8509f7dcfdc77ba Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 16:11:09 -0800 Subject: [PATCH 106/157] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index bf05870d..10f9e7ef 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit bf05870d225564772c44cf5505a40b1a742aa5f7 +Subproject commit 10f9e7efe0b4f532037575e114b8b5fbfb47d211 From d19bcaa765e4e0cf246fa4065ffbc70bacad0d25 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 16:42:52 -0800 Subject: [PATCH 107/157] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 10f9e7ef..593596c5 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 10f9e7efe0b4f532037575e114b8b5fbfb47d211 +Subproject commit 593596c5a854f69d28d0c3b9389175a03fa4c696 From 7f9cd0f012e143229fc5022dd4f380b9ba772583 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 21:51:58 -0800 Subject: [PATCH 108/157] Bump FireSim | CI Fix Attempt: Increase heap --- .circleci/defaults.sh | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 02558101..015aaee7 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -33,7 +33,7 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim -REMOTE_JAVA_OPTS="-Xmx9G -Xss8M" +REMOTE_JAVA_OPTS="-Xmx10G -Xss8M" # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI REMOTE_SBT_ARGS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install diff --git a/sims/firesim b/sims/firesim index 593596c5..f9ca2f49 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 593596c5a854f69d28d0c3b9389175a03fa4c696 +Subproject commit f9ca2f49f95e2b51cf0e966ac13b1f285db341cf From f1df2ec69e1dab0666f8a2fb66849886a25717f1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Dec 2020 12:51:24 -0800 Subject: [PATCH 109/157] Bump FireSim/Hwacha | Cleanup linting --- build.sbt | 3 +++ generators/hwacha | 2 +- sims/firesim | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 1132dde1..b50bc200 100644 --- a/build.sbt +++ b/build.sbt @@ -1,5 +1,8 @@ import Tests._ +// Ignore linting for traceLevel +Global / excludeLintKeys += traceLevel + // This gives us a nicer handle to the root project instead of using the // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) diff --git a/generators/hwacha b/generators/hwacha index b67d8ed0..27e03b7e 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit b67d8ed06172c2ecd76807d3ef2bd5c79903f182 +Subproject commit 27e03b7e2694b4389c64c92a3518b1dba5304905 diff --git a/sims/firesim b/sims/firesim index f9ca2f49..515ac120 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f9ca2f49f95e2b51cf0e966ac13b1f285db341cf +Subproject commit 515ac12059a347f34b13833888ace941a9629be5 From d0079a96599f2fa545e37e10ea459ba4e30fb672 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Dec 2020 14:06:55 -0800 Subject: [PATCH 110/157] Cleanup helper sbt targets | Use project/target/active.json for SBT timestamp --- .gitignore | 1 - common.mk | 17 +++++++++++------ sims/firesim | 2 +- variables.mk | 3 ++- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/.gitignore b/.gitignore index a80f88ab..257d2c58 100644 --- a/.gitignore +++ b/.gitignore @@ -20,4 +20,3 @@ tags env-riscv-tools.sh env-esp-tools.sh .bsp/ -*_TIMESTAMP diff --git a/common.mk b/common.mk index 159e7ea6..a474454a 100644 --- a/common.mk +++ b/common.mk @@ -66,14 +66,14 @@ SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties ######################################################################################### -# SBT Server Setup (needed to rebuild project correctly) +# SBT Server Setup (start server / rebuild proj. defs. if SBT_SOURCES change) ######################################################################################### $(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES) ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP))) cd $(base_dir) && $(SBT) "reload" touch $@ else - touch $@ + cd $(base_dir) && $(SBT) "exit" endif ######################################################################################### @@ -223,18 +223,23 @@ $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) ################################################ -# Helper to run SBT or shutdown the SBT server +# Helper to run SBT or manage the SBT server ################################################ +SBT_COMMAND ?= shell .PHONY: launch-sbt launch-sbt: - cd $(base_dir) && $(SBT) + cd $(base_dir) && $(SBT_NON_THIN) "$(SBT_COMMAND)" -.PHONY: shutdown-sbt -shutdown-sbt: +.PHONY: shutdown-sbt-server +shutdown-sbt-server: cd $(base_dir) && $(SBT) "shutdown" rm -rf $(SBT_THIN_CLIENT_TIMESTAMP) +.PHONY: start-sbt-server +start-sbt-server: + cd $(base_dir) && $(SBT) "exit" + ######################################################################################### # print help text ######################################################################################### diff --git a/sims/firesim b/sims/firesim index 515ac120..6dc98f6c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 515ac12059a347f34b13833888ace941a9629be5 +Subproject commit 6dc98f6cff25b348d3e2bf72fa17f2348c816b2f diff --git a/variables.mk b/variables.mk index c8f72b3f..88ba73ee 100644 --- a/variables.mk +++ b/variables.mk @@ -156,7 +156,7 @@ override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) -SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/SBT_TIMESTAMP +SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json ifdef ENABLE_SBT_THIN_CLIENT override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP) @@ -165,6 +165,7 @@ SBT_CLIENT_FLAG = --client endif SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG) +SBT_NON_THIN ?= $(subst $(SBT_CLIENT_FLAG),,$(SBT)) define run_scala_main cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" From 70fa0a037dc2857980181592376aeea73223d9db Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Dec 2020 14:57:05 -0800 Subject: [PATCH 111/157] Print full stack traces (default traceLevel = 0) | Bump FireSim --- build.sbt | 4 ---- sims/firesim | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/build.sbt b/build.sbt index b50bc200..8856a20c 100644 --- a/build.sbt +++ b/build.sbt @@ -1,8 +1,5 @@ import Tests._ -// Ignore linting for traceLevel -Global / excludeLintKeys += traceLevel - // This gives us a nicer handle to the root project instead of using the // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) @@ -11,7 +8,6 @@ lazy val commonSettings = Seq( organization := "edu.berkeley.cs", version := "1.3", scalaVersion := "2.12.10", - traceLevel := 15, test in assembly := {}, assemblyMergeStrategy in assembly := { _ match { case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard diff --git a/sims/firesim b/sims/firesim index 6dc98f6c..2addd725 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 6dc98f6cff25b348d3e2bf72fa17f2348c816b2f +Subproject commit 2addd72598212424d8a4832b2d78b11c95d74337 From 714687c9622ff920e1b1e0eb542c63592572f2ef Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 4 Dec 2020 14:18:51 -0800 Subject: [PATCH 112/157] Add to help target | Cleanup build.sbt a bit more --- build.sbt | 21 ++++++++------------- common.mk | 7 +++++-- sims/firesim | 2 +- 3 files changed, 14 insertions(+), 16 deletions(-) diff --git a/build.sbt b/build.sbt index 8856a20c..b24fa748 100644 --- a/build.sbt +++ b/build.sbt @@ -13,7 +13,7 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), // TODO: Needed for just Rocket? + addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { // drop dependencies (org, name) @@ -71,6 +71,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // -- Rocket Chip -- +// This needs to stay in sync with the chisel3 and firrtl git submodules val chiselVersion = "3.4.0" lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion @@ -83,16 +84,10 @@ lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion val firrtlVersion = "1.4.+" lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion -//lazy val firrtlLibDeps = (firrtlRef / Keys.libraryDependencies) // TODO: Won't work because of antlr plugin -lazy val firrtlLibDeps = Seq( - "org.scalatest" %% "scalatest" % "3.2.0" % "test", - "org.scalatestplus" %% "scalacheck-1-14" % "3.1.3.0" % "test", - "com.github.scopt" %% "scopt" % "3.7.1", - "net.jcazevedo" %% "moultingyaml" % "0.4.2", - "org.json4s" %% "json4s-native" % "3.6.9", - "org.apache.commons" % "commons-text" % "1.8", - "org.antlr" % "antlr4-runtime" % "4.7.1" -) +val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4") +Global / firrtlLibDeps := { + (firrtlRef / Keys.libraryDependencies).value.filterNot(_.name == "antlr4") +} // Rocket-chip dependencies (subsumes making RC a RootProject) lazy val hardfloat = (project in rocketChipDir / "hardfloat") @@ -153,14 +148,14 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .sourceDependency(firrtlRef, firrtlLib) - .settings(libraryDependencies ++= firrtlLibDeps) .settings(commonSettings) + .settings(libraryDependencies ++= (Global / firrtlLibDeps).value) lazy val firrtlInterpreterLibDeps = (firrtl_interpreter / Keys.libraryDependencies) lazy val treadle = (project in file("tools/treadle")) .sourceDependency(firrtlRef, firrtlLib) - .settings(libraryDependencies ++= firrtlLibDeps) .settings(commonSettings) + .settings(libraryDependencies ++= (Global / firrtlLibDeps).value) lazy val treadleLibDeps = (treadle / Keys.libraryDependencies) lazy val chisel_testers = (project in file("tools/chisel-testers")) diff --git a/common.mk b/common.mk index a474454a..33c0137c 100644 --- a/common.mk +++ b/common.mk @@ -17,7 +17,8 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_CXXFLAGS = additional CXXFLAGS for building simulators" \ " EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ " EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ -" EXTRA_SIM_REQS = additional make requirements to build the simulator" +" EXTRA_SIM_REQS = additional make requirements to build the simulator" \ +" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client" EXTRA_GENERATOR_REQS ?= EXTRA_SIM_CXXFLAGS ?= @@ -41,7 +42,9 @@ HELP_COMMANDS += \ " run-binary-fast = run [./$(shell basename $(sim))] and don't log instructions" \ " run-binary-debug = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \ " verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" \ -" run-tests = run all assembly and benchmark tests" +" firrtl = generate intermediate firrtl files from chisel elaboration" \ +" run-tests = run all assembly and benchmark tests" \ +" launch-sbt = start sbt terminal" ######################################################################################### # include additional subproject make fragments diff --git a/sims/firesim b/sims/firesim index 2addd725..7ab7bc4a 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 2addd72598212424d8a4832b2d78b11c95d74337 +Subproject commit 7ab7bc4a2baaf04f5d8c03094c976e43dc1b2344 From 76ba68b02f6cc925772f7ac75925e21995b07caa Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 10 Dec 2020 06:34:30 +0000 Subject: [PATCH 113/157] Bump hwacha --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index 27e03b7e..a354150c 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit 27e03b7e2694b4389c64c92a3518b1dba5304905 +Subproject commit a354150cb50fdc0c0ddd356e37850c8e36e02588 From 1787fda8c3ef936b59d50e040a93afe6355ab613 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 10 Dec 2020 06:34:39 +0000 Subject: [PATCH 114/157] Bump icenet --- generators/icenet | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/icenet b/generators/icenet index 277a9080..084ca507 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 +Subproject commit 084ca5070605ea7919358f917289cca240d0289a From ee436c9b3f73c239ce3b80726a3094225f3e3b56 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 10 Dec 2020 07:18:12 +0000 Subject: [PATCH 115/157] [firechip] Fix a uart multiclock bug --- generators/firechip/src/main/scala/BridgeBinders.scala | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 0572fabd..cdb026e1 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -4,12 +4,13 @@ package firesim.firesim import chisel3._ import chisel3.experimental.annotate +import chisel3.util.experimental.BoringUtils import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} import freechips.rocketchip.amba.axi4.{AXI4Bundle} -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart._ @@ -86,7 +87,12 @@ class WithNICBridge extends OverrideHarnessBinder({ class WithUARTBridge extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) => - ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil + val uartSyncClock = Wire(Clock()) + uartSyncClock := false.B.asClock + val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode + val pbusClock = pbusClockNode.in.head._1.clock + BoringUtils.bore(pbusClock, Seq(uartSyncClock)) + ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ From f1f479912c85d1938d47b3f63d52647e1e365f6b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 11 Dec 2020 03:22:59 +0000 Subject: [PATCH 116/157] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 7ab7bc4a..e43828a1 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7ab7bc4a2baaf04f5d8c03094c976e43dc1b2344 +Subproject commit e43828a1fc9608123ae94abc40dfe813ccf23860 From db15419e1092e4475cd7b0b921b9b690b2644838 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 11 Dec 2020 03:55:49 +0000 Subject: [PATCH 117/157] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 3a29f535..15fa68b3 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 3a29f535726a191d09164470eb1ce1a1ddd5bf9a +Subproject commit 15fa68b3a40addc5ac77a78ced37497dbce3f687 From d4d483c081869185f4e24063f17430b31ac98add Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 10:19:02 -0800 Subject: [PATCH 118/157] Bump BOOM | Use ucb-bar fork chisel-testers --- .gitmodules | 2 +- generators/boom | 2 +- tools/chisel-testers | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index 55b4be56..bb803d98 100644 --- a/.gitmodules +++ b/.gitmodules @@ -76,7 +76,7 @@ url = https://github.com/ucb-bar/dsptools.git [submodule "tools/chisel-testers"] path = tools/chisel-testers - url = https://github.com/abejgonzalez/chisel-testers.git + url = https://github.com/ucb-bar/chisel-testers.git [submodule "tools/treadle"] path = tools/treadle url = https://github.com/freechipsproject/treadle.git diff --git a/generators/boom b/generators/boom index a53372fc..eab35947 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit a53372fcff4c1095a513eb8bb6e8a2b9cdb971a0 +Subproject commit eab359478622cb089ac3164e8efc158a9b0b5028 diff --git a/tools/chisel-testers b/tools/chisel-testers index 5b9cc56d..461e8d3a 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit 5b9cc56dd80c8d3bce67d54385d769037e2481d8 +Subproject commit 461e8d3a3e2f2e4c78d60c239428214cf8c7d773 From 5c7c1295a1ea5f1184121944c61be090260682b1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 11:37:25 -0800 Subject: [PATCH 119/157] Bump Gemmini+Dsptools | Fix SBT_OPTs in CI --- .circleci/defaults.sh | 2 +- generators/gemmini | 2 +- tools/dsptools | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 015aaee7..12c4531f 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -35,7 +35,7 @@ REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim REMOTE_JAVA_OPTS="-Xmx10G -Xss8M" # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI -REMOTE_SBT_ARGS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" +REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) diff --git a/generators/gemmini b/generators/gemmini index eb719930..70517c52 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit eb7199307d3adf994c78b02a54859f3e37ac7012 +Subproject commit 70517c52f2d36c0fc1370b3b9836297646a70289 diff --git a/tools/dsptools b/tools/dsptools index 27304bde..aad6a3db 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 27304bdeae3e4fb969c7cac1e0bda358be7cdb12 +Subproject commit aad6a3db1520a05ae668681941a19bdcc40aec03 From 939e3a9f94d5bfef9671f49c37cd3acd5fc26128 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 14:18:18 -0800 Subject: [PATCH 120/157] Bump paradise plugin | Remove extra rm for SBT-server timestamp | Small bump for barstools --- build.sbt | 2 +- common.mk | 1 - sims/firesim | 2 +- tools/barstools | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) diff --git a/build.sbt b/build.sbt index b24fa748..e984de86 100644 --- a/build.sbt +++ b/build.sbt @@ -13,7 +13,7 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), + addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { // drop dependencies (org, name) diff --git a/common.mk b/common.mk index 33c0137c..24ab5687 100644 --- a/common.mk +++ b/common.mk @@ -237,7 +237,6 @@ launch-sbt: .PHONY: shutdown-sbt-server shutdown-sbt-server: cd $(base_dir) && $(SBT) "shutdown" - rm -rf $(SBT_THIN_CLIENT_TIMESTAMP) .PHONY: start-sbt-server start-sbt-server: diff --git a/sims/firesim b/sims/firesim index e43828a1..52a9d0fd 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e43828a1fc9608123ae94abc40dfe813ccf23860 +Subproject commit 52a9d0fd2fd3f4ef32337ebd07e36e7ec16d906a diff --git a/tools/barstools b/tools/barstools index 15fa68b3..62f31165 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 15fa68b3a40addc5ac77a78ced37497dbce3f687 +Subproject commit 62f311654a4b31ccbc2839beaee64cd770ecd4a0 From fe4aa6cade03840b80c32911873c9586cce224f4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 14:20:09 -0800 Subject: [PATCH 121/157] Bump BOOM/Gemmini --- generators/boom | 2 +- generators/gemmini | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index eab35947..4bb6464f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit eab359478622cb089ac3164e8efc158a9b0b5028 +Subproject commit 4bb6464ff392cf75e9caf8c06bc252b4f1ac8a28 diff --git a/generators/gemmini b/generators/gemmini index 70517c52..e6e14f71 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 70517c52f2d36c0fc1370b3b9836297646a70289 +Subproject commit e6e14f711760b976d8eb00c32d0fe2423aeda211 From f1e3117ae38f1f41d56a696d5c7bd89c4d93d146 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 15:02:43 -0800 Subject: [PATCH 122/157] Bump barstools for test fixes | Small bump FireSim --- sims/firesim | 2 +- tools/barstools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/firesim b/sims/firesim index 52a9d0fd..f1dafa1b 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 52a9d0fd2fd3f4ef32337ebd07e36e7ec16d906a +Subproject commit f1dafa1bae05b8e4d752843ab489fd85e6df75bc diff --git a/tools/barstools b/tools/barstools index 62f31165..689ebdc0 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 62f311654a4b31ccbc2839beaee64cd770ecd4a0 +Subproject commit 689ebdc06e29028861f3282d9af6f2304541c9db From 8f1e20936fbc515875b24c11367343aed9748dba Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 12 Dec 2020 13:41:32 -0800 Subject: [PATCH 123/157] Update FireSim CI. Push threading into test context --- .../src/test/scala/ScalaTestSuite.scala | 23 +++++++++++-------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 64b9b4ba..51695690 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -42,10 +42,9 @@ abstract class FireSimTestSuite( } def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { - behavior of s"${name} running on ${backend} in MIDAS-level simulation" compileMlSimulator(backend, debug) if (isCmdAvailable(backend)) { - it should s"pass" in { + it should s"pass in ML simualtion on ${backend}" in { assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0) } } @@ -59,13 +58,15 @@ abstract class FireSimTestSuite( case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv" case _ => "" } - val results = suite.names.toSeq sliding (N, N) map { t => - val subresults = t map (name => - Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug))) - Await result (Future sequence subresults, Duration.Inf) - } - results.flatten foreach { case (name, exitcode) => - it should s"pass $name" in { assert(exitcode == 0) } + it should s"pass all tests in ${suite.makeTargetName}" in { + val results = suite.names.toSeq sliding (N, N) map { t => + val subresults = t map (name => + Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug))) + Await result (Future sequence subresults, Duration.Inf) + } + results.flatten foreach { case (name, exitcode) => + assert(exitcode == 0, "Failed $name") + } } } else { ignore should s"pass $backend" @@ -96,7 +97,9 @@ abstract class FireSimTestSuite( } } - clean + mkdirs + behavior of s"Tuple: ${targetTuple}" + elaborateAndCompile() runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) runSuite("verilator")(benchmarks) } From 1bd51447fe890cd0a6450bb655dc6d84c79fe851 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 13 Dec 2020 10:45:51 -0500 Subject: [PATCH 124/157] [ci skip] Fix Typo in firechip/src/test/scala/ScalaTestSuite.scala Co-authored-by: Abraham Gonzalez --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 51695690..64b217b8 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -44,7 +44,7 @@ abstract class FireSimTestSuite( def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { compileMlSimulator(backend, debug) if (isCmdAvailable(backend)) { - it should s"pass in ML simualtion on ${backend}" in { + it should s"pass in ML simulation on ${backend}" in { assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0) } } From a8d6daef93a6e17dab181de3f8875743e93ef58f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 13 Dec 2020 09:32:44 -0800 Subject: [PATCH 125/157] Small build.sbt comments --- build.sbt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index e984de86..e80b2a5e 100644 --- a/build.sbt +++ b/build.sbt @@ -16,7 +16,7 @@ lazy val commonSettings = Seq( addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { - // drop dependencies (org, name) + // drop specific maven dependencies in subprojects in favor of Chipyard's version val dropDeps = Seq( ("edu.berkeley.cs", "firrtl"), ("edu.berkeley.cs", "chisel3"), @@ -86,6 +86,7 @@ lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4") Global / firrtlLibDeps := { + // drop antlr4 compile dep. but keep antlr4-runtime dep. (compile needs the plugin to be setup) (firrtlRef / Keys.libraryDependencies).value.filterNot(_.name == "antlr4") } @@ -144,7 +145,7 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir) ) lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) -// -- "Problematic" Projects -- +// -- Chipyard-managed External Projects -- lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .sourceDependency(firrtlRef, firrtlLib) @@ -168,7 +169,7 @@ lazy val chisel_testers = (project in file("tools/chisel-testers")) .settings(commonSettings) lazy val chiselTestersLibDeps = (chisel_testers / Keys.libraryDependencies) -// -- UCB-controlled Projects -- +// -- Normal Projects -- // Contains annotations & firrtl passes you may wish to use in rocket-chip without // introducing a circular dependency between RC and MIDAS From 02f22e0061ee475103d8b34a2ad6da26dad072ba Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 13 Dec 2020 09:37:48 -0800 Subject: [PATCH 126/157] Bump build.sbt.patch [ci skip] --- scripts/tutorial-patches/build.sbt.patch | 26 ++++++++++++++---------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index cb289b6f..62cecb8d 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,26 +1,30 @@ diff --git a/build.sbt b/build.sbt -index 5d642c1..56f6fda 100644 +index e80b2a5..b1989d9 100644 --- a/build.sbt +++ b/build.sbt -@@ -130,7 +130,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) - - lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, +@@ -184,7 +184,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO + lazy val chipyard = (project in file("generators/chipyard")) + .sourceDependency(testchipip, testchipipLib) + .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) + .settings(libraryDependencies ++= rocketLibDeps.value) +@@ -227,11 +227,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -@@ -158,9 +158,9 @@ lazy val cva6 = (project in file("generators/cva6")) - .dependsOn(rocketchip) - .settings(commonSettings) - + -lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, chisel_testers, midasTargetUtils) +- .settings(libraryDependencies ++= rocketLibDeps.value) +- .settings(libraryDependencies ++= chiselTestersLibDeps.value) - .settings(commonSettings) +//lazy val sha3 = (project in file("generators/sha3")) +// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) ++// .settings(libraryDependencies ++= rocketLibDeps.value) ++// .settings(libraryDependencies ++= chiselTestersLibDeps.value) +// .settings(commonSettings) - + lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(rocketchip, chisel_testers, testchipip) + .sourceDependency(testchipip, testchipipLib) From 0754c1e52b73cae7d79a429384a771bbd94a2397 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Mon, 14 Dec 2020 15:10:24 -0800 Subject: [PATCH 127/157] toolchains: Disable CC and CXX overrides for libgloss build --- scripts/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 1897d157..92cd24dc 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -135,7 +135,7 @@ module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf" # Common tools (not in any particular toolchain dir) -SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknown-elf" --host=riscv64-unknown-elf +CC= CXX= SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknown-elf" --host=riscv64-unknown-elf if [ -z "$IGNOREQEMU" ] ; then SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu From 8836f84c79772e2cf9b8fc9118fb862ed2cce9a7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 15 Dec 2020 16:49:01 -0800 Subject: [PATCH 128/157] [vlsi] Add USE_SRAM_COMPILER Makefile flag to use memory compiler defined in tech library (#740) --- vlsi/Makefile | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 0e1989dd..06f1a1b4 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -25,9 +25,15 @@ tech_dir ?= $(if $(filter $(tech_name),asap7 nangate45),\ SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json -MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\ - --mode synflops,\ - -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict) + +ifeq ($(tech_name),asap7) + MACROCOMPILER_MODE ?= --mode synflops +else ifdef USE_SRAM_COMPILER + MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict +else + MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict +endif + ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ example-nangate45.yml,\ From f693972e1249aaac5d882d6e55e4eb5a81a99bd0 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 17:56:01 +0000 Subject: [PATCH 129/157] Start RC bump Bump to pre-merge chipsalliance/rocket-chip#2764 to get it going while picking up the chisel/firrtl bugfixes in 3/1.4.1+ --- build.sbt | 4 ++-- generators/rocket-chip | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/build.sbt b/build.sbt index e80b2a5e..c3aa9515 100644 --- a/build.sbt +++ b/build.sbt @@ -72,7 +72,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // -- Rocket Chip -- // This needs to stay in sync with the chisel3 and firrtl git submodules -val chiselVersion = "3.4.0" +val chiselVersion = "3.4.1" lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) @@ -81,7 +81,7 @@ lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -val firrtlVersion = "1.4.+" +val firrtlVersion = "1.4.1" lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4") diff --git a/generators/rocket-chip b/generators/rocket-chip index 577994e3..a7b016e4 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 577994e38e3115cafa3a232b0fc60584aacb996e +Subproject commit a7b016e46e22e4fdc013357051e30511f80df082 diff --git a/tools/chisel3 b/tools/chisel3 index d379dca4..58d38f96 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit d379dca4413d4cb08b02165a493faff01f3ddbb9 +Subproject commit 58d38f9620e7e91e4668266686484073c0ba7d2e diff --git a/tools/firrtl b/tools/firrtl index 05d047a9..7756f8f9 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit 05d047a9befda3877f5d8a0a9e1076ffd520ddf9 +Subproject commit 7756f8f9634b68a1375d2c2ca13abc5742234201 From 95420baccfd1ce26354d6af70a09c7f3b50d448b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 17:57:05 +0000 Subject: [PATCH 130/157] Bump boom for riscv-boom/riscv-boom#508 non-master pre-merge bump --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 4bb6464f..1899670a 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 4bb6464ff392cf75e9caf8c06bc252b4f1ac8a28 +Subproject commit 1899670ad92e402e7a5d21c13bdf025f546bb779 From c6dfa1d8c5de36bedfc6e3119ae2394fae2ded86 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 18:03:51 +0000 Subject: [PATCH 131/157] Bump testchipip for ucb-bar/testchipip#111 --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 6fbb1b77..ca67a843 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6fbb1b77b90da5e88bfde8e504595a332cca0e0b +Subproject commit ca67a843bd8f568e205981380c11d321d1bad677 From 5ff5b4e8b7601b461e5d222856ea1a2aaabdab0b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:05:29 +0000 Subject: [PATCH 132/157] Bump sifive-cache for sifive/block-inclusivecache-sifive#18 --- generators/sifive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-cache b/generators/sifive-cache index d4db623f..b1160adc 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit d4db623ff534f775ffc49f59c4a9ef24d5d759d0 +Subproject commit b1160adce09a73df6f5bd40f1e111ab3cefd7300 From f7a372153acf34416f9c6f9c6a10afb95675ab43 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:52:00 +0000 Subject: [PATCH 133/157] Bump hwacha for ucb-bar/hwacha#24 --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index a354150c..62c01f5a 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit a354150cb50fdc0c0ddd356e37850c8e36e02588 +Subproject commit 62c01f5a8858aa1b827f0f9372a4392d7b596fca From 022dbf976ff6f389b40a9e058a2406945b88670e Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:52:30 +0000 Subject: [PATCH 134/157] Bump boom along in the same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 1899670a..ad27160f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 1899670ad92e402e7a5d21c13bdf025f546bb779 +Subproject commit ad27160f2a6f17bb91c70d570299a066b17255a7 From 2ce5f6a40723200761506be0c23042597d1a0045 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:54:31 +0000 Subject: [PATCH 135/157] Bump cva6 for ucb-bar/cva6-wrapper#11 --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index d40a8f5c..139741a5 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit d40a8f5c844f4169c8e74d3fa05f36286f9e4bb6 +Subproject commit 139741a584d7e3c0446db592b5d99529bd6cf9fa From a2ce14f8d3528cb2e86c990a35d82655c3f4cc9e Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 21:03:12 +0000 Subject: [PATCH 136/157] Bump sodor for ucb-bar/riscv-sodor#60 --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index cca8a7aa..8fc51640 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit cca8a7aa5743b9f9bf25779b87b464187c5c3fbc +Subproject commit 8fc516409fde12e447ad78f9d13962b5451c4485 From cb558b59529a328164e7f96bbcba21629df4fc11 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:20:31 +0000 Subject: [PATCH 137/157] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index ad27160f..e250c70f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit ad27160f2a6f17bb91c70d570299a066b17255a7 +Subproject commit e250c70fade22134fe9dc3347cfb5f608e1ee80e From a7e6de835ad5c641c516dc310269a0b921e24452 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:22:03 +0000 Subject: [PATCH 138/157] rm *XTypeKey. upstreamed to RC --- .../chipyard/src/main/scala/CustomBusTopologies.scala | 8 -------- 1 file changed, 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index ee694d22..0a5c1c30 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -13,14 +13,6 @@ import freechips.rocketchip.subsystem._ // For subsystem/BusTopology.scala -/** - * Keys that serve as a means to define crossing types from a Parameters instance - */ -case object SbusToMbusXTypeKey extends Field[ClockCrossingType](NoCrossing) -case object SbusToCbusXTypeKey extends Field[ClockCrossingType](NoCrossing) -case object CbusToPbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) -case object FbusToSbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) - // Biancolin: This, modified from Henry's email /** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */ case class CoherentMulticlockBusTopologyParams( From 72d084da8f8244e29420dfff0a95494d06489562 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:24:19 +0000 Subject: [PATCH 139/157] update parameter classes for RC additions --- generators/chipyard/src/main/scala/example/TutorialTile.scala | 4 ++++ generators/tracegen/src/main/scala/Tile.scala | 2 ++ 2 files changed, 6 insertions(+) diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 23b05f76..fad51c01 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -15,6 +15,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.prci.ClockSinkParameters // Example parameter class copied from CVA6, not included in documentation but for compile check only // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure @@ -39,6 +40,7 @@ case class MyCoreParams( val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket val nLocalInterrupts: Int = 0 + val useNMI: Boolean = false val nPMPs: Int = 0 // TODO: Check val pmpGranularity: Int = 4 // copied from Rocket val nBreakpoints: Int = 0 // TODO: Check @@ -51,6 +53,7 @@ case class MyCoreParams( val misaWritable: Boolean = false val haveCFlush: Boolean = false val nL2TLBEntries: Int = 512 // copied from Rocket + val nL2TLBWays: Int = 1 val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket val mtvecWritable: Boolean = true // copied from Rocket val instBits: Int = if (useCompressed) 16 else 32 @@ -83,6 +86,7 @@ case class MyTileParams( val boundaryBuffers: Boolean = false val dcache: Option[DCacheParams] = Some(DCacheParams()) val icache: Option[ICacheParams] = Some(ICacheParams()) + val clockSinkParams: ClockSinkParameters = ClockSinkParameters() def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = { new MyTile(this, crossing, lookup) } diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 5ff9af56..712cffc1 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.subsystem._ import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO} import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule} +import freechips.rocketchip.prci.ClockSinkParameters class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) @@ -190,6 +191,7 @@ case class BoomTraceGenParams( val blockerCtrlAddr = None val name = None val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId) + val clockSinkParams: ClockSinkParameters = ClockSinkParameters() } class BoomTraceGenTile private( From 29ab6301e0786def4608f7ad3d6456ae36b93c8f Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Mon, 21 Dec 2020 18:15:49 +0000 Subject: [PATCH 140/157] bump sifive-cache for merged sifive/block-inclusivecache-sifive#15 my previous bump duplicated an earlier PR --- generators/sifive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-cache b/generators/sifive-cache index b1160adc..e3a3000c 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit b1160adce09a73df6f5bd40f1e111ab3cefd7300 +Subproject commit e3a3000cc1fd4cdf3a4e638e4d081b8aae94ebf0 From e22350092bdcb11c1f303cf7205eb6caec77efff Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Mon, 21 Dec 2020 18:27:47 +0000 Subject: [PATCH 141/157] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index e250c70f..75399e3c 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit e250c70fade22134fe9dc3347cfb5f608e1ee80e +Subproject commit 75399e3cd94e4ad64f007f9d8ba0f39e6ff7ec16 From 36b9bf86ff9b0aec442be5d0f415e5e45924e76b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 22 Dec 2020 22:45:58 -0800 Subject: [PATCH 142/157] Update MINGIT version to 1.8.5 (#745) 1.8.5 is necessary for `git -C` to work. --- scripts/init-submodules-no-riscv-tools-nolog.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index c861658d..803e9889 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -11,7 +11,7 @@ case ${MYGIT} in [1-9]*) ;; *) echo 'warning: unknown git version' ;; esac -MINGIT="1.7.8" +MINGIT="1.8.5" if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then echo "This script requires git version $MINGIT or greater. Exiting." false From 0f47d80edb350ec41d96586d57b886f50882af2b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Wed, 23 Dec 2020 15:00:57 +0000 Subject: [PATCH 143/157] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 75399e3c..e1a70afe 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 75399e3cd94e4ad64f007f9d8ba0f39e6ff7ec16 +Subproject commit e1a70afed7de77f6ba9f6e501de71f7f41afc47c From 7a0ca12f599c608381dc2ac5e20f48f30f54e3cc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 27 Dec 2020 21:27:01 -0800 Subject: [PATCH 144/157] Bump build.sbt --- build.sbt | 1 + 1 file changed, 1 insertion(+) diff --git a/build.sbt b/build.sbt index 3cb903ef..f44eeb66 100644 --- a/build.sbt +++ b/build.sbt @@ -313,6 +313,7 @@ lazy val firechip = (project in file("generators/firechip")) ) lazy val fpga_shells = (project in file("./fpga/fpga-shells")) .dependsOn(rocketchip, sifive_blocks) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val fpga_platforms = (project in file("./fpga")) From b797077334ffefcb5f9ab5c6397fe4c7fd18baf8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 27 Dec 2020 22:00:06 -0800 Subject: [PATCH 145/157] Fix Arty documentation link --- fpga/src/main/scala/arty/Configs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index fa9a47e0..66391b41 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -38,4 +38,4 @@ class WithArtyTweaks extends Config( class TinyRocketArtyConfig extends Config( new WithArtyTweaks ++ new chipyard.TinyRocketConfig) -// DOC include start: AbstractArty and Rocket +// DOC include end: AbstractArty and Rocket From cb488b8137bd1edc68e37762e5636b20f92ea046 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 27 Dec 2020 22:49:24 -0800 Subject: [PATCH 146/157] Init fpga-shells submod in CI --- .circleci/do-rtl-build.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index fcc76bfa..ed233df1 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -19,6 +19,7 @@ trap clean EXIT cd $LOCAL_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh +./scripts/init-fpga.sh # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" From fbb8ad3e61d664173361a1853ee7ef90246acab1 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 28 Dec 2020 10:50:10 -0700 Subject: [PATCH 147/157] Fix small documentation errors --- docs/Prototyping/Arty.rst | 4 ++-- docs/Prototyping/General.rst | 2 +- docs/Prototyping/VCU118.rst | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/docs/Prototyping/Arty.rst b/docs/Prototyping/Arty.rst index d01cc5c2..204eacec 100644 --- a/docs/Prototyping/Arty.rst +++ b/docs/Prototyping/Arty.rst @@ -1,8 +1,8 @@ Running a Design on Arty ======================== -Basic Design ------------- +Basic Arty Design +----------------- The default Xilinx Arty 35T harness is setup to have JTAG available over the board's PMOD pins, and UART available over its FTDI serial USB adapter. The pin mappings for JTAG signals are identical to those described in the `SiFive Freedom E310 Arty 35T Getting Started Guide `__. The JTAG interface allows a user to connect to the core via OpenOCD, run bare-metal applications, and debug these applications with gdb. UART allows a user to communicate with the core over a USB connection and serial console running on a PC. diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index a653f20a..0221b82b 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -15,7 +15,7 @@ To initialize the ``fpga-shells`` submodule repository, run the included initial ./scripts/init-fpga.sh Generating a Bitstream ------------------- +---------------------- Generating a bitstream for any FPGA target using Vivado is similar to building RTL for a software RTL simulation. Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado: diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index 9deb8739..c12e3714 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -1,8 +1,8 @@ Running a Design on VCU118 ========================== -Basic Design ------------- +Basic VCU118 Design +------------------- The default Xilinx VCU118 harness is setup to have UART, a SPI SDCard, and DDR backing memory. This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). @@ -52,4 +52,4 @@ This example extends the default test harness and creates new ``Overlays`` to co .. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. - See :ref:`Making a Bitstream` for information on the various make variables. + See :ref:`Generating a Bitstream` for information on the various make variables. From b1cedf2d61b925b0b44655302f41a1b08b36e885 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 28 Dec 2020 09:55:10 -0800 Subject: [PATCH 148/157] Make TinyRocketConfig work with multi-clock work --- .../chipyard/src/main/scala/CustomBusTopologies.scala | 10 ++++++++++ .../chipyard/src/main/scala/config/RocketConfigs.scala | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index 0a5c1c30..7bbd53f1 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -70,3 +70,13 @@ class WithMulticlockCoherentBusTopology extends Config((site, here, up) => { l2 = site(BankedL2Key), sbusToMbusXType = site(SbusToMbusXTypeKey))) }) + +class WithMulticlockIncoherentBusTopology extends Config((site, here, up) => { + case TLNetworkTopologyLocated(InSubsystem) => List( + JustOneBusTopologyParams(sbus = site(SystemBusKey)), + HierarchicalMulticlockBusTopologyParams( + pbus = site(PeripheryBusKey), + fbus = site(FrontBusKey), + cbus = site(ControlBusKey), + xTypes = SubsystemCrossingParams())) +}) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index fab1a9d5..308ebc39 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -15,7 +15,7 @@ class TinyRocketConfig extends Config( new chipyard.config.WithTLSerialLocation( freechips.rocketchip.subsystem.FBUS, freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses - new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology + new chipyard.WithMulticlockIncoherentBusTopology ++ // use incoherent bus topology new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core @@ -189,7 +189,7 @@ class MMIORocketConfig extends Config( class MulticlockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Frequency specifications - new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 + new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 new chipyard.config.WithSystemBusFrequency(800.0) ++ // Ditto new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) new chipyard.config.WithPeripheryBusFrequency(100) ++ // Retains the default pbus frequency From a6ca3d21ad55e9010ffc8b1cbc9ad3d121396af6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 28 Dec 2020 16:07:57 -0800 Subject: [PATCH 149/157] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 71d04939..0e06d3c0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 71d049390348b273caf74cb90231ea05272322ae +Subproject commit 0e06d3c054ddbc9c3d3fc7681819b52b1d1f40fd From 5099a96a7b943b15e4e9fd56c20cb2dc0ac90541 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 28 Dec 2020 16:09:34 -0800 Subject: [PATCH 150/157] Bump fpga-shells (to sifive/master) --- .gitmodules | 2 +- fpga/fpga-shells | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 69ce8245..17c9a4b4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -133,4 +133,4 @@ url = https://github.com/ucb-bar/riscv-sodor.git [submodule "fpga/fpga-shells"] path = fpga/fpga-shells - url = https://github.com/abejgonzalez/fpga-shells.git + url = https://github.com/sifive/fpga-shells.git diff --git a/fpga/fpga-shells b/fpga/fpga-shells index fcfadb4c..f9fb9fd3 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit fcfadb4cf36dfbcd7cfee525404b56bf661793b9 +Subproject commit f9fb9fd338e5fca2ff5116b1d01506c424280d70 From 2e1aba653a8b3c944b017c2ccb703f5804510261 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 29 Dec 2020 11:04:07 -0800 Subject: [PATCH 151/157] Bump chisel-testers back to freechipsproject --- .gitmodules | 2 +- tools/chisel-testers | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index bb803d98..7054c14f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -76,7 +76,7 @@ url = https://github.com/ucb-bar/dsptools.git [submodule "tools/chisel-testers"] path = tools/chisel-testers - url = https://github.com/ucb-bar/chisel-testers.git + url = https://github.com/freechipsproject/chisel-testers.git [submodule "tools/treadle"] path = tools/treadle url = https://github.com/freechipsproject/treadle.git diff --git a/tools/chisel-testers b/tools/chisel-testers index 461e8d3a..ce4e027e 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit 461e8d3a3e2f2e4c78d60c239428214cf8c7d773 +Subproject commit ce4e027e5f3d871df59236b8471ea3e5be40130e From 06dccdb588d6bd42b2ac337f3fcc2b9985e5df49 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 29 Dec 2020 10:54:05 -0800 Subject: [PATCH 152/157] Organize check commit CI printout | Don't copy .git folder in CI --- .circleci/check-commit.sh | 16 +++++++++++----- .circleci/defaults.sh | 2 +- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 2660fa49..91ee9e80 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -124,19 +124,25 @@ search # turn off verbose printing to make this easier to read set +x -# print all result strings +# print 0's for str in "${all_names[@]}"; do - echo "$str" + if [ 0 = $(echo "$str" | awk '{print$3}') ]; then + echo "$str" + fi done -# check if there was a non-zero return code +echo "" + +# check if there was a non-zero return code and print 1's +EXIT=0 for str in "${all_names[@]}"; do if [ ! 0 = $(echo "$str" | awk '{print$3}') ]; then - exit 1 + echo "$str" + EXIT=1 fi done echo "Done checking all submodules" - +exit $EXIT diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 12c4531f..11053f60 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -1,7 +1,7 @@ #!/bin/bash copy () { - rsync -avzp -e 'ssh' $1 $2 + rsync -avzp -e 'ssh' --exclude '.git' $1 $2 } run () { From 6f9dcf547863db05e4941a33f8ff5917e0611b76 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 29 Dec 2020 20:51:29 -0800 Subject: [PATCH 153/157] Add new SSH key to access build server --- .circleci/config.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index f18f0e62..478ff315 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -49,6 +49,7 @@ commands: - add_ssh_keys: fingerprints: - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" + - "32:d6:89:d2:97:fa:db:de:a8:2d:2a:f2:70:dd:80:89" - checkout setup-tools: From ec1efc150e89e7c17aa0634a7cf32b318aa335a8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 29 Dec 2020 21:26:23 -0800 Subject: [PATCH 154/157] Add small comment --- .circleci/do-rtl-build.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 1e065437..316c9c6d 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -56,6 +56,7 @@ run "export RISCV=\"$TOOLS_DIR\"; \ read -a keys <<< ${grouping[$1]} +# need to set the PATH to use the new verilator (with the new verilator root) for key in "${keys[@]}" do run "export RISCV=\"$TOOLS_DIR\"; \ From c8cbfbe3c50326db5a915f74d72fc855faa27115 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 31 Dec 2020 14:15:24 -0800 Subject: [PATCH 155/157] Small documentation addition on bringup --- docs/Prototyping/VCU118.rst | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index c12e3714..6d759f82 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -47,8 +47,13 @@ After the harness is created, the ``BundleBridgeSource``'s must be connected to This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`. -An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. -This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. +Introduction to the Bringup Platform +------------------------------------ + +An example of a more complicated design used for Chipyard test chips can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. +This example extends the default test harness and creates new ``Overlays`` to connect to a DUT (connected to the FMC port). +Extensions include another UART (connected over FMC), I2C (connected over FMC), miscellaneous GPIOS (can be connected to anything), and a TSI Host Widget. +The TSI Host Widget is used to interact with the DUT from the prototype over a SerDes link (sometimes called the Low BandWidth InterFace - LBWIF) and provide access to a channel of the FPGA's DRAM. .. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. From 4d3ff26a733e2a5e9b6e86afb89216cbbb8ccece Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 4 Jan 2021 15:36:00 -0800 Subject: [PATCH 156/157] Bump testchipip --- fpga/src/main/scala/vcu118/bringup/Configs.scala | 12 +++++++++--- fpga/src/main/scala/vcu118/bringup/TestHarness.scala | 6 +++--- generators/testchipip | 2 +- 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index ec1ea1e3..62c2af31 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -6,6 +6,7 @@ import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} import freechips.rocketchip.tilelink._ import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.subsystem.{MasterPortParams} import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} @@ -39,10 +40,9 @@ class WithBringupPeripherals extends Config((site, here, up) => { case TSIClockMaxFrequencyKey => 100 case PeripheryTSIHostKey => List( TSIHostParams( - serialIfWidth = 4, + offchipSerialIfWidth = 4, mmioBaseAddress = BigInt(0x64006000), mmioSourceId = 1 << 13, // manager source - targetSize = site(VCU118DDR2Size), serdesParams = TSIHostSerdesParams( clientPortParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( @@ -61,7 +61,13 @@ class WithBringupPeripherals extends Config((site, here, up) => { supportsArithmetic = TransferSizes(1, 64), supportsLogical = TransferSizes(1, 64))), endSinkId = 1 << 6, // manager sink - beatBytes = 8)))) + beatBytes = 8)), + targetMasterPortParams = MasterPortParams( + base = BigInt("80000000", 16), + size = site(VCU118DDR2Size), + beatBytes = 8, // comes from test chip + idBits = 4) // comes from VCU118 idBits in XilinxVCU118MIG + )) }) class WithBringupVCU118System extends Config((site, here, up) => { diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 2e86e646..2406cb7b 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -72,10 +72,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) - val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetBaseAddress, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr + val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetMasterPortParams.base, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr - val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) - dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.serialIfWidth, io_tsi_serial_bb)) + val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth))) + dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb)) // connect 1 mem. channel to the FPGA DDR val inTsiParams = topDesign match { case td: ChipTop => diff --git a/generators/testchipip b/generators/testchipip index 0e06d3c0..39ed56be 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 0e06d3c054ddbc9c3d3fc7681819b52b1d1f40fd +Subproject commit 39ed56be3e72ce09f64889b9d63c8b9fd98eb726 From 5505aef30fb455aca2a97dc8b8dae3544bcc6a67 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Jan 2021 10:56:30 -0800 Subject: [PATCH 157/157] Bump sifive-blocks --- .gitmodules | 2 +- generators/sifive-blocks | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 17c9a4b4..d5e9ae73 100644 --- a/.gitmodules +++ b/.gitmodules @@ -21,7 +21,7 @@ url = https://github.com/riscv-boom/riscv-boom.git [submodule "generators/sifive-blocks"] path = generators/sifive-blocks - url = https://github.com/abejgonzalez/sifive-blocks.git + url = https://github.com/sifive/sifive-blocks.git [submodule "generators/hwacha"] path = generators/hwacha url = https://github.com/ucb-bar/hwacha.git diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 6cc6128b..545a396f 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 6cc6128b8aeab1f92d4ef55a0a06809a95eee730 +Subproject commit 545a396f3486132b01ceef3cbce2085608984478