diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index 7b1640ba..11a99421 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -1,7 +1,6 @@
 package chipyard.fpga.arty100t
 
 import chisel3._
-import chisel3.experimental.{DataMirror, Direction}
 
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem.{PeripheryBusKey}
diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
index 24b7aa9a..c80f828e 100644
--- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
+++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
@@ -1,7 +1,7 @@
 package chipyard.fpga.vcu118.bringup
 
 import chisel3._
-import chisel3.experimental.{IO, DataMirror}
+import chisel3.reflect.DataMirror
 
 import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.tilelink.{TLBundle}
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index 993dad02..011a3c11 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -6,7 +6,6 @@
 package chipyard
 
 import chisel3._
-import chisel3.internal.sourceinfo.{SourceInfo}
 
 import freechips.rocketchip.prci._
 import org.chipsalliance.cde.config.{Field, Parameters}
diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
index 9eeabecf..8bbbb205 100644
--- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
+++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
@@ -1,7 +1,6 @@
 package chipyard.example
 
 import chisel3._
-import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
 import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 
 import org.chipsalliance.cde.config.{Field, Parameters}
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index 59d4110d..909f1638 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -2,7 +2,8 @@ package chipyard.harness
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
+import chisel3.reflect.DataMirror
+import chisel3.experimental.Direction
 
 import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
index 4f32880e..5da69fc7 100644
--- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
@@ -2,7 +2,6 @@ package chipyard.harness
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{DataMirror, Direction}
 
 import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}