From 489ae695fc8427b7dca264916ce6844f81d59e11 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Oct 2020 10:19:43 -0700 Subject: [PATCH 1/4] Add tile-resetter to all designs --- .../chipyard/src/main/scala/Clocks.scala | 18 +++++++++++++++--- generators/testchipip | 2 +- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 554e9905..8dfb9ac6 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -5,12 +5,13 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci._ -import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} +import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey, InstantiatesTiles} import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy.{OutwardNodeHandle, InModuleBody, LazyModule} import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider} import barstools.iocell.chisel._ +import testchipip.{TLTileResetCtrl} import chipyard.clocking.{DividerOnlyClockGenerator, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier} @@ -109,9 +110,20 @@ object ClockingSchemeGenerators { l.asyncClockGroupsNode } + // Add a control register for each tile's reset + val resetSetter = chiptop.lazySystem match { + case sys: BaseSubsystem with InstantiatesTiles => TLTileResetCtrl(sys) + case _ => ClockGroupEphemeralNode() + } + val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node - chiptop.implicitClockSinkNode := ClockGroup() := aggregator - systemAsyncClockGroup := ClockGroupNamePrefixer() := aggregator + (chiptop.implicitClockSinkNode + := ClockGroup() + := aggregator) + (systemAsyncClockGroup + := resetSetter + := ClockGroupNamePrefixer() + := aggregator) val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) (aggregator diff --git a/generators/testchipip b/generators/testchipip index bdca33ec..89b528de 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bdca33ec1684e6e00df2f5c9aebc0b41fb593585 +Subproject commit 89b528decffa8fd33f21dd7a6feabb639274f99a From 164617e2d64c716643dfff5925c450c502e9609f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Oct 2020 10:20:10 -0700 Subject: [PATCH 2/4] Fix no-mbus example design --- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 11399a62..ab0e16ec 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -117,6 +117,7 @@ class LoopbackNICRocketConfig extends Config( // DOC include start: l1scratchpadrocket class ScratchpadOnlyRocketConfig extends Config( + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ From 79042e4ce86302a7335ab49e9c703a181a237bef Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Oct 2020 10:21:43 -0700 Subject: [PATCH 3/4] Bump to support firesim simulation of no-AXI4DRAM designs --- generators/firechip/src/main/scala/BridgeBinders.scala | 9 +++++---- sims/firesim | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 653f8026..1f8bb418 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} import freechips.rocketchip.amba.axi4.{AXI4Bundle} -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp} +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem} import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart._ @@ -67,9 +67,10 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { class WithSerialBridge extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { - ports.map { p => - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset) - SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system)) + ports.map { port => + implicit val p = GetSystemParameters(system) + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) + SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) } Nil } diff --git a/sims/firesim b/sims/firesim index 801baeb9..ef615d35 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 801baeb901c207beb0511311e09ae10e0dbb8b5f +Subproject commit ef615d35da118e73f5128d373f17b80884100773 From 3d0022667a905321e4d0af8dc0f1b5672d330e10 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 1 Oct 2020 22:43:43 -0700 Subject: [PATCH 4/4] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 89b528de..b3aa1bea 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 89b528decffa8fd33f21dd7a6feabb639274f99a +Subproject commit b3aa1bea536ee96a1e69796d35f7651a314c2f6a