From b613c14f1c4cee96ee5abf181ee19df54494fd29 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Fri, 4 Sep 2020 20:03:12 -0700
Subject: [PATCH] Fix remaining HarnessBinders bugs

---
 .circleci/defaults.sh                            |  4 ++--
 .../chipyard/src/main/scala/HarnessBinders.scala |  5 ++++-
 .../chipyard/src/main/scala/IOBinders.scala      | 16 ++++++++--------
 3 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh
index 7ffb1d3c..703737cd 100755
--- a/.circleci/defaults.sh
+++ b/.circleci/defaults.sh
@@ -61,8 +61,8 @@ mapping["chipyard-ariane"]=" CONFIG=ArianeConfig"
 mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
 mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
 mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
-mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem"
-mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig TOP=TraceGenSystem"
+mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
+mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
 mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"
 mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
 mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"
diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala
index 54c99042..89017172 100644
--- a/generators/chipyard/src/main/scala/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/HarnessBinders.scala
@@ -240,7 +240,10 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
 
 class WithTiedOffSerial extends OverrideHarnessBinder({
   (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    ports.map { case p: SerialIO => SerialAdapter.tieoff(Some(p)) }
+    ports.map {
+      case p: SerialIO => SerialAdapter.tieoff(Some(p))
+      case _ =>
+    }
     Nil
   }
 })
diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
index 0dad7e21..acd57207 100644
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -270,8 +270,8 @@ class WithAXI4MemPunchthrough extends OverrideIOBinder({
     } else {
       None
     }
-    val ports = system.mem_axi4.map({ m =>
-      val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_mem")
+    val ports = system.mem_axi4.zipWithIndex.map({ case (m, i) =>
+      val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName(s"axi4_mem_${i}")
       p <> m
       p
     })
@@ -286,8 +286,8 @@ class WithAXI4MMIOPunchthrough extends OverrideIOBinder({
     } else {
       None
     }
-    val ports = system.mmio_axi4.map({ m =>
-      val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_mmio")
+    val ports = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
+      val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName(s"axi4_mmio_${i}")
       p <> m
       p
     })
@@ -297,11 +297,11 @@ class WithAXI4MMIOPunchthrough extends OverrideIOBinder({
 
 class WithL2FBusAXI4Punchthrough extends OverrideIOBinder({
   (system: CanHaveSlaveAXI4Port) => {
-    val port = system.l2_frontend_bus_axi4.map { m =>
-      val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_fbus")
-      p <> m
+    val port = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>
+      val p = IO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_fbus_${i}")
+      m <> p
       p
-    }
+    })
     (port, Nil)
   }
 })