diff --git a/.circleci/config.yml b/.circleci/config.yml
index eac8504a..a6d2e495 100644
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -73,7 +73,7 @@ commands:
             tools-version:
                 type: string
                 default: "riscv-tools"
-            project-key:
+            group-key:
                 type: string
             timeout:
                 type: string
@@ -85,11 +85,11 @@ commands:
             - setup-tools:
                 tools-version: "<< parameters.tools-version >>"
             - run:
-                name: Building << parameters.project-key >> subproject using Verilator
-                command: .circleci/<< parameters.build-script >> << parameters.project-key >>
+                name: Building << parameters.group-key >> subproject using Verilator
+                command: .circleci/<< parameters.build-script >> << parameters.group-key >>
                 no_output_timeout: << parameters.timeout >>
             - save_cache:
-                key: << parameters.project-key >>-{{ .Branch }}-{{ .Revision }}
+                key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }}
                 paths:
                     - "/home/riscvuser/project"
 
@@ -99,11 +99,10 @@ commands:
             tools-version:
                 type: string
                 default: "riscv-tools"
+            group-key:
+                type: string
             project-key:
                 type: string
-            extra-cache-restore:
-                type: string
-                default: ""
             run-script:
                 type: string
                 default: "run-tests.sh"
@@ -115,13 +114,7 @@ commands:
                 tools-version: "<< parameters.tools-version >>"
             - restore_cache:
                 keys:
-                    - << parameters.project-key >>-{{ .Branch }}-{{ .Revision }}
-            - when:
-                condition: << parameters.extra-cache-restore >>
-                steps:
-                    - restore_cache:
-                        keys:
-                            - << parameters.extra-cache-restore >>-{{ .Branch }}-{{ .Revision }}
+                    - << parameters.group-key >>-{{ .Branch }}-{{ .Revision }}
             - run:
                 name: Run << parameters.project-key >> subproject tests
                 command: .circleci/<< parameters.run-script >> << parameters.project-key >>
@@ -194,177 +187,154 @@ jobs:
                 key: extra-tests-{{ .Branch }}-{{ .Revision }}
                 paths:
                     - "/home/riscvuser/project/tests"
-    prepare-chipyard-rocket:
+
+    prepare-chipyard-cores:
         executor: main-env
         steps:
             - prepare-rtl:
-                project-key: "chipyard-rocket"
-    prepare-chipyard-dmirocket:
+                group-key: "group-cores"
+    prepare-chipyard-peripherals:
         executor: main-env
         steps:
             - prepare-rtl:
-                project-key: "chipyard-dmirocket"
-    prepare-chipyard-sha3:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-sha3"
-    prepare-chipyard-streaming-fir:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-streaming-fir"
-    prepare-chipyard-streaming-passthrough:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-streaming-passthrough"
-    prepare-chipyard-hetero:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-hetero"
-                timeout: "240m"
-    prepare-chipyard-boom:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-boom"
-    prepare-chipyard-blkdev:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-blkdev"
-    prepare-chipyard-hwacha:
+                group-key: "group-peripherals"
+    prepare-chipyard-accels:
         executor: main-env
         steps:
             - prepare-rtl:
                 tools-version: "esp-tools"
-                project-key: "chipyard-hwacha"
-    prepare-chipyard-gemmini:
+                group-key: "group-accels"
+    prepare-chipyard-tracegen:
         executor: main-env
         steps:
             - prepare-rtl:
-                tools-version: "esp-tools"
-                project-key: "chipyard-gemmini"
-    prepare-tracegen:
+                group-key: "group-tracegen"
+    prepare-chipyard-other:
         executor: main-env
         steps:
             - prepare-rtl:
-                project-key: "tracegen"
-    prepare-tracegen-boom:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "tracegen-boom"
-    prepare-chipyard-ariane:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-ariane"
-    prepare-icenet:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "icenet"
-    prepare-testchipip:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "testchipip"
-    prepare-chipyard-nvdla:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-nvdla"
-    prepare-chipyard-spiflashwrite:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-spiflashwrite"
-    prepare-chipyard-spiflashread:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-spiflashread"
-    prepare-chipyard-mmios:
-        executor: main-env
-        steps:
-            - prepare-rtl:
-                project-key: "chipyard-mmios"
+                group-key: "group-other"
+
     chipyard-rocket-run-tests:
         executor: main-env
         steps:
             - run-tests:
+                group-key: "group-cores"
                 project-key: "chipyard-rocket"
-    chipyard-dmirocket-run-tests:
-        executor: main-env
-        steps:
-            - run-tests:
-                project-key: "chipyard-dmirocket"
-    chipyard-sha3-run-tests:
-        executor: main-env
-        steps:
-            - run-tests:
-                project-key: "chipyard-sha3"
-    chipyard-streaming-fir-run-tests:
-        executor: main-env
-        steps:
-            - run-tests:
-                project-key: "chipyard-streaming-fir"
-    chipyard-streaming-passthrough-run-tests:
-        executor: main-env
-        steps:
-            - run-tests:
-                project-key: "chipyard-streaming-passthrough"
     chipyard-hetero-run-tests:
         executor: main-env
         steps:
             - run-tests:
+                group-key: "group-cores"
                 project-key: "chipyard-hetero"
                 timeout: "15m"
     chipyard-boom-run-tests:
         executor: main-env
         steps:
             - run-tests:
+                group-key: "group-cores"
                 project-key: "chipyard-boom"
+    chipyard-ariane-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-cores"
+                project-key: "chipyard-ariane"
+                timeout: "30m"
+    chipyard-dmirocket-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-peripherals"
+                project-key: "chipyard-dmirocket"
+    chipyard-spiflashwrite-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-peripherals"
+                project-key: "chipyard-spiflashwrite"
+    chipyard-spiflashread-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-peripherals"
+                project-key: "chipyard-spiflashread"
+    chipyard-lbwif-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-peripherals"
+                project-key: "chipyard-lbwif"
+
+    chipyard-sha3-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-accels"
+                project-key: "chipyard-sha3"
+    chipyard-streaming-fir-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-accels"
+                project-key: "chipyard-streaming-fir"
+    chipyard-streaming-passthrough-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-accels"
+                project-key: "chipyard-streaming-passthrough"
     chipyard-hwacha-run-tests:
         executor: main-env
         steps:
             - run-tests:
                 tools-version: "esp-tools"
+                group-key: "group-accels"
                 project-key: "chipyard-hwacha"
     chipyard-gemmini-run-tests:
         executor: main-env
         steps:
             - run-tests:
                 tools-version: "esp-tools"
+                group-key: "group-accels"
                 project-key: "chipyard-gemmini"
-    chipyard-spiflashwrite-run-tests:
+    chipyard-nvdla-run-tests:
         executor: main-env
         steps:
             - run-tests:
-                project-key: "chipyard-spiflashwrite"
-    chipyard-spiflashread-run-tests:
-        executor: main-env
-        steps:
-            - run-tests:
-                project-key: "chipyard-spiflashread"
+                group-key: "group-accels"
+                project-key: "chipyard-nvdla"
     tracegen-run-tests:
         executor: main-env
         steps:
             - run-tests:
+                group-key: "group-tracegen"
                 project-key: "tracegen"
     tracegen-boom-run-tests:
         executor: main-env
         steps:
             - run-tests:
+                group-key: "group-tracegen"
                 project-key: "tracegen-boom"
+    icenet-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-other"
+                project-key: "icenet"
+                timeout: "30m"
+    testchipip-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-other"
+                project-key: "testchipip"
+                timeout: "30m"
     firesim-run-tests:
         executor: main-env
         steps:
             - run-tests:
-                extra-cache-restore: "extra-tests"
+                group-key: "extra-tests"
                 project-key: "firesim"
                 run-script: "run-firesim-scala-tests.sh"
                 timeout: "20m"
@@ -372,7 +342,7 @@ jobs:
         executor: main-env
         steps:
             - run-tests:
-                extra-cache-restore: "extra-tests"
+                group-key: "extra-tests"
                 project-key: "fireboom"
                 run-script: "run-firesim-scala-tests.sh"
                 timeout: "45m"
@@ -380,33 +350,10 @@ jobs:
         executor: main-env
         steps:
             - run-tests:
-                extra-cache-restore: "extra-tests"
+                group-key: "extra-tests"
                 project-key: "firesim-multiclock"
                 run-script: "run-firesim-scala-tests.sh"
                 timeout: "20m"
-    chipyard-ariane-run-tests:
-        executor: main-env
-        steps:
-            - run-tests:
-                project-key: "chipyard-ariane"
-                timeout: "30m"
-    chipyard-nvdla-run-tests:
-        executor: main-env
-        steps:
-            - run-tests:
-                project-key: "chipyard-nvdla"
-    icenet-run-tests:
-        executor: main-env
-        steps:
-            - run-tests:
-                project-key: "icenet"
-                timeout: "30m"
-    testchipip-run-tests:
-        executor: main-env
-        steps:
-            - run-tests:
-                project-key: "testchipip"
-                timeout: "30m"
 
 # Order and dependencies of jobs to run
 workflows:
@@ -446,154 +393,86 @@ workflows:
                     - install-riscv-toolchain
 
             # Prepare the verilator builds
-            - prepare-chipyard-rocket:
+            - prepare-chipyard-cores:
                 requires:
                     - install-riscv-toolchain
                     - install-verilator
-
-            - prepare-chipyard-dmirocket:
+            - prepare-chipyard-peripherals:
                 requires:
                     - install-riscv-toolchain
                     - install-verilator
-
-            - prepare-chipyard-sha3:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-chipyard-streaming-fir:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-chipyard-streaming-passthrough:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-chipyard-hetero:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-chipyard-boom:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-chipyard-blkdev:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-chipyard-hwacha:
+            - prepare-chipyard-accels:
                 requires:
                     - install-esp-toolchain
                     - install-verilator
-
-            - prepare-chipyard-gemmini:
-                requires:
-                    - install-esp-toolchain
-                    - install-verilator
-
-            - prepare-tracegen:
+            - prepare-chipyard-tracegen:
                 requires:
                     - install-riscv-toolchain
                     - install-verilator
-
-            - prepare-tracegen-boom:
+            - prepare-chipyard-other:
                 requires:
                     - install-riscv-toolchain
                     - install-verilator
 
-            - prepare-chipyard-ariane:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-icenet:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-testchipip:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-chipyard-nvdla:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-chipyard-spiflashwrite:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-chipyard-spiflashread:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
-            - prepare-chipyard-mmios:
-                requires:
-                    - install-riscv-toolchain
-
-            # Run the respective tests
-
             # Run the example tests
             - chipyard-rocket-run-tests:
                 requires:
-                    - prepare-chipyard-rocket
+                    - prepare-chipyard-cores
+            - chipyard-hetero-run-tests:
+                requires:
+                    - prepare-chipyard-cores
+            - chipyard-boom-run-tests:
+                requires:
+                    - prepare-chipyard-cores
+            - chipyard-ariane-run-tests:
+                requires:
+                    - prepare-chipyard-cores
 
             - chipyard-dmirocket-run-tests:
                 requires:
-                    - prepare-chipyard-dmirocket
+                    - prepare-chipyard-peripherals
+            - chipyard-spiflashwrite-run-tests:
+                requires:
+                    - prepare-chipyard-peripherals
+            - chipyard-spiflashread-run-tests:
+                requires:
+                    - prepare-chipyard-peripherals
+            - chipyard-lbwif-run-tests:
+                requires:
+                    - prepare-chipyard-peripherals
 
             - chipyard-sha3-run-tests:
                 requires:
-                    - prepare-chipyard-sha3
-
+                    - prepare-chipyard-accels
             - chipyard-streaming-fir-run-tests:
                 requires:
-                    - prepare-chipyard-streaming-fir
-
+                    - prepare-chipyard-accels
             - chipyard-streaming-passthrough-run-tests:
                 requires:
-                    - prepare-chipyard-streaming-passthrough
-
-            - chipyard-hetero-run-tests:
-                requires:
-                    - prepare-chipyard-hetero
-
-            - chipyard-boom-run-tests:
-                requires:
-                    - prepare-chipyard-boom
-
+                    - prepare-chipyard-accels
             - chipyard-hwacha-run-tests:
                 requires:
-                    - prepare-chipyard-hwacha
-
+                    - prepare-chipyard-accels
             - chipyard-gemmini-run-tests:
                 requires:
-                    - prepare-chipyard-gemmini
+                    - prepare-chipyard-accels
+            - chipyard-nvdla-run-tests:
+                requires:
+                    - prepare-chipyard-accels
 
             - tracegen-run-tests:
                 requires:
-                    - prepare-tracegen
-
+                    - prepare-chipyard-tracegen
             - tracegen-boom-run-tests:
                 requires:
-                    - prepare-tracegen-boom
+                    - prepare-chipyard-tracegen
 
-            - chipyard-spiflashwrite-run-tests:
+            - icenet-run-tests:
                 requires:
-                    - prepare-chipyard-spiflashwrite
-
-            - chipyard-spiflashread-run-tests:
+                    - prepare-chipyard-other
+            - testchipip-run-tests:
                 requires:
-                    - prepare-chipyard-spiflashread
+                    - prepare-chipyard-other
 
             # Run the firesim tests
             - firesim-run-tests:
@@ -612,17 +491,4 @@ workflows:
                     - install-verilator
                     - build-extra-tests
 
-            - chipyard-ariane-run-tests:
-                requires:
-                    - prepare-chipyard-ariane
 
-            - chipyard-nvdla-run-tests:
-                requires:
-                    - prepare-chipyard-nvdla
-            - icenet-run-tests:
-                requires:
-                    - prepare-icenet
-
-            - testchipip-run-tests:
-                requires:
-                    - prepare-testchipip
diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh
index 703737cd..80e3b112 100755
--- a/.circleci/defaults.sh
+++ b/.circleci/defaults.sh
@@ -45,10 +45,19 @@ LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR
 LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator
 LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
 
+# key value store to get the build groups
+declare -A grouping
+grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
+grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
+grouping["group-tracegen"]="tracegen tracegen-boom"
+grouping["group-other"]="icenet testchipip"
+
 # key value store to get the build strings
 declare -A mapping
 mapping["chipyard-rocket"]=""
 mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
+mapping["chipyard-lbwif"]=" CONFIG=LBWIFRocketConfig"
 mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
 mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig"
 mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig"
@@ -64,6 +73,7 @@ mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
 mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
 mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"
+
 mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
 mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"
 mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh
index 3973026f..784dbc04 100755
--- a/.circleci/do-rtl-build.sh
+++ b/.circleci/do-rtl-build.sh
@@ -31,7 +31,7 @@ run "cp -r ~/.sbt  $REMOTE_WORK_DIR"
 TOOLS_DIR=$REMOTE_RISCV_DIR
 LD_LIB_DIR=$REMOTE_RISCV_DIR/lib
 
-if [ $1 = "chipyard-gemmini" ]; then
+if [ $1 = "group-accels" ]; then
     export RISCV=$LOCAL_ESP_DIR
     export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib
     export PATH=$RISCV/bin:$PATH
@@ -40,9 +40,7 @@ if [ $1 = "chipyard-gemmini" ]; then
     git submodule update --init --recursive gemmini-rocc-tests
     cd gemmini-rocc-tests
     ./build.sh
-fi
 
-if [ $1 = "chipyard-hwacha" ] || [ $1 = "chipyard-gemmini" ]; then
     TOOLS_DIR=$REMOTE_ESP_DIR
     LD_LIB_DIR=$REMOTE_ESP_DIR/lib
     run "mkdir -p $REMOTE_ESP_DIR"
@@ -54,16 +52,19 @@ fi
 
 # enter the verilator directory and build the specific config on remote server
 run "export RISCV=\"$TOOLS_DIR\"; \
-     export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
-     export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
-     export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
-     export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
-     make -C $REMOTE_SIM_DIR clean; \
-     make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}"
-run "rm -rf $REMOTE_CHIPYARD_DIR/project"
+     make -C $REMOTE_SIM_DIR clean;"
 
-# copy back the final build
+read -a keys <<< ${grouping[$1]}
 
+for key in "${keys[@]}"
+do
+    run "export RISCV=\"$TOOLS_DIR\"; \
+         export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
+         export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
+         export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
+         export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
+         make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}"
+done
 
 run "rm -rf $REMOTE_CHIPYARD_DIR/project"
 
diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh
index 3e7b0285..20104f18 100755
--- a/.circleci/run-tests.sh
+++ b/.circleci/run-tests.sh
@@ -35,6 +35,9 @@ case $1 in
     chipyard-dmirocket)
         run_bmark ${mapping[$1]}
         ;;
+    chipyard-lbwif)
+        run_bmark ${mapping[$1]}
+        ;;
     chipyard-boom)
         run_bmark ${mapping[$1]}
         ;;
@@ -89,7 +92,7 @@ case $1 in
         run_tracegen ${mapping[$1]}
         ;;
     chipyard-ariane)
-        make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
+        make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv
         ;;
     chipyard-nvdla)
         make -C $LOCAL_CHIPYARD_DIR/tests
diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala
index 531f6add..b54d5c42 100644
--- a/generators/chipyard/src/main/scala/Clocks.scala
+++ b/generators/chipyard/src/main/scala/Clocks.scala
@@ -60,16 +60,15 @@ object GenerateReset {
     val reset_wire = Wire(Input(Reset()))
     val (reset_io, resetIOCell) = p(GlobalResetSchemeKey) match {
       case GlobalResetSynchronous =>
-        IOCell.generateIOFromSignal(reset_wire, Some("iocell_reset"))
+        IOCell.generateIOFromSignal(reset_wire, "reset")
       case GlobalResetAsynchronousFull =>
-        IOCell.generateIOFromSignal(reset_wire, Some("iocell_reset"), abstractResetAsAsync = true)
+        IOCell.generateIOFromSignal(reset_wire, "reset", abstractResetAsAsync = true)
       case GlobalResetAsynchronous => {
         val async_reset_wire = Wire(Input(AsyncReset()))
         reset_wire := ResetCatchAndSync(clock, async_reset_wire.asBool())
-        IOCell.generateIOFromSignal(async_reset_wire, Some("iocell_reset"), abstractResetAsAsync = true)
+        IOCell.generateIOFromSignal(async_reset_wire, "reset", abstractResetAsAsync = true)
       }
     }
-    reset_io.suggestName("reset")
     chiptop.iocells ++= resetIOCell
     chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {
       reset_io := th.dutReset
@@ -124,9 +123,8 @@ object ClockingSchemeGenerators {
     InModuleBody {
       val clock_wire = Wire(Input(Clock()))
       val reset_wire = GenerateReset(chiptop, clock_wire)
-      val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock"))
+      val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock")
       chiptop.iocells ++= clockIOCell
-      clock_io.suggestName("clock")
 
       referenceClockSource.out.unzip._1.map { o =>
         o.clock := clock_wire
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index a065b6be..c0ac1ff7 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -16,7 +16,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
   with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
   with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
-  with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
+  with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
   with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
   with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
   with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala
index 06a3af5d..e5cfacfb 100644
--- a/generators/chipyard/src/main/scala/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/HarnessBinders.scala
@@ -223,20 +223,24 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
 })
 
 
-class WithTiedOffSerial extends OverrideHarnessBinder({
-  (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
-    ports.map { p => SerialAdapter.tieoff(Some(p.bits)) }
-    Nil
+class WithSerialAdapterTiedOff extends OverrideHarnessBinder({
+  (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+    implicit val p = chipyard.iobinders.GetSystemParameters(system)
+    ports.map({ port =>
+      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
+      SerialAdapter.tieoff(ram.module.io.tsi_ser)
+    })
   }
 })
 
 class WithSimSerial extends OverrideHarnessBinder({
-  (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
-    ports.map { p =>
-      val ser_success = SerialAdapter.connectSimSerial(p.bits, p.clock, th.harnessReset)
-      when (ser_success) { th.success := true.B }
-    }
-    Nil
+  (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+    implicit val p = chipyard.iobinders.GetSystemParameters(system)
+    ports.map({ port =>
+      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
+      val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, port.clock, th.harnessReset.asBool)
+      when (success) { th.success := true.B }
+    })
   }
 })
 
diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
index 78233118..4a31e2c0 100644
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -146,8 +146,7 @@ class WithGPIOCells extends OverrideIOBinder({
 class WithUARTIOCells extends OverrideIOBinder({
   (system: HasPeripheryUARTModuleImp) => {
     val (ports: Seq[UARTPortIO], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
-      val (port, ios) = IOCell.generateIOFromSignal(u, Some(s"iocell_uart_${i}"), system.p(IOCellKey))
-      port.suggestName(s"uart_${i}")
+      val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey))
       (port, ios)
     }).unzip
     (ports, cells2d.flatten)
@@ -158,8 +157,9 @@ class WithUARTIOCells extends OverrideIOBinder({
 class WithSPIIOCells extends OverrideIOBinder({
   (system: HasPeripherySPIFlashModuleImp) => {
     val (ports: Seq[SPIChipIO], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
-      val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"spi_${i}")
-      val iocellBase = s"iocell_spi_${i}"
+      val name = s"spi_${i}"
+      val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
+      val iocellBase = s"iocell_${name}"
 
       // SCK and CS are unidirectional outputs
       val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey))
@@ -185,8 +185,7 @@ class WithSPIIOCells extends OverrideIOBinder({
 class WithExtInterruptIOCells extends OverrideIOBinder({
   (system: HasExtInterruptsModuleImp) => {
     if (system.outer.nExtInterrupts > 0) {
-      val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts"), system.p(IOCellKey))
-      port.suggestName("ext_interrupts")
+      val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey))
       (Seq(port), cells)
     } else {
       (Nil, Nil)
@@ -230,19 +229,16 @@ class WithDebugIOCells extends OverrideIOBinder({
 
       // Add IOCells for the DMI/JTAG/APB ports
       val dmiTuple = debug.clockeddmi.map { d =>
-        IOCell.generateIOFromSignal(d, Some("iocell_dmi"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
+        IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
       }
-      dmiTuple.map(_._1).foreach(_.suggestName("dmi"))
 
       val jtagTuple = debug.systemjtag.map { j =>
-        IOCell.generateIOFromSignal(j.jtag, Some("iocell_jtag"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
+        IOCell.generateIOFromSignal(j.jtag, "jtag", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
       }
-      jtagTuple.map(_._1).foreach(_.suggestName("jtag"))
 
       val apbTuple = debug.apb.map { a =>
-        IOCell.generateIOFromSignal(a, Some("iocell_apb"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
+        IOCell.generateIOFromSignal(a, "apb", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
       }
-      apbTuple.map(_._1).foreach(_.suggestName("apb"))
 
       val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq
       (allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq)
@@ -250,11 +246,10 @@ class WithDebugIOCells extends OverrideIOBinder({
   }
 })
 
-class WithSerialIOCells extends OverrideIOBinder({
-  (system: CanHavePeripherySerial) => system.serial.map({ s =>
+class WithSerialTLIOCells extends OverrideIOBinder({
+  (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>
     val sys = system.asInstanceOf[BaseSubsystem]
-    val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial"), sys.p(IOCellKey))
-    port.suggestName("serial")
+    val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey))
     (Seq(port), cells)
   }).getOrElse((Nil, Nil))
 })
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index 92753db5..5dd6ac18 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -25,12 +25,12 @@ import freechips.rocketchip.amba.axi4._
 import boom.common.{BoomTile}
 
 
-import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey}
+import testchipip.{DromajoHelper, CanHavePeripheryTLSerial, SerialTLKey}
 
 trait CanHaveHTIF { this: BaseSubsystem =>
   // Advertise HTIF if system can communicate with fesvr
   if (this match {
-    case _: CanHavePeripherySerial if p(SerialKey) => true
+    case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true
     case _: HasPeripheryDebug if p(ExportDebug).dmi => true
     case _ => false
   }) {
diff --git a/generators/chipyard/src/main/scala/clocking/ClockDividerN.scala b/generators/chipyard/src/main/scala/clocking/ClockDividerN.scala
index c9513b88..06ea2661 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockDividerN.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockDividerN.scala
@@ -1,4 +1,4 @@
-// See LICENSE.SiFive for license details.
+// See LICENSE for license details.
 
 package chipyard.clocking
 
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index 85d3961b..9b04788c 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -14,8 +14,8 @@ class AbstractConfig extends Config(
   // The HarnessBinders control generation of hardware in the TestHarness
   new chipyard.harness.WithUARTAdapter ++                       // add UART adapter to display UART on stdout, if uart is present
   new chipyard.harness.WithBlackBoxSimMem ++                    // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
+  new chipyard.harness.WithSimSerial ++                         // add external serial-adapter and RAM
   new chipyard.harness.WithSimDebug ++                          // add SimJTAG or SimDTM adapters if debug module is enabled
-  new chipyard.harness.WithSimSerial ++                         // add SimSerial adapter for HTIF, if serial port is present
   new chipyard.harness.WithGPIOTiedOff ++                       // tie-off chiptop GPIOs, if GPIOs are present
   new chipyard.harness.WithSimSPIFlashModel ++                  // add simulated SPI flash memory, if SPI is enabled
   new chipyard.harness.WithSimAXIMMIO ++                        // add SimAXIMem for axi4 mmio port, if enabled
@@ -29,7 +29,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++
   new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++
   new chipyard.iobinders.WithNICIOPunchthrough ++
-  new chipyard.iobinders.WithSerialIOCells ++
+  new chipyard.iobinders.WithSerialTLIOCells ++
   new chipyard.iobinders.WithDebugIOCells ++
   new chipyard.iobinders.WithUARTIOCells ++
   new chipyard.iobinders.WithGPIOCells ++
@@ -38,8 +38,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithTraceIOPunchthrough ++
   new chipyard.iobinders.WithExtInterruptIOCells ++
 
-
-  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new testchipip.WithDefaultSerialTL ++                          // use serialized tilelink port to external serialadapter/harnessRAM
   new chipyard.config.WithBootROM ++                             // use default bootrom
   new chipyard.config.WithUART ++                                // add a UART
   new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala
index 9f701331..6e75ac54 100644
--- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala
@@ -13,7 +13,7 @@ class ArianeConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class dmiArianeConfig extends Config(
-  new chipyard.harness.WithTiedOffSerial ++            // Tie off the serial port, override default instantiation of SimSerial
+  new chipyard.harness.WithSerialAdapterTiedOff ++     // Tie off the serial port, override default instantiation of SimSerial
   new chipyard.config.WithDMIDTM ++                    // have debug module expose a clocked DMI port
   new ariane.WithNArianeCores(1) ++                    // single Ariane core
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index dd186828..11399a62 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -25,7 +25,7 @@ class GemminiRocketConfig extends Config(
 
 // DOC include start: DmiRocket
 class dmiRocketConfig extends Config(
-  new chipyard.harness.WithTiedOffSerial ++                      // don't use serial to drive the chip, since we use DMI instead
+  new chipyard.harness.WithSerialAdapterTiedOff ++               // don't attach an external SimSerial
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
@@ -179,3 +179,9 @@ class DividedClockRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
+
+class LBWIFRocketConfig extends Config(
+  new testchipip.WithSerialTLMem(isMainMemory=true) ++      // set lbwif memory base to DRAM_BASE, use as main memory
+  new freechips.rocketchip.subsystem.WithNoMemPort ++       // remove AXI4 backing memory
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index 9197215c..653f8026 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -66,9 +66,10 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
 })
 
 class WithSerialBridge extends OverrideHarnessBinder({
-  (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+  (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     ports.map { p =>
-      SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system))
+      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset)
+      SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system))
     }
     Nil
   }
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index fcacde8b..b70ef647 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -84,7 +84,7 @@ class WithFireSimConfigTweaks extends Config(
   // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
   // for signalling simulation termination under simulation success. This fragment can
   // be removed if you supply an auxiliary bridge that signals simulation termination
-  new testchipip.WithTSI ++
+  new testchipip.WithDefaultSerialTL ++
   // Optional: Removing this will require using an initramfs under linux
   new testchipip.WithBlockDevice ++
   // Required*: Scale default baud rate with periphery bus frequency
@@ -131,7 +131,7 @@ class FireSimSmallSystemConfig extends Config(
   new WithoutClockGating ++
   new WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
-  new testchipip.WithTSI ++
+  new testchipip.WithDefaultSerialTL ++
   new testchipip.WithBlockDevice ++
   new chipyard.config.WithUART ++
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
diff --git a/generators/testchipip b/generators/testchipip
index a86c827c..bdca33ec 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit a86c827ca6e4e9d8320117ef1223da0ff752d064
+Subproject commit bdca33ec1684e6e00df2f5c9aebc0b41fb593585
diff --git a/scripts/smartelf2hex.sh b/scripts/smartelf2hex.sh
index 782977ff..dd035690 100755
--- a/scripts/smartelf2hex.sh
+++ b/scripts/smartelf2hex.sh
@@ -8,7 +8,9 @@ binary=$1
 segments=`readelf --segments --wide $binary`
 entry_hex=`echo -e "$segments" | grep "Entry point" | cut -f3 -d' ' | sed 's/0x//' | tr [:lower:] [:upper:]`
 entry_dec=`bc <<< "ibase=16;$entry_hex"`
-length_hex=`echo "$segments" | grep LOAD | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '`
+length_hex=`echo "$segments" | grep "LOAD\|TLS" | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '`
 length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc`
 power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l`
-elf2hex 64 $power_2_length $binary $entry_dec
+width=64
+depth=$((power_2_length / width))
+elf2hex $width $depth $binary $entry_dec
diff --git a/sims/firesim b/sims/firesim
index 4342b333..54ffa13d 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 4342b33301ae9b3f53b98ca3b1d1afff73d64997
+Subproject commit 54ffa13d980609549be47222a284521b73e56188
diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim
index aa332c6a..fa94e84d 160000
--- a/toolchains/esp-tools/riscv-isa-sim
+++ b/toolchains/esp-tools/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit aa332c6a9a5ec77a9b97cdb4a1978ad394b17f1e
+Subproject commit fa94e84d4ff3e23ba909a63376b294e444234752
diff --git a/tools/barstools b/tools/barstools
index 31590a79..4a5c75fc 160000
--- a/tools/barstools
+++ b/tools/barstools
@@ -1 +1 @@
-Subproject commit 31590a7948db47fd16beed266c4833579acc305b
+Subproject commit 4a5c75fcf85f03af858f1d7db04303d4b0733de7