From 6c5bce5430002e60a676a9089f7d5822523e13ff Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 13 Sep 2020 11:59:16 -0700 Subject: [PATCH 01/10] Support Tilelink over serial --- .circleci/config.yml | 19 ++++++++++ .circleci/defaults.sh | 1 + .circleci/run-tests.sh | 3 ++ .../chipyard/src/main/scala/DigitalTop.scala | 3 +- .../src/main/scala/HarnessBinders.scala | 36 ++++++++++++++++--- .../chipyard/src/main/scala/IOBinders.scala | 17 ++++++--- .../chipyard/src/main/scala/Subsystem.scala | 4 +-- .../main/scala/config/AbstractConfig.scala | 7 ++-- .../src/main/scala/config/ArianeConfigs.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 10 ++++-- .../src/main/scala/BridgeBinders.scala | 2 +- .../src/main/scala/TargetConfigs.scala | 4 +-- generators/testchipip | 2 +- sims/firesim | 2 +- 14 files changed, 90 insertions(+), 22 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index eac8504a..1b239354 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -204,6 +204,11 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-dmirocket" + prepare-chipyard-tlserial: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-tlserial" prepare-chipyard-sha3: executor: main-env steps: @@ -302,6 +307,11 @@ jobs: steps: - run-tests: project-key: "chipyard-dmirocket" + chipyard-tlserial-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-tlserial" chipyard-sha3-run-tests: executor: main-env steps: @@ -456,6 +466,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-tlserial: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-chipyard-sha3: requires: - install-riscv-toolchain @@ -551,6 +566,10 @@ workflows: requires: - prepare-chipyard-dmirocket + - chipyard-tlserial-run-tests: + requires: + - prepare-chipyard-tlserial + - chipyard-sha3-run-tests: requires: - prepare-chipyard-sha3 diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 703737cd..2a744e89 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -49,6 +49,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim declare -A mapping mapping["chipyard-rocket"]="" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" +mapping["chipyard-tlserial"]=" CONFIG=TLSerialRocketConfig" mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig" mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 3e7b0285..cee04dd3 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -35,6 +35,9 @@ case $1 in chipyard-dmirocket) run_bmark ${mapping[$1]} ;; + chipyard-tlserial) + run_bmark ${mapping[$1]} + ;; chipyard-boom) run_bmark ${mapping[$1]} ;; diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index a065b6be..f967b8fc 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -16,7 +16,8 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device - with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port + with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the tilelink-over-serial backing memory + with testchipip.CanHavePeripheryTSISerial // Enables optionally adding the TSI serial-adapter and port with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 06a3af5d..c1b57f72 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -223,15 +223,15 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ }) -class WithTiedOffSerial extends OverrideHarnessBinder({ - (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { +class WithTiedOffTSISerial extends OverrideHarnessBinder({ + (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { p => SerialAdapter.tieoff(Some(p.bits)) } Nil } }) -class WithSimSerial extends OverrideHarnessBinder({ - (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { +class WithSimTSISerial extends OverrideHarnessBinder({ + (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { p => val ser_success = SerialAdapter.connectSimSerial(p.bits, p.clock, th.harnessReset) when (ser_success) { th.success := true.B } @@ -240,6 +240,34 @@ class WithSimSerial extends OverrideHarnessBinder({ } }) +class WithSimTLSerial(withHarnessSerialAdapter: Boolean = false) extends OverrideHarnessBinder({ + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + implicit val p = chipyard.iobinders.GetSystemParameters(system) + ports.map({ port => + withClockAndReset(port.clock, th.harnessReset) { + val lRam = LazyModule(new SerialRAM( + p(SerialTLKey).get.width, + p(SerialTLKey).get.memParams.master.size, + p(SerialTLKey).get.memParams.master.base, + managerEdge = system.serdesser.get.managerNode.edges.in(0), + clientEdge = system.serdesser.get.clientNode.edges.out(0) + )) + val ram = Module(lRam.module) + ram.io.ser <> port.bits + + require(lRam.serdesser.module.mergedParams == system.serdesser.get.module.mergedParams, + "Mismatch between chip-side diplomatic params and testram diplomatic params") + if (withHarnessSerialAdapter) { + val success = SerialAdapter.connectSimSerial(Some(ram.io.tsi_ser), port.clock, th.harnessReset.asBool) + when (success) { th.success := true.B } + } else { + SerialAdapter.tieoff(Some(ram.io.tsi_ser)) + } + } + }) + } +}) + class WithTraceGenSuccess extends OverrideHarnessBinder({ (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { ports.map { p => when (p) { th.success := true.B } } diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 78233118..03138cc1 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -250,11 +250,20 @@ class WithDebugIOCells extends OverrideIOBinder({ } }) -class WithSerialIOCells extends OverrideIOBinder({ - (system: CanHavePeripherySerial) => system.serial.map({ s => +class WithSerialTSIIOCells extends OverrideIOBinder({ + (system: CanHavePeripheryTSISerial) => system.serial_tsi.map({ s => val sys = system.asInstanceOf[BaseSubsystem] - val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial"), sys.p(IOCellKey)) - port.suggestName("serial") + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial_tsi"), sys.p(IOCellKey)) + port.suggestName("serial_tsi") + (Seq(port), cells) + }).getOrElse((Nil, Nil)) +}) + +class WithSerialTLIOCells extends OverrideIOBinder({ + (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s => + val sys = system.asInstanceOf[BaseSubsystem] + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial_tl"), sys.p(IOCellKey)) + port.suggestName("serial_tl") (Seq(port), cells) }).getOrElse((Nil, Nil)) }) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 7f089ce1..35c41e0c 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -25,12 +25,12 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile} -import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey} +import testchipip.{DromajoHelper, CanHavePeripheryTSISerial, SerialTSIKey} trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { - case _: CanHavePeripherySerial if p(SerialKey) => true + case _: CanHavePeripheryTSISerial if p(SerialTSIKey).nonEmpty => true case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true case _ => false }) { diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 950cb4b4..aed55d02 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -15,7 +15,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled - new chipyard.harness.WithSimSerial ++ // add SimSerial adapter for HTIF, if serial port is present + new chipyard.harness.WithSimTSISerial ++ // add SimSerial adapter for HTIF, if serial port is present new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled @@ -29,7 +29,8 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++ new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++ new chipyard.iobinders.WithNICIOPunchthrough ++ - new chipyard.iobinders.WithSerialIOCells ++ + new chipyard.iobinders.WithSerialTSIIOCells ++ + new chipyard.iobinders.WithSerialTLIOCells ++ new chipyard.iobinders.WithDebugIOCells ++ new chipyard.iobinders.WithUARTIOCells ++ new chipyard.iobinders.WithGPIOCells ++ @@ -39,7 +40,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithExtInterruptIOCells ++ - new testchipip.WithTSI ++ // use testchipip serial offchip link + new testchipip.WithSerialTSI ++ // use testchipip serial offchip link new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index 9f701331..b7c347dc 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -13,7 +13,7 @@ class ArianeConfig extends Config( new chipyard.config.AbstractConfig) class dmiArianeConfig extends Config( - new chipyard.harness.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.harness.WithTiedOffTSISerial ++ // Tie off the serial port, override default instantiation of SimSerial new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new ariane.WithNArianeCores(1) ++ // single Ariane core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 16d298fb..9f2a97de 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -25,7 +25,7 @@ class GemminiRocketConfig extends Config( // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.harness.WithTiedOffSerial ++ // don't use serial to drive the chip, since we use DMI instead + new chipyard.harness.WithTiedOffTSISerial ++ // don't use serial to drive the chip, since we use DMI instead new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -182,4 +182,10 @@ class DividedClockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) - +class TLSerialRocketConfig extends Config( + new chipyard.harness.WithSimTLSerial(withHarnessSerialAdapter = true) ++ // add external TL backing memory, and external serial adapter + new testchipip.WithDefaultSerialTL ++ // support tilelink-over-serial + new testchipip.WithNoSerialTSI ++ // remove internal serial adapter + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory + new chipyard.config.AbstractConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index f42a1adf..ebd629c7 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -56,7 +56,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { }) class WithSerialBridge extends OverrideHarnessBinder({ - (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { p => withClockAndReset(p.clock, th.harnessReset) { SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system)) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 2dede960..7df0bf61 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -84,7 +84,7 @@ class WithFireSimConfigTweaks extends Config( // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible // for signalling simulation termination under simulation success. This fragment can // be removed if you supply an auxiliary bridge that signals simulation termination - new testchipip.WithTSI ++ + new testchipip.WithSerialTSI ++ // Optional: Removing this will require using an initramfs under linux new testchipip.WithBlockDevice ++ // Required*: Scale default baud rate with periphery bus frequency @@ -131,7 +131,7 @@ class FireSimSmallSystemConfig extends Config( new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ - new testchipip.WithTSI ++ + new testchipip.WithSerialTSI ++ new testchipip.WithBlockDevice ++ new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ diff --git a/generators/testchipip b/generators/testchipip index a86c827c..6f815737 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit a86c827ca6e4e9d8320117ef1223da0ff752d064 +Subproject commit 6f8157375451fbb32e9dae291f2c65878a2b1dcd diff --git a/sims/firesim b/sims/firesim index c1cd3e5e..2b52057e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c1cd3e5e7013b30f30508c7f47ff13180949eafe +Subproject commit 2b52057e158fd91d44c6259aa08869622a88040a From 0d8e87126cb4070044a3a86da7fe7bdac125a4fc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 14 Sep 2020 19:41:02 -0700 Subject: [PATCH 02/10] Deprecate support for on-chip SerialAdapter --- .../chipyard/src/main/scala/DigitalTop.scala | 1 - .../src/main/scala/HarnessBinders.scala | 50 +++++-------------- .../chipyard/src/main/scala/IOBinders.scala | 9 ---- .../chipyard/src/main/scala/Subsystem.scala | 4 +- .../main/scala/config/AbstractConfig.scala | 6 +-- .../src/main/scala/config/ArianeConfigs.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 10 ++-- .../src/main/scala/BridgeBinders.scala | 5 +- .../src/main/scala/TargetConfigs.scala | 4 +- generators/testchipip | 2 +- tools/barstools | 2 +- 11 files changed, 29 insertions(+), 66 deletions(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index f967b8fc..a14a3fbe 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -17,7 +17,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the tilelink-over-serial backing memory - with testchipip.CanHavePeripheryTSISerial // Enables optionally adding the TSI serial-adapter and port with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index c1b57f72..e5cfacfb 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -223,47 +223,23 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ }) -class WithTiedOffTSISerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { - ports.map { p => SerialAdapter.tieoff(Some(p.bits)) } - Nil - } -}) - -class WithSimTSISerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { - ports.map { p => - val ser_success = SerialAdapter.connectSimSerial(p.bits, p.clock, th.harnessReset) - when (ser_success) { th.success := true.B } - } - Nil - } -}) - -class WithSimTLSerial(withHarnessSerialAdapter: Boolean = false) extends OverrideHarnessBinder({ +class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - withClockAndReset(port.clock, th.harnessReset) { - val lRam = LazyModule(new SerialRAM( - p(SerialTLKey).get.width, - p(SerialTLKey).get.memParams.master.size, - p(SerialTLKey).get.memParams.master.base, - managerEdge = system.serdesser.get.managerNode.edges.in(0), - clientEdge = system.serdesser.get.clientNode.edges.out(0) - )) - val ram = Module(lRam.module) - ram.io.ser <> port.bits + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) + SerialAdapter.tieoff(ram.module.io.tsi_ser) + }) + } +}) - require(lRam.serdesser.module.mergedParams == system.serdesser.get.module.mergedParams, - "Mismatch between chip-side diplomatic params and testram diplomatic params") - if (withHarnessSerialAdapter) { - val success = SerialAdapter.connectSimSerial(Some(ram.io.tsi_ser), port.clock, th.harnessReset.asBool) - when (success) { th.success := true.B } - } else { - SerialAdapter.tieoff(Some(ram.io.tsi_ser)) - } - } +class WithSimSerial extends OverrideHarnessBinder({ + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + implicit val p = chipyard.iobinders.GetSystemParameters(system) + ports.map({ port => + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) + val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, port.clock, th.harnessReset.asBool) + when (success) { th.success := true.B } }) } }) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 03138cc1..73a8acfd 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -250,15 +250,6 @@ class WithDebugIOCells extends OverrideIOBinder({ } }) -class WithSerialTSIIOCells extends OverrideIOBinder({ - (system: CanHavePeripheryTSISerial) => system.serial_tsi.map({ s => - val sys = system.asInstanceOf[BaseSubsystem] - val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial_tsi"), sys.p(IOCellKey)) - port.suggestName("serial_tsi") - (Seq(port), cells) - }).getOrElse((Nil, Nil)) -}) - class WithSerialTLIOCells extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s => val sys = system.asInstanceOf[BaseSubsystem] diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index c3ca93b7..172be692 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -25,12 +25,12 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile} -import testchipip.{DromajoHelper, CanHavePeripheryTSISerial, SerialTSIKey} +import testchipip.{DromajoHelper, CanHavePeripheryTLSerial, SerialTLKey} trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { - case _: CanHavePeripheryTSISerial if p(SerialTSIKey).nonEmpty => true + case _: CanHavePeripheryTKSerial if p(SerialTLKey).nonEmpty => true case _: HasPeripheryDebug if p(ExportDebug).dmi => true case _ => false }) { diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index aed55d02..5b356c74 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -14,8 +14,8 @@ class AbstractConfig extends Config( // The HarnessBinders control generation of hardware in the TestHarness new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled + new chipyard.harness.WithSimSerial ++ // add external serial-adapter and RAM new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled - new chipyard.harness.WithSimTSISerial ++ // add SimSerial adapter for HTIF, if serial port is present new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled @@ -29,7 +29,6 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++ new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++ new chipyard.iobinders.WithNICIOPunchthrough ++ - new chipyard.iobinders.WithSerialTSIIOCells ++ new chipyard.iobinders.WithSerialTLIOCells ++ new chipyard.iobinders.WithDebugIOCells ++ new chipyard.iobinders.WithUARTIOCells ++ @@ -39,8 +38,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithExtInterruptIOCells ++ - - new testchipip.WithSerialTSI ++ // use testchipip serial offchip link + new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index b7c347dc..6e75ac54 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -13,7 +13,7 @@ class ArianeConfig extends Config( new chipyard.config.AbstractConfig) class dmiArianeConfig extends Config( - new chipyard.harness.WithTiedOffTSISerial ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new ariane.WithNArianeCores(1) ++ // single Ariane core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 9f2a97de..42b5f3b0 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -25,7 +25,7 @@ class GemminiRocketConfig extends Config( // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.harness.WithTiedOffTSISerial ++ // don't use serial to drive the chip, since we use DMI instead + new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -182,10 +182,8 @@ class DividedClockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -class TLSerialRocketConfig extends Config( - new chipyard.harness.WithSimTLSerial(withHarnessSerialAdapter = true) ++ // add external TL backing memory, and external serial adapter - new testchipip.WithDefaultSerialTL ++ // support tilelink-over-serial - new testchipip.WithNoSerialTSI ++ // remove internal serial adapter +class LBWIFMemoryRocketConfig extends Config( + new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory new chipyard.config.AbstractConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 98f672a9..4943e130 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -66,10 +66,11 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { }) class WithSerialBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { p => + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset) withClockAndReset(p.clock, th.harnessReset) { - SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system)) + SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system)) } } Nil diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 7df0bf61..678afccf 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -84,7 +84,7 @@ class WithFireSimConfigTweaks extends Config( // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible // for signalling simulation termination under simulation success. This fragment can // be removed if you supply an auxiliary bridge that signals simulation termination - new testchipip.WithSerialTSI ++ + new testchipip.WithDefaultSerialTL ++ // Optional: Removing this will require using an initramfs under linux new testchipip.WithBlockDevice ++ // Required*: Scale default baud rate with periphery bus frequency @@ -131,7 +131,7 @@ class FireSimSmallSystemConfig extends Config( new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ - new testchipip.WithSerialTSI ++ + new testchipip.WithDefaultSerialTL ++ new testchipip.WithBlockDevice ++ new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ diff --git a/generators/testchipip b/generators/testchipip index 6f815737..e845cb3f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6f8157375451fbb32e9dae291f2c65878a2b1dcd +Subproject commit e845cb3f50bb141fec7e8291a40d0b46d5ef5c12 diff --git a/tools/barstools b/tools/barstools index 31590a79..847f72ec 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 31590a7948db47fd16beed266c4833579acc305b +Subproject commit 847f72eca0fa3207ab7140c07e980ac9f8cf1251 From aa8b7c15ecfed723d8f01748ebb3af6e64516cde Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 14 Sep 2020 23:04:58 -0700 Subject: [PATCH 03/10] Reduce CI redundancy by grouping builds --- .circleci/config.yml | 386 ++++++++++++-------------------------- .circleci/defaults.sh | 9 + .circleci/do-rtl-build.sh | 19 +- 3 files changed, 142 insertions(+), 272 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index eac8504a..6ed04488 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -99,11 +99,10 @@ commands: tools-version: type: string default: "riscv-tools" + group-key: + type: string project-key: type: string - extra-cache-restore: - type: string - default: "" run-script: type: string default: "run-tests.sh" @@ -115,13 +114,7 @@ commands: tools-version: "<< parameters.tools-version >>" - restore_cache: keys: - - << parameters.project-key >>-{{ .Branch }}-{{ .Revision }} - - when: - condition: << parameters.extra-cache-restore >> - steps: - - restore_cache: - keys: - - << parameters.extra-cache-restore >>-{{ .Branch }}-{{ .Revision }} + - << parameters.group-key >>-{{ .Branch }}-{{ .Revision }} - run: name: Run << parameters.project-key >> subproject tests command: .circleci/<< parameters.run-script >> << parameters.project-key >> @@ -194,177 +187,147 @@ jobs: key: extra-tests-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project/tests" - prepare-chipyard-rocket: + + prepare-chipyard-cores: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-rocket" - prepare-chipyard-dmirocket: + project-key: "group-cores" + prepare-chipyard-peripherals: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-dmirocket" - prepare-chipyard-sha3: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-sha3" - prepare-chipyard-streaming-fir: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-streaming-fir" - prepare-chipyard-streaming-passthrough: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-streaming-passthrough" - prepare-chipyard-hetero: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-hetero" - timeout: "240m" - prepare-chipyard-boom: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-boom" - prepare-chipyard-blkdev: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-blkdev" - prepare-chipyard-hwacha: + project-key: "group-peripherals" + prepare-chipyard-accels: executor: main-env steps: - prepare-rtl: tools-version: "esp-tools" - project-key: "chipyard-hwacha" - prepare-chipyard-gemmini: + project-key: "group-accels" + prepare-chipyard-tracegen: executor: main-env steps: - prepare-rtl: - tools-version: "esp-tools" - project-key: "chipyard-gemmini" - prepare-tracegen: + project-key: "group-tracegen" + prepare-chipyard-other: executor: main-env steps: - prepare-rtl: - project-key: "tracegen" - prepare-tracegen-boom: - executor: main-env - steps: - - prepare-rtl: - project-key: "tracegen-boom" - prepare-chipyard-ariane: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-ariane" - prepare-icenet: - executor: main-env - steps: - - prepare-rtl: - project-key: "icenet" - prepare-testchipip: - executor: main-env - steps: - - prepare-rtl: - project-key: "testchipip" - prepare-chipyard-nvdla: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-nvdla" - prepare-chipyard-spiflashwrite: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-spiflashwrite" - prepare-chipyard-spiflashread: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-spiflashread" - prepare-chipyard-mmios: - executor: main-env - steps: - - prepare-rtl: - project-key: "chipyard-mmios" + project-key: "group-other" + chipyard-rocket-run-tests: executor: main-env steps: - run-tests: + group-key: "group-cores" project-key: "chipyard-rocket" - chipyard-dmirocket-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-dmirocket" - chipyard-sha3-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-sha3" - chipyard-streaming-fir-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-streaming-fir" - chipyard-streaming-passthrough-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-streaming-passthrough" chipyard-hetero-run-tests: executor: main-env steps: - run-tests: + group-key: "group-cores" project-key: "chipyard-hetero" timeout: "15m" chipyard-boom-run-tests: executor: main-env steps: - run-tests: + group-key: "group-cores" project-key: "chipyard-boom" + chipyard-ariane-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-cores" + project-key: "chipyard-ariane" + timeout: "30m" + chipyard-dmirocket-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-peripherals" + project-key: "chipyard-dmirocket" + chipyard-spiflashwrite-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-peripherals" + project-key: "chipyard-spiflashwrite" + chipyard-spiflashread-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-peripherals" + project-key: "chipyard-spiflashread" + chipyard-sha3-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-accels" + project-key: "chipyard-sha3" + chipyard-streaming-fir-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-accels" + project-key: "chipyard-streaming-fir" + chipyard-streaming-passthrough-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-accels" + project-key: "chipyard-streaming-passthrough" chipyard-hwacha-run-tests: executor: main-env steps: - run-tests: tools-version: "esp-tools" + group-key: "group-accels" project-key: "chipyard-hwacha" chipyard-gemmini-run-tests: executor: main-env steps: - run-tests: tools-version: "esp-tools" + group-key: "group-accels" project-key: "chipyard-gemmini" - chipyard-spiflashwrite-run-tests: + chipyard-nvdla-run-tests: executor: main-env steps: - run-tests: - project-key: "chipyard-spiflashwrite" - chipyard-spiflashread-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-spiflashread" + group-key: "group-accels" + project-key: "chipyard-nvdla" tracegen-run-tests: executor: main-env steps: - run-tests: + group-key: "group-tracegen" project-key: "tracegen" tracegen-boom-run-tests: executor: main-env steps: - run-tests: + group-key: "group-tracegen" project-key: "tracegen-boom" + icenet-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-other" + project-key: "icenet" + timeout: "30m" + testchipip-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-other" + project-key: "testchipip" + timeout: "30m" firesim-run-tests: executor: main-env steps: - run-tests: - extra-cache-restore: "extra-tests" + group-key: "extra-tests" project-key: "firesim" run-script: "run-firesim-scala-tests.sh" timeout: "20m" @@ -372,7 +335,7 @@ jobs: executor: main-env steps: - run-tests: - extra-cache-restore: "extra-tests" + group-key: "extra-tests" project-key: "fireboom" run-script: "run-firesim-scala-tests.sh" timeout: "45m" @@ -380,33 +343,10 @@ jobs: executor: main-env steps: - run-tests: - extra-cache-restore: "extra-tests" + group-key: "extra-tests" project-key: "firesim-multiclock" run-script: "run-firesim-scala-tests.sh" timeout: "20m" - chipyard-ariane-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-ariane" - timeout: "30m" - chipyard-nvdla-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "chipyard-nvdla" - icenet-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "icenet" - timeout: "30m" - testchipip-run-tests: - executor: main-env - steps: - - run-tests: - project-key: "testchipip" - timeout: "30m" # Order and dependencies of jobs to run workflows: @@ -446,154 +386,83 @@ workflows: - install-riscv-toolchain # Prepare the verilator builds - - prepare-chipyard-rocket: + - prepare-chipyard-cores: requires: - install-riscv-toolchain - install-verilator - - - prepare-chipyard-dmirocket: + - prepare-chipyard-peripherals: requires: - install-riscv-toolchain - install-verilator - - - prepare-chipyard-sha3: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-streaming-fir: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-streaming-passthrough: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-hetero: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-boom: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-blkdev: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-hwacha: + - prepare-chipyard-accels: requires: - install-esp-toolchain - install-verilator - - - prepare-chipyard-gemmini: - requires: - - install-esp-toolchain - - install-verilator - - - prepare-tracegen: + - prepare-chipyard-tracegen: requires: - install-riscv-toolchain - install-verilator - - - prepare-tracegen-boom: + - prepare-chipyard-other: requires: - install-riscv-toolchain - install-verilator - - prepare-chipyard-ariane: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-icenet: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-testchipip: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-nvdla: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-spiflashwrite: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-spiflashread: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-chipyard-mmios: - requires: - - install-riscv-toolchain - - # Run the respective tests - # Run the example tests - chipyard-rocket-run-tests: requires: - - prepare-chipyard-rocket + - prepare-chipyard-cores + - chipyard-hetero-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-boom-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-ariane-run-tests: + requires: + - prepare-chipyard-cores - chipyard-dmirocket-run-tests: requires: - - prepare-chipyard-dmirocket + - prepare-chipyard-peripherals + - chipyard-spiflashwrite-run-tests: + requires: + - prepare-chipyard-peripherals + - chipyard-spiflashread-run-tests: + requires: + - prepare-chipyard-peripherals - chipyard-sha3-run-tests: requires: - - prepare-chipyard-sha3 - + - prepare-chipyard-accels - chipyard-streaming-fir-run-tests: requires: - - prepare-chipyard-streaming-fir - + - prepare-chipyard-accels - chipyard-streaming-passthrough-run-tests: requires: - - prepare-chipyard-streaming-passthrough - - - chipyard-hetero-run-tests: - requires: - - prepare-chipyard-hetero - - - chipyard-boom-run-tests: - requires: - - prepare-chipyard-boom - + - prepare-chipyard-accels - chipyard-hwacha-run-tests: requires: - - prepare-chipyard-hwacha - + - prepare-chipyard-accels - chipyard-gemmini-run-tests: requires: - - prepare-chipyard-gemmini + - prepare-chipyard-accels + - chipyard-nvdla-run-tests: + requires: + - prepare-chipyard-accels - tracegen-run-tests: requires: - - prepare-tracegen - + - prepare-chipyard-tracegen - tracegen-boom-run-tests: requires: - - prepare-tracegen-boom + - prepare-chipyard-tracegen - - chipyard-spiflashwrite-run-tests: + - icenet-run-tests: requires: - - prepare-chipyard-spiflashwrite - - - chipyard-spiflashread-run-tests: + - prepare-chipyard-other + - testchipip-run-tests: requires: - - prepare-chipyard-spiflashread + - prepare-chipyard-other # Run the firesim tests - firesim-run-tests: @@ -612,17 +481,4 @@ workflows: - install-verilator - build-extra-tests - - chipyard-ariane-run-tests: - requires: - - prepare-chipyard-ariane - - chipyard-nvdla-run-tests: - requires: - - prepare-chipyard-nvdla - - icenet-run-tests: - requires: - - prepare-icenet - - - testchipip-run-tests: - requires: - - prepare-testchipip diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 703737cd..6f74c26d 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -45,6 +45,14 @@ LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim +# key value store to get the build groups +declare -A grouping +grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom" +grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios" +grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" +grouping["group-tracegen"]="tracegen tracegen-boom" +grouping["group-other"]="icenet testchipip" + # key value store to get the build strings declare -A mapping mapping["chipyard-rocket"]="" @@ -64,6 +72,7 @@ mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" + mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 3973026f..9093b29e 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -31,7 +31,7 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -if [ $1 = "chipyard-gemmini" ]; then +if [ $1 = "group-accels" ]; then export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH @@ -40,9 +40,7 @@ if [ $1 = "chipyard-gemmini" ]; then git submodule update --init --recursive gemmini-rocc-tests cd gemmini-rocc-tests ./build.sh -fi -if [ $1 = "chipyard-hwacha" ] || [ $1 = "chipyard-gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR LD_LIB_DIR=$REMOTE_ESP_DIR/lib run "mkdir -p $REMOTE_ESP_DIR" @@ -58,12 +56,19 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -C $REMOTE_SIM_DIR clean; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" -run "rm -rf $REMOTE_CHIPYARD_DIR/project" + make -C $REMOTE_SIM_DIR clean;" -# copy back the final build +read -a keys <<< ${grouping[$1]} +for key in "${keys[@]}" +do + run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ + make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" +done run "rm -rf $REMOTE_CHIPYARD_DIR/project" From 36ccb12560ef24eb492b93baf5c2da996badf1b8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 16 Sep 2020 10:29:03 -0700 Subject: [PATCH 04/10] Bump testchipip --- generators/chipyard/src/main/scala/Subsystem.scala | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 172be692..5dd6ac18 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -30,7 +30,7 @@ import testchipip.{DromajoHelper, CanHavePeripheryTLSerial, SerialTLKey} trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr if (this match { - case _: CanHavePeripheryTKSerial if p(SerialTLKey).nonEmpty => true + case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true case _: HasPeripheryDebug if p(ExportDebug).dmi => true case _ => false }) { diff --git a/generators/testchipip b/generators/testchipip index e845cb3f..57cac41f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit e845cb3f50bb141fec7e8291a40d0b46d5ef5c12 +Subproject commit 57cac41f71653ca2a04d936f36ee8c78ec9919fd From 269af01a70d6fe6411dcc6ba5ef7f5aed5fa4e1d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 16 Sep 2020 12:06:36 -0700 Subject: [PATCH 05/10] Bump testchipip --- .circleci/defaults.sh | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 2a744e89..6053b367 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -49,7 +49,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim declare -A mapping mapping["chipyard-rocket"]="" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" -mapping["chipyard-tlserial"]=" CONFIG=TLSerialRocketConfig" +mapping["chipyard-tlserial"]=" CONFIG=LBWIFMemoryRocketConfig" mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig" mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig" diff --git a/generators/testchipip b/generators/testchipip index 57cac41f..f2efec8e 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 57cac41f71653ca2a04d936f36ee8c78ec9919fd +Subproject commit f2efec8ee7bd6988b94a6fa3615ae7f864714004 From 687430898116d98ff625fa9258ae89473dd26135 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 16 Sep 2020 15:27:43 -0700 Subject: [PATCH 06/10] Address review comments --- .circleci/config.yml | 18 +++++++++--------- .circleci/do-rtl-build.sh | 4 ---- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 6ed04488..48ed4883 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -73,7 +73,7 @@ commands: tools-version: type: string default: "riscv-tools" - project-key: + group-key: type: string timeout: type: string @@ -85,11 +85,11 @@ commands: - setup-tools: tools-version: "<< parameters.tools-version >>" - run: - name: Building << parameters.project-key >> subproject using Verilator - command: .circleci/<< parameters.build-script >> << parameters.project-key >> + name: Building << parameters.group-key >> subproject using Verilator + command: .circleci/<< parameters.build-script >> << parameters.group-key >> no_output_timeout: << parameters.timeout >> - save_cache: - key: << parameters.project-key >>-{{ .Branch }}-{{ .Revision }} + key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" @@ -192,28 +192,28 @@ jobs: executor: main-env steps: - prepare-rtl: - project-key: "group-cores" + group-key: "group-cores" prepare-chipyard-peripherals: executor: main-env steps: - prepare-rtl: - project-key: "group-peripherals" + group-key: "group-peripherals" prepare-chipyard-accels: executor: main-env steps: - prepare-rtl: tools-version: "esp-tools" - project-key: "group-accels" + group-key: "group-accels" prepare-chipyard-tracegen: executor: main-env steps: - prepare-rtl: - project-key: "group-tracegen" + group-key: "group-tracegen" prepare-chipyard-other: executor: main-env steps: - prepare-rtl: - project-key: "group-other" + group-key: "group-other" chipyard-rocket-run-tests: executor: main-env diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 9093b29e..784dbc04 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -52,10 +52,6 @@ fi # enter the verilator directory and build the specific config on remote server run "export RISCV=\"$TOOLS_DIR\"; \ - export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ - export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ - export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ make -C $REMOTE_SIM_DIR clean;" read -a keys <<< ${grouping[$1]} From aa355c7c1abb3980f28ba167b8ebac89b9255fb2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 18 Sep 2020 10:41:59 -0700 Subject: [PATCH 07/10] Bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 2b52057e..7b2691c9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 2b52057e158fd91d44c6259aa08869622a88040a +Subproject commit 7b2691c935aef13fd9de0e8d95d99ad9bceaab2e From bbf941c865f660fbf15ddac2c4f579a55628191f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 18 Sep 2020 10:43:58 -0700 Subject: [PATCH 08/10] Bump Firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 7b2691c9..3dbe8aee 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7b2691c935aef13fd9de0e8d95d99ad9bceaab2e +Subproject commit 3dbe8aee3f917079e7319391bac5d23d2ba5e6de From 6c297e3179a7e32c00dd4a0edb8ed7729b6f2c05 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 22 Sep 2020 11:08:52 -0700 Subject: [PATCH 09/10] Fix smartelf2hex.sh creating files 64x the minimum size --- scripts/smartelf2hex.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/smartelf2hex.sh b/scripts/smartelf2hex.sh index 782977ff..e6fd1f7a 100755 --- a/scripts/smartelf2hex.sh +++ b/scripts/smartelf2hex.sh @@ -11,4 +11,6 @@ entry_dec=`bc <<< "ibase=16;$entry_hex"` length_hex=`echo "$segments" | grep LOAD | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '` length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc` power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l` -elf2hex 64 $power_2_length $binary $entry_dec +width=64 +depth=$((power_2_length / width)) +elf2hex $width $depth $binary $entry_dec From d5660c01f3ada775c671409e593826b56cd9f7bf Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 22 Sep 2020 12:58:34 -0700 Subject: [PATCH 10/10] Bump esp-isa-sim for loadmem-fix add TLS segments to smartelf2hex --- scripts/smartelf2hex.sh | 2 +- toolchains/esp-tools/riscv-isa-sim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/smartelf2hex.sh b/scripts/smartelf2hex.sh index e6fd1f7a..dd035690 100755 --- a/scripts/smartelf2hex.sh +++ b/scripts/smartelf2hex.sh @@ -8,7 +8,7 @@ binary=$1 segments=`readelf --segments --wide $binary` entry_hex=`echo -e "$segments" | grep "Entry point" | cut -f3 -d' ' | sed 's/0x//' | tr [:lower:] [:upper:]` entry_dec=`bc <<< "ibase=16;$entry_hex"` -length_hex=`echo "$segments" | grep LOAD | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '` +length_hex=`echo "$segments" | grep "LOAD\|TLS" | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '` length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc` power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l` width=64 diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index aa332c6a..fa94e84d 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit aa332c6a9a5ec77a9b97cdb4a1978ad394b17f1e +Subproject commit fa94e84d4ff3e23ba909a63376b294e444234752