From b7bc96b6d659fb2863a20137fa05528c0ea82f20 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 16 Jul 2019 21:36:36 -0700 Subject: [PATCH] rename missing vcs/verilator names | fix ci path --- .circleci/config.yml | 2 +- .circleci/do-rtl-build.sh | 2 +- .../Adding-An-Accelerator-Tutorial.rst | 2 +- docs/Getting-Started/Chipyard-Basics.rst | 8 ++--- docs/Getting-Started/Running-A-Simulation.rst | 8 ++--- docs/Simulation/Software-RTL-Simulators.rst | 4 +-- scripts/regression.sh | 31 ------------------- sims/verilator/Makefile | 2 +- 8 files changed, 14 insertions(+), 45 deletions(-) delete mode 100755 scripts/regression.sh diff --git a/.circleci/config.yml b/.circleci/config.yml index 4630446d..db4eb614 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -253,7 +253,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the blockdevrocketchip subproject using Verilator command: .circleci/do-rtl-build.sh blockdevrocketchip diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 2c7242cc..00dc7290 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -39,7 +39,7 @@ else copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR fi -# enter the verisim directory and build the specific config on remote server +# enter the verilator directory and build the specific config on remote server run "make -C $REMOTE_SIM_DIR clean" run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" ${mapping[$1]}" run "rm -rf $REMOTE_CHIPYARD_DIR/project" diff --git a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst index 4eefe9b8..4edbde1b 100644 --- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst +++ b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst @@ -227,7 +227,7 @@ Now with all of that done, we can go ahead and run our simulation. .. code-block:: shell - cd verisim + cd verilator make CONFIG=PWMConfig ./simulator-example-PWMConfig ../tests/pwm.riscv diff --git a/docs/Getting-Started/Chipyard-Basics.rst b/docs/Getting-Started/Chipyard-Basics.rst index 7b9f1bbe..c5aa5a62 100644 --- a/docs/Getting-Started/Chipyard-Basics.rst +++ b/docs/Getting-Started/Chipyard-Basics.rst @@ -81,14 +81,14 @@ Toolchains Sims ------------------------------------------- -**verisim (Verilator wrapper)** +**verilator (Verilator wrapper)** Verilator is an open source Verilog simulator. - The ``verisim`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). + The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). See :ref:`Verilator` for more information. -**vsim (VCS wrapper)** +**vcs (VCS wrapper)** VCS is a proprietary Verilog simulator. - Assuming the user has valid VCS licenses and installations, the ``vsim`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). + Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). See :ref:`VCS` for more information. **FireSim** diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index 0cc4a024..39128f30 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -15,9 +15,9 @@ The following instructions assume at least one of these simulators is installed. Verilator/VCS Flows ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Verilator is an open-source RTL simulator. -We run Verilator simulations from within the ``sims/verisim`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations. +We run Verilator simulations from within the ``sims/verilator`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations. On the other hand, VCS is a proprietary RTL simulator. -We run VCS simulations from within the ``sims/vsim`` directory. +We run VCS simulations from within the ``sims/vcs`` directory. Assuming VCS is already installed on the machine running simulations (and is found on our ``PATH``), then this guide is the same for both Verilator and VCS. First, we will start by entering the Verilator or VCS directory: @@ -25,12 +25,12 @@ First, we will start by entering the Verilator or VCS directory: .. code-block:: shell # Enter Verilator directory - cd sims/verisim + cd sims/verilator # OR # Enter VCS directory - cd sims/vsim + cd sims/vcs In order to construct the simulator with our custom design, we run the following command within the simulator directory: diff --git a/docs/Simulation/Software-RTL-Simulators.rst b/docs/Simulation/Software-RTL-Simulators.rst index 9df94d52..cef1b1f3 100644 --- a/docs/Simulation/Software-RTL-Simulators.rst +++ b/docs/Simulation/Software-RTL-Simulators.rst @@ -9,7 +9,7 @@ The Chipyard framework can download, build, and execute simulations using Verila To run a simulation using Verilator, perform the following steps: -To compile the example design, run ``make`` in the ``sims/verisim`` directory. +To compile the example design, run ``make`` in the ``sims/verilator`` directory. This will elaborate the ``DefaultRocketConfig`` in the example project. An executable called ``simulator-example-DefaultRocketConfig`` will be produced. @@ -47,7 +47,7 @@ To run a simulation using VCS, perform the following steps: Make sure that the VCS simulator is on your ``PATH``. -To compile the example design, run make in the ``sims/vsim`` directory. +To compile the example design, run make in the ``sims/vcs`` directory. This will elaborate the ``DefaultRocketConfig`` in the example project. An executable called ``simulator-example-DefaultRocketConfig`` will be produced. diff --git a/scripts/regression.sh b/scripts/regression.sh deleted file mode 100755 index 3175891c..00000000 --- a/scripts/regression.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/bash - -# NOTE: TEMPORARY UNTIL CI IS ONLINE - -# Run by just giving the test to run (run-bmark-tests | run-asm-tests) -# Runs in vsim and verisim - -set -ex -set -euo pipefail - -cd sims/vsim/ - -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 -make SUB_PROJECT=boom CONFIG=BoomConfig -make SUB_PROJECT=boom CONFIG=BoomConfig $1 -make SUB_PROJECT=example CONFIG=DefaultRocketConfig -make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 -make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig -make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 - -cd ../verisim/ - -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 -make SUB_PROJECT=boom CONFIG=BoomConfig -make SUB_PROJECT=boom CONFIG=BoomConfig $1 -make SUB_PROJECT=example CONFIG=DefaultRocketConfig -make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 -make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig -make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 3edbc953..c97f9844 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -92,7 +92,7 @@ $(sim_debug): $(model_mk_debug) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk ######################################################################################### -# create a verisim vpd rule +# create a verilator vpd rule ######################################################################################### $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd