From b7d9472b4ad6a6ba3ad85b3845de812e1be3cfe7 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 19 Aug 2020 22:10:18 -0700 Subject: [PATCH] Cleanup help commands --- common.mk | 22 +++++++++++++++------- sims/vcs/Makefile | 7 ------- sims/verilator/Makefile | 7 ------- variables.mk | 2 +- 4 files changed, 16 insertions(+), 22 deletions(-) diff --git a/common.mk b/common.mk index be787a9d..83b74287 100644 --- a/common.mk +++ b/common.mk @@ -13,11 +13,11 @@ endif # specify user-interface variables ######################################################################################### HELP_COMPILATION_VARIABLES += \ -" EXTRA_GENERATOR_REQS = requirements needed for the main generator" \ -" EXTRA_SIM_CXXFLAGS = CXXFLAGS for building simulators" \ -" EXTRA_SIM_LDFLAGS = LDFLAGS for building simulators" \ -" EXTRA_SIM_SOURCES = simulation sources needed for simulator" \ -" EXTRA_SIM_REQS = requirements to build the simulator" +" EXTRA_GENERATOR_REQS = additional make requirements needed for the main generator" \ +" EXTRA_SIM_CXXFLAGS = additional CXXFLAGS for building simulators" \ +" EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ +" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ +" EXTRA_SIM_REQS = additional make requirements to build the simulator" EXTRA_GENERATOR_REQS ?= EXTRA_SIM_CXXFLAGS ?= @@ -27,7 +27,7 @@ EXTRA_SIM_REQS ?= #---------------------------------------------------------------------------- HELP_SIMULATION_VARIABLES += \ -" EXTRA_SIM_FLAGS = runtime simulation flags (passed within +permissive)" +" EXTRA_SIM_FLAGS = additional runtime simulation flags (passed within +permissive)" EXTRA_SIM_FLAGS ?= @@ -36,7 +36,8 @@ HELP_COMMANDS += \ " run-binary = run [./$(shell basename $(sim))] and log instructions to file" \ " run-binary-fast = run [./$(shell basename $(sim))] and don't log instructions" \ " run-binary-debug = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \ -" verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" +" verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" \ +" run-tests = run all assembly and benchmark tests" ######################################################################################### # include additional subproject make fragments @@ -232,6 +233,13 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) +######################################################################################### +# print help text +######################################################################################### +.PHONY: help +help: + @for line in $(HELP_LINES); do echo "$$line"; done + ######################################################################################### # Implicit rule handling ######################################################################################### diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index efe0dc3c..ac792e63 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -72,10 +72,3 @@ clean-sim: clean-sim-debug: rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h - -######################################################################################### -# print help text -######################################################################################### -.PHONY: help -help: - @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index f71f9de5..9965001d 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -232,10 +232,3 @@ clean-sim: clean-sim-debug: rm -rf $(model_dir_debug) $(sim_debug) - -######################################################################################### -# print help text -######################################################################################### -.PHONY: help -help: - @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/variables.mk b/variables.mk index be022e12..7f3d1eee 100644 --- a/variables.mk +++ b/variables.mk @@ -17,7 +17,7 @@ HELP_PROJECT_VARIABLES = \ " TOP = top level module of the project (normally the module instantiated by the harness) [$(TOP)]" HELP_SIMULATION_VARIABLES = \ -" BINARY = riscv binary that the simulator will run" \ +" BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \ " VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" # include default simulation rules