From b8d3e4a66d6e8a984bc49cc0ca1d11f0d49a87ed Mon Sep 17 00:00:00 2001
From: David Biancolin <david.biancolin@gmail.com>
Date: Wed, 16 Sep 2020 16:30:25 -0700
Subject: [PATCH] Update Idealized PLL config

---
 generators/chipyard/src/main/scala/Clocks.scala          | 4 ++--
 generators/chipyard/src/main/scala/ConfigFragments.scala | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala
index afe04eaf..7c9ade21 100644
--- a/generators/chipyard/src/main/scala/Clocks.scala
+++ b/generators/chipyard/src/main/scala/Clocks.scala
@@ -179,7 +179,7 @@ object ClockingSchemeGenerators {
     implicit val p = chiptop.p
 
     // Requires existence of undriven asyncClockGroups in subsystem
-    val systemAsyncClockGroup = chiptop.lSystem match {
+    val systemAsyncClockGroup = chiptop.lazySystem match {
       case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) =>
         l.asyncClockGroupsNode
     }
@@ -204,7 +204,7 @@ object ClockingSchemeGenerators {
         o.reset := reset_wire
       }
 
-      chiptop.harnessFunctions += ((th: HasHarnessUtils) => {
+      chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {
         clock_io := th.harnessClock
         Nil })
     }
diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala
index 9fb3adb2..03ccdbca 100644
--- a/generators/chipyard/src/main/scala/ConfigFragments.scala
+++ b/generators/chipyard/src/main/scala/ConfigFragments.scala
@@ -193,5 +193,5 @@ class WithForcedTileFrequency(fMHz: Double) extends Config((site, here, up) => {
 })
 
 class WithIdealizedPLL extends Config((site, here, up) => {
-  case ChipyardClockKey => ClockDrivers.idealizedPLL
+  case ClockingSchemeKey => ClockingSchemeGenerators.idealizedPLL
 })