From b8e95e03052541f399f10a81d602aa5f0d2e2ba2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 12 May 2023 15:11:44 -0700 Subject: [PATCH] Rename implicit clock/reset to referenceclock/reset --- fpga/src/main/scala/arty/TestHarness.scala | 4 ++-- fpga/src/main/scala/arty100t/Harness.scala | 4 ++-- fpga/src/main/scala/vc707/TestHarness.scala | 8 ++++---- fpga/src/main/scala/vcu118/TestHarness.scala | 8 ++++---- .../src/main/scala/harness/HasHarnessInstantiators.scala | 8 ++++---- .../chipyard/src/main/scala/harness/TestHarness.scala | 4 ++-- generators/firechip/src/main/scala/FireSim.scala | 4 ++-- 7 files changed, 20 insertions(+), 20 deletions(-) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 4968b189..8bf6e751 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -21,8 +21,8 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell def success = {require(false, "Success not supported"); false.B } - def implicitClock = clock_32MHz - def implicitReset = hReset + def referenceClock = clock_32MHz + def referenceReset = hReset instantiateChipTops() } diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index 78035cda..21e910b5 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -76,8 +76,8 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset) - def implicitClock = dutClock.in.head._1.clock - def implicitReset = dutClock.in.head._1.reset + def referenceClock = dutClock.in.head._1.clock + def referenceReset = dutClock.in.head._1.reset def success = { require(false, "Unused"); false.B } ddrOverlay.mig.module.clock := harnessBinderClock diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 99232d6e..7b9d58af 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -114,12 +114,12 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul val hReset = Wire(Reset()) hReset := _outer.dutClock.in.head._1.reset - def implicitClock = _outer.dutClock.in.head._1.clock - def implicitReset = hReset + def referenceClock = _outer.dutClock.in.head._1.clock + def referenceReset = hReset def success = { require(false, "Unused"); false.B } - childClock := implicitClock - childReset := implicitReset + childClock := referenceClock + childReset := referenceReset instantiateChipTops() } diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index b2032596..96bba231 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -118,12 +118,12 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod val hReset = Wire(Reset()) hReset := _outer.dutClock.in.head._1.reset - def implicitClock = _outer.dutClock.in.head._1.clock - def implicitReset = hReset + def referenceClock = _outer.dutClock.in.head._1.clock + def referenceReset = hReset def success = { require(false, "Unused"); false.B } - childClock := implicitClock - childReset := implicitReset + childClock := referenceClock + childReset := referenceReset instantiateChipTops() } diff --git a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala index 05323fdd..af27e073 100644 --- a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala +++ b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala @@ -53,8 +53,8 @@ trait HasHarnessInstantiators { val harnessBinderReset = Wire(Reset()) // classes which inherit this trait should provide the below definitions - def implicitClock: Clock - def implicitReset: Reset + def referenceClock: Clock + def referenceReset: Reset def success: Bool // This can be accessed to get new clocks from the harness @@ -86,9 +86,9 @@ trait HasHarnessInstantiators { val harnessBinderClk = harnessClockInstantiator.requestClockMHz("harnessbinder_clock", getHarnessBinderClockFreqMHz) println(s"Harness binder clock is $harnessBinderClockFreq") harnessBinderClock := harnessBinderClk - harnessBinderReset := implicitReset + harnessBinderReset := ResetCatchAndSync(harnessBinderClk, referenceReset.asBool) - harnessClockInstantiator.instantiateHarnessClocks(implicitClock) + harnessClockInstantiator.instantiateHarnessClocks(referenceClock) lazyDuts } diff --git a/generators/chipyard/src/main/scala/harness/TestHarness.scala b/generators/chipyard/src/main/scala/harness/TestHarness.scala index c42cbf41..80f32c0a 100644 --- a/generators/chipyard/src/main/scala/harness/TestHarness.scala +++ b/generators/chipyard/src/main/scala/harness/TestHarness.scala @@ -24,8 +24,8 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessInst val success = WireInit(false.B) io.success := success - def implicitClock = clock - def implicitReset = reset + def referenceClock = clock + def referenceReset = reset instantiateChipTops() } diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index d43b9a59..6d43928d 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -72,8 +72,8 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta // In effect, the bridge counts the length of the reset in terms of this clock. resetBridge.io.clock := harnessBinderClock - def implicitClock = false.B.asClock // unused - def implicitReset = resetBridge.io.reset + def referenceClock = false.B.asClock // unused + def referenceReset = resetBridge.io.reset def success = { require(false, "success should not be used in Firesim"); false.B } instantiateChipTops()