From ba199879844ccb163203f39b0ead3ec1393157c5 Mon Sep 17 00:00:00 2001
From: David Biancolin <david.biancolin@gmail.com>
Date: Sun, 1 Dec 2019 22:27:12 -0800
Subject: [PATCH] [firechip] Label FASED instances with an associated memory
 region name

---
 .../src/main/scala/BridgeBinders.scala        | 26 ++++++++++++++++---
 .../firechip/src/main/scala/FireSim.scala     | 11 +++++++-
 2 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index ebd12d1b..4276890b 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -28,9 +28,14 @@ import boom.common.{BoomTile}
 import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
 import chipyard.HasChipyardTilesModuleImp
 
+object MainMemoryConsts {
+  val regionNamePrefix = "MainMemory"
+  def globalName(): String = s"${regionNamePrefix}_${NodeIdx()}"
+}
+
 class WithSerialBridge extends OverrideIOBinder({
   (c, r, s, target: CanHavePeripherySerialModuleImp) =>
-    target.serial.map(s => SerialBridge(target.clock, s)(target.p)).toSeq
+    target.serial.map(s => SerialBridge(target.clock, s, MainMemoryConsts.globalName)(target.p)).toSeq
 })
 
 class WithNICBridge extends OverrideIOBinder({
@@ -48,7 +53,19 @@ class WithBlockDeviceBridge extends OverrideIOBinder({
     target.bdev.map(b => BlockDevBridge(target.clock, b, target.reset.toBool)(target.p)).toSeq
 })
 
-class WithFASEDBridge extends OverrideIOBinder({
+// Assign a unique name to each target memory space, consisting of one or more
+// memory channels. In the multi-node case, serial widgets can then disambiguate
+// each memory region using this string instead of relying on the assumption
+// the target has a single memory channel.
+object MemoryRegionNames {
+  var idx = -1
+  def getName(): String = {
+    idx += 1
+    s"memory_${idx}"
+  }
+}
+
+class WithFASEDBridge extends OverrideIOBinder ({
   (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => {
     implicit val p = t.p
     (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
@@ -57,7 +74,10 @@ class WithFASEDBridge extends OverrideIOBinder({
                                        axi4Bundle.ar.bits.addr.getWidth,
                                        axi4Bundle.ar.bits.id.getWidth)
         FASEDBridge(t.clock, axi4Bundle, t.reset.toBool,
-          CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
+          CompleteConfig(p(firesim.configs.MemModelKey),
+                         nastiKey,
+                         Some(AXI4EdgeSummary(edge)),
+                         Some(MainMemoryConsts.globalName)))
       })
     }).toSeq
   }
diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala
index 221548c3..0cd8f410 100644
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -20,6 +20,14 @@ class WithNumNodes(n: Int) extends Config((pname, site, here) => {
   case NumNodes => n
 })
 
+// Hacky: Set before each node is generated. Ideally we'd give IO binders
+// accesses to the the Harness's parameters instance. We could then alter that.
+object NodeIdx {
+  private var idx = 0
+  def increment(): Unit = {idx = idx + 1 }
+  def apply(): Int = idx
+}
+
 class FireSim(implicit val p: Parameters) extends RawModule {
   val clockBridge = Module(new RationalClockBridge)
   val clock = clockBridge.io.clocks.head
@@ -32,8 +40,9 @@ class FireSim(implicit val p: Parameters) extends RawModule {
     // if that Mixin trait is present in the target's class instance
     //
     // Apply each partial function to each DUT instance
-    for ((target) <- targets) {
+    for (target <- targets) {
       p(IOBinders).values.map(fn => fn(clock, reset.asBool, false.B, target))
+      NodeIdx.increment()
     }
   }
 }