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more on customization of L1

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Howard Mao
2019-09-12 14:34:57 -07:00
parent 069bb55442
commit bc903b8407
1 changed files with 14 additions and 0 deletions
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docs/Customization/Memory-Hierarchy.rst
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@@ -22,6 +22,20 @@ configure 4 KiB direct-mapped caches for L1I and L1D.
new WithNMediumCores(1) ++ new WithNMediumCores(1) ++
new RocketConfig) new RocketConfig)
If you only want to change the size or associativity, there are configuration
mixins for those too.
.. code-block:: scala
import freechips.rocketchip.subsystem.{WithL1ICacheSets, WithL1DCacheSets, WithL1ICacheWays, WithL1DCacheWays}
class MyL1RocketConfig extends Config(
new WithL1ICacheSets(128) ++
new WithL1ICacheWays(2) ++
new WithL1DCacheSets(128) ++
new WithL1DCacheWays(2) ++
new RocketConfig)
You can also configure the L1 data cache as an data scratchpad instead. You can also configure the L1 data cache as an data scratchpad instead.
However, there are some limitations on this. If you are using a data scratchpad, However, there are some limitations on this. If you are using a data scratchpad,
you can only use a single core and you cannot give the design an external DRAM. you can only use a single core and you cannot give the design an external DRAM.