From bd0b3e8f1d81ddb8a6874b1eff8d21496f075daf Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 14 Oct 2022 10:58:03 -0700 Subject: [PATCH] Update paths | Allow sed overrides --- common.mk | 16 +++++++--------- sims/common-sim-flags.mk | 2 +- sims/verilator/Makefile | 2 +- vcs.mk | 2 +- 4 files changed, 10 insertions(+), 12 deletions(-) diff --git a/common.mk b/common.mk index 474bf922..518b9955 100644 --- a/common.mk +++ b/common.mk @@ -1,7 +1,5 @@ -######################################################################################### -# set default shell for make -######################################################################################### SHELL=/bin/bash +SED ?= sed ifndef RISCV $(error RISCV is unset. Did you source the Chipyard auto-generated env file (which activates the default conda environment)?) @@ -199,7 +197,7 @@ $(FIRTOOL_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) --disable-annotation-classless \ --disable-annotation-unknown \ --warn-on-unprocessed-annotations \ - --lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \ + --lowering-options=disallowPackedArrays,emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,explicitBitcast,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ --repl-seq-mem \ --repl-seq-mem-circuit=$(MODEL) \ --repl-seq-mem-file=$(FIRTOOL_SMEMS_CONF) \ @@ -207,7 +205,7 @@ $(FIRTOOL_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) --split-verilog \ -o $(OUT_DIR) \ $(SFC_FIRRTL_FILE) - sed -i 's/.*/& /' $(FIRTOOL_SMEMS_CONF) # need trailing space for SFC macrocompiler + $(SED) -i 's/.*/& /' $(FIRTOOL_SMEMS_CONF) # need trailing space for SFC macrocompiler # DOC include end: FirrtlCompiler $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) &: $(FIRTOOL_MODEL_MOD_HRCHY_JSON) $(FIRTOOL_FILELIST) $(FIRTOOL_BB_MODS_FILELIST) @@ -218,10 +216,10 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL --out-model-filelist $(MODEL_MODS_FILELIST) \ --in-all-filelist $(FIRTOOL_FILELIST) \ --target-dir $(OUT_DIR) - sed -e 's;^;$(OUT_DIR)/;' $(FIRTOOL_BB_MODS_FILELIST) > $(BB_MODS_FILELIST) - sed -i 's/\.\///' $(TOP_MODS_FILELIST) - sed -i 's/\.\///' $(MODEL_MODS_FILELIST) - sed -i 's/\.\///' $(BB_MODS_FILELIST) + $(SED) -e 's;^;$(OUT_DIR)/;' $(FIRTOOL_BB_MODS_FILELIST) > $(BB_MODS_FILELIST) + $(SED) -i 's/\.\///' $(TOP_MODS_FILELIST) + $(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST) + $(SED) -i 's/\.\///' $(BB_MODS_FILELIST) sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST) $(TOP_SMEMS_CONF) $(HARNESS_SMEMS_CONF) &: $(FIRTOOL_TOP_SMEMS_JSON) $(FIRTOOL_MODEL_SMEMS_JSON) $(FIRTOOL_SMEMS_CONF) diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 6cf3c761..cf974f92 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -9,7 +9,7 @@ SIM_CXXFLAGS = \ -std=c++17 \ -I$(RISCV)/include \ -I$(dramsim_dir) \ - -I$(build_dir) \ + -I$(OUT_DIR) \ $(EXTRA_SIM_CXXFLAGS) SIM_LDFLAGS = \ diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index cf5b7c88..5c15973a 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -143,7 +143,7 @@ CHIPYARD_VERILATOR_FLAGS := \ # options dependent on whether external IP (cva6/NVDLA) or just chipyard is used # NOTE: defer the evaluation of this until it is used! PLATFORM_OPTS = $(shell \ - if grep -qiP "module\s+(CVA6|NVDLA)" $(build_dir)/*.*v; \ + if grep -qiP "module\s+(CVA6|NVDLA)" $(OUT_DIR)/*.*v; \ then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \ else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi) diff --git a/vcs.mk b/vcs.mk index 2f8c3d0e..002fd09a 100644 --- a/vcs.mk +++ b/vcs.mk @@ -51,7 +51,7 @@ VCS_NONCC_OPTS = \ -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ -debug_pp \ - +incdir+$(build_dir) + +incdir+$(OUT_DIR) PREPROC_DEFINES = \ +define+VCS \