diff --git a/.github/actions/create-conda-env/action.yml b/.github/actions/create-conda-env/action.yml
index 1c302764..b9fd6066 100644
--- a/.github/actions/create-conda-env/action.yml
+++ b/.github/actions/create-conda-env/action.yml
@@ -11,15 +11,18 @@ runs:
echo "Creating a conda environment for each toolchain with the toolchain installed"
conda activate base
conda-lock install --conda $(which conda) -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools ./conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
- conda-lock install --conda $(which conda) -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools ./conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
conda deactivate
- echo "Add extra toolchain collateral to RISC-V install area"
+ echo "Add extra toolchain collateral + CIRCT to RISC-V install area"
+ git submodule update --init ./tools/install-circt
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
./scripts/build-toolchain-extra.sh riscv-tools -p $CONDA_PREFIX/riscv-tools
- conda deactivate
- conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools
- ./scripts/build-toolchain-extra.sh esp-tools -p $CONDA_PREFIX/esp-tools
+ ./tools/install-circt/bin/download-release-or-nightly-circt.sh \
+ -f circt-full-shared-linux-x64.tar.gz \
+ -i $CONDA_PREFIX \
+ -v version-file \
+ -x ./conda-reqs/circt.json \
+ -g ${{ github.token }}
conda deactivate
fi
shell: bash -leo pipefail {0}
diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh
index b15c571d..a4a95611 100755
--- a/.github/scripts/check-commit.sh
+++ b/.github/scripts/check-commit.sh
@@ -45,7 +45,7 @@ search () {
done
}
-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle")
+submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
dir="generators"
branches=("master" "main" "dev")
search
@@ -81,14 +81,20 @@ dir="toolchains"
branches=("master")
search
+submodules=("firesim")
+dir="sims"
+branches=("main")
+search
+
+
submodules=("coremark" "firemarshal" "nvdla-workload" "spec2017")
dir="software"
branches=("master" "dev")
search
-submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture")
+submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde")
dir="tools"
-branches=("master" "dev")
+branches=("master" "dev" "main")
search
submodules=("fpga-shells")
diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
index 88dca6c1..22532887 100755
--- a/.github/scripts/defaults.sh
+++ b/.github/scripts/defaults.sh
@@ -29,13 +29,13 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
# key value store to get the build groups
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered"
-grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric"
+grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-gpu"]="chipyard-vortex chipyard-coalescer coalescer"
grouping["group-tracegen"]="tracegen tracegen-boom"
-grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
-grouping["group-fpga"]="arty vcu118 vc707 arty100t"
+grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
+grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
# key value store to get the build strings
declare -A mapping
@@ -59,6 +59,7 @@ mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_F
mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
+mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig"
mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
@@ -68,6 +69,8 @@ mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig"
mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
+mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog"
+mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"
mapping["chipyard-vortex"]=" CONFIG=RadianceROMConfig"
mapping["chipyard-coalescer"]=" CONFIG=MemtraceCoreConfig"
@@ -82,7 +85,8 @@ mapping["rocketchip-tlsimple"]="SUB_PROJECT=rocketchip CONFIG=TLSimpleUnitTestCo
mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig"
mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig"
-mapping["arty"]="SUB_PROJECT=arty verilog"
-mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"
-mapping["vc707"]="SUB_PROJECT=vc707 verilog"
+mapping["arty35t"]="SUB_PROJECT=arty35t verilog"
mapping["arty100t"]="SUB_PROJECT=arty100t verilog"
+mapping["nexysvideo"]="SUB_PROJECT=nexysvideo verilog"
+mapping["vc707"]="SUB_PROJECT=vc707 verilog"
+mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"
diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
index 378dae0c..7c60f74a 100755
--- a/.github/scripts/run-tests.sh
+++ b/.github/scripts/run-tests.sh
@@ -118,6 +118,10 @@ case $1 in
make -C $LOCAL_CHIPYARD_DIR/tests
run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1 EXTRA_SIM_FLAGS="+cflush_addr=0x2010200"
;;
+ chipyard-symmetric)
+ make -C $LOCAL_CHIPYARD_DIR/tests
+ run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1
+ ;;
tracegen)
run_tracegen
;;
diff --git a/.github/workflows/chipyard-full-flow.yml b/.github/workflows/chipyard-full-flow.yml
index 9c6bf0bc..3d4a9866 100644
--- a/.github/workflows/chipyard-full-flow.yml
+++ b/.github/workflows/chipyard-full-flow.yml
@@ -65,7 +65,7 @@ jobs:
name: setup-repo
needs: [change-filters, cancel-prior-workflows]
if: needs.change-filters.outputs.needs-rtl == 'true'
- runs-on: jktqos
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -88,7 +88,7 @@ jobs:
run-cfg-finder:
name: run-cfg-finder
needs: [setup-repo]
- runs-on: jktqos
+ runs-on: as4
steps:
- name: Run config finder
run: |
@@ -101,7 +101,7 @@ jobs:
run-tutorial:
name: run-tutorial
needs: [setup-repo]
- runs-on: jktqos
+ runs-on: as4
steps:
- name: Run smoke test
run: |
@@ -124,7 +124,7 @@ jobs:
conda config --add channels litex-hub
# installs for example-sky130.yml
- conda create -y --prefix ./.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
+ conda create -y --prefix ./.conda-sky130 open_pdks.sky130a=1.0.457_0_g32e8f23
git clone https://github.com/rahulk29/sram22_sky130_macros.git
# installs for example-openroad.yml
@@ -170,7 +170,7 @@ jobs:
cleanup:
name: cleanup
needs: [run-tutorial]
- runs-on: jktqos
+ runs-on: as4
if: ${{ always() }}
steps:
- name: Delete repo copy and conda env
diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml
index 3e171fef..b524ae37 100644
--- a/.github/workflows/chipyard-run-tests.yml
+++ b/.github/workflows/chipyard-run-tests.yml
@@ -62,32 +62,11 @@ jobs:
- '**/.gitignore'
- '.github/ISSUE_TEMPLATE/**'
- create-conda-env-jktgz:
- name: create-conda-env-jktgz
+ create-conda-env-as4:
+ name: create-conda-env-as4
needs: [change-filters, cancel-prior-workflows]
if: needs.change-filters.outputs.needs-rtl == 'true'
- runs-on: jktgz
- steps:
- - name: Delete old checkout
- run: |
- ls -alh .
- rm -rf ${{ github.workspace }}/* || true
- rm -rf ${{ github.workspace }}/.* || true
- ls -alh .
- - name: Checkout
- uses: actions/checkout@v3
- - name: Git workaround
- uses: ./.github/actions/git-workaround
- - name: Cleanup conda
- uses: ./.github/actions/cleanup-conda
- - name: Create conda env
- uses: ./.github/actions/create-conda-env
-
- create-conda-env-jktqos:
- name: create-conda-env-jktqos
- needs: [change-filters, cancel-prior-workflows]
- if: needs.change-filters.outputs.needs-rtl == 'true'
- runs-on: jktqos
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -109,7 +88,7 @@ jobs:
# When adding new prep jobs, please add them to `needs` below
setup-complete:
name: setup-complete
- needs: [create-conda-env-jktgz, create-conda-env-jktqos]
+ needs: [create-conda-env-as4]
runs-on: ubuntu-latest
steps:
- name: Set up complete
@@ -121,7 +100,7 @@ jobs:
name: commit-on-master-check
needs: [setup-complete]
if: needs.change-filters.outputs.needs-rtl == 'true'
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -144,7 +123,7 @@ jobs:
name: tutorial-setup-check
needs: [setup-complete]
if: needs.change-filters.outputs.needs-rtl == 'true'
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -166,7 +145,7 @@ jobs:
documentation-check:
name: documentation-check
needs: [setup-complete]
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -192,7 +171,7 @@ jobs:
name: build-extra-tests
needs: [setup-complete]
if: needs.change-filters.outputs.needs-rtl == 'true'
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -224,7 +203,7 @@ jobs:
prepare-chipyard-cores:
name: prepare-chipyard-cores
needs: setup-complete
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -246,7 +225,7 @@ jobs:
prepare-chipyard-constellation:
name: prepare-chipyard-constellation
needs: setup-complete
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -268,7 +247,7 @@ jobs:
prepare-chipyard-peripherals:
name: prepare-chipyard-peripherals
needs: setup-complete
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -290,7 +269,7 @@ jobs:
prepare-chipyard-accels:
name: prepare-chipyard-accels
needs: setup-complete
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -312,7 +291,7 @@ jobs:
prepare-chipyard-tracegen:
name: prepare-chipyard-tracegen
needs: setup-complete
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -334,7 +313,7 @@ jobs:
prepare-chipyard-other:
name: prepare-chipyard-other
needs: setup-complete
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -356,7 +335,7 @@ jobs:
prepare-chipyard-fpga:
name: prepare-chipyard-fpga
needs: setup-complete
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -381,7 +360,7 @@ jobs:
chipyard-spike-gemmini-run-tests:
name: chipyard-spike-gemmini-run-tests
needs: prepare-chipyard-accels # technically doesn't depend on RTL but should be after the build.sh for Gemmini
- runs-on: jktqos
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -410,7 +389,7 @@ jobs:
chipyard-rocket-run-tests:
name: chipyard-rocket-run-tests
needs: prepare-chipyard-cores
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -433,7 +412,7 @@ jobs:
chipyard-prefetchers-run-tests:
name: chipyard-prefetchers-run-tests
needs: prepare-chipyard-cores
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -456,7 +435,7 @@ jobs:
chipyard-hetero-run-tests:
name: chipyard-hetero-run-tests
needs: prepare-chipyard-cores
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -479,7 +458,7 @@ jobs:
chipyard-boom-run-tests:
name: chipyard-boom-run-tests
needs: prepare-chipyard-cores
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -502,7 +481,7 @@ jobs:
chipyard-shuttle-run-tests:
name: chipyard-shuttle-run-tests
needs: prepare-chipyard-cores
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -525,7 +504,7 @@ jobs:
chipyard-cva6-run-tests:
name: chipyard-cva6-run-tests
needs: prepare-chipyard-cores
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -548,7 +527,7 @@ jobs:
chipyard-ibex-run-tests:
name: chipyard-ibex-run-tests
needs: prepare-chipyard-cores
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -571,7 +550,7 @@ jobs:
chipyard-sodor-run-tests:
name: chipyard-sodor-run-tests
needs: prepare-chipyard-cores
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -594,7 +573,7 @@ jobs:
chipyard-spike-run-tests:
name: chipyard-spike-run-tests
needs: prepare-chipyard-cores
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -617,7 +596,7 @@ jobs:
chipyard-dmirocket-run-tests:
name: chipyard-dmirocket-run-tests
needs: prepare-chipyard-peripherals
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -640,7 +619,7 @@ jobs:
chipyard-dmiboom-run-tests:
name: chipyard-dmiboom-run-tests
needs: prepare-chipyard-peripherals
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -663,7 +642,7 @@ jobs:
chipyard-spiflashwrite-run-tests:
name: chipyard-spiflashwrite-run-tests
needs: prepare-chipyard-peripherals
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -686,7 +665,7 @@ jobs:
chipyard-manyperipherals-run-tests:
name: chipyard-manyperipherals-run-tests
needs: prepare-chipyard-peripherals
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -709,7 +688,7 @@ jobs:
chipyard-tethered-run-tests:
name: chipyard-tethered-run-tests
needs: prepare-chipyard-peripherals
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -729,10 +708,33 @@ jobs:
group-key: "group-peripherals"
project-key: "chipyard-tethered"
+ chipyard-symmetric-run-tests:
+ name: chipyard-symmetric-run-tests
+ needs: prepare-chipyard-peripherals
+ runs-on: as4
+ steps:
+ - name: Delete old checkout
+ run: |
+ ls -alh .
+ rm -rf ${{ github.workspace }}/* || true
+ rm -rf ${{ github.workspace }}/.* || true
+ ls -alh .
+ - name: Checkout
+ uses: actions/checkout@v3
+ - name: Git workaround
+ uses: ./.github/actions/git-workaround
+ - name: Create conda env
+ uses: ./.github/actions/create-conda-env
+ - name: Run tests
+ uses: ./.github/actions/run-tests
+ with:
+ group-key: "group-peripherals"
+ project-key: "chipyard-symmetric"
+
chipyard-sha3-run-tests:
name: chipyard-sha3-run-tests
needs: prepare-chipyard-accels
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -755,7 +757,7 @@ jobs:
chipyard-gemmini-run-tests:
name: chipyard-gemmini-run-tests
needs: prepare-chipyard-accels
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -778,7 +780,7 @@ jobs:
chipyard-manymmioaccels-run-tests:
name: chipyard-manymmioaccels-run-tests
needs: prepare-chipyard-accels
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -801,7 +803,7 @@ jobs:
# chipyard-nvdla-run-tests:
# name: chipyard-nvdla-run-tests
# needs: prepare-chipyard-accels
- # runs-on: self-hosted
+ # runs-on: as4
# steps:
# - name: Delete old checkout
# run: |
@@ -824,7 +826,7 @@ jobs:
chipyard-mempress-run-tests:
name: chipyard-mempress-run-tests
needs: prepare-chipyard-accels
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -848,7 +850,7 @@ jobs:
tracegen-boom-run-tests:
name: tracegen-boom-run-tests
needs: prepare-chipyard-tracegen
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -871,7 +873,7 @@ jobs:
tracegen-run-tests:
name: tracegen-run-tests
needs: prepare-chipyard-tracegen
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -894,7 +896,7 @@ jobs:
icenet-run-tests:
name: icenet-run-tests
needs: prepare-chipyard-other
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -917,7 +919,7 @@ jobs:
testchipip-run-tests:
name: testchipip-run-tests
needs: prepare-chipyard-other
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -940,7 +942,7 @@ jobs:
rocketchip-run-tests:
name: rocketchip-run-tests
needs: prepare-chipyard-other
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -979,7 +981,7 @@ jobs:
constellation-run-tests:
name: constellation-run-tests
needs: prepare-chipyard-other
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -1002,7 +1004,7 @@ jobs:
chipyard-constellation-run-tests:
name: chipyard-constellation-run-tests
needs: prepare-chipyard-constellation
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -1026,7 +1028,7 @@ jobs:
firesim-run-tests:
name: firesim-run-tests
needs: setup-complete
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -1050,7 +1052,7 @@ jobs:
fireboom-run-tests:
name: fireboom-run-tests
needs: setup-complete
- runs-on: self-hosted
+ runs-on: as4
steps:
- name: Delete old checkout
run: |
@@ -1092,6 +1094,7 @@ jobs:
chipyard-spiflashwrite-run-tests,
chipyard-manyperipherals-run-tests,
chipyard-tethered-run-tests,
+ chipyard-symmetric-run-tests,
chipyard-sha3-run-tests,
chipyard-gemmini-run-tests,
chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
diff --git a/.github/workflows/update-circt.yml b/.github/workflows/update-circt.yml
new file mode 100644
index 00000000..2d52a155
--- /dev/null
+++ b/.github/workflows/update-circt.yml
@@ -0,0 +1,25 @@
+name: update-circt
+
+# run daily
+on:
+ schedule:
+ - cron: 0,15,30,45 * * * *
+ #- cron: 0 8 * * *
+
+defaults:
+ run:
+ shell: bash -leo pipefail {0}
+
+jobs:
+ update-circt:
+ name: update-circt
+ runs-on: ubuntu-latest
+ steps:
+ - name: Update CIRCT
+ uses: circt/update-circt@v1.0.0
+ with:
+ user: 'bartender'
+ email: 'firesimchipyard@gmail.com'
+ pr-reviewers: ''
+ pr-labels: 'changelog:changed'
+ circt-config: './conda-reqs/circt.json'
diff --git a/.gitmodules b/.gitmodules
index c3d70dc1..e155d953 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,9 +13,6 @@
[submodule "generators/boom"]
path = generators/boom
url = https://github.com/riscv-boom/riscv-boom.git
-[submodule "generators/sifive-blocks"]
- path = generators/sifive-blocks
- url = https://github.com/chipsalliance/rocket-chip-blocks.git
[submodule "generators/hwacha"]
path = generators/hwacha
url = https://github.com/ucb-bar/hwacha.git
@@ -25,9 +22,6 @@
[submodule "generators/icenet"]
path = generators/icenet
url = https://github.com/firesim/icenet.git
-[submodule "generators/block-inclusivecache-sifive"]
- path = generators/sifive-cache
- url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "tools/dsptools"]
path = tools/dsptools
url = https://github.com/ucb-bar/dsptools.git
@@ -64,6 +58,9 @@
[submodule "software/nvdla-workload"]
path = software/nvdla-workload
url = https://github.com/ucb-bar/nvdla-workload.git
+[submodule "software/baremetal-ide"]
+ path = software/baremetal-ide
+ url = https://github.com/ucb-bar/Baremetal-IDE.git
[submodule "generators/riscv-sodor"]
path = generators/riscv-sodor
url = https://github.com/ucb-bar/riscv-sodor.git
@@ -133,6 +130,24 @@
[submodule "generators/hardfloat"]
path = generators/hardfloat
url = https://github.com/ucb-bar/berkeley-hardfloat.git
+[submodule "generators/caliptra-aes-acc"]
+ path = generators/caliptra-aes-acc
+ url = https://github.com/ucb-bar/caliptra-aes-acc
+[submodule "generators/rocc-acc-utils"]
+ path = generators/rocc-acc-utils
+ url = https://github.com/ucb-bar/rocc-acc-utils
+[submodule "tools/install-circt"]
+ path = tools/install-circt
+ url = https://github.com/circt/install-circt/
+[submodule "toolchains/riscv-tools/riscv-spike-devices"]
+ path = toolchains/riscv-tools/riscv-spike-devices
+ url = https://github.com/ucb-bar/spike-devices.git
+[submodule "generators/rocket-chip-blocks"]
+ path = generators/rocket-chip-blocks
+ url = https://github.com/chipsalliance/rocket-chip-blocks.git
+[submodule "generators/rocket-chip-inclusive-cache"]
+ path = generators/rocket-chip-inclusive-cache
+ url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "generators/rocket-gpu"]
path = generators/rocket-gpu
url = git@github.com:hansungk/rocket-gpu.git
diff --git a/README.md b/README.md
index 0d68cf77..8bb2e3e3 100644
--- a/README.md
+++ b/README.md
@@ -85,7 +85,7 @@ These additional publications cover many of the internal components used in Chip
## Acknowledgements
-This work is supported by the NSF CCRI ENS Chipyard Award #201662.
+This work is supported by the NSF CCRI ENS Chipyard Award #2016662.
[hwacha]:https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.pdf
[hammer]:https://github.com/ucb-bar/hammer
diff --git a/build.sbt b/build.sbt
index cc8edee6..99fff46b 100644
--- a/build.sbt
+++ b/build.sbt
@@ -95,7 +95,7 @@ lazy val chiselSettings = Seq(
// -- Rocket Chip --
-lazy val hardfloat = freshProject("hardfloat", rocketChipDir / "hardfloat/hardfloat")
+lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
.settings(chiselSettings)
.dependsOn(midasTargetUtils)
.settings(commonSettings)
@@ -141,17 +141,17 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
lazy val testchipip = (project in file("generators/testchipip"))
- .dependsOn(rocketchip, sifive_blocks)
+ .dependsOn(rocketchip, rocketchip_blocks)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val chipyard = (project in file("generators/chipyard"))
- .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+ .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
radiance,
sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, rocket_dsp_utils,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
- constellation, mempress, barf, shuttle)
+ constellation, mempress, barf, shuttle, caliptra_aes)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(
libraryDependencies ++= Seq(
@@ -181,7 +181,7 @@ lazy val fft_generator = (project in file("generators/fft-generator"))
.settings(commonSettings)
lazy val tracegen = (project in file("generators/tracegen"))
- .dependsOn(testchipip, rocketchip, sifive_cache, boom)
+ .dependsOn(testchipip, rocketchip, rocketchip_inclusive_cache, boom)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
@@ -240,6 +240,16 @@ lazy val nvdla = (project in file("generators/nvdla"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
+lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc"))
+ .dependsOn(rocketchip, rocc_acc_utils, testchipip, midasTargetUtils)
+ .settings(libraryDependencies ++= rocketLibDeps.value)
+ .settings(commonSettings)
+
+lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils"))
+ .dependsOn(rocketchip)
+ .settings(libraryDependencies ++= rocketLibDeps.value)
+ .settings(commonSettings)
+
lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "iocell")
.settings(chiselSettings)
.settings(commonSettings)
@@ -275,12 +285,12 @@ lazy val rocket_dsp_utils = freshProject("rocket-dsp-utils", file("./tools/rocke
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
-lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
+lazy val rocketchip_blocks = (project in file("generators/rocket-chip-blocks"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
-lazy val sifive_cache = (project in file("generators/sifive-cache"))
+lazy val rocketchip_inclusive_cache = (project in file("generators/rocket-chip-inclusive-cache"))
.settings(
commonSettings,
Compile / scalaSource := baseDirectory.value / "design/craft")
@@ -300,7 +310,7 @@ lazy val firechip = (project in file("generators/firechip"))
Test / testOptions += Tests.Argument("-oF")
)
lazy val fpga_shells = (project in file("./fpga/fpga-shells"))
- .dependsOn(rocketchip, sifive_blocks)
+ .dependsOn(rocketchip, rocketchip_blocks)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
diff --git a/common.mk b/common.mk
index c8c29b1f..3763584f 100644
--- a/common.mk
+++ b/common.mk
@@ -28,7 +28,6 @@ EXTRA_SIM_CXXFLAGS ?=
EXTRA_SIM_LDFLAGS ?=
EXTRA_SIM_SOURCES ?=
EXTRA_SIM_REQS ?=
-ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_YOSYS_FLOW)
ifneq ($(ASPECTS), )
comma = ,
@@ -58,7 +57,8 @@ HELP_COMMANDS += \
" firrtl = generate intermediate firrtl files from chisel elaboration" \
" run-tests = run all assembly and benchmark tests" \
" launch-sbt = start sbt terminal" \
-" find-config-fragments = list all config. fragments"
+" find-config-fragments = list all config. fragments" \
+" check-submodule-status = check that all submodules in generators/ have been initialized"
#########################################################################################
# include additional subproject make fragments
@@ -84,6 +84,8 @@ endif
# Returns a list of files in directories $1 with *any* of the file extensions in $2
lookup_srcs_by_multiple_type = $(foreach type,$(2),$(call lookup_srcs,$(1),$(type)))
+CHECK_SUBMODULES_COMMAND = echo "Checking all submodules in generators/ are initialized. Uninitialized submodules will be displayed" ; ! git submodule status $(base_dir)/generators | grep ^-
+
SCALA_EXT = scala
VLOG_EXT = sv v
CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src)
@@ -119,12 +121,13 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
#########################################################################################
# compile scala jars
#########################################################################################
-$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
+$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
+ $(CHECK_SUBMODULES_COMMAND)
mkdir -p $(dir $@)
$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
# order only dependency between sbt runs needed to avoid concurrent sbt runs
-$(TAPEOUT_CLASSPATH_TARGETS) &: $(BARSTOOLS_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(CHIPYARD_CLASSPATH_TARGETS)
+$(TAPEOUT_CLASSPATH_TARGETS) &: $(BARSTOOLS_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(BARSTOOLS_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS)
mkdir -p $(dir $@)
$(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH))
@@ -227,7 +230,7 @@ $(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(SFC_LEVEL)
touch $@
$(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX)
-$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) $(CHIPYARD_VLOG_SOURCES) $(BARSTOOLS_VLOG_SOURCES)
+$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS)
rm -rf $(GEN_COLLATERAL_DIR)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\
--no-dedup \
@@ -246,9 +249,7 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F
@if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json && rm $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi
firtool \
--format=fir \
- --dedup \
--export-module-hierarchy \
- --emit-metadata \
--verify-each=true \
--warn-on-unprocessed-annotations \
--disable-annotation-classless \
@@ -257,13 +258,13 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F
--lowering-options=$(shell cat $(MFC_LOWERING_OPTIONS)) \
--repl-seq-mem \
--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
- --repl-seq-mem-circuit=$(MODEL) \
--annotation-file=$(SFC_ANNO_FILE) \
--split-verilog \
-o $(GEN_COLLATERAL_DIR) \
$(SFC_FIRRTL_FILE)
-mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) 2> /dev/null
$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
+ touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it
# DOC include end: FirrtlCompiler
$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_TOP_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST)
@@ -454,6 +455,14 @@ find-config-fragments:
help:
@for line in $(HELP_LINES); do echo "$$line"; done
+#########################################################################################
+# Check submodule status
+#########################################################################################
+
+.PHONY: check-submodule-status
+check-submodule-status:
+ $(CHECK_SUBMODULES_COMMAND)
+
#########################################################################################
# Implicit rule handling
#########################################################################################
diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml
index 81a3ea67..ec49a0a4 100644
--- a/conda-reqs/chipyard.yaml
+++ b/conda-reqs/chipyard.yaml
@@ -23,13 +23,13 @@ dependencies:
# bundle FireSim driver with deps into installer shell-script
- constructor
- - gcc<13
- - gxx<13
+ - gcc<12
+ - gxx<12
- sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version
- conda-gcc-specs
- binutils
- - firtool==1.30.0 # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock
+ # firtool handled outside of conda
# misc
- autoconf
@@ -88,7 +88,7 @@ dependencies:
- graphviz
- expect
- dtc
- - verilator==5.008
+ - verilator==5.020
- screen
- elfutils
- libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock
@@ -102,7 +102,7 @@ dependencies:
- sty
- open_pdks.sky130a
- pip:
- - hammer-vlsi[asap7]==1.1.2
+ - hammer-vlsi[asap7]==1.2.0
# doc requirements
- sphinx
diff --git a/conda-reqs/circt.json b/conda-reqs/circt.json
new file mode 100644
index 00000000..42d4fa09
--- /dev/null
+++ b/conda-reqs/circt.json
@@ -0,0 +1,3 @@
+{
+ "version": "firtool-1.60.0"
+}
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
index 2c3ad90e..f63afc45 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
@@ -9,7 +9,7 @@
# To update a single package to the latest version compatible with the version constraints in the source:
# conda-lock lock --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml --update PACKAGE
# To re-solve the entire environment, e.g. after changing a version constraint in the source file:
-# conda-lock -f /scratch/abejgonza/cy/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy/conda-reqs/esp-tools.yaml -f /scratch/abejgonza/firesim/target-design/chipyard/conda-reqs/chipyard.yaml -f /scratch/abejgonza/firesim/target-design/chipyard/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml
+# conda-lock -f /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/chipyard.yaml -f /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml
metadata:
channels:
- url: ucb-bar
@@ -21,14 +21,12 @@ metadata:
- url: nodefaults
used_env_vars: []
content_hash:
- linux-64: f800845ae6c2481c1c2508f993d739a035bb8e0338f57b72b74ba660f677f51e
+ linux-64: de1e2d263317a6a0c7c45acb734d166b9975ff1a94cd138e3427bb7b7bdd8db4
platforms:
- linux-64
sources:
- - /scratch/abejgonza/cy/conda-reqs/chipyard.yaml
- - /scratch/abejgonza/cy/conda-reqs/esp-tools.yaml
- - /scratch/abejgonza/firesim/target-design/chipyard/conda-reqs/chipyard.yaml
- - /scratch/abejgonza/firesim/target-design/chipyard/conda-reqs/esp-tools.yaml
+ - /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/chipyard.yaml
+ - /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/esp-tools.yaml
package:
- category: main
dependencies: {}
@@ -66,25 +64,25 @@ package:
- category: main
dependencies: {}
hash:
- md5: a73ecd2988327ad4c8f2c331482917f2
- sha256: 525b7b6b5135b952ec1808de84e5eca57c7c7ff144e29ef3e96ae4040ff432c1
+ md5: 01ffc8d36f9eba0ce0b3c1955fa780ee
+ sha256: fb4b9f4b7d885002db0b93e22f44b5b03791ef3d4efdc9d0662185a0faafd6b6
manager: conda
name: ca-certificates
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2023.7.22-hbcca054_0.conda
- version: 2023.7.22
+ url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2023.11.17-hbcca054_0.conda
+ version: 2023.11.17
- category: main
dependencies: {}
hash:
- md5: 8d22677b00e9ea665f757c70a98d2c6f
- sha256: 327b40fc91521ad7ba7cc979e9ae40fafec145536b23c8f87a73cbb403eee1d8
+ md5: 9936f9d4393c27069e6ee70338f955a5
+ sha256: 5098310ea9ec4dae611a658c1ea26436001b2d2a4ed3c8e9468881337e02682f
manager: conda
name: conda-standalone
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/conda-standalone-23.7.2-ha770c72_0.conda
- version: 23.7.2
+ url: https://conda.anaconda.org/conda-forge/linux-64/conda-standalone-23.10.0-ha770c72_0.conda
+ version: 23.10.0
- category: main
dependencies: {}
hash:
@@ -121,13 +119,13 @@ package:
- category: main
dependencies: {}
hash:
- md5: 19410c3df09dfb12d1206132a1d357c5
- sha256: 470d5db54102bd51dbb0c5990324a2f4a0bc976faa493b22193338adb9882e2e
+ md5: 6185f640c43843e5ad6fd1c5372c3f80
+ sha256: 056c85b482d58faab5fd4670b6c1f5df0986314cca3bc831d458b22e4ef2c792
manager: conda
name: font-ttf-ubuntu
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/font-ttf-ubuntu-0.83-hab24e00_0.tar.bz2
+ url: https://conda.anaconda.org/conda-forge/noarch/font-ttf-ubuntu-0.83-h77eed37_1.conda
version: '0.83'
- category: main
dependencies: {}
@@ -143,80 +141,69 @@ package:
- category: main
dependencies: {}
hash:
- md5: b9ae31bc2e565684ebaf82d4bd954d55
- sha256: 257495088b78d4344c7ea21145581ed6da1c5bf8320f49b659ce2ed2d6265f76
+ md5: 2390dcf3fd78c2c426f1c5b6664fa4b7
+ sha256: 12904b795e5cb877ce6a7bb30feba9bfbe1dd38bd5f520e6af8d89a51bb6b6a6
manager: conda
name: libgcc-devel_linux-64
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/libgcc-devel_linux-64-12.3.0-h8bca6fd_0.conda
- version: 12.3.0
+ url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-11.4.0-h922705a_103.conda
+ version: 11.4.0
- category: main
dependencies: {}
hash:
- md5: afb656a334c409dd9805508af1c89c7a
- sha256: a06235f4c4b85b463d9b8a73c9e10c1b5b4105f8a0ea8ac1f2f5f64edac3dfe7
- manager: conda
- name: libgfortran5
- optional: false
- platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/libgfortran5-13.1.0-h15d22d2_0.conda
- version: 13.1.0
-- category: main
- dependencies: {}
- hash:
- md5: 7c80158949230e6d837186b20b2fcf13
- sha256: b311dad92ffafd29668fca6330dc707f4d7f154a4fa4c3859832897416de39ec
+ md5: be10a739476d68c464101836773463f1
+ sha256: 4957848888d7a8cdc77c605357e759f0c9b08c18510f08a205f567666602ca2b
manager: conda
name: libstdcxx-devel_linux-64
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-devel_linux-64-12.3.0-h8bca6fd_0.conda
- version: 12.3.0
+ url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-11.4.0-h922705a_103.conda
+ version: 11.4.0
- category: main
dependencies: {}
hash:
- md5: 067bcc23164642f4c226da631f2a2e1d
- sha256: 6f9eb2d7a96687938c0001166a3b308460a8eb02b10e9d0dd9e251f0219ea05c
+ md5: 937eaed008f6bf2191c5fe76f87755e9
+ sha256: 6c6c49efedcc5709a66f19fb6b26b69c6a5245310fd1d9a901fd5e38aaf7f882
manager: conda
name: libstdcxx-ng
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-ng-13.1.0-hfd8a6a1_0.conda
- version: 13.1.0
+ url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-ng-13.2.0-h7e041cc_3.conda
+ version: 13.2.0
- category: main
dependencies: {}
hash:
- md5: 9da14a0b14cf61245d1a026b2f281405
- sha256: 423a10bbf512b1530c98c01c414ef97d551d0b0920d393ecc164dde17ce475f7
+ md5: ca8ce27415e2e304ec35b3de2af12364
+ sha256: b6f56d6c0a95dbd27bdcd5c666781c58c037850cebbaf62536a4fdf2bdcf2a2e
manager: conda
name: open_pdks.sky130a
optional: false
platform: linux-64
- url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.440_0_g43e733e-20230724_080446.tar.bz2
- version: 1.0.440_0_g43e733e
+ url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.460_0_gfdb1863-20231104_052339.tar.bz2
+ version: 1.0.460_0_gfdb1863
- category: main
dependencies: {}
hash:
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manager: conda
name: python_abi
optional: false
platform: linux-64
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+ url: https://conda.anaconda.org/conda-forge/linux-64/python_abi-3.9-4_cp39.conda
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manager: conda
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optional: false
platform: linux-64
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- version: 2023c
+ url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023d-h0c530f3_0.conda
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platform: linux-64
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- version: 13.1.0
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url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.9-hd590300_0.conda
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platform: linux-64
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url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.3.1-hd590300_0.conda
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url: https://conda.anaconda.org/conda-forge/linux-64/yaml-0.2.5-h7f98852_2.tar.bz2
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platform: linux-64
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platform: linux-64
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platform: linux-64
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url: https://conda.anaconda.org/conda-forge/linux-64/libedit-3.1.20191231-he28a2e2_2.tar.bz2
version: 3.1.20191231
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libstdcxx-ng: '>=12'
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platform: linux-64
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- category: main
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platform: linux-64
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platform: linux-64
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platform: linux-64
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libgcc-ng: '>=12'
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platform: linux-64
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name: perl
optional: false
platform: linux-64
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platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.2-h8228510_1.conda
version: '8.2'
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- category: main
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url: https://conda.anaconda.org/conda-forge/linux-64/autoconf-2.71-pl5321h2b4cb7a_1.conda
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- category: main
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- libbrotlienc: 1.1.0 hd590300_0
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url: https://conda.anaconda.org/conda-forge/linux-64/libllvm16-16.0.3-hbf9e925_1.conda
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url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-haa2dc70_1.conda
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+ url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml.clib-0.2.7-py39hd1e30aa_2.conda
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frozenlist: '>=1.1.1'
libgcc-ng: '>=12'
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- version: 3.8.5
+ url: https://conda.anaconda.org/conda-forge/linux-64/aiohttp-3.9.1-py39hd1e30aa_0.conda
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+ url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.34.11-pyhd8ed1ab_0.conda
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url: https://conda.anaconda.org/conda-forge/noarch/conda-package-streaming-0.9.0-pyhd8ed1ab_0.conda
version: 0.9.0
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+ url: https://conda.anaconda.org/conda-forge/linux-64/contourpy-1.2.0-py39h7633fee_0.conda
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+ click: '>=5.1'
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+ requests: '>=2'
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+ version: 1.4.3
- category: main
dependencies:
flask: '>=0.9'
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ukkonen: ''
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name: identify
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.27-pyhd8ed1ab_0.conda
- version: 2.5.27
+ url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.33-pyhd8ed1ab_0.conda
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- category: main
dependencies:
importlib_metadata: ''
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+ python: '>=3.7'
hash:
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name: jsonpickle
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platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/jsonpickle-2.2.0-pyhd8ed1ab_0.tar.bz2
- version: 2.2.0
+ url: https://conda.anaconda.org/conda-forge/noarch/jsonpickle-3.0.2-pyhd8ed1ab_1.conda
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+ name: jsonschema
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- url: https://conda.anaconda.org/conda-forge/noarch/jsonschema-spec-0.1.4-pyhd8ed1ab_0.conda
- version: 0.1.4
+ url: https://conda.anaconda.org/conda-forge/noarch/jsonschema-4.20.0-pyhd8ed1ab_0.conda
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+ url: https://conda.anaconda.org/conda-forge/noarch/jsonschema-path-0.3.2-pyhd8ed1ab_0.conda
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- category: main
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elfutils: '>=0.187,<0.188.0a0'
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- python-dateutil: '>=2.7'
- python_abi: 3.9.* *_cp39
- tk: '>=8.6.12,<8.7.0a0'
+ cryptography: <44,>=0.6
+ pyjwt: <3,>=1.0.0
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+ name: msal
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platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/matplotlib-base-3.7.1-py39he190548_0.conda
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- url: https://conda.anaconda.org/conda-forge/noarch/openapi-schema-validator-0.4.4-pyhd8ed1ab_0.conda
- version: 0.4.4
+ url: https://conda.anaconda.org/conda-forge/noarch/msal-1.26.0-pyhd8ed1ab_0.conda
+ version: 1.26.0
- category: main
dependencies:
alsa-lib: '>=1.2.9,<1.2.10.0a0'
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platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/openjdk-20.0.0-h8e330f5_0.conda
version: 20.0.0
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+ libstdcxx-ng: '>=12'
+ numpy: '>=1.22.4,<2.0a0'
+ python: '>=3.9,<3.10.0a0'
+ python-dateutil: '>=2.8.1'
+ python-tzdata: '>=2022a'
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+ pytz: '>=2020.1'
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+ platform: linux-64
+ url: https://conda.anaconda.org/conda-forge/linux-64/pandas-2.1.4-py39hddac248_0.conda
+ version: 2.1.4
- category: main
dependencies:
cairo: '>=1.16.0,<2.0a0'
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platform: linux-64
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- version: 3.3.1
+ url: https://conda.anaconda.org/conda-forge/noarch/paramiko-3.4.0-pyhd8ed1ab_0.conda
+ version: 3.4.0
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+ platform: linux-64
+ url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.5.3-pyhd8ed1ab_0.conda
+ version: 2.5.3
+- category: main
+ dependencies:
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name: pyopenssl
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platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-23.2.0-pyhd8ed1ab_1.conda
- version: 23.2.0
+ url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-23.1.1-pyhd8ed1ab_0.conda
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- category: main
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cryptography: ''
@@ -4764,6 +5105,36 @@ package:
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url: https://conda.anaconda.org/conda-forge/noarch/python-jose-3.3.0-pyh6c4a22f_1.tar.bz2
version: 3.3.0
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+ platform: linux-64
+ url: https://conda.anaconda.org/conda-forge/noarch/responses-0.24.1-pyhd8ed1ab_0.conda
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platform: linux-64
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+ url: https://conda.anaconda.org/conda-forge/linux-64/secretstorage-3.3.3-py39hf3d152e_2.conda
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dependencies:
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+ name: awscli
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platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.24.4-pyhd8ed1ab_0.conda
- version: 20.24.4
+ url: https://conda.anaconda.org/conda-forge/linux-64/awscli-2.15.6-py39hf3d152e_0.conda
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cryptography: '>=2.5'
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- msal_extensions: '>=0.3.0,<2.0.0'
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python: '>=3.7'
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name: azure-identity
optional: false
platform: linux-64
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+ url: https://conda.anaconda.org/conda-forge/noarch/azure-identity-1.15.0-pyhd8ed1ab_0.conda
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python: ''
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name: boto3-stubs
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.28.41-pyhd8ed1ab_0.conda
- version: 1.28.41
+ url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.34.11-pyhd8ed1ab_0.conda
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+- category: main
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+ boltons: '>=23.0.0'
+ conda-package-handling: '>=2.2.0'
+ jsonpatch: '>=1.32'
+ packaging: '>=23.0'
+ pluggy: '>=1.0.0'
+ pycosat: '>=0.6.3'
+ pyopenssl: '>=16.2.0'
+ python: '>=3.9,<3.10.0a0'
+ python_abi: 3.9.* *_cp39
+ requests: '>=2.27.0,<3'
+ ruamel.yaml: '>=0.11.14,<0.18'
+ setuptools: '>=60.0.0'
+ tqdm: '>=4'
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+ manager: conda
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+ url: https://conda.anaconda.org/conda-forge/linux-64/conda-23.9.0-py39hf3d152e_2.conda
+ version: 23.9.0
- category: main
dependencies:
cachecontrol-with-filecache: '>=0.12.9'
@@ -5370,32 +5527,79 @@ package:
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- category: main
dependencies:
- boto3: ''
- python: '>=3.6'
- typing-extensions: ''
+ cairo: '>=1.16.0,<2.0a0'
+ expat: ''
+ fontconfig: '>=2.14.2,<3.0a0'
+ fonts-conda-ecosystem: ''
+ freetype: '>=2.12.1,<3.0a0'
+ gdk-pixbuf: '>=2.42.10,<3.0a0'
+ gtk2: ''
+ gts: '>=0.7.6,<0.8.0a0'
+ libexpat: '>=2.5.0,<3.0a0'
+ libgcc-ng: '>=12'
+ libgd: '>=2.3.3,<2.4.0a0'
+ libglib: '>=2.76.2,<3.0a0'
+ librsvg: '>=2.56.0,<3.0a0'
+ libstdcxx-ng: '>=12'
+ libtool: ''
+ libwebp-base: '>=1.3.0,<2.0a0'
+ libzlib: '>=1.2.13,<1.3.0a0'
+ pango: '>=1.50.14,<2.0a0'
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manager: conda
- name: mypy-boto3-s3
+ name: graphviz
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.28.36-pyhd8ed1ab_0.conda
- version: 1.28.36
+ url: https://conda.anaconda.org/conda-forge/linux-64/graphviz-8.0.5-h28d9a01_0.conda
+ version: 8.0.5
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+ manager: conda
+ name: mypy-boto3-s3
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+ platform: linux-64
+ url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.34.0-pyhd8ed1ab_0.conda
+ version: 1.34.0
+- category: main
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+ python: '>=3.6'
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optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.28.41-pyhd8ed1ab_0.conda
- version: 1.28.41
+ url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.34.4-pyhd8ed1ab_0.conda
+ version: 1.34.4
+- category: main
+ dependencies:
+ importlib_resources: '>=5.8,<7.0'
+ jsonschema: '>=4.18.0,<5.0.0'
+ jsonschema-path: '>=0.3.1,<0.4.0'
+ lazy-object-proxy: '>=1.7.1,<2.0.0'
+ openapi-schema-validator: '>=0.6.0,<0.7.0'
+ python: '>=3.8.0'
+ hash:
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+ sha256: b3aff38febb575647f1b5ad246dc4a9f221e3f712027a71be6e2554c3fe44220
+ manager: conda
+ name: openapi-spec-validator
+ optional: false
+ platform: linux-64
+ url: https://conda.anaconda.org/conda-forge/noarch/openapi-spec-validator-0.7.1-pyhd8ed1ab_0.conda
+ version: 0.7.1
- category: main
dependencies:
boto3: ''
@@ -5412,26 +5616,72 @@ package:
version: 0.4.2
- category: main
dependencies:
- aws-sam-translator: '>=1.73.0'
+ aws-sam-translator: '>=1.82.0'
jschema-to-python: '>=1.2.3,<1.3.dev0'
jsonpatch: ''
- jsonschema: '>=3.0,<4.18'
+ jsonschema: '>=3.0,<5'
junit-xml: '>=1.9,<2.dev0'
networkx: '>=2.4,<4'
python: '>=3.7,<4.0'
pyyaml: '>5.4'
- regex: ''
+ regex: '>=2021.7.1'
sarif-om: '>=1.0.4,<1.1.dev0'
sympy: '>=1.0.0'
hash:
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+ sha256: deed7d4700694a25d440816d13de89468fe92dfc87ba506f3fee72b5d1131c75
manager: conda
name: cfn-lint
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.79.9-pyhd8ed1ab_0.conda
- version: 0.79.9
+ url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.83.6-pyhd8ed1ab_0.conda
+ version: 0.83.6
+- category: main
+ dependencies:
+ colorama: ''
+ conda: ''
+ networkx: ''
+ python: '>=3.6'
+ hash:
+ md5: 184216409957e082712d750862782903
+ sha256: 54e9cf114ca4eaeda91b5bb11a09d4391ba4be8a4fb2911259fc7dc2ec636054
+ manager: conda
+ name: conda-tree
+ optional: false
+ platform: linux-64
+ url: https://conda.anaconda.org/conda-forge/noarch/conda-tree-1.1.0-pyhd8ed1ab_2.conda
+ version: 1.1.0
+- category: main
+ dependencies:
+ __unix: ''
+ conda: '>=4.6'
+ conda-standalone: ''
+ jinja2: ''
+ pillow: '>=3.1'
+ python: '>=3.7'
+ ruamel.yaml: '>=0.11.14,<0.18'
+ hash:
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+ sha256: a4304eff880a3150e027f8af8d158cc9bf6e6c8444d2affda4e2b17125f44a85
+ manager: conda
+ name: constructor
+ optional: false
+ platform: linux-64
+ url: https://conda.anaconda.org/conda-forge/noarch/constructor-3.5.0-pyhe4f9e05_0.conda
+ version: 3.5.0
+- category: main
+ dependencies:
+ graphviz: '>=2.46.1'
+ python: '>=3'
+ hash:
+ md5: 196447bc6fd769c3eb2d51de1aa866a5
+ sha256: 55e25bf761438b6b52e67ed06d3e5575445177a58636e873a9899aa7fd9c8585
+ manager: conda
+ name: python-graphviz
+ optional: false
+ platform: linux-64
+ url: https://conda.anaconda.org/conda-forge/noarch/python-graphviz-0.20.1-pyh22cad53_0.tar.bz2
+ version: 0.20.1
- category: main
dependencies:
aws-xray-sdk: '!=0.96,>=0.93'
@@ -5461,14 +5711,14 @@ package:
werkzeug: '>=0.5,!=2.2.0,!=2.2.1'
xmltodict: ''
hash:
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- sha256: d5128b843ac0f338f955bb1a93c3565be87b6a5c241300ee2a34fcd4509f7390
+ md5: 9447c344fde58f458a55b05729ae74aa
+ sha256: f0586fd89bcc4e7df9cd12e66627473bed9b4bc33814b01f48e6059628af2f6b
manager: conda
name: moto
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/moto-4.2.2-pyhd8ed1ab_0.conda
- version: 4.2.2
+ url: https://conda.anaconda.org/conda-forge/noarch/moto-4.2.12-pyhd8ed1ab_0.conda
+ version: 4.2.12
- category: main
dependencies:
livereload: '>=2.3.0'
@@ -5537,19 +5787,19 @@ package:
version: '4.1'
- category: main
dependencies:
- docutils: <0.19
- python: '>=2.7,!=3.0.*,!=3.1.*,!=3.2.*,!=3.3.*,!=3.4.*,!=3.5.*'
- sphinx: '>=1.6,<8'
+ docutils: <0.21
+ python: '>=3.6'
+ sphinx: '>=5,<8'
sphinxcontrib-jquery: '>=4,<5'
hash:
- md5: a615c369167e508293d8409973b34863
- sha256: 1288aac6167e320b576d89855262f05b1903e446c3dfc92cc67b12b39fb62502
+ md5: baf6d9a33df1a789ca55e3b404c7ea28
+ sha256: 8545c806d03092fd0236db6663c88036eab2dc99e34c91cd36c0704db03b148a
manager: conda
name: sphinx_rtd_theme
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/sphinx_rtd_theme-1.3.0-pyha770c72_0.conda
- version: 1.3.0
+ url: https://conda.anaconda.org/conda-forge/noarch/sphinx_rtd_theme-2.0.0-pyha770c72_0.conda
+ version: 2.0.0
- category: main
dependencies:
python: '>=3.9'
@@ -5566,32 +5816,32 @@ package:
- category: main
dependencies:
alabaster: '>=0.7,<0.8'
- babel: '>=1.3'
- colorama: '>=0.3.5'
- docutils: '>=0.14,<0.20'
- imagesize: ''
- importlib-metadata: '>=4.4'
- jinja2: '>=2.3'
- packaging: ''
- pygments: '>=2.0'
- python: '>=3.7'
- requests: '>=2.5.0'
- snowballstemmer: '>=1.1'
+ babel: '>=2.9'
+ colorama: '>=0.4.5'
+ docutils: '>=0.18.1,<0.21'
+ imagesize: '>=1.3'
+ importlib-metadata: '>=4.8'
+ jinja2: '>=3.0'
+ packaging: '>=21.0'
+ pygments: '>=2.14'
+ python: '>=3.9'
+ requests: '>=2.25.0'
+ snowballstemmer: '>=2.0'
sphinxcontrib-applehelp: ''
sphinxcontrib-devhelp: ''
sphinxcontrib-htmlhelp: '>=2.0.0'
sphinxcontrib-jsmath: ''
sphinxcontrib-qthelp: ''
- sphinxcontrib-serializinghtml: '>=1.1.5'
+ sphinxcontrib-serializinghtml: '>=1.1.9'
hash:
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- sha256: 9d614432deff37f90ba406855fd9a21799ef09ab43ec27f5af12ac810fcd1dd1
+ md5: bbfd1120d1824d2d073bc65935f0e4c0
+ sha256: 665d1fe6d20c6cc672ff20e6ebb405860f878b487d3d8d86a5952733fb7bbc42
manager: conda
name: sphinx
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/sphinx-5.1.1-pyhd8ed1ab_1.tar.bz2
- version: 5.1.1
+ url: https://conda.anaconda.org/conda-forge/noarch/sphinx-7.2.6-pyhd8ed1ab_0.conda
+ version: 7.2.6
- category: main
dependencies:
python: '>=3.9'
@@ -5615,25 +5865,17 @@ package:
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url: https://files.pythonhosted.org/packages/6b/20/471f41173930550f279ccb65596a5ac19b9ac974a8d93679bcd3e0c31498/mock-5.1.0-py3-none-any.whl
version: 5.1.0
-- dependencies: {}
- hash:
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- manager: pip
- name: pyyaml
- platform: linux-64
- url: https://files.pythonhosted.org/packages/12/fc/a4d5a7554e0067677823f7265cb3ae22aed8a238560b5133b58cda252dad/PyYAML-6.0-cp39-cp39-manylinux_2_5_x86_64.manylinux1_x86_64.manylinux_2_12_x86_64.manylinux2010_x86_64.whl
- version: '6.0'
- category: main
dependencies:
- six: '*'
+ six: '>=1.12.0'
hash:
- sha256: 6b0ac9e93fb0335014d382b8fa9b3afa7df546984258005da0b9e7095b3deb1c
+ sha256: 051ed49c3dcae8913ea7cd08e46a606dba30b79993209636c4875bc1d637bc24
manager: pip
name: asttokens
optional: false
platform: linux-64
- url: https://files.pythonhosted.org/packages/f3/e1/64679d9d0759db5b182222c81ff322c2fe2c31e156a59afd6e9208c960e5/asttokens-2.2.1-py2.py3-none-any.whl
- version: 2.2.1
+ url: https://files.pythonhosted.org/packages/45/86/4736ac618d82a20d87d2f92ae19441ebc7ac9e7a581d7e58bbe79233b24a/asttokens-2.4.1-py2.py3-none-any.whl
+ version: 2.4.1
- category: main
dependencies:
numpy: '*'
@@ -5660,23 +5902,23 @@ package:
- dependencies:
typing-extensions: '>=4.2.0'
hash:
- sha256: abade85268cc92dff86d6effcd917893130f0ff516f3d637f50dadc22ae93999
+ sha256: 9849f031cf8a2f0a928fe885e5a04b08006d6d41876b8bbd2fc68a18f9f2e3fd
manager: pip
name: pydantic
platform: linux-64
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- version: 1.10.11
+ url: https://files.pythonhosted.org/packages/18/57/11b1e218908aae98d7df4364accc5e5a69db0a9396c011f494c69947e1b9/pydantic-1.10.13-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.whl
+ version: 1.10.13
- category: main
dependencies:
ruamel.yaml.clib: '>=0.2.7'
hash:
- sha256: 23cd2ed620231677564646b0c6a89d138b6822a0d78656df7abda5879ec4f447
+ sha256: b16b6c3816dff0a93dca12acf5e70afd089fa5acb80604afd1ffa8b465b7722c
manager: pip
name: ruamel.yaml
optional: false
platform: linux-64
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- version: 0.17.32
+ url: https://files.pythonhosted.org/packages/35/79/5e2cffa1c77432f11cd93a5351f30732c997a239d3a3090856a72d6d8ba7/ruamel.yaml-0.17.40-py3-none-any.whl
+ version: 0.17.40
- category: main
dependencies:
mock: '*'
@@ -5709,25 +5951,25 @@ package:
pyyaml: '>=6.0,<7.0'
ruamel.yaml: '>=0.17.21,<0.18.0'
hash:
- sha256: 47f1fc5904756b01d46a8d23a4f3950382086b716138e21a027cd44dc5101f27
+ sha256: 7c237557d2a7c5f403474e54f9e5498758c71c24844e524a02656ac16369196d
manager: pip
name: hammer-vlsi
optional: false
platform: linux-64
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- version: 1.1.2
+ url: https://files.pythonhosted.org/packages/dd/85/8a7ffd385db1dc84295ef3101559fe7ae0f8fa39942253ca270728642dc5/hammer_vlsi-1.2.0-py3-none-any.whl
+ version: 1.2.0
- category: main
dependencies:
asttokens: '>=2,<3'
typing-extensions: '*'
hash:
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+ sha256: 1ba4e88f909d3a4b97a565e1ea1199e5b050aa4bdad190c69086bfaed9680cc2
manager: pip
name: icontract
optional: false
platform: linux-64
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- version: 2.6.2
+ url: https://files.pythonhosted.org/packages/49/6f/92ae156eb6afd94ad4ecd38adadff16c83caa4c6d52bd4503a583cf054ab/icontract-2.6.6-py3-none-any.whl
+ version: 2.6.6
- category: main
dependencies:
icontract: '>=2.0.1,<3'
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
index 64bd5ff6..61cc9654 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
@@ -9,7 +9,7 @@
# To update a single package to the latest version compatible with the version constraints in the source:
# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE
# To re-solve the entire environment, e.g. after changing a version constraint in the source file:
-# conda-lock -f /scratch/abejgonza/cy/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy/conda-reqs/riscv-tools.yaml -f /scratch/abejgonza/firesim/target-design/chipyard/conda-reqs/chipyard.yaml -f /scratch/abejgonza/firesim/target-design/chipyard/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml
+# conda-lock -f /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/chipyard.yaml -f /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml
metadata:
channels:
- url: ucb-bar
@@ -21,14 +21,12 @@ metadata:
- url: nodefaults
used_env_vars: []
content_hash:
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+ linux-64: ca6a27eca59955764c48c1f6e92b9c0d88ab3b0ce2cf79bc2b35e847e0aecff4
platforms:
- linux-64
sources:
- - /scratch/abejgonza/cy/conda-reqs/chipyard.yaml
- - /scratch/abejgonza/cy/conda-reqs/riscv-tools.yaml
- - /scratch/abejgonza/firesim/target-design/chipyard/conda-reqs/chipyard.yaml
- - /scratch/abejgonza/firesim/target-design/chipyard/conda-reqs/riscv-tools.yaml
+ - /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/chipyard.yaml
+ - /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/riscv-tools.yaml
package:
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dependencies: {}
@@ -66,25 +64,25 @@ package:
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manager: conda
name: ca-certificates
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2023.7.22-hbcca054_0.conda
- version: 2023.7.22
+ url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2023.11.17-hbcca054_0.conda
+ version: 2023.11.17
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- sha256: 327b40fc91521ad7ba7cc979e9ae40fafec145536b23c8f87a73cbb403eee1d8
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manager: conda
name: conda-standalone
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/conda-standalone-23.7.2-ha770c72_0.conda
- version: 23.7.2
+ url: https://conda.anaconda.org/conda-forge/linux-64/conda-standalone-23.10.0-ha770c72_0.conda
+ version: 23.10.0
- category: main
dependencies: {}
hash:
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manager: conda
name: font-ttf-ubuntu
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/font-ttf-ubuntu-0.83-hab24e00_0.tar.bz2
+ url: https://conda.anaconda.org/conda-forge/noarch/font-ttf-ubuntu-0.83-h77eed37_1.conda
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- category: main
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@@ -143,80 +141,69 @@ package:
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manager: conda
name: libgcc-devel_linux-64
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/libgcc-devel_linux-64-12.3.0-h8bca6fd_0.conda
- version: 12.3.0
+ url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-11.4.0-h922705a_103.conda
+ version: 11.4.0
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dependencies: {}
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- sha256: b311dad92ffafd29668fca6330dc707f4d7f154a4fa4c3859832897416de39ec
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manager: conda
name: libstdcxx-devel_linux-64
optional: false
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- url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-devel_linux-64-12.3.0-h8bca6fd_0.conda
- version: 12.3.0
+ url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-11.4.0-h922705a_103.conda
+ version: 11.4.0
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optional: false
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- url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-ng-13.1.0-hfd8a6a1_0.conda
- version: 13.1.0
+ url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-ng-13.2.0-h7e041cc_3.conda
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manager: conda
name: open_pdks.sky130a
optional: false
platform: linux-64
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- version: 1.0.440_0_g43e733e
+ url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.460_0_gfdb1863-20231104_052339.tar.bz2
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manager: conda
name: python_abi
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/python_abi-3.10-3_cp310.conda
+ url: https://conda.anaconda.org/conda-forge/linux-64/python_abi-3.10-4_cp310.conda
version: '3.10'
- category: main
dependencies: {}
hash:
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manager: conda
name: tzdata
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023c-h71feb2d_0.conda
- version: 2023c
+ url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023d-h0c530f3_0.conda
+ version: 2023d
- category: main
dependencies:
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@@ -244,30 +231,18 @@ package:
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url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_13.tar.bz2
version: 3.10.0
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manager: conda
name: libgomp
optional: false
platform: linux-64
- url: https://conda.anaconda.org/conda-forge/linux-64/libgomp-13.1.0-he5830b7_0.conda
- version: 13.1.0
+ url: https://conda.anaconda.org/conda-forge/linux-64/libgomp-13.2.0-h807b86a_3.conda
+ version: 13.2.0
- category: main
dependencies:
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@@ -324,14 +299,14 @@ package:
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platform: linux-64
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- version: 13.1.0
+ url: https://conda.anaconda.org/conda-forge/linux-64/libgcc-ng-13.2.0-h807b86a_3.conda
+ version: 13.2.0
- category: main
dependencies:
libgcc-ng: '>=12'
@@ -344,6 +319,18 @@ package:
platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.9-hd590300_0.conda
version: 1.2.9
+- category: main
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+ manager: conda
+ name: aws-c-common
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+ url: https://conda.anaconda.org/conda-forge/linux-64/aws-c-common-0.9.10-hd590300_0.conda
+ version: 0.9.10
- category: main
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libgcc-ng: '>=9.4.0'
@@ -370,28 +357,28 @@ package:
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- category: main
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manager: conda
name: bzip2
optional: false
platform: linux-64
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+ url: https://conda.anaconda.org/conda-forge/linux-64/bzip2-1.0.8-hd590300_5.conda
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manager: conda
name: c-ares
optional: false
platform: linux-64
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- version: 1.19.1
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+ version: 1.24.0
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@@ -416,18 +403,6 @@ package:
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url: https://conda.anaconda.org/conda-forge/linux-64/ctags-5.8-h14c3975_1000.tar.bz2
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- category: main
dependencies:
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- libstdcxx-ng: '>=7.5.0'
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platform: linux-64
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- version: 6.2.1
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@@ -505,16 +480,16 @@ package:
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- category: main
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platform: linux-64
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- version: '1.12'
+ url: https://conda.anaconda.org/conda-forge/linux-64/gzip-1.13-hd590300_0.conda
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- version: '20230125.3'
+ url: https://conda.anaconda.org/conda-forge/linux-64/libabseil-20230802.1-cxx17_h59595ed_0.conda
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- url: https://conda.anaconda.org/conda-forge/linux-64/libnsl-2.0.0-h7f98852_0.tar.bz2
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+ version: 2.0.1
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platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.3.1-hd590300_0.conda
version: 1.3.1
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name: ncurses
optional: false
platform: linux-64
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+ url: https://conda.anaconda.org/conda-forge/linux-64/ncurses-6.4-h59595ed_2.conda
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platform: linux-64
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- version: 3.8.1
+ url: https://conda.anaconda.org/conda-forge/linux-64/nettle-3.9.1-h7ab15ed_0.conda
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platform: linux-64
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- version: 6.9.8
+ url: https://conda.anaconda.org/conda-forge/linux-64/oniguruma-6.9.9-hd590300_0.conda
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optional: false
platform: linux-64
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@@ -908,16 +893,17 @@ package:
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platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/yaml-0.2.5-h7f98852_2.tar.bz2
version: 0.2.5
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url: https://conda.anaconda.org/conda-forge/linux-64/findutils-4.6.0-h166bdaf_1001.tar.bz2
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platform: linux-64
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+ url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlidec-1.1.0-hd590300_1.conda
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url: https://conda.anaconda.org/conda-forge/linux-64/libedit-3.1.20191231-he28a2e2_2.tar.bz2
version: 3.1.20191231
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- category: main
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libstdcxx-ng: '>=12'
libzlib: '>=1.2.13,<1.3.0a0'
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- category: main
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platform: linux-64
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+ url: https://conda.anaconda.org/conda-forge/linux-64/perl-5.32.1-7_hd590300_perl5.conda
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url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.2-h8228510_1.conda
version: '8.2'
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- category: main
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- libzlib: '>=1.2.11,<1.3.0a0'
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platform: linux-64
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- version: 8.6.12
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url: https://conda.anaconda.org/conda-forge/linux-64/autoconf-2.71-pl5321h2b4cb7a_1.conda
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- category: main
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- libbrotlienc: 1.1.0 hd590300_0
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platform: linux-64
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+ url: https://conda.anaconda.org/conda-forge/linux-64/brotli-bin-1.1.0-hd590300_1.conda
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optional: false
platform: linux-64
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+ url: https://conda.anaconda.org/conda-forge/linux-64/freetype-2.12.1-h267a509_2.conda
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- version: 12.3.0
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libstdcxx-ng: '>=12'
libtasn1: '>=4.19.0,<5.0a0'
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- version: 3.7.8
+ url: https://conda.anaconda.org/conda-forge/linux-64/gnutls-3.7.9-hb077bed_0.conda
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- libstdcxx-devel_linux-64: 12.3.0 h8bca6fd_0
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lzo: '>=2.10,<3.0a0'
openssl: '>=3.0.3,<4.0a0'
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hash:
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gettext: '>=0.21.1,<1.0a0'
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libstdcxx-ng: '>=12'
libzlib: '>=1.2.13,<1.3.0a0'
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- version: 3.9.0
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libgcc-ng: '>=12'
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platform: linux-64
url: https://conda.anaconda.org/conda-forge/linux-64/libllvm16-16.0.3-hbf9e925_1.conda
version: 16.0.3
+- category: main
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libzlib: '>=1.2.13,<1.3.0a0'
ncurses: '>=6.4,<7.0a0'
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optional: false
platform: linux-64
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dependencies:
libgcc-ng: '>=12'
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url: https://conda.anaconda.org/conda-forge/noarch/appdirs-1.4.4-pyh9f0ad1d_0.tar.bz2
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url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-haa2dc70_1.conda
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-- dependencies: {}
- hash:
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- manager: pip
- name: pyyaml
- platform: linux-64
- url: https://files.pythonhosted.org/packages/02/25/6ba9f6bb50a3d4fbe22c1a02554dc670682a07c8701d1716d19ddea2c940/PyYAML-6.0-cp310-cp310-manylinux_2_5_x86_64.manylinux1_x86_64.manylinux_2_12_x86_64.manylinux2010_x86_64.whl
- version: '6.0'
- category: main
dependencies:
- six: '*'
+ six: '>=1.12.0'
hash:
- sha256: 6b0ac9e93fb0335014d382b8fa9b3afa7df546984258005da0b9e7095b3deb1c
+ sha256: 051ed49c3dcae8913ea7cd08e46a606dba30b79993209636c4875bc1d637bc24
manager: pip
name: asttokens
optional: false
platform: linux-64
- url: https://files.pythonhosted.org/packages/f3/e1/64679d9d0759db5b182222c81ff322c2fe2c31e156a59afd6e9208c960e5/asttokens-2.2.1-py2.py3-none-any.whl
- version: 2.2.1
+ url: https://files.pythonhosted.org/packages/45/86/4736ac618d82a20d87d2f92ae19441ebc7ac9e7a581d7e58bbe79233b24a/asttokens-2.4.1-py2.py3-none-any.whl
+ version: 2.4.1
- category: main
dependencies:
numpy: '*'
@@ -5648,23 +5903,23 @@ package:
- dependencies:
typing-extensions: '>=4.2.0'
hash:
- sha256: 16928fdc9cb273c6af00d9d5045434c39afba5f42325fb990add2c241402d151
+ sha256: 1740068fd8e2ef6eb27a20e5651df000978edce6da6803c2bef0bc74540f9548
manager: pip
name: pydantic
platform: linux-64
- url: https://files.pythonhosted.org/packages/b6/8e/7dd215f91528487535e7aa048e4092c20ecd0168df958e58809e2235cece/pydantic-1.10.11-cp310-cp310-manylinux_2_17_x86_64.manylinux2014_x86_64.whl
- version: 1.10.11
+ url: https://files.pythonhosted.org/packages/e0/2f/d6f17f8385d718233bcae893d27525443d41201c938b68a4af3d591a33e4/pydantic-1.10.13-cp310-cp310-manylinux_2_17_x86_64.manylinux2014_x86_64.whl
+ version: 1.10.13
- category: main
dependencies:
ruamel.yaml.clib: '>=0.2.7'
hash:
- sha256: 23cd2ed620231677564646b0c6a89d138b6822a0d78656df7abda5879ec4f447
+ sha256: b16b6c3816dff0a93dca12acf5e70afd089fa5acb80604afd1ffa8b465b7722c
manager: pip
name: ruamel.yaml
optional: false
platform: linux-64
- url: https://files.pythonhosted.org/packages/d9/0e/2a05efa11ea33513fbdf4a2e2576fe94fd8fa5ad226dbb9c660886390974/ruamel.yaml-0.17.32-py3-none-any.whl
- version: 0.17.32
+ url: https://files.pythonhosted.org/packages/35/79/5e2cffa1c77432f11cd93a5351f30732c997a239d3a3090856a72d6d8ba7/ruamel.yaml-0.17.40-py3-none-any.whl
+ version: 0.17.40
- category: main
dependencies:
mock: '*'
@@ -5697,25 +5952,25 @@ package:
pyyaml: '>=6.0,<7.0'
ruamel.yaml: '>=0.17.21,<0.18.0'
hash:
- sha256: 47f1fc5904756b01d46a8d23a4f3950382086b716138e21a027cd44dc5101f27
+ sha256: 7c237557d2a7c5f403474e54f9e5498758c71c24844e524a02656ac16369196d
manager: pip
name: hammer-vlsi
optional: false
platform: linux-64
- url: https://files.pythonhosted.org/packages/30/e4/37b77c7921b80d58d8b2a325c031e75d656319b676e7fd4555e02b651a9d/hammer_vlsi-1.1.2-py3-none-any.whl
- version: 1.1.2
+ url: https://files.pythonhosted.org/packages/dd/85/8a7ffd385db1dc84295ef3101559fe7ae0f8fa39942253ca270728642dc5/hammer_vlsi-1.2.0-py3-none-any.whl
+ version: 1.2.0
- category: main
dependencies:
asttokens: '>=2,<3'
typing-extensions: '*'
hash:
- sha256: 1a441dad41c9a0615c6ae96464190eddccd2de8153254059ff18ffd7b3b84800
+ sha256: 1ba4e88f909d3a4b97a565e1ea1199e5b050aa4bdad190c69086bfaed9680cc2
manager: pip
name: icontract
optional: false
platform: linux-64
- url: https://files.pythonhosted.org/packages/d8/91/9756e7cf0b155e80bf9a62beffdd1dec4afce43cc6ab7f432f2267c62762/icontract-2.6.2-py3-none-any.whl
- version: 2.6.2
+ url: https://files.pythonhosted.org/packages/49/6f/92ae156eb6afd94ad4ecd38adadff16c83caa4c6d52bd4503a583cf054ab/icontract-2.6.6-py3-none-any.whl
+ version: 2.6.6
- category: main
dependencies:
icontract: '>=2.0.1,<3'
diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst
index 8f8e9045..669bfdfc 100644
--- a/docs/Chipyard-Basics/Chipyard-Components.rst
+++ b/docs/Chipyard-Basics/Chipyard-Components.rst
@@ -53,9 +53,9 @@ System Components:
**icenet**
A Network Interface Controller (NIC) designed to achieve up to 200 Gbps.
-**sifive-blocks**
- System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
- These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
+**rocket-chip-blocks**
+ System components originally implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
+ Now maintained by Chips Alliance. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
**AWL (Analog Widget Library)**
Digital components required for integration with high speed serial links.
@@ -106,6 +106,9 @@ Software
FireMarshal is the default workload generation tool that Chipyard uses to create software to run on its platforms.
See :ref:`fire-marshal` for more information.
+**Baremetal-IDE**
+ Baremetal-IDE is an all-in-one tool for baremetal-level C/C++ program development. See `Tutorial `_ for more information.
+
Sims
-------------------------------------------
diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
index 9f31624e..948b7e2e 100644
--- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst
+++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
@@ -46,7 +46,7 @@ This is done by the following:
.. code-block:: shell
- conda install -n base conda-lock=1.4
+ conda install -n base conda-lock==1.4.0
conda activate base
diff --git a/docs/Customization/Boot-Process.rst b/docs/Customization/Boot-Process.rst
index a84c4e99..52ea32c1 100644
--- a/docs/Customization/Boot-Process.rst
+++ b/docs/Customization/Boot-Process.rst
@@ -12,7 +12,7 @@ Device Tree Binary (dtb) which details the components of the system.
The assembly for the BootROM code is located in
`generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.S `_.
The BootROM address space starts at ``0x10000`` (determined by the ``BootROMParams`` key in the configuration) and execution starts at address
-``0x10040`` (given by the linker script and reset vector in the ``BootROMParams``), which is marked by the ``_hang`` label in the BootROM assembly.
+``0x10000`` (given by the linker script and reset vector in the ``BootROMParams``), which is marked by the ``_hang`` label in the BootROM assembly.
The Chisel generator encodes the assembled instructions into the BootROM
hardware at elaboration time, so if you want to change the BootROM code, you
diff --git a/docs/Customization/Custom-Chisel.rst b/docs/Customization/Custom-Chisel.rst
index 121ca712..a3b4ef72 100644
--- a/docs/Customization/Custom-Chisel.rst
+++ b/docs/Customization/Custom-Chisel.rst
@@ -59,7 +59,7 @@ should look something like this:
.. code-block:: scala
lazy val chipyard = (project in file("generators/chipyard"))
- .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+ .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
sha3, dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
yourproject, // <- added to the middle of the list for simplicity
diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst
index d3626a03..d7e65223 100644
--- a/docs/Customization/IOBinders.rst
+++ b/docs/Customization/IOBinders.rst
@@ -13,7 +13,7 @@ The ``IOBinder`` functions are responsible for instantiating IO cells and IOPort
For example, the ``WithUARTIOCells`` IOBinder will, for any ``System`` that might have UART ports (``HasPeripheryUARTModuleImp``, generate ports within the ``ChipTop`` (``ports``) as well as IOCells with the appropriate type and direction (``cells2d``). This function returns a the list of generated ports, and the list of generated IOCells. The list of generated ports is passed to the ``HarnessBinders`` such that they can be connected to ``TestHarness`` devices.
-.. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala
+.. literalinclude:: ../../generators/chipyard/src/main/scala/iobinders/IOBinders.scala
:language: scala
:start-after: DOC include start: WithUARTIOCells
:end-before: DOC include end: WithUARTIOCells
diff --git a/docs/Customization/Incorporating-Verilog-Blocks.rst b/docs/Customization/Incorporating-Verilog-Blocks.rst
index 3198d087..7724ffb2 100644
--- a/docs/Customization/Incorporating-Verilog-Blocks.rst
+++ b/docs/Customization/Incorporating-Verilog-Blocks.rst
@@ -161,4 +161,31 @@ transformed or augmented by any Chipyard FIRRTL transform.
As mentioned earlier in this section, ``BlackBox`` resource files must
be integrated into the build process, so any project providing
``BlackBox`` resources must be made visible to the ``tapeout`` project
-in ``build.sbt``
+in ``build.sbt``.
+
+Differences between ``HasBlackBoxPath`` and ``HasBlackBoxResource``
+-------------------------------------------------------------------
+
+Chisel provides two mechanisms for integrating blackbox files into a Chisel project that work slightly differently in Chipyard: ``HasBlackBoxPath`` and ``HasBlackBoxResource``.
+
+``HasBlackBoxResource`` incorporates extra files by looking up the relative path of the files within the ``src/main/resources`` area of project.
+This requires that the file added by ``addResource`` is present in the ``src/main/resources`` area and is **not** auto-generated (the file is static throughout the lifetime of generating RTL).
+This is due to the fact that when the Chisel sources are compiled they are put in a ``jar`` file, along with the ``src/main/resources`` area, and that ``jar`` is used to run the Chisel generator.
+Files referenced by the ``addResource`` must be located within this ``jar`` file during the Chisel elaboration.
+Thus if a file is generated during Chisel generation it will not be present in the ``jar`` file until the next time the Chisel sources are compiled.
+
+``HasBlackBoxPath`` differs in that it incorporates extra files by using an absolute path to them.
+Later in the build process, the FIRRTL compiler will copy the file from that location to the generated sources directory.
+Thus, the file must be present before the FIRRTL compiler is run (i.e. the file doesn't need to be in the ``src/main/resources`` or it can be auto-generated during Chisel elaboration).
+
+Additionally, both mechanisms do not enforce the order of files added.
+For example:
+
+.. code-block:: scala
+
+ addResource("fileA")
+ addResource("fileB")
+
+In this case, ``fileA`` is not guaranteed to be before ``fileB`` when passed to downstream tools.
+To bypass this, it is recommended to auto-generate a single file with the ordering needed by concatenating the files and using ``addPath`` given by ``HasBlackBoxPath``.
+An example of this is https://github.com/ucb-bar/ibex-wrapper/blob/main/src/main/scala/IbexCoreBlackbox.scala.
diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst
index 623d4544..11bc132b 100644
--- a/docs/Customization/Memory-Hierarchy.rst
+++ b/docs/Customization/Memory-Hierarchy.rst
@@ -46,17 +46,17 @@ agents and MMIO peripherals. Ordinarily, it is a fully-connected crossbar, but
a network-on-chip-based implementation can be generated using Constellation.
See :ref:`Customization/NoC-SoCs:SoCs with NoC-based Interconnects` for more.
-The SiFive L2 Cache
--------------------
+The Inclusive Last-Level Cache
+---------------------------------
-The default ``RocketConfig`` provided in the Chipyard example project uses SiFive's
+The default ``RocketConfig`` provided in the Chipyard example project uses the Rocket-Chip
InclusiveCache generator to produce a shared L2 cache. In the default
configuration, the L2 uses a single cache bank with 512 KiB capacity and 8-way
set-associativity. However, you can change these parameters to obtain your
desired cache configuration. The main restriction is that the number of ways
and the number of banks must be powers of 2.
-Refer to the ``CacheParameters`` object defined in sifive-cache for
+Refer to the ``CacheParameters`` object defined in ``rocket-chip-inclusive-cache`` for
customization options.
The Broadcast Hub
@@ -94,10 +94,10 @@ memory channel.
Instead of connecting to off-chip DRAM, you can instead connect a scratchpad
and remove the off-chip link. This is done by adding a fragment like
-``testchipip.WithScratchpad`` to your configuration and removing the
+``testchipip.soc.WithScratchpad`` to your configuration and removing the
memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``.
-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
+.. literalinclude:: ../../generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
:language: scala
:start-after: DOC include start: mbusscratchpadrocket
:end-before: DOC include end: mbusscratchpadrocket
diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/Rocket-Chip-Generators.rst
similarity index 72%
rename from docs/Generators/SiFive-Generators.rst
rename to docs/Generators/Rocket-Chip-Generators.rst
index d6b174ef..435fa1dd 100644
--- a/docs/Generators/SiFive-Generators.rst
+++ b/docs/Generators/Rocket-Chip-Generators.rst
@@ -1,19 +1,19 @@
-SiFive Generators
-==================
+Rocket-Chip Generators
+======================
-Chipyard includes several open-source generators developed and maintained by `SiFive `__.
-These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``.
+Chipyard includes several open-source generators developed by `SiFive `__, and now openly maintained as part of Chips Alliance.
+These are currently organized within two submodules named ``rocket-chip-blocks`` and ``rocket-chip-inclusive-cache``.
Last-Level Cache Generator
-----------------------------
-``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration.
+``rocket-chip-inclusive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration.
To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section.
Peripheral Devices Overview
----------------------------
-``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
+``rocket-chip-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well.
All the peripheral blocks comes with a default memory address that would not collide with each other, but if integrating multiple duplicated blocks in the SoC is needed, you will need to explicitly specify an approriate memory address for that device.
@@ -34,7 +34,7 @@ Finally, you add the relevant config fragment to the SoC config. For example:
General Purpose I/Os (GPIO) Device
----------------------------------
-GPIO device is a periphery device provided by ``sifive-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
+GPIO device is a periphery device provided by ``rocket-chip-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
GPIO main features
@@ -78,7 +78,7 @@ Including GPIO in the SoC
Universal Asynchronous Receiver/Transmitter (UART) Device
----------------------------------------------------------
-UART device is a periphery device provided by ``sifive-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers.
+UART device is a periphery device provided by ``rocket-chip-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers.
UART main features
@@ -125,7 +125,7 @@ Including UART in the SoC
Inter-Integrated Circuit (I2C) Interface Device
-------------------------------------------------
-I2C device is a periphery device provided by ``sifive-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
+I2C device is a periphery device provided by ``rocket-chip-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
I2C main features
@@ -169,7 +169,7 @@ Including I2C in the SoC
Serial Peripheral Interface (SPI) Device
-------------------------------------------------
-SPI device is a periphery device provided by ``sifive-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
+SPI device is a periphery device provided by ``rocket-chip-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCLK) to the external slave device.
diff --git a/docs/Generators/Rocket-Chip.rst b/docs/Generators/Rocket-Chip.rst
index 856d01e1..3e404939 100644
--- a/docs/Generators/Rocket-Chip.rst
+++ b/docs/Generators/Rocket-Chip.rst
@@ -1,8 +1,8 @@
Rocket Chip
===========
-Rocket Chip generator is an SoC generator developed at Berkeley and now supported by
-`SiFive `__. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
+Rocket Chip generator is an SoC generator developed at Berkeley and SiFive, and now maintained openly in Chips Alliance.
+Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
`Rocket Chip` is distinct from `Rocket core`, the in-order RISC-V CPU generator.
Rocket Chip includes many parts of the SoC besides the CPU. Though Rocket Chip
diff --git a/docs/Generators/Rocket.rst b/docs/Generators/Rocket.rst
index 6c55b761..536d6991 100644
--- a/docs/Generators/Rocket.rst
+++ b/docs/Generators/Rocket.rst
@@ -1,7 +1,7 @@
Rocket Core
====================================
-`Rocket `__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and currently supported by `SiFive `__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
+`Rocket `__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and `SiFive `__, and now maintained by Chips Alliance. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
The Rocket core supports the open-source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.
diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst
index 2c382d4f..32e76f5b 100644
--- a/docs/Generators/TestChipIP.rst
+++ b/docs/Generators/TestChipIP.rst
@@ -92,3 +92,15 @@ The SPI flash model is a device that models a simple SPI flash device. It curren
only supports single read, quad read, single write, and quad write instructions. The
memory is backed by a file which is provided using ``+spiflash#=``,
where ``#`` is the SPI flash ID (usually ``0``).
+
+Chip ID Pin
+---------------
+
+The chip ID pin sets the chip ID for the chip it is added to. This is most useful in
+multi-chip configs. The pin value is driven by the chip ID value set in the harness
+binder and the chip ID value can be read through MMIO at the address ``0x2000`` by default.
+
+The pin can be added to a system with the ``testchipip.soc.WithChipIdPin`` config. The pin
+width and MMIO address are parameterizable and can be set by passing ``ChipIdPinParams`` as an
+argument to the config. The width can additionally be set using the ``testchipip.soc.WithChipIdPinWidth``
+config.
diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst
index c2bf3719..651a6bae 100644
--- a/docs/Generators/index.rst
+++ b/docs/Generators/index.rst
@@ -26,7 +26,7 @@ so changes to the generators themselves will automatically be used when building
Gemmini
IceNet
TestChipIP
- SiFive-Generators
+ Rocket-Chip-Generators
SHA3
CVA6
Ibex
diff --git a/docs/Prototyping/Arty.rst b/docs/Prototyping/Arty.rst
index 15347cf8..843c05f5 100644
--- a/docs/Prototyping/Arty.rst
+++ b/docs/Prototyping/Arty.rst
@@ -2,18 +2,18 @@ Running a Design on Arty
========================
Arty100T Instructions
-----------------------
+---------------------
-The default Xilinx Arty 100T harness uses a TSI-over-UART adapter to bringup the FPGA.
-A user can connect to the Arty 100T target using a special ``uart_tsi`` program that opens a UART TTY.
+The default Digilent Arty A7-100T harness uses a TSI-over-UART adapter to bringup the FPGA.
+A user can connect to the Arty A7-100T target using a special ``uart_tsi`` program that opens a UART TTY.
The interface for the ``uart_tsi`` program provides unique functionality that is useful for bringing up test chips.
-To build the design, run:
+To build the design (Vivado should be added to the ``PATH``), run:
.. code-block:: shell
cd fpga/
- make SUB_PROJECT=arty100t
+ make SUB_PROJECT=arty100t bitstream
To build the UART-based frontend server, run:
@@ -34,7 +34,7 @@ Probe an address on the target system:
.. code-block:: shell
- ./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10040 none
+ ./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10000 none
Write some address before running a program:
@@ -58,7 +58,7 @@ Run a design at a higher baud rate than default (For example, if ``CONFIG=UART92
Arty35T Legacy Instructions
---------------------------
-The default Xilinx Arty 35T harness is setup to have JTAG available over the board's PMOD pins, and UART available over its FTDI serial USB adapter. The pin mappings for JTAG signals are identical to those described in the `SiFive Freedom E310 Arty 35T Getting Started Guide `__.
+The default Digilent Arty A7-35T harness is setup to have JTAG available over the board's PMOD pins, and UART available over its FTDI serial USB adapter. The pin mappings for JTAG signals are identical to those described in the `SiFive Freedom E310 Arty 35T Getting Started Guide `__.
The JTAG interface allows a user to connect to the core via OpenOCD, run bare-metal applications, and debug these applications with gdb. UART allows a user to communicate with the core over a USB connection and serial console running on a PC.
To extend this design, a user may create their own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``.
Adding this config. fragment will enable and connect the JTAG and UART interfaces to your Chipyard design.
@@ -68,13 +68,13 @@ Adding this config. fragment will enable and connect the JTAG and UART interface
:start-after: DOC include start: AbstractArty and Rocket
:end-before: DOC include end: AbstractArty and Rocket
-Future peripherals to be supported include the Arty 35T SPI Flash EEPROM, and I2C/PWM/SPI over the Arty 35T GPIO pins. These peripherals are available as part of sifive-blocks.
+Future peripherals to be supported include the Arty A7-35T SPI Flash EEPROM, and I2C/PWM/SPI over the Arty A7-35T GPIO pins. These peripherals are available as part of sifive-blocks.
Brief Implementation Description and Guidance for Adding/Changing Xilinx Collateral
-----------------------------------------------------------------------------------
-Like the VCU118, the basis for the Arty 35T design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design.
-This is done with the ``ArtyTestHarness`` in the basic default Arty 35T target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``.
-Unlike the VCU118 and other more complicated test harnesses, the Arty 35T Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``.
+Like the VCU118, the basis for the Arty A7-35T design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design.
+This is done with the ``ArtyTestHarness`` in the basic default Arty A7-35T target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``.
+Unlike the VCU118 and other more complicated test harnesses, the Arty A7-35T Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``.
If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinders`` and ``IOBinders``.
Examples of a simple ``IOBinder`` and ``HarnessBinder`` for routing signals (in this case the debug and JTAG resets) from the core to the test harness are the ``WithResetPassthrough`` and ``WithArtyResetHarnessBinder``.
diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst
index 2b7a7332..051cbcf8 100644
--- a/docs/Prototyping/General.rst
+++ b/docs/Prototyping/General.rst
@@ -2,7 +2,7 @@ General Setup and Usage
==============================
Sources
----------------------------
+-------
All FPGA prototyping-related collateral and sources are located in the ``fpga`` top-level Chipyard directory.
This includes the ``fpga-shells`` submodule and the ``src`` directory that hold both Scala, TCL and other collateral.
diff --git a/docs/Prototyping/NexysVideo.rst b/docs/Prototyping/NexysVideo.rst
new file mode 100644
index 00000000..5256261f
--- /dev/null
+++ b/docs/Prototyping/NexysVideo.rst
@@ -0,0 +1,49 @@
+Running a Design on Nexys Video
+===============================
+
+Nexys Video Instructions
+------------------------
+
+The default Digilent Nexys Video harness uses a TSI-over-UART adapter to bringup the FPGA.
+A user can connect to the Nexys Video target using a special ``uart_tsi`` program that opens a UART TTY.
+The interface for the ``uart_tsi`` program provides unique functionality that is useful for bringing up test chips.
+
+To build the design (Vivado should be added to the ``PATH``), run:
+
+.. code-block:: shell
+
+ cd fpga/
+ make SUB_PROJECT=nexysvideo bitstream
+
+To build the UART-based frontend server, run:
+
+.. code-block:: shell
+
+ cd generators/testchipip/uart_tsi
+ make
+
+After programming the bitstream, and connecting the Nexys Video's UART to a host PC via the USB cable, the ``uart_tsi`` program can be run to interact with the target.
+
+Running a program:
+
+.. code-block:: shell
+
+ ./uart_tsi +tty=/dev/ttyUSBX dhrystone.riscv
+
+Probe an address on the target system:
+
+.. code-block:: shell
+
+ ./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10000 none
+
+Write some address before running a program:
+
+.. code-block:: shell
+
+ ./uart_tsi +tty=/dev/ttyUSBX +init_write=0x80000000:0xdeadbeef none
+
+Self-check that binary loading proceeded correctly:
+
+.. code-block:: shell
+
+ ./uart_tsi +tty=/dev/ttyUSBX +selfcheck dhrystone.riscv
diff --git a/docs/Prototyping/index.rst b/docs/Prototyping/index.rst
index ba0dff49..a2332a25 100644
--- a/docs/Prototyping/index.rst
+++ b/docs/Prototyping/index.rst
@@ -2,10 +2,10 @@ Prototyping Flow
================
Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__.
-This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty 35T board.
+This includes popular FPGAs such as the Xilinx VCU118 and the Digilent Arty A7-35T/A7-100T board.
-.. Note:: While ``fpga-shells`` provides harnesses for other FPGA development boards such as the Xilinx VC707 and some MicroSemi PolarFire, only harnesses for the Xilinx VCU118 and Xilinx Arty 35T boards are currently supported in Chipyard.
- However, the VCU118 and Arty 35T examples demonstrate how a user may implement support for other harnesses provided by fpga-shells.
+.. Note:: While ``fpga-shells`` provides harnesses for other FPGA development boards such as the Xilinx VC707 and some MicroSemi PolarFire, only harnesses for the Xilinx VCU118 and Digilent Arty A7-35T/A7-100T boards are currently supported in Chipyard.
+ However, the VCU118 and Arty A7-35T/A7-100T examples demonstrate how a user may implement support for other harnesses provided by fpga-shells.
.. toctree::
:maxdepth: 2
@@ -14,3 +14,4 @@ This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty 35T bo
General
VCU118
Arty
+ NexysVideo
diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst
index 2e832182..8c87cc80 100644
--- a/docs/Simulation/Software-RTL-Simulation.rst
+++ b/docs/Simulation/Software-RTL-Simulation.rst
@@ -81,6 +81,24 @@ For example:
.. _sw-sim-custom:
+Custom Benchmarks/Tests
+-------------------------------
+
+To compile your own bare-metal code to run in a Verilator/VCS simulation, add it to Chipyard's ``tests`` directory then add its name to the list of ``PROGRAMS`` inside the ``Makefile``. These binaries are compiled with the libgloss-htif library, which implements a minimal set of useful syscalls for bare-metal binaries. Then when you run ``make``, all of the programs inside ``tests`` will be compiled into ``.riscv`` ELF binaries, which can be used with the simulator as described above.
+
+.. code-block:: shell
+
+ # Enter Tests directory
+ cd tests
+ make
+
+ # Enter Verilator or VCS directory
+ cd ../sims/verilator
+ make run-binary BINARY=../../tests/hello.riscv
+
+.. Note:: On multi-core configurations, only hart (**har**\ dware **t**\ hread) 0 executes the ``main()`` function. All other harts execute the secondary ``__main()`` function, which defaults to a busy loop. To run a multi-threaded workload on a Verilator/VCS simulation, override ``__main()`` with your own code. More details can be found `here `_
+
+
Makefile Variables and Commands
-------------------------------
You can get a list of useful Makefile variables and commands available from the Verilator or VCS directories. simply run ``make help``:
diff --git a/docs/Software/Spike.rst b/docs/Software/Spike.rst
index e9abe0c0..10fa8429 100644
--- a/docs/Software/Spike.rst
+++ b/docs/Software/Spike.rst
@@ -50,3 +50,24 @@ Spike-as-a-Tile can be configured with custom IPC, commit logging, and other beh
* ``+spike-fast-clint``: Enables fast-forwarding through WFI stalls by generating fake timer interrupts
* ``+spike-debug``: Enables debug Spike logging
* ``+spike-verbose``: Enables Spike commit-log generation
+
+Adding a new spike device model
+-------------------------------
+
+Spike comes with a few functional device models such as UART, CLINT, and PLIC.
+However, you may want to add custom device models into Spike such as a block device.
+Example devices are in the ``toolchains/riscv-tools/riscv-spike-devices`` directory.
+These devices are compiled as a shared library that can be dynamically linked to Spike.
+
+To compile these plugins, run ``make`` inside ``toolchains/riscv-tools/riscv-spike-devices``. This will generate a ``libspikedevices.so``.
+
+To hook up a block device to spike and provide a default image to initialize the block device, run
+
+.. code-block:: shell
+
+ spike --extlib=libspikedevices.so --device="iceblk,img="
+
+.
+
+The ``--device`` option consists of the device name and arguments.
+In the above example ``iceblk`` is the device name and ``img=`` is the argument passed on to the plugin device.
diff --git a/docs/VLSI/Sky130-Commercial-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst
index 9ca81583..92e4330c 100644
--- a/docs/VLSI/Sky130-Commercial-Tutorial.rst
+++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst
@@ -60,7 +60,7 @@ The prerequisite setup for this tutorial may eventually be scripted, but for now
.. code-block:: shell
# download all files for Sky130A PDK
- conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
+ conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.457_0_g32e8f23
# clone the SRAM22 Sky130 SRAM macros
git clone https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros
@@ -123,8 +123,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e
and (2) the mapping of memory instances in the design to SRAM macros;
all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory.
Note that the files in ``generated-src`` vary for each tool/technology flow.
-This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
-(due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate
+This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows, so these flows should be run in separate
chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst
index a9cfa7b1..0c138d66 100644
--- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst
+++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst
@@ -49,7 +49,7 @@ Prerequisites
* OpenROAD flow tools (NOTE: tutorial may break with different tool versions):
* **Yosys 0.27+3** (synthesis), install `using conda `__ or `from source `__
- * **OpenROAD v2.0-7070-g0264023b6** (place-and-route), install `using conda `__ (note that GUI is disabled in conda package) or
+ * **OpenROAD v2.0-7070-g0264023b6** (place-and-route), install `using conda `__ (note that GUI is disabled in conda package) or
`from source `__ (git hash: 0264023b6c2a8ae803b8d440478d657387277d93)
* **KLayout 0.28.5** (DEF to GDSII conversion, DRC), install `using conda `__ or `from source `__
* **Magic 8.3.376** (DRC), install `using conda `__ or `from source `__
@@ -73,7 +73,7 @@ Note that we create a new conda environment for each tool because some of them h
conda config --add channels defaults
# download all files for Sky130A PDK
- conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
+ conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.457_0_g32e8f23
# clone the SRAM22 Sky130 SRAM macros
git clone https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros
@@ -161,8 +161,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e
and (2) the mapping of memory instances in the design to SRAM macros;
all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory.
Note that the files in ``generated-src`` vary for each tool/technology flow.
-This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
-(due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate
+This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows, so these flows should be run in separate
chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
@@ -175,7 +174,6 @@ which will cause additional variables to be set in ``tutorial.mk``, a few of whi
* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
* ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
* ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
-* ``ENABLE_YOSYS_FLOW = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog.
Running the VLSI Flow
---------------------
@@ -275,7 +273,7 @@ This is because Magic and Netgen, as of the writing of this tutorial, do not hav
so to view the DRC/LVS results for debugging you must launch the tool interactively, then run DRC/LVS checks,
which is done by the ``generated-scripts/view_[drc|lvs]`` scripts. This is not the case for KLayout, which does have a loadable database format.
-Below is the window you should see when loading the KLayout DRC results interactively. Note that most of these DRC errors are
+Below is the window you should see when loading the KLayout DRC results interactively. Note that most of these DRC errors are
from special rules relating to Sky130 SRAMs, which have been verified separately. In the future the KLayout tool plugin should blackbox these
SRAM macros by default, but this feature does not exist yet.
diff --git a/fpga/Makefile b/fpga/Makefile
index 7521b1ed..a4d3bf99 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -57,11 +57,26 @@ ifeq ($(SUB_PROJECT),bringup)
BOARD ?= vcu118
FPGA_BRAND ?= xilinx
endif
-ifeq ($(SUB_PROJECT),arty)
+
+ifeq ($(SUB_PROJECT),nexysvideo)
+ SBT_PROJECT ?= fpga_platforms
+ MODEL ?= NexysVideoHarness
+ VLOG_MODEL ?= NexysVideoHarness
+ MODEL_PACKAGE ?= chipyard.fpga.nexysvideo
+ CONFIG ?= RocketNexysVideoConfig
+ CONFIG_PACKAGE ?= chipyard.fpga.nexysvideo
+ GENERATOR_PACKAGE ?= chipyard
+ TB ?= none # unused
+ TOP ?= ChipTop
+ BOARD ?= nexys_video
+ FPGA_BRAND ?= xilinx
+endif
+
+ifeq ($(SUB_PROJECT),arty35t)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
- MODEL ?= ArtyFPGATestHarness
- VLOG_MODEL ?= ArtyFPGATestHarness
+ MODEL ?= Arty35THarness
+ VLOG_MODEL ?= Arty35THarness
MODEL_PACKAGE ?= chipyard.fpga.arty
CONFIG ?= TinyRocketArtyConfig
CONFIG_PACKAGE ?= chipyard.fpga.arty
@@ -122,7 +137,7 @@ include $(base_dir)/common.mk
# copy from other directory
#########################################################################################
all_vsrcs := \
- $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v
+ $(base_dir)/generators/rocket-chip-blocks/vsrc/SRLatch.v
#########################################################################################
# vivado rules
diff --git a/fpga/bootrom.rv32.img b/fpga/bootrom.rv32.img
new file mode 100755
index 00000000..fbab5033
Binary files /dev/null and b/fpga/bootrom.rv32.img differ
diff --git a/fpga/bootrom.rv64.img b/fpga/bootrom.rv64.img
new file mode 100755
index 00000000..8d4fea05
Binary files /dev/null and b/fpga/bootrom.rv64.img differ
diff --git a/fpga/fpga-shells b/fpga/fpga-shells
index 7d0b79f8..93004b7b 160000
--- a/fpga/fpga-shells
+++ b/fpga/fpga-shells
@@ -1 +1 @@
-Subproject commit 7d0b79f8559b9bcea1bde8d0293576a502a7a896
+Subproject commit 93004b7bd02eb7cc32a25cc1bc40595b93add118
diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c
index f1bdb61e..bc1a68e8 100644
--- a/fpga/src/main/resources/vcu118/sdboot/sd.c
+++ b/fpga/src/main/resources/vcu118/sdboot/sd.c
@@ -22,7 +22,16 @@
#error Must define TL_CLK
#endif
-#define F_CLK TL_CLK
+#define F_CLK (TL_CLK)
+
+// SPI SCLK frequency, in kHz
+// We are using the 25MHz High Speed mode. If this speed is not supported by the
+// SD card, consider changing to the Default Speed mode (12.5 MHz).
+#define SPI_CLK 25000
+
+// SPI clock divisor value
+// @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi
+#define SPI_DIV (((F_CLK * 1000) / SPI_CLK) / 2 - 1)
static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
@@ -79,7 +88,9 @@ static inline void sd_cmd_end(void)
static void sd_poweron(void)
{
long i;
- REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL);
+ // HACK: frequency change
+
+ REG32(spi, SPI_REG_SCKDIV) = SPI_DIV;
REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF;
for (i = 10; i > 0; i--) {
sd_dummy();
@@ -171,12 +182,10 @@ static int copy(void)
dputs("CMD18");
- kprintf("LOADING 0x%xB PAYLOAD\r\n", PAYLOAD_SIZE_B);
+ kprintf("LOADING 0x%x B PAYLOAD\r\n", PAYLOAD_SIZE_B);
kprintf("LOADING ");
- // TODO: Speed up SPI freq. (breaks between these two values)
- //REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL);
- REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL);
+ REG32(spi, SPI_REG_SCKDIV) = SPI_DIV;
if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) {
sd_cmd_end();
return 1;
diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
index 1cf7bfce..7f10b174 100644
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -11,13 +11,14 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem}
// DOC include start: AbstractArty and Rocket
class WithArtyTweaks extends Config(
- new WithArtyResetHarnessBinder ++
+ new WithArtyDebugResetHarnessBinder ++
+ new WithArtyJTAGResetHarnessBinder ++
new WithArtyJTAGHarnessBinder ++
new WithArtyUARTHarnessBinder ++
new WithDebugResetPassthrough ++
@@ -26,8 +27,12 @@ class WithArtyTweaks extends Config(
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.config.WithDTSTimebase(32000) ++
new chipyard.config.WithSystemBusFrequency(32) ++
+ new chipyard.config.WithFrontBusFrequency(32) ++
+ new chipyard.config.WithControlBusFrequency(32) ++
new chipyard.config.WithPeripheryBusFrequency(32) ++
- new testchipip.WithNoSerialTL
+ new chipyard.config.WithControlBusFrequency(32) ++
+ new testchipip.serdes.WithNoSerialTL ++
+ new testchipip.soc.WithNoScratchpads
)
class TinyRocketArtyConfig extends Config(
diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index 1d96cecf..39ddd204 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -11,68 +11,61 @@ import sifive.blocks.devices.pinctrl.{BasePin}
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
-import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
-import chipyard.iobinders.JTAGChipIO
+import chipyard.harness.{HarnessBinder}
+import chipyard.iobinders._
-class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
- (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
- val resetPorts = ports.collect { case b: Bool => b }
- require(resetPorts.size == 2)
+class WithArtyDebugResetHarnessBinder extends HarnessBinder({
+ case (th: Arty35THarness, port: DebugResetPort, chipId: Int) => {
+ th.dut_ndreset := port.io // Debug module reset
+ }
+})
+
+class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
+ case (th: Arty35THarness, port: JTAGResetPort, chipId: Int) => {
+ port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
+ }
+})
+
+class WithArtyJTAGHarnessBinder extends HarnessBinder({
+ case (th: Arty35THarness, port: JTAGPort, chipId: Int) => {
+ val jtag_wire = Wire(new JTAGIO)
+ jtag_wire.TDO.data := port.io.TDO
+ jtag_wire.TDO.driven := true.B
+ port.io.TCK := jtag_wire.TCK
+ port.io.TMS := jtag_wire.TMS
+ port.io.TDI := jtag_wire.TDI
+
+ val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
+
+ JTAGPinsFromPort(io_jtag, jtag_wire)
+
+ io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool
+
+ IOBUF(th.jd_5, io_jtag.TMS)
+ PULLUP(th.jd_5)
+
+ IOBUF(th.jd_4, io_jtag.TDI)
+ PULLUP(th.jd_4)
+
+ IOBUF(th.jd_0, io_jtag.TDO)
+
+ // mimic putting a pullup on this line (part of reset vote)
+ th.SRST_n := IOBUF(th.jd_6)
+ PULLUP(th.jd_6)
+
+ // ignore the po input
+ io_jtag.TCK.i.po.map(_ := DontCare)
+ io_jtag.TDI.i.po.map(_ := DontCare)
+ io_jtag.TMS.i.po.map(_ := DontCare)
+ io_jtag.TDO.i.po.map(_ := DontCare)
+ }
+})
+
+class WithArtyUARTHarnessBinder extends HarnessBinder({
+ case (th: Arty35THarness, port: UARTPort, chipId: Int) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) {
- // Debug module reset
- th.dut_ndreset := resetPorts(0)
-
- // JTAG reset
- resetPorts(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
- }
- }
-})
-
-class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
- (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
- ports.map {
- case j: JTAGChipIO => {
- val jtag_wire = Wire(new JTAGIO)
- jtag_wire.TDO.data := j.TDO
- jtag_wire.TDO.driven := true.B
- j.TCK := jtag_wire.TCK
- j.TMS := jtag_wire.TMS
- j.TDI := jtag_wire.TDI
-
- val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
-
- JTAGPinsFromPort(io_jtag, jtag_wire)
-
- io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool
-
- IOBUF(th.jd_5, io_jtag.TMS)
- PULLUP(th.jd_5)
-
- IOBUF(th.jd_4, io_jtag.TDI)
- PULLUP(th.jd_4)
-
- IOBUF(th.jd_0, io_jtag.TDO)
-
- // mimic putting a pullup on this line (part of reset vote)
- th.SRST_n := IOBUF(th.jd_6)
- PULLUP(th.jd_6)
-
- // ignore the po input
- io_jtag.TCK.i.po.map(_ := DontCare)
- io_jtag.TDI.i.po.map(_ := DontCare)
- io_jtag.TMS.i.po.map(_ := DontCare)
- io_jtag.TDO.i.po.map(_ := DontCare)
- }
- case b: Bool =>
- }
- }
-})
-
-class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
- (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
- withClockAndReset(th.clock_32MHz, th.ck_rst) {
- IOBUF(th.uart_rxd_out, ports.head.txd)
- ports.head.rxd := IOBUF(th.uart_txd_in)
+ IOBUF(th.uart_rxd_out, port.io.txd)
+ port.io.rxd := IOBUF(th.uart_txd_in)
}
}
})
diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala
index da6c7318..eb3185f9 100644
--- a/fpga/src/main/scala/arty/IOBinders.scala
+++ b/fpga/src/main/scala/arty/IOBinders.scala
@@ -5,7 +5,7 @@ import chisel3.experimental.{IO}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
-import chipyard.iobinders.{ComposeIOBinder}
+import chipyard.iobinders.{ComposeIOBinder, DebugResetPort, JTAGResetPort}
class WithDebugResetPassthrough extends ComposeIOBinder({
(system: HasPeripheryDebug) => {
@@ -18,6 +18,6 @@ class WithDebugResetPassthrough extends ComposeIOBinder({
val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
sjtag.reset := io_sjtag_reset
- (Seq(io_ndreset, io_sjtag_reset), Nil)
+ (Seq(DebugResetPort(() => io_ndreset), JTAGResetPort(() => io_sjtag_reset)), Nil)
}
})
diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala
index 2d524fe3..cdb1d4e4 100644
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -9,9 +9,8 @@ import org.chipsalliance.cde.config.{Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.harness.{HasHarnessInstantiators}
-import chipyard.iobinders.{HasIOBinders}
-class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
+class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
// Convert harness resets from Bool to Reset type.
val hReset = Wire(Reset())
hReset := ~ck_rst
diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index 4a0fb293..bb4b8e22 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -12,30 +12,34 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
import sifive.fpgashells.shell.{DesignKey}
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem}
// don't use FPGAShell's DesignKey
class WithNoDesignKey extends Config((site, here, up) => {
- case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
+ case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
})
-class WithArty100TTweaks extends Config(
+// By default, this uses the on-board USB-UART for the TSI-over-UART link
+// The PMODUART HarnessBinder maps the actual UART device to JD pin
+class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
+ new WithArty100TPMODUART ++
new WithArty100TUARTTSI ++
new WithArty100TDDRTL ++
+ new WithArty100TJTAG ++
new WithNoDesignKey ++
- new testchipip.WithUARTTSIClient ++
+ new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
- new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
- new chipyard.config.WithMemoryBusFrequency(50.0) ++
- new chipyard.config.WithFrontBusFrequency(50.0) ++
- new chipyard.config.WithSystemBusFrequency(50.0) ++
- new chipyard.config.WithPeripheryBusFrequency(50.0) ++
+ new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
+ new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
+ new chipyard.config.WithFrontBusFrequency(freqMHz) ++
+ new chipyard.config.WithSystemBusFrequency(freqMHz) ++
+ new chipyard.config.WithPeripheryBusFrequency(freqMHz) ++
+ new chipyard.config.WithControlBusFrequency(freqMHz) ++
+ new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
- new chipyard.config.WithNoDebug ++ // no jtag
- new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
new freechips.rocketchip.subsystem.WithoutTLMonitors)
@@ -45,22 +49,14 @@ class RocketArty100TConfig extends Config(
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.RocketConfig)
-class UART230400RocketArty100TConfig extends Config(
- new WithArty100TUARTTSI(uartBaudRate = 230400) ++
- new RocketArty100TConfig)
-
-class UART460800RocketArty100TConfig extends Config(
- new WithArty100TUARTTSI(uartBaudRate = 460800) ++
- new RocketArty100TConfig)
-
-class UART921600RocketArty100TConfig extends Config(
- new WithArty100TUARTTSI(uartBaudRate = 921600) ++
- new RocketArty100TConfig)
-
-
class NoCoresArty100TConfig extends Config(
new WithArty100TTweaks ++
- new chipyard.config.WithMemoryBusFrequency(50.0) ++
- new chipyard.config.WithPeripheryBusFrequency(50.0) ++ // Match the sbus and pbus frequency
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.NoCoresConfig)
+
+// This will fail to close timing above 50 MHz
+class BringupArty100TConfig extends Config(
+ new WithArty100TSerialTLToGPIO ++
+ new WithArty100TTweaks(freqMHz = 50) ++
+ new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialParams(freqMHz=50)) ++
+ new chipyard.ChipBringupHostConfig)
diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala
index 47ffe7e0..30601124 100644
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -5,19 +5,18 @@ import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink._
-import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
+import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem.{SystemBusKey}
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.blocks.devices.uart._
import chipyard._
import chipyard.harness._
-import chipyard.iobinders.{HasIOBinders}
class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell {
def dp = designParameters
@@ -34,9 +33,6 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
harnessSysPLLNode := clockOverlay.overlayOutput.node
- val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
- val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
-
val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
name = "chip_ddr",
@@ -80,6 +76,9 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
def referenceReset = dutClock.in.head._1.reset
def success = { require(false, "Unused"); false.B }
+ childClock := harnessBinderClock
+ childReset := harnessBinderReset
+
ddrOverlay.mig.module.clock := harnessBinderClock
ddrOverlay.mig.module.reset := harnessBinderReset
ddrBlockDuringReset.module.clock := harnessBinderClock
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index 060e3d8d..7b1640ba 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -1,6 +1,7 @@
package chipyard.fpga.arty100t
import chisel3._
+import chisel3.experimental.{DataMirror, Direction}
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
@@ -11,38 +12,138 @@ import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
import sifive.blocks.devices.pinctrl.{BasePin}
-
-import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
-
+import sifive.fpgashells.shell._
+import sifive.fpgashells.ip.xilinx._
+import sifive.fpgashells.shell.xilinx._
+import sifive.fpgashells.clocks._
import chipyard._
import chipyard.harness._
-import chipyard.iobinders.JTAGChipIO
+import chipyard.iobinders._
+import testchipip.serdes._
-import testchipip._
-
-class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarnessBinder({
- (system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTTSIIO]) => {
- implicit val p = chipyard.iobinders.GetSystemParameters(system)
- require(ports.size <= 1)
+class WithArty100TUARTTSI extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
- ports.map({ port =>
- ath.io_uart_bb.bundle <> port.uart
- ath.other_leds(1) := port.dropped
- ath.other_leds(9) := port.tsi2tl_state(0)
- ath.other_leds(10) := port.tsi2tl_state(1)
- ath.other_leds(11) := port.tsi2tl_state(2)
- ath.other_leds(12) := port.tsi2tl_state(3)
- })
+ val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi")
+ harnessIO <> port.io.uart
+ val packagePinsWithPackageIOs = Seq(
+ ("A9" , IOPin(harnessIO.rxd)),
+ ("D10", IOPin(harnessIO.txd)))
+ packagePinsWithPackageIOs foreach { case (pin, io) => {
+ ath.xdc.addPackagePin(io, pin)
+ ath.xdc.addIOStandard(io, "LVCMOS33")
+ ath.xdc.addIOB(io)
+ } }
+
+ ath.other_leds(1) := port.io.dropped
+ ath.other_leds(9) := port.io.tsi2tl_state(0)
+ ath.other_leds(10) := port.io.tsi2tl_state(1)
+ ath.other_leds(11) := port.io.tsi2tl_state(2)
+ ath.other_leds(12) := port.io.tsi2tl_state(3)
}
})
-class WithArty100TDDRTL extends OverrideHarnessBinder({
- (system: CanHaveMasterTLMemPort, th: HasHarnessInstantiators, ports: Seq[HeterogeneousBag[TLBundle]]) => {
- require(ports.size == 1)
+
+class WithArty100TDDRTL extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val bundles = artyTh.ddrClient.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
- ddrClientBundle <> ports.head
+ ddrClientBundle <> port.io
+ }
+})
+
+// Uses PMOD JA/JB
+class WithArty100TSerialTLToGPIO extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) => {
+ val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+ val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
+ harnessIO <> port.io
+
+ harnessIO match {
+ case io: DecoupledSerialIO => {
+ val clkIO = io match {
+ case io: InternalSyncSerialIO => IOPin(io.clock_out)
+ case io: ExternalSyncSerialIO => IOPin(io.clock_in)
+ }
+ val packagePinsWithPackageIOs = Seq(
+ ("G13", clkIO),
+ ("B11", IOPin(io.out.valid)),
+ ("A11", IOPin(io.out.ready)),
+ ("D12", IOPin(io.in.valid)),
+ ("D13", IOPin(io.in.ready)),
+ ("B18", IOPin(io.out.bits, 0)),
+ ("A18", IOPin(io.out.bits, 1)),
+ ("K16", IOPin(io.out.bits, 2)),
+ ("E15", IOPin(io.out.bits, 3)),
+ ("E16", IOPin(io.in.bits, 0)),
+ ("D15", IOPin(io.in.bits, 1)),
+ ("C15", IOPin(io.in.bits, 2)),
+ ("J17", IOPin(io.in.bits, 3))
+ )
+ packagePinsWithPackageIOs foreach { case (pin, io) => {
+ artyTh.xdc.addPackagePin(io, pin)
+ artyTh.xdc.addIOStandard(io, "LVCMOS33")
+ }}
+
+ // Don't add IOB to the clock, if its an input
+ io match {
+ case io: InternalSyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
+ artyTh.xdc.addIOB(io)
+ }}
+ case io: ExternalSyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
+ artyTh.xdc.addIOB(io)
+ }}
+ }
+
+ artyTh.sdc.addClock("ser_tl_clock", clkIO, 100)
+ artyTh.sdc.addGroup(pins = Seq(clkIO))
+ artyTh.xdc.clockDedicatedRouteFalse(clkIO)
+ }
+ }
+ }
+})
+
+// Maps the UART device to the on-board USB-UART
+class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => {
+ val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+ val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
+ harnessIO <> port.io
+ val packagePinsWithPackageIOs = Seq(
+ (rxdPin, IOPin(harnessIO.rxd)),
+ (txdPin, IOPin(harnessIO.txd)))
+ packagePinsWithPackageIOs foreach { case (pin, io) => {
+ ath.xdc.addPackagePin(io, pin)
+ ath.xdc.addIOStandard(io, "LVCMOS33")
+ ath.xdc.addIOB(io)
+ } }
+ }
+})
+
+// Maps the UART device to PMOD JD pins 3/7
+class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
+
+class WithArty100TJTAG extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => {
+ val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+ val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
+ harnessIO <> port.io
+
+ ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
+ ath.sdc.addGroup(clocks = Seq("JTCK"))
+ ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK))
+ val packagePinsWithPackageIOs = Seq(
+ ("F4", IOPin(harnessIO.TCK)),
+ ("D2", IOPin(harnessIO.TMS)),
+ ("E2", IOPin(harnessIO.TDI)),
+ ("D4", IOPin(harnessIO.TDO))
+ )
+ packagePinsWithPackageIOs foreach { case (pin, io) => {
+ ath.xdc.addPackagePin(io, pin)
+ ath.xdc.addIOStandard(io, "LVCMOS33")
+ ath.xdc.addPullup(io)
+ } }
}
})
diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala
new file mode 100644
index 00000000..ce8fbae8
--- /dev/null
+++ b/fpga/src/main/scala/nexysvideo/Configs.scala
@@ -0,0 +1,74 @@
+// See LICENSE for license details.
+package chipyard.fpga.nexysvideo
+
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.system._
+import freechips.rocketchip.tile._
+
+import sifive.blocks.devices.uart._
+import sifive.fpgashells.shell.{DesignKey}
+
+import testchipip.serdes.{SerialTLKey}
+
+import chipyard.{BuildSystem}
+
+// don't use FPGAShell's DesignKey
+class WithNoDesignKey extends Config((site, here, up) => {
+ case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
+})
+
+// DOC include start: WithNexysVideoTweaks and Rocket
+class WithNexysVideoTweaks extends Config(
+ new WithNexysVideoUARTTSI ++
+ new WithNexysVideoDDRTL ++
+ new WithNoDesignKey ++
+ new testchipip.tsi.WithUARTTSIClient ++
+ new chipyard.harness.WithSerialTLTiedOff ++
+ new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
+ new chipyard.config.WithMemoryBusFrequency(50.0) ++
+ new chipyard.config.WithFrontBusFrequency(50.0) ++
+ new chipyard.config.WithSystemBusFrequency(50.0) ++
+ new chipyard.config.WithPeripheryBusFrequency(50.0) ++
+ new chipyard.config.WithControlBusFrequency(50.0) ++
+ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
+ new chipyard.clocking.WithPassthroughClockGenerator ++
+ new chipyard.config.WithNoDebug ++ // no jtag
+ new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
+ new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
+ new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(512) << 20) ++ // 512mb on Nexys Video
+ new freechips.rocketchip.subsystem.WithoutTLMonitors)
+
+class RocketNexysVideoConfig extends Config(
+ new WithNexysVideoTweaks ++
+ new chipyard.config.WithBroadcastManager ++ // no l2
+ new chipyard.RocketConfig)
+// DOC include end: WithNexysVideoTweaks and Rocket
+
+// DOC include start: WithTinyNexysVideoTweaks and Rocket
+class WithTinyNexysVideoTweaks extends Config(
+ new WithNexysVideoUARTTSI ++
+ new WithNoDesignKey ++
+ new sifive.fpgashells.shell.xilinx.WithNoNexysVideoShellDDR ++ // no DDR
+ new testchipip.tsi.WithUARTTSIClient ++
+ new chipyard.harness.WithSerialTLTiedOff ++
+ new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
+ new chipyard.config.WithMemoryBusFrequency(50.0) ++
+ new chipyard.config.WithFrontBusFrequency(50.0) ++
+ new chipyard.config.WithSystemBusFrequency(50.0) ++
+ new chipyard.config.WithPeripheryBusFrequency(50.0) ++
+ new chipyard.config.WithControlBusFrequency(50.0) ++
+ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
+ new chipyard.clocking.WithPassthroughClockGenerator ++
+ new chipyard.config.WithNoDebug ++ // no jtag
+ new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
+ new freechips.rocketchip.subsystem.WithoutTLMonitors)
+
+class TinyRocketNexysVideoConfig extends Config(
+ new WithTinyNexysVideoTweaks ++
+ new chipyard.config.WithBroadcastManager ++ // no l2
+ new chipyard.TinyRocketConfig)
+ // DOC include end: WithTinyNexysVideoTweaks and Rocket
diff --git a/fpga/src/main/scala/nexysvideo/Harness.scala b/fpga/src/main/scala/nexysvideo/Harness.scala
new file mode 100644
index 00000000..c9583f0e
--- /dev/null
+++ b/fpga/src/main/scala/nexysvideo/Harness.scala
@@ -0,0 +1,91 @@
+// See LICENSE for license details.
+package chipyard.fpga.nexysvideo
+
+import chisel3._
+import chisel3.util._
+import freechips.rocketchip.diplomacy._
+import org.chipsalliance.cde.config.{Parameters}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.subsystem.{SystemBusKey}
+import freechips.rocketchip.prci._
+import sifive.fpgashells.shell.xilinx._
+import sifive.fpgashells.shell._
+import sifive.fpgashells.clocks._
+
+import sifive.blocks.devices.uart._
+
+import chipyard._
+import chipyard.harness._
+
+class NexysVideoHarness(override implicit val p: Parameters) extends NexysVideoShell {
+ def dp = designParameters
+
+ val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
+ val harnessSysPLL = dp(PLLFactoryKey)
+ val harnessSysPLLNode = harnessSysPLL()
+ val dutFreqMHz = (dp(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toInt
+ val dutClock = ClockSinkNode(freqMHz = dutFreqMHz)
+ println(s"NexysVideo FPGA Base Clock Freq: ${dutFreqMHz} MHz")
+ val dutWrangler = LazyModule(new ResetWrangler())
+ val dutGroup = ClockGroup()
+ dutClock := dutWrangler.node := dutGroup := harnessSysPLLNode
+
+ harnessSysPLLNode := clockOverlay.overlayOutput.node
+
+ val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
+ val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
+
+ // Optional DDR
+ val ddrOverlay = if (p(NexysVideoShellDDR)) Some(dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRNexysVideoPlacedOverlay]) else None
+ val ddrClient = if (p(NexysVideoShellDDR)) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
+ name = "chip_ddr",
+ sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
+ )))))) else None
+ val ddrBlockDuringReset = if (p(NexysVideoShellDDR)) Some(LazyModule(new TLBlockDuringReset(4))) else None
+ if (p(NexysVideoShellDDR)) { ddrOverlay.get.overlayOutput.ddr := ddrBlockDuringReset.get.node := ddrClient.get }
+
+ val ledOverlays = dp(LEDOverlayKey).map(_.place(LEDDesignInput()))
+ val all_leds = ledOverlays.map(_.overlayOutput.led)
+ val status_leds = all_leds.take(2)
+ val other_leds = all_leds.drop(2)
+
+
+ override lazy val module = new HarnessLikeImpl
+
+ class HarnessLikeImpl extends Impl with HasHarnessInstantiators {
+ all_leds.foreach(_ := DontCare)
+ clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin
+
+ val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock
+
+ // Blink the status LEDs for sanity
+ withClockAndReset(clk_100mhz, dutClock.in.head._1.reset) {
+ val period = (BigInt(100) << 20) / status_leds.size
+ val counter = RegInit(0.U(log2Ceil(period).W))
+ val on = RegInit(0.U(log2Ceil(status_leds.size).W))
+ status_leds.zipWithIndex.map { case (o,s) => o := on === s.U }
+ counter := Mux(counter === (period-1).U, 0.U, counter + 1.U)
+ when (counter === 0.U) {
+ on := Mux(on === (status_leds.size-1).U, 0.U, on + 1.U)
+ }
+ }
+
+ other_leds(0) := resetPin
+
+ harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)
+
+ def referenceClockFreqMHz = dutFreqMHz
+ def referenceClock = dutClock.in.head._1.clock
+ def referenceReset = dutClock.in.head._1.reset
+ def success = { require(false, "Unused"); false.B }
+
+ if (p(NexysVideoShellDDR)) {
+ ddrOverlay.get.mig.module.clock := harnessBinderClock
+ ddrOverlay.get.mig.module.reset := harnessBinderReset
+ ddrBlockDuringReset.get.module.clock := harnessBinderClock
+ ddrBlockDuringReset.get.module.reset := harnessBinderReset.asBool || !ddrOverlay.get.mig.module.io.port.init_calib_complete
+ }
+
+ instantiateChipTops()
+ }
+}
diff --git a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
new file mode 100644
index 00000000..29deeadb
--- /dev/null
+++ b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
@@ -0,0 +1,37 @@
+// See LICENSE for license details.
+package chipyard.fpga.nexysvideo
+
+import chisel3._
+
+import freechips.rocketchip.subsystem.{PeripheryBusKey}
+import freechips.rocketchip.tilelink.{TLBundle}
+import freechips.rocketchip.util.{HeterogeneousBag}
+import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
+
+import sifive.blocks.devices.uart.{UARTParams}
+
+import chipyard._
+import chipyard.harness._
+import chipyard.iobinders._
+
+class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
+ val nexysvideoth = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
+ nexysvideoth.io_uart_bb.bundle <> port.io.uart
+ nexysvideoth.other_leds(1) := port.io.dropped
+ nexysvideoth.other_leds(2) := port.io.tsi2tl_state(0)
+ nexysvideoth.other_leds(3) := port.io.tsi2tl_state(1)
+ nexysvideoth.other_leds(4) := port.io.tsi2tl_state(2)
+ nexysvideoth.other_leds(5) := port.io.tsi2tl_state(3)
+ }
+})
+
+class WithNexysVideoDDRTL extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
+ val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
+ val bundles = nexysTh.ddrClient.get.out.map(_._1)
+ val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
+ bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
+ ddrClientBundle <> port.io
+ }
+})
diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala
index 55ce8e06..4842434e 100644
--- a/fpga/src/main/scala/vc707/Configs.scala
+++ b/fpga/src/main/scala/vc707/Configs.scala
@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem, ExtTLMem}
import chipyard.harness._
@@ -35,7 +35,7 @@ class WithSystemModifications extends Config((site, here, up) => {
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin")
}
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size (note the size)
- case SerialTLKey => None // remove serialized tl port
+ case SerialTLKey => Nil // remove serialized tl port
})
class WithVC707Tweaks extends Config (
@@ -45,6 +45,8 @@ class WithVC707Tweaks extends Config (
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
+ new chipyard.config.WithControlBusFrequency(50.0) ++
+ new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new WithFPGAFrequency(50) ++ // default 50MHz freq
@@ -53,10 +55,6 @@ class WithVC707Tweaks extends Config (
new WithVC707UARTHarnessBinder ++
new WithVC707SPISDCardHarnessBinder ++
new WithVC707DDRMemHarnessBinder ++
- // io binders
- new WithUARTIOPassthrough ++
- new WithSPIIOPassthrough ++
- new WithTLIOPassthrough ++
// other configuration
new WithDefaultPeripherals ++
new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
@@ -78,8 +76,11 @@ class BoomVC707Config extends Config (
)
class WithFPGAFrequency(fMHz: Double) extends Config (
- new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
- new chipyard.config.WithMemoryBusFrequency(fMHz)
+ new chipyard.config.WithPeripheryBusFrequency(fMHz) ++
+ new chipyard.config.WithMemoryBusFrequency(fMHz) ++
+ new chipyard.config.WithSystemBusFrequency(fMHz) ++
+ new chipyard.config.WithControlBusFrequency(fMHz) ++
+ new chipyard.config.WithFrontBusFrequency(fMHz)
)
class WithFPGAFreq25MHz extends WithFPGAFrequency(25)
diff --git a/fpga/src/main/scala/vc707/HarnessBinders.scala b/fpga/src/main/scala/vc707/HarnessBinders.scala
index cf5bbb5e..d08fba76 100644
--- a/fpga/src/main/scala/vc707/HarnessBinders.scala
+++ b/fpga/src/main/scala/vc707/HarnessBinders.scala
@@ -11,36 +11,29 @@ import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{HasSystemXilinxVC707PCIeX1ModuleImp, XilinxVC707PCIeX1IO}
import chipyard.{CanHaveMasterTLMemPort}
-import chipyard.harness.{OverrideHarnessBinder}
+import chipyard.harness.{HarnessBinder}
+import chipyard.iobinders._
/*** UART ***/
-class WithVC707UARTHarnessBinder extends OverrideHarnessBinder({
- (system: HasPeripheryUARTModuleImp, th: BaseModule, ports: Seq[UARTPortIO]) => {
- th match { case vc707th: VC707FPGATestHarnessImp => {
- vc707th.vc707Outer.io_uart_bb.bundle <> ports.head
- }}
+class WithVC707UARTHarnessBinder extends HarnessBinder({
+ case (th: VC707FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
+ th.vc707Outer.io_uart_bb.bundle <> port.io
}
})
/*** SPI ***/
-class WithVC707SPISDCardHarnessBinder extends OverrideHarnessBinder({
- (system: HasPeripherySPI, th: BaseModule, ports: Seq[SPIPortIO]) => {
- th match { case vc707th: VC707FPGATestHarnessImp => {
- vc707th.vc707Outer.io_spi_bb.bundle <> ports.head
- }}
+class WithVC707SPISDCardHarnessBinder extends HarnessBinder({
+ case (th: VC707FPGATestHarnessImp, port: SPIPort, chipId: Int) => {
+ th.vc707Outer.io_spi_bb.bundle <> port.io
}
})
/*** Experimental DDR ***/
-class WithVC707DDRMemHarnessBinder extends OverrideHarnessBinder({
- (system: CanHaveMasterTLMemPort, th: BaseModule, ports: Seq[HeterogeneousBag[TLBundle]]) => {
- th match { case vc707th: VC707FPGATestHarnessImp => {
- require(ports.size == 1)
-
- val bundles = vc707th.vc707Outer.ddrClient.out.map(_._1)
- val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
- bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
- ddrClientBundle <> ports.head
- }}
+class WithVC707DDRMemHarnessBinder extends HarnessBinder({
+ case (th: VC707FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
+ val bundles = th.vc707Outer.ddrClient.out.map(_._1)
+ val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
+ bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
+ ddrClientBundle <> port.io
}
})
diff --git a/fpga/src/main/scala/vc707/IOBinders.scala b/fpga/src/main/scala/vc707/IOBinders.scala
deleted file mode 100644
index ad485571..00000000
--- a/fpga/src/main/scala/vc707/IOBinders.scala
+++ /dev/null
@@ -1,53 +0,0 @@
-package chipyard.fpga.vc707
-
-import chisel3._
-import chisel3.experimental.{IO, DataMirror}
-
-import freechips.rocketchip.diplomacy.{ResourceBinding, Resource, ResourceAddress, InModuleBody}
-import freechips.rocketchip.subsystem.{BaseSubsystem}
-import freechips.rocketchip.util.{HeterogeneousBag}
-import freechips.rocketchip.tilelink.{TLBundle}
-
-import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp}
-import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice}
-import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{HasSystemXilinxVC707PCIeX1ModuleImp}
-
-import chipyard.{CanHaveMasterTLMemPort}
-import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder}
-
-class WithUARTIOPassthrough extends OverrideIOBinder({
- (system: HasPeripheryUARTModuleImp) => {
- val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") }
- (io_uart_pins_temp zip system.uart).map { case (io, sysio) =>
- io <> sysio
- }
- (io_uart_pins_temp, Nil)
- }
-})
-
-class WithSPIIOPassthrough extends OverrideLazyIOBinder({
- (system: HasPeripherySPI) => {
- // attach resource to 1st SPI
- ResourceBinding {
- Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
- }
-
- InModuleBody {
- system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => {
- val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") }
- (io_spi_pins_temp zip system.spi).map { case (io, sysio) =>
- io <> sysio
- }
- (io_spi_pins_temp, Nil)
- } }
- }
- }
-})
-
-class WithTLIOPassthrough extends OverrideIOBinder({
- (system: CanHaveMasterTLMemPort) => {
- val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
- io_tl_mem_pins_temp <> system.mem_tl
- (Seq(io_tl_mem_pins_temp), Nil)
- }
-})
diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala
index 008e2399..317dedf6 100644
--- a/fpga/src/main/scala/vc707/TestHarness.scala
+++ b/fpga/src/main/scala/vc707/TestHarness.scala
@@ -7,18 +7,18 @@ import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem.{SystemBusKey}
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
+import freechips.rocketchip.prci._
import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks.{PLLFactoryKey}
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import chipyard._
-import chipyard.iobinders.{HasIOBinders}
import chipyard.harness._
class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer =>
@@ -88,6 +88,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
}
class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
+ override def provideImplicitClockToLazyChildren = true
val vc707Outer = _outer
val reset = IO(Input(Bool())).suggestName("reset")
diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala
index bd48fb4e..ff46deee 100644
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
import chipyard._
import chipyard.harness._
@@ -36,7 +36,7 @@ class WithSystemModifications extends Config((site, here, up) => {
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
}
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size
- case SerialTLKey => None // remove serialized tl port
+ case SerialTLKey => Nil // remove serialized tl port
})
// DOC include start: AbstractVCU118 and Rocket
@@ -46,15 +46,14 @@ class WithVCU118Tweaks extends Config(
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithMemoryBusFrequency(100) ++
new chipyard.config.WithSystemBusFrequency(100) ++
+ new chipyard.config.WithControlBusFrequency(100) ++
new chipyard.config.WithPeripheryBusFrequency(100) ++
+ new chipyard.config.WithControlBusFrequency(100) ++
new WithFPGAFrequency(100) ++ // default 100MHz freq
// harness binders
new WithUART ++
new WithSPISDCard ++
new WithDDRMem ++
- // io binders
- new WithUARTIOPassthrough ++
- new WithSPIIOPassthrough ++
// other configuration
new WithDefaultPeripherals ++
new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
@@ -79,7 +78,9 @@ class BoomVCU118Config extends Config(
class WithFPGAFrequency(fMHz: Double) extends Config(
new chipyard.harness.WithHarnessBinderClockFreqMHz(fMHz) ++
new chipyard.config.WithSystemBusFrequency(fMHz) ++
- new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
+ new chipyard.config.WithPeripheryBusFrequency(fMHz) ++
+ new chipyard.config.WithControlBusFrequency(fMHz) ++
+ new chipyard.config.WithFrontBusFrequency(fMHz) ++
new chipyard.config.WithMemoryBusFrequency(fMHz)
)
diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala
index 02669b79..473a015d 100644
--- a/fpga/src/main/scala/vcu118/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala
@@ -5,7 +5,7 @@ import chisel3._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
-
+import freechips.rocketchip.prci._
import sifive.fpgashells.shell._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell.xilinx._
@@ -79,7 +79,7 @@ class DDR2VCU118PlacedOverlay(val shell: VCU118FPGATestHarness, name: String, va
ui.reset := /*!port.mmcm_locked ||*/ port.c0_ddr4_ui_clk_sync_rst
port.c0_sys_clk_i := sys.clock.asUInt
port.sys_rst := sys.reset // pllReset
- port.c0_ddr4_aresetn := !ar.reset
+ port.c0_ddr4_aresetn := !(ar.reset.asBool)
// This was just copied from the SiFive example, but it's hard to follow.
// The pins are emitted in the following order:
diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala
index f17b654f..c03f551f 100644
--- a/fpga/src/main/scala/vcu118/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala
@@ -11,35 +11,28 @@ import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import chipyard._
import chipyard.harness._
+import chipyard.iobinders._
/*** UART ***/
-class WithUART extends OverrideHarnessBinder({
- (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[UARTPortIO]) => {
- th match { case vcu118th: VCU118FPGATestHarnessImp => {
- vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head
- } }
+class WithUART extends HarnessBinder({
+ case (th: VCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
+ th.vcu118Outer.io_uart_bb.bundle <> port.io
}
})
/*** SPI ***/
-class WithSPISDCard extends OverrideHarnessBinder({
- (system: HasPeripherySPI, th: BaseModule with HasHarnessInstantiators, ports: Seq[SPIPortIO]) => {
- th match { case vcu118th: VCU118FPGATestHarnessImp => {
- vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head
- } }
+class WithSPISDCard extends HarnessBinder({
+ case (th: VCU118FPGATestHarnessImp, port: SPIPort, chipId: Int) => {
+ th.vcu118Outer.io_spi_bb.bundle <> port.io
}
})
/*** Experimental DDR ***/
-class WithDDRMem extends OverrideHarnessBinder({
- (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessInstantiators, ports: Seq[HeterogeneousBag[TLBundle]]) => {
- th match { case vcu118th: VCU118FPGATestHarnessImp => {
- require(ports.size == 1)
-
- val bundles = vcu118th.vcu118Outer.ddrClient.out.map(_._1)
- val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
- bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
- ddrClientBundle <> ports.head
- } }
+class WithDDRMem extends HarnessBinder({
+ case (th: VCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
+ val bundles = th.vcu118Outer.ddrClient.out.map(_._1)
+ val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
+ bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
+ ddrClientBundle <> port.io
}
})
diff --git a/fpga/src/main/scala/vcu118/IOBinders.scala b/fpga/src/main/scala/vcu118/IOBinders.scala
deleted file mode 100644
index 279f9865..00000000
--- a/fpga/src/main/scala/vcu118/IOBinders.scala
+++ /dev/null
@@ -1,44 +0,0 @@
-package chipyard.fpga.vcu118
-
-import chisel3._
-import chisel3.experimental.{IO, DataMirror}
-
-import freechips.rocketchip.diplomacy.{ResourceBinding, Resource, ResourceAddress, InModuleBody}
-import freechips.rocketchip.subsystem.{BaseSubsystem}
-import freechips.rocketchip.util.{HeterogeneousBag}
-import freechips.rocketchip.tilelink.{TLBundle}
-
-import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp}
-import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice}
-
-import chipyard.{CanHaveMasterTLMemPort}
-import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder}
-
-class WithUARTIOPassthrough extends OverrideIOBinder({
- (system: HasPeripheryUARTModuleImp) => {
- val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") }
- (io_uart_pins_temp zip system.uart).map { case (io, sysio) =>
- io <> sysio
- }
- (io_uart_pins_temp, Nil)
- }
-})
-
-class WithSPIIOPassthrough extends OverrideLazyIOBinder({
- (system: HasPeripherySPI) => {
- // attach resource to 1st SPI
- ResourceBinding {
- Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
- }
-
- InModuleBody {
- system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => {
- val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") }
- (io_spi_pins_temp zip system.spi).map { case (io, sysio) =>
- io <> sysio
- }
- (io_spi_pins_temp, Nil)
- } }
- }
- }
-})
diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala
index 6bffc9a7..78dee3e6 100644
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -8,17 +8,16 @@ import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
import freechips.rocketchip.subsystem.{SystemBusKey}
-
+import freechips.rocketchip.prci._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import chipyard._
-import chipyard.iobinders.{HasIOBinders}
import chipyard.harness._
class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays {
@@ -91,6 +90,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
}
class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
+ override def provideImplicitClockToLazyChildren = true
val vcu118Outer = _outer
val reset = IO(Input(Bool())).suggestName("reset")
diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala
index bff715dc..0760fa72 100644
--- a/fpga/src/main/scala/vcu118/bringup/Configs.scala
+++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala
@@ -15,11 +15,12 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
-import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
+import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
import chipyard.{BuildSystem}
import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size}
+import chipyard.iobinders.{WithGPIOPunchthrough}
class WithBringupPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L)))
@@ -80,8 +81,7 @@ class WithBringupAdditions extends Config(
new WithBringupGPIO ++
new WithBringupTSIHost ++
new WithTSITLIOPassthrough ++
- new WithI2CIOPassthrough ++
- new WithGPIOIOPassthrough ++
+ new WithGPIOPunchthrough ++
new WithBringupPeripherals ++
new WithBringupVCU118System)
diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
index 4b9604f9..a52a1b5e 100644
--- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
@@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.clocks._
import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
-import testchipip.{TSIHostWidgetIO}
+import testchipip.tsi.{TSIHostWidgetIO}
import chipyard.fpga.vcu118.{FMCPMap}
diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
index c5401d32..e4efbdc7 100644
--- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
+++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
@@ -17,7 +17,7 @@ import chipyard.{DigitalTop, DigitalTopModule}
class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop
with sifive.blocks.devices.i2c.HasPeripheryI2C
- with testchipip.HasPeripheryTSIHostWidget
+ with testchipip.tsi.HasPeripheryTSIHostWidget
{
override lazy val module = new BringupVCU118DigitalTopModule(this)
}
diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
index 97d62ae2..27933bf6 100644
--- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
@@ -11,59 +11,41 @@ import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort}
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
-import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.harness._
+import chipyard.iobinders._
/*** UART ***/
-class WithBringupUART extends ComposeHarnessBinder({
- (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[UARTPortIO]) => {
- th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
- require(ports.size == 2)
-
- vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last
- } }
+class WithBringupUART extends HarnessBinder({
+ case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
+ th.bringupOuter.io_fmc_uart_bb.bundle <> port.io
}
})
/*** I2C ***/
-class WithBringupI2C extends OverrideHarnessBinder({
- (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[I2CPort]) => {
- th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
- require(ports.size == 1)
-
- vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head
- } }
+class WithBringupI2C extends HarnessBinder({
+ case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort, chipId: Int) => {
+ th.bringupOuter.io_i2c_bb.bundle <> port.io
}
})
/*** GPIO ***/
-class WithBringupGPIO extends OverrideHarnessBinder({
- (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[GPIOPortIO]) => {
- th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
- (vcu118th.bringupOuter.io_gpio_bb zip ports).map { case (bb_io, dut_io) =>
- bb_io.bundle <> dut_io
- }
- } }
+class WithBringupGPIO extends HarnessBinder({
+ case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort, chipId: Int) => {
+ th.bringupOuter.io_gpio_bb(port.pinId).bundle <> port.io
}
})
/*** TSI Host Widget ***/
-class WithBringupTSIHost extends OverrideHarnessBinder({
- (system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessInstantiators, ports: Seq[Data]) => {
- th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
- require(ports.size == 2) // 1st goes to the TL mem, 2nd goes to the serial link
-
- ports.head match { case tlPort: HeterogeneousBag[TLBundle] =>
- val tsiBundles = vcu118th.bringupOuter.tsiDdrClient.out.map(_._1)
- val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
- tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
- tsiDdrClientBundle <> tlPort
- }
-
- ports.last match { case serialPort: TSIHostWidgetIO =>
- vcu118th.bringupOuter.io_tsi_serial_bb.bundle <> serialPort
- }
- } }
+class WithBringupTSIHost extends HarnessBinder({
+ case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
+ val tsiBundles = th.bringupOuter.tsiDdrClient.out.map(_._1)
+ val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
+ tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
+ tsiDdrClientBundle <> port.io
+ }
+ case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort, chipId: Int) => {
+ th.bringupOuter.io_tsi_serial_bb.bundle <> port.io
}
})
diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
index 87763cde..24b7aa9a 100644
--- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
+++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
@@ -9,29 +9,12 @@ import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
-import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
-import chipyard.iobinders.{OverrideIOBinder}
+import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
-class WithGPIOIOPassthrough extends OverrideIOBinder({
- (system: HasPeripheryGPIOModuleImp) => {
- val io_gpio_pins_temp = system.gpio.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"gpio_$i") }
- (io_gpio_pins_temp zip system.gpio).map { case (io, sysio) =>
- io <> sysio
- }
- (io_gpio_pins_temp, Nil)
- }
-})
-
-class WithI2CIOPassthrough extends OverrideIOBinder({
- (system: HasPeripheryI2CModuleImp) => {
- val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") }
- (io_i2c_pins_temp zip system.i2c).map { case (io, sysio) =>
- io <> sysio
- }
- (io_i2c_pins_temp, Nil)
- }
-})
+case class TSIHostWidgetPort(val getIO: () => TSIHostWidgetIO)
+ extends Port[TSIHostWidgetIO]
class WithTSITLIOPassthrough extends OverrideIOBinder({
(system: HasPeripheryTSIHostWidget) => {
@@ -42,6 +25,6 @@ class WithTSITLIOPassthrough extends OverrideIOBinder({
require(system.tsiSerial.size == 1)
val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial")
io_tsi_serial_pins_temp <> system.tsiSerial.head
- (Seq(io_tsi_tl_mem_pins_temp, io_tsi_serial_pins_temp), Nil)
+ (Seq(TLMemPort(() => io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(() => io_tsi_serial_pins_temp)), Nil)
}
})
diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
index 12398d8f..3de1e595 100644
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -5,7 +5,7 @@ import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
-
+import freechips.rocketchip.prci._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell._
@@ -16,7 +16,8 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.gpio._
-import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO}
+import testchipip.util.{TLSinkSetter}
import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}
diff --git a/generators/bar-fetchers b/generators/bar-fetchers
index a5bd985d..12d1506f 160000
--- a/generators/bar-fetchers
+++ b/generators/bar-fetchers
@@ -1 +1 @@
-Subproject commit a5bd985d29b07940e326d78964b370fa1cefec71
+Subproject commit 12d1506f610048906d2407b40a706923cbe6571e
diff --git a/generators/boom b/generators/boom
index 96da674b..9459af0c 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 96da674bc97955e7fa068f0a9a1d0a7a479d1d0b
+Subproject commit 9459af0c1f6847f8411622dac770ac78fe10847c
diff --git a/generators/caliptra-aes-acc b/generators/caliptra-aes-acc
new file mode 160000
index 00000000..8bcd6b6b
--- /dev/null
+++ b/generators/caliptra-aes-acc
@@ -0,0 +1 @@
+Subproject commit 8bcd6b6bc118e7bb493ed7cf2fed0472624f9093
diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc
index 3b14079b..dd02d55e 100644
--- a/generators/chipyard/src/main/resources/csrc/spiketile.cc
+++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc
@@ -12,7 +12,7 @@
#if __has_include("spiketile_tsi.h")
#define SPIKETILE_HTIF_TSI
-extern htif_t* tsi;
+extern std::map tsis;
#endif
#if __has_include("spiketile_dtm.h")
#define SPIKETILE_HTIF_DTM
@@ -346,8 +346,8 @@ extern "C" void spike_tile(int hartid, char* isa,
chipyard_simif_t* simif = tile->simif;
processor_t* proc = tile->proc;
#if defined(SPIKETILE_HTIF_TSI)
- if (!simif->htif && tsi)
- simif->htif = tsi;
+ if (!simif->htif && tsis.size() > 0 && tsis[0])
+ simif->htif = tsis[0];
#endif
#if defined(SPIKETILE_HTIF_DTM)
if (!simif->htif && dtm)
@@ -447,18 +447,6 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways,
use_stq(false),
htif(nullptr),
fast_clint(false),
- cfg(std::make_pair(0, 0),
- nullptr,
- isastr,
- "MSU",
- "vlen:128,elen:64",
- false,
- endianness_little,
- pmpregions,
- std::vector(),
- std::vector(),
- false,
- 0),
accessed_tofrom_host(false),
icache_ways(icache_ways),
icache_sets(icache_sets),
@@ -470,6 +458,19 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways,
mmio_inflight(false)
{
+ cfg.initrd_bounds = std::make_pair(0, 0);
+ cfg.bootargs = nullptr;
+ cfg.isa = isastr;
+ cfg.priv = "MSU";
+ cfg.varch = "vlen:128,elen:64";
+ cfg.misaligned = false;
+ cfg.endianness = endianness_little;
+ cfg.pmpregions = pmpregions;
+ cfg.mem_layout = std::vector();
+ cfg.hartids = std::vector();
+ cfg.explicit_hartids = false;
+ cfg.trigger_count = 0;
+
icache.resize(icache_ways);
for (auto &w : icache) {
w.resize(icache_sets);
diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala
index 150221b6..d80d71af 100644
--- a/generators/chipyard/src/main/scala/ChipTop.scala
+++ b/generators/chipyard/src/main/scala/ChipTop.scala
@@ -5,10 +5,9 @@ import chisel3._
import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
-import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
-import freechips.rocketchip.util.{ResetCatchAndSync}
+import freechips.rocketchip.util.{DontTouch}
import chipyard.iobinders._
import barstools.iocell.chisel._
@@ -31,5 +30,5 @@ class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
// of ChipTop (ex: ClockGroup) do not receive clock or reset.
// However. anonymous children of ChipTop should not need an implicit Clock or Reset
// anyways, they probably need to be explicitly clocked.
- lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) { }
+ lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) with DontTouch { }
}
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index 1316d786..d00a26ce 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -13,13 +13,14 @@ import freechips.rocketchip.devices.tilelink._
// DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends ChipyardSystem
- with testchipip.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
- with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
- with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register
- with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
- with testchipip.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
- with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
- with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
+ with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
+ with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
+ with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register
+ with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
+ with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
+ with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
+ with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
+ with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs
with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
@@ -39,6 +40,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution
+ with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
{
@@ -46,7 +48,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
}
class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
- with testchipip.CanHaveTraceIOModuleImp
with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index fc822c22..97866c50 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -2,7 +2,7 @@ package chipyard
import chisel3._
import chisel3.util._
-import chisel3.experimental.{IntParam, StringParam, IO}
+import chisel3.experimental.{IntParam, StringParam}
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
@@ -77,14 +77,15 @@ case class SpikeTileAttachParams(
}
case class SpikeTileParams(
- hartId: Int = 0,
+ tileId: Int = 0,
val core: SpikeCoreParams = SpikeCoreParams(),
icacheParams: ICacheParams = ICacheParams(nWays = 32),
dcacheParams: DCacheParams = DCacheParams(nWays = 32),
tcmParams: Option[MasterPortParams] = None // tightly coupled memory
) extends InstantiableTileParams[SpikeTile]
{
- val name = Some("spike_tile")
+ val baseName = "spike_tile"
+ val uniqueName = s"${baseName}_$tileId"
val beuAddr = None
val blockerCtrlAddr = None
val btb = None
@@ -92,7 +93,7 @@ case class SpikeTileParams(
val dcache = Some(dcacheParams)
val icache = Some(icacheParams)
val clockSinkParams = ClockSinkParameters()
- def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): SpikeTile = {
+ def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): SpikeTile = {
new SpikeTile(this, crossing, lookup)
}
}
@@ -106,11 +107,11 @@ class SpikeTile(
with SourcesExternalNotifications
{
// Private constructor ensures altered LazyModule.p is used implicitly
- def this(params: SpikeTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
+ def this(params: SpikeTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)
// Required TileLink nodes
- val intOutwardNode = IntIdentityNode()
+ val intOutwardNode = None
val masterNode = visibilityNode
val slaveNode = TLIdentityNode()
@@ -129,21 +130,21 @@ class SpikeTile(
}
ResourceBinding {
- Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
+ Resource(cpuDevice, "reg").bind(ResourceAddress(tileId))
}
val icacheNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1),
- name = s"Core ${staticIdForMetadataUseOnly} ICache")))))
+ name = s"Core ${tileId} ICache")))))
val dcacheNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
- name = s"Core ${staticIdForMetadataUseOnly} DCache",
+ name = s"Core ${tileId} DCache",
sourceId = IdRange(0, tileParams.dcache.get.nMSHRs),
supportsProbe = TransferSizes(p(CacheBlockBytes), p(CacheBlockBytes)))))))
val mmioNode = TLClientNode((Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
- name = s"Core ${staticIdForMetadataUseOnly} MMIO",
+ name = s"Core ${tileId} MMIO",
sourceId = IdRange(0, 1),
requestFifo = true))))))
@@ -313,7 +314,7 @@ class SpikeBlackBox(
}
class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
-
+ val tileParams = outer.tileParams
// We create a bundle here and decode the interrupt.
val int_bundle = Wire(new TileInterrupts())
outer.decodeCoreInterrupts(int_bundle)
@@ -337,7 +338,7 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
// then the DTM-based bringup with SimDTM will be used. This isn't required to be
// true, but it usually is
val useDTM = p(ExportDebug).protocols.contains(DMI)
- val spike = Module(new SpikeBlackBox(hartId, isaDTS, tileParams.core.nPMPs,
+ val spike = Module(new SpikeBlackBox(outer.tileId, outer.isaDTS, tileParams.core.nPMPs,
tileParams.icache.get.nSets, tileParams.icache.get.nWays,
tileParams.dcache.get.nSets, tileParams.dcache.get.nWays,
tileParams.dcache.get.nMSHRs,
@@ -467,19 +468,21 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
}
}
-class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams(),
- overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
+class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams()
+) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
// Calculate the next available hart ID (since hart ID cannot be duplicated)
val prev = up(TilesLocated(InSubsystem), site)
- val idOffset = overrideIdOffset.getOrElse(prev.size)
+ val idOffset = up(NumTiles)
// Create TileAttachParams for every core to be instantiated
(0 until n).map { i =>
SpikeTileAttachParams(
- tileParams = tileParams.copy(hartId = i + idOffset)
+ tileParams = tileParams.copy(tileId = i + idOffset)
)
} ++ prev
}
+ case NumTiles => up(NumTiles) + n
+
})
class WithSpikeTCM extends Config((site, here, up) => {
@@ -492,5 +495,5 @@ class WithSpikeTCM extends Config((site, here, up) => {
)))
}
case ExtMem => None
- case BankedL2Key => up(BankedL2Key).copy(nBanks = 0)
+ case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey).copy(nBanks = 0)
})
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index d25d4fa3..993dad02 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -24,12 +24,12 @@ import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile}
-import testchipip.{CanHavePeripheryTLSerial, SerialTLKey}
+import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr
if (this match {
- case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true
+ case _: CanHavePeripheryTLSerial if (p(SerialTLKey).size != 0) => true
case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true
case _ => false
}) {
@@ -71,18 +71,24 @@ trait CanHaveChosenInDTS { this: BaseSubsystem =>
}
class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
- with HasTiles
- with HasPeripheryDebug
- with CanHaveHTIF
- with CanHaveChosenInDTS
+ with InstantiatesHierarchicalElements
+ with HasTileNotificationSinks
+ with HasTileInputConstants
+ with CanHavePeripheryCLINT
+ with CanHavePeripheryPLIC
+ with HasPeripheryDebug
+ with HasHierarchicalElementsRootContext
+ with HasHierarchicalElements
+ with CanHaveHTIF
+ with CanHaveChosenInDTS
{
- def coreMonitorBundles = tiles.map {
+ def coreMonitorBundles = totalTiles.values.map {
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
case b: BoomTile => b.module.core.coreMonitorBundle
}.toList
// No-tile configs have to be handled specially.
- if (tiles.size == 0) {
+ if (totalTiles.size == 0) {
// no PLIC, so sink interrupts to nowhere
require(!p(PLICKey).isDefined)
val intNexus = IntNexusNode(sourceFn = x => x.head, sinkFn = x => x.head)
@@ -90,16 +96,12 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
intSink := intNexus :=* ibus.toPLIC
// avoids a bug when there are no interrupt sources
- ibus.fromAsync := NullIntSource()
+ ibus { ibus.fromAsync := NullIntSource() }
// Need to have at least 1 driver to the tile notification sinks
tileHaltXbarNode := IntSourceNode(IntSourcePortSimple())
tileWFIXbarNode := IntSourceNode(IntSourcePortSimple())
tileCeaseXbarNode := IntSourceNode(IntSourcePortSimple())
-
- // Sink reset vectors to nowhere
- val resetVectorSink = BundleBridgeSink[UInt](Some(() => UInt(28.W)))
- resetVectorSink := tileResetVectorNode
}
// Relying on [[TLBusWrapperConnection]].driveClockFromMaster for
@@ -107,7 +109,7 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
// ClockGroup. This makes it impossible to determine which clocks are driven
// by which bus based on the member names, which is problematic when there is
// a rational crossing between two buses. Instead, provide all bus clocks
- // directly from the asyncClockGroupsNode in the subsystem to ensure bus
+ // directly from the allClockGroupsNode in the subsystem to ensure bus
// names are always preserved in the top-level clock names.
//
// For example, using a RationalCrossing between the Sbus and Cbus, and
@@ -116,12 +118,12 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
// Conversly, if an async crossing is used, they instead receive names of the
// form "subsystem_cbus_[0-9]*". The assignment below provides the latter names in all cases.
Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc =>
- tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode }
+ tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := allClockGroupsNode }
}
override lazy val module = new ChipyardSubsystemModuleImp(this)
}
class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
- with HasTilesModuleImp
+ with HasHierarchicalElementsRootContextModuleImp
{
}
diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala
index 5643e380..b8a04eac 100644
--- a/generators/chipyard/src/main/scala/System.scala
+++ b/generators/chipyard/src/main/scala/System.scala
@@ -32,13 +32,6 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
- // If there is no bootrom, the tile reset vector bundle will be tied to zero
- if (bootROM.isEmpty) {
- val fakeResetVectorSourceNode = BundleBridgeSource[UInt]()
- InModuleBody { fakeResetVectorSourceNode.bundle := 0.U }
- tileResetVectorNexusNode := fakeResetVectorSourceNode
- }
-
override lazy val module = new ChipyardSystemModule(this)
}
diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala
index 0e4e3310..2a88ebb2 100644
--- a/generators/chipyard/src/main/scala/TestSuites.scala
+++ b/generators/chipyard/src/main/scala/TestSuites.scala
@@ -65,7 +65,7 @@ class TestSuiteHelper
*/
def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = {
val xlen = p(XLen)
- tiles.find(_.hartId == 0).map { tileParams =>
+ tiles.find(_.tileId == 0).map { tileParams =>
val coreParams = tileParams.core
val vm = coreParams.useVM
val env = if (vm) List("p","v") else List("p")
diff --git a/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
new file mode 100644
index 00000000..9af30ddf
--- /dev/null
+++ b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
@@ -0,0 +1,27 @@
+package chipyard.clocking
+
+import chisel3._
+
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.util._
+import freechips.rocketchip.tile._
+import freechips.rocketchip.prci._
+
+case object ClockTapKey extends Field[Boolean](true)
+
+trait CanHaveClockTap { this: BaseSubsystem =>
+ require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem must not drive clocks from IO")
+ val clockTapNode = Option.when(p(ClockTapKey)) {
+ val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
+ clockTap := ClockGroup() := allClockGroupsNode
+ clockTap
+ }
+ val clockTapIO = clockTapNode.map { node => InModuleBody {
+ val clock_tap = IO(Output(Clock()))
+ clock_tap := node.in.head._1.clock
+ clock_tap
+ }}
+}
diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
index 412dd43d..fdb2ec9e 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
@@ -2,47 +2,36 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
-import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey}
+import chipyard.iobinders._
import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import barstools.iocell.chisel._
-class ClockWithFreq(val freqMHz: Double) extends Bundle {
- val clock = Clock()
-}
-
// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate
// the requested clocks. This also adds TileLink ClockDivider and ClockSelector
// blocks, which allow memory-mapped control of clock division, and clock muxing
// between the FakePLL and the slow off-chip clock
// Note: This will not simulate properly with firesim
-class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
+// Unsetting enable will prevent the divider/selector from actually modifying the clock,
+// while preserving the address map. Unsetting enable should only be done for RTL
+// simulators (Verilator) which do not model reset properly
+class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
// Connect the implicit clock
implicit val p = GetSystemParameters(system)
- val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
- system.connectImplicitClockSinkNode(implicitClockSinkNode)
- InModuleBody {
- val implicit_clock = implicitClockSinkNode.in.head._1.clock
- val implicit_reset = implicitClockSinkNode.in.head._1.reset
- system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => {
- l.clock := implicit_clock
- l.reset := implicit_reset
- }}
- }
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere)
val baseAddress = system.prciParams.baseAddress
- val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) }
- val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
+ val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes, enable=enable)) }
+ val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
- system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
+ system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
// Connect all other requested clocks
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
@@ -58,13 +47,13 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
pllCtrlSink := pllCtrl.ctrlNode
InModuleBody {
- val clock_wire = Wire(Input(new ClockWithFreq(100)))
+ val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
slowClockSource.out.unzip._1.map { o =>
- o.clock := clock_wire.clock
+ o.clock := clock_wire
o.reset := reset_wire
}
@@ -79,31 +68,20 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
o.reset := reset_wire
}
- (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell)
+ (Seq(ClockPort(() => clock_io, 100), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
}
}
})
-
+
// This passes all clocks through to the TestHarness
class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
- // Connect the implicit clock
implicit val p = GetSystemParameters(system)
- val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
- system.connectImplicitClockSinkNode(implicitClockSinkNode)
- InModuleBody {
- val implicit_clock = implicitClockSinkNode.in.head._1.clock
- val implicit_reset = implicitClockSinkNode.in.head._1.reset
- system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => {
- l.clock := implicit_clock
- l.reset := implicit_reset
- }}
- }
// This aggregate node should do nothing
val clockGroupAggNode = ClockGroupAggregateNode("fake")
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
- system.allClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
+ system.chiptopClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
InModuleBody {
val reset_io = IO(Input(AsyncReset()))
@@ -114,12 +92,21 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
require(m.take.isDefined, s"""Clock ${m.name.get} has no requested frequency
|Clocks: ${edge.sink.members.map(_.name.get)}""".stripMargin)
val freq = m.take.get.freqMHz
- val clock_io = IO(Input(new ClockWithFreq(freq))).suggestName(s"clock_${m.name.get}")
- b.clock := clock_io.clock
+ val clock_io = IO(Input(Clock())).suggestName(s"clock_${m.name.get}")
+ b.clock := clock_io
b.reset := reset_io
- clock_io
+ ClockPort(() => clock_io, freq)
}.toSeq
- ((clock_ios :+ reset_io), Nil)
+ ((clock_ios :+ ResetPort(() => reset_io)), Nil)
}
}
})
+
+class WithClockTapIOCells extends OverrideIOBinder({
+ (system: CanHaveClockTap) => {
+ system.clockTapIO.map { tap =>
+ val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap")
+ (Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell)
+ }.getOrElse((Nil, Nil))
+ }
+})
diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
index e5236804..9b53cbef 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
index e52ec674..42c45db6 100644
--- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
+++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
@@ -51,7 +51,7 @@ object FrequencyUtils {
require(!requestedOutputs.contains(0.0))
val requestedFreqs = requestedOutputs.map(_.freqMHz)
val fastestFreq = requestedFreqs.max
- require(fastestFreq <= maximumAllowableFreqMHz)
+ require(fastestFreq <= maximumAllowableFreqMHz, s"Fastest Freq $fastestFreq > Max Freq $maximumAllowableFreqMHz")
val candidateFreqs =
Seq.tabulate(Math.ceil(maximumAllowableFreqMHz / fastestFreq).toInt)(i => (i + 1) * fastestFreq)
diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
index 356a0432..9b140e20 100644
--- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
+++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -14,7 +14,8 @@ import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.prci._
-import testchipip.{TLTileResetCtrl, ClockGroupFakeResetSynchronizer}
+import testchipip.boot.{TLTileResetCtrl}
+import testchipip.clocking.{ClockGroupFakeResetSynchronizer}
case class ChipyardPRCIControlParams(
slaveWhere: TLBusWrapperLocation = CBUS,
@@ -29,15 +30,14 @@ case class ChipyardPRCIControlParams(
case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams())
-trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
- require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven")
+trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements =>
+ require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks")
val prciParams = p(ChipyardPRCIControlKey)
// Set up clock domain
private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
- val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control")))
- prci_ctrl_domain.clockNode := tlbus.fixedClockNode
+ val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
@@ -48,29 +48,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
// Aggregate all the clock groups into a single node
val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
- val allClockGroupsNode = ClockGroupEphemeralNode()
- // There are two "sets" of clocks which must be dealt with
-
- // 1. The implicit clock from the subsystem. RC is moving away from depending on this
- // clock, but some modules still use it. Since the implicit clock sink node
- // is created in the ChipTop (the hierarchy wrapping the subsystem), this function
- // is provided to allow connecting that clock to the clock aggregator. This function
- // should be called in the ChipTop context
- def connectImplicitClockSinkNode(sink: ClockSinkNode) = {
- val implicitClockGrouper = this { ClockGroup() }
- (sink
- := implicitClockGrouper
- := aggregator)
- }
-
- // 2. The rest of the diplomatic clocks in the subsystem are routed to this asyncClockGroupsNode
+ // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode
val clockNamePrefixer = ClockGroupNamePrefixer()
- (asyncClockGroupsNode
+ (allClockGroupsNode
:*= clockNamePrefixer
:*= aggregator)
-
// Once all the clocks are gathered in the aggregator node, several steps remain
// 1. Assign frequencies to any clock groups which did not specify a frequency.
// 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain)
@@ -91,7 +75,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
} }
val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
- tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil))
+ tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil))
reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
reset_setter
} }
@@ -115,11 +99,14 @@ RTL SIMULATORS, NAMELY VERILATOR.
""" + Console.RESET)
}
+ // The chiptopClockGroupsNode shouuld be what ClockBinders attach to
+ val chiptopClockGroupsNode = ClockGroupEphemeralNode()
+
(aggregator
:= frequencySpecifier
:= clockGroupCombiner
:= resetSynchronizer
:= tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
:= tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
- := allClockGroupsNode)
+ := chiptopClockGroupsNode)
}
diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
index 45f9374d..958c9194 100644
--- a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
+++ b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
@@ -11,15 +11,31 @@ import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.util.ElaborationArtefacts
-import testchipip._
+import testchipip.clocking._
// This module adds a TileLink memory-mapped clock divider to the clock graph
// The output clock/reset pairs from this module should be synchronized later
-class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit p: Parameters) extends LazyModule {
+// If enable is unset, this will not divide the clock
+// DO NOT unset enable for VLSI, or prototyping flows. The disable feature is a work around for
+// some RTL simulators which do not simulate the reset synchronization properly
+class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8, enable: Boolean = true)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice(s"clk-div-ctrl", Nil)
val clockNode = ClockGroupIdentityNode()
val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
+ if (!enable) println(Console.RED + s"""
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+WARNING:
+
+YOU ARE USING THE TLCLOCKDIVIDER IN
+"DISABLED" MODE. THIS SHOULD ONLY BE DONE
+FOR RTL SIMULATION
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+""" + Console.RESET)
+
lazy val module = new LazyModuleImp(this) {
require (clockNode.out.size == 1)
val sources = clockNode.in.head._1.member.data.toSeq
@@ -38,20 +54,28 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit
val reg = Module(new AsyncResetRegVec(w=divBits, init=0))
println(s"${(address+i*4).toString(16)}: Clock domain $sinkName divider")
- val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
+ val divider = Module(new ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
divider.io.clockIn := sources(i).clock
// busReset is expected to be high for a long time, since reset will take a while to propagate
// to the TL bus. While reset is propagating, make sure we propagate a fast, undivided clock
// by setting divisor=0. The divisor signal into the ClockDividerOrPass is synchronized internally
divider.io.divisor := Mux(busReset.asBool, 0.U, reg.io.q)
divider.io.resetAsync := ResetStretcher(sources(i).clock, asyncReset, 20).asAsyncReset
- sinks(i)._2.clock := divider.io.clockOut
- // Note this is not synchronized to the output clock, which takes time to appear
- // so this is still asyncreset
- // Stretch the reset for 40 cycles, to give enough time to reset any downstream
- // digital logic
- sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset
+ if (enable) {
+ sinks(i)._2.clock := divider.io.clockOut
+
+ // Note this is not synchronized to the output clock, which takes time to appear
+ // so this is still asyncreset
+ // Stretch the reset for 40 cycles, to give enough time to reset any downstream
+ // digital logic
+ sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset
+ } else {
+ // WARNING: THIS IS FOR RTL SIMULATION ONLY
+ sinks(i)._2.clock := sources(i).clock
+ sinks(i)._2.reset := sources(i).reset
+ }
+
reg
}
diff --git a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
index 27870428..8c6371f1 100644
--- a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
+++ b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
@@ -11,7 +11,7 @@ import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.util.ElaborationArtefacts
-import testchipip._
+import testchipip.clocking._
case class ClockSelNode()(implicit valName: ValName)
extends MixedNexusNode(ClockImp, ClockGroupImp)(
@@ -21,12 +21,30 @@ case class ClockSelNode()(implicit valName: ValName)
// This module adds a TileLink memory-mapped clock mux for each downstream clock domain
// in the clock graph. The output clock/reset should be synchronized downstream
-class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule {
+// If enable is unset, this will always pass through the 0'th clock
+// DO NOT unset enable for VLSI, or prototyping flows. The disable feature is a work around for
+// some RTL simulators which do not simulate the reset synchronization properly
+class TLClockSelector(address: BigInt, beatBytes: Int, enable: Boolean = true)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("clk-sel-ctrl", Nil)
val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
val clockNode = ClockSelNode()
+ if (!enable) println(Console.RED + s"""
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+WARNING:
+
+YOU ARE USING THE TLCLOCKSELECTOR IN
+"DISABLED" MODE. THIS SHOULD ONLY BE DONE
+FOR RTL SIMULATION
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+""" + Console.RESET)
+
+
+
lazy val module = new LazyModuleImp(this) {
val asyncReset = clockNode.in.map(_._1).map(_.reset).toSeq(0)
val clocks = clockNode.in.map(_._1).map(_.clock)
@@ -40,13 +58,18 @@ class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) e
sel := reg.io.q
println(s"${(address+i*4).toString(16)}: Clock domain $sinkName clock mux")
- val mux = testchipip.ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
+ val mux = ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
mux.io.sel := sel
mux.io.resetAsync := asyncReset.asAsyncReset
- sinks(i).clock := mux.io.clockOut
- // Stretch the reset for 20 cycles, to give time to reset any downstream digital logic
- sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset
-
+ if (enable) {
+ sinks(i).clock := mux.io.clockOut
+ // Stretch the reset for 20 cycles, to give time to reset any downstream digital logic
+ sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset
+ } else {
+ // WARNING: THIS IS FOR RTL SIMULATION ONLY
+ sinks(i).clock := clocks(0)
+ sinks(i).reset := asyncReset
+ }
reg
}
tlNode.regmap((0 until sinks.size).map { i =>
diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
index e299d0a9..c92e05bc 100644
--- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
index 53dd36d0..88916d17 100644
--- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index 44235cbd..8a328daf 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -15,15 +15,18 @@ class AbstractConfig extends Config(
new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM
- new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled
+ new chipyard.harness.WithSimJTAGDebug ++ // add SimJTAG if JTAG for debug exposed
+ new chipyard.harness.WithSimDMI ++ // add SimJTAG if DMI exposed
new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present
new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled
new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled
new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present
new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present
new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present
+ new chipyard.harness.WithDriveChipIdPin ++ // drive chip id pin from harness binder, if chip id pin is present
new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port
- new chipyard.harness.WithClockAndResetFromHarness ++ // all Clock/Reset I/O in ChipTop should be driven by harnessClockInstantiator
+ new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator
+ new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz
// The IOBinders instantiate ChipTop IOs to match desired digital IOs
@@ -32,11 +35,14 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithDebugIOCells ++
new chipyard.iobinders.WithUARTIOCells ++
new chipyard.iobinders.WithGPIOCells ++
- new chipyard.iobinders.WithSPIIOCells ++
+ new chipyard.iobinders.WithSPIFlashIOCells ++
new chipyard.iobinders.WithExtInterruptIOCells ++
+ new chipyard.iobinders.WithChipIdIOCells ++
new chipyard.iobinders.WithCustomBootPin ++
// The "punchthrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO
// Instead, they directly pass through the DigitalTop ports to ports in the ChipTop
+ new chipyard.iobinders.WithI2CPunchthrough ++
+ new chipyard.iobinders.WithSPIIOPunchthrough ++
new chipyard.iobinders.WithAXI4MemPunchthrough ++
new chipyard.iobinders.WithAXI4MMIOPunchthrough ++
new chipyard.iobinders.WithTLMemPunchthrough ++
@@ -47,22 +53,33 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithUARTTSIPunchthrough ++
new chipyard.iobinders.WithNMITiedOff ++
- // By default, punch out IOs to the Harness
- new chipyard.clocking.WithPassthroughClockGenerator ++
- new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
+ new chipyard.clocking.WithClockTapIOCells ++ // Default generate a clock tapio
+ new chipyard.clocking.WithPassthroughClockGenerator ++ // Default punch out IOs to the Harness
+ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", // Default merge all the bus clocks
+ Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"), Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
+ new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
+ new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
+ new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus
+ new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus
+ new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus
- new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
- new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
- new testchipip.WithSerialTLClientIdBits(4) ++ // support up to 1 << 4 simultaneous requests from serialTL port
- new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance
- new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM
+ new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
+ new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
+ new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface
+ testchipip.serdes.SerialTLParams(
+ client = Some(testchipip.serdes.SerialTLClientParams()), // serial-tilelink interface will master the FBUS, and support 4 idBits
+ phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) // serial-tilelink interface with 32 lanes
+ )
+ )) ++
+ new testchipip.soc.WithMbusScratchpad(base = 0x08000000, // add 64 KiB on-chip scratchpad
+ size = 64 * 1024) ++
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
- new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
+ new chipyard.config.WithNoSubsystemClockIO ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
index cc61794c..52f39a03 100644
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -3,7 +3,7 @@ package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{MBUS, SBUS}
-import testchipip.{OBUS}
+import testchipip.soc.{OBUS}
// A simple config demonstrating how to set up a basic chip in Chipyard
class ChipLikeRocketConfig extends Config(
@@ -22,16 +22,26 @@ class ChipLikeRocketConfig extends Config(
//==================================
// Set up I/O
//==================================
- new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO
- new testchipip.WithSerialTLBackingMemory ++ // Configure the off-chip memory accessible over serial-tl as backing memory
- new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory
+ new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( // 1 serial tilelink port
+ manager = Some(testchipip.serdes.SerialTLManagerParams( // port acts as a manager of offchip memory
+ memParams = Seq(testchipip.serdes.ManagerRAMParams( // 4 GB of off-chip memory
+ address = BigInt("80000000", 16),
+ size = BigInt("100000000", 16)
+ )),
+ isMemoryDevice = true
+ )),
+ client = Some(testchipip.serdes.SerialTLClientParams()), // Allow an external manager to probe this chip
+ phyParams = testchipip.serdes.ExternalSyncSerialParams(width=4) // 4-bit bidir interface, sync'd to an external clock
+ ))) ++
+
+ new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
//==================================
// Set up buses
//==================================
- new testchipip.WithOffchipBusClient(MBUS) ++ // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory
- new testchipip.WithOffchipBus ++ // attach a offchip bus, since the serial-tl will master some external tilelink memory
+ new testchipip.soc.WithOffchipBusClient(MBUS) ++ // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory
+ new testchipip.soc.WithOffchipBus ++ // attach a offchip bus, since the serial-tl will master some external tilelink memory
//==================================
// Set up clock./reset
@@ -43,6 +53,10 @@ class ChipLikeRocketConfig extends Config(
new chipyard.config.AbstractConfig)
+class FlatChipTopChipLikeRocketConfig extends Config(
+ new chipyard.example.WithFlatChipTop ++
+ new chipyard.ChipLikeRocketConfig)
+
// A simple config demonstrating a "bringup prototype" to bringup the ChipLikeRocketconfig
class ChipBringupHostConfig extends Config(
//=============================
@@ -56,17 +70,23 @@ class ChipBringupHostConfig extends Config(
//=============================
// Setup the SerialTL side on the bringup device
//=============================
- new testchipip.WithSerialTLWidth(4) ++ // match width with the chip
- new testchipip.WithSerialTLMem(base = 0x0, size = 0x80000000L, // accessible memory of the chip that doesn't come from the tethered host
- idBits = 4, isMainMemory = false) ++ // This assumes off-chip mem starts at 0x8000_0000
- new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
+ new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
+ manager = Some(testchipip.serdes.SerialTLManagerParams(
+ memParams = Seq(testchipip.serdes.ManagerRAMParams( // Bringup platform can access all memory from 0 to DRAM_BASE
+ address = BigInt("00000000", 16),
+ size = BigInt("80000000", 16)
+ ))
+ )),
+ client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM)
+ phyParams = testchipip.serdes.InternalSyncSerialParams(width=4, freqMHz = 75) // bringup platform provides the clock
+ ))) ++
//============================
// Setup bus topology on the bringup system
//============================
- new testchipip.WithOffchipBusClient(SBUS, // offchip bus hangs off the SBUS
+ new testchipip.soc.WithOffchipBusClient(SBUS, // offchip bus hangs off the SBUS
blockRange = AddressSet.misaligned(0x80000000L, (BigInt(1) << 30) * 4)) ++ // offchip bus should not see the main memory of the testchip, since that can be accessed directly
- new testchipip.WithOffchipBus ++ // offchip bus
+ new testchipip.soc.WithOffchipBus ++ // offchip bus
//=============================
// Set up memory on the bringup system
@@ -76,7 +96,7 @@ class ChipBringupHostConfig extends Config(
//=============================
// Generate the TSI-over-UART side of the bringup system
//=============================
- new testchipip.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++ // nonstandard baud rate to improve performance
+ new testchipip.tsi.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++ // nonstandard baud rate to improve performance
//=============================
// Set up clocks of the bringup system
@@ -85,6 +105,9 @@ class ChipBringupHostConfig extends Config(
new chipyard.config.WithFrontBusFrequency(75.0) ++ // run all buses of this system at 75 MHz
new chipyard.config.WithMemoryBusFrequency(75.0) ++
new chipyard.config.WithPeripheryBusFrequency(75.0) ++
+ new chipyard.config.WithSystemBusFrequency(75.0) ++
+ new chipyard.config.WithControlBusFrequency(75.0) ++
+ new chipyard.config.WithOffchipBusFrequency(75.0) ++
// Base is the no-cores config
new chipyard.NoCoresConfig)
@@ -103,5 +126,9 @@ class TetheredChipLikeRocketConfig extends Config(
class VerilatorCITetheredChipLikeRocketConfig extends Config(
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute freqs for sims in the harness
new chipyard.harness.WithMultiChipSerialTL(0, 1) ++ // connect the serial-tl ports of the chips together
- new chipyard.harness.WithMultiChip(0, new chipyard.config.WithNoResetSynchronizers ++ new ChipLikeRocketConfig) ++
+ new chipyard.harness.WithMultiChip(0, // These fragments remove all troublesome
+ new chipyard.clocking.WithPLLSelectorDividerClockGenerator(enable=false) ++ // clocking features from the design
+ new chipyard.iobinders.WithDebugIOCells(syncReset = false) ++
+ new chipyard.config.WithNoResetSynchronizers ++
+ new ChipLikeRocketConfig) ++
new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig))
diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
new file mode 100644
index 00000000..a7d2113f
--- /dev/null
+++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
@@ -0,0 +1,47 @@
+package chipyard
+
+import org.chipsalliance.cde.config.{Config}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.subsystem.{SBUS}
+import testchipip.soc.{OBUS}
+
+// ------------------------------------------------
+// Configs demonstrating chip-to-chip communication
+// ------------------------------------------------
+
+// Simple design which exposes a second serial-tl port that can connect to another instance of itself
+class SymmetricChipletRocketConfig extends Config(
+ new testchipip.soc.WithChipIdPin ++ // Add pin to identify chips
+ new chipyard.harness.WithSerialTLTiedOff(tieoffs=Some(Seq(1))) ++ // Tie-off the chip-to-chip link in single-chip sims
+ new testchipip.serdes.WithSerialTL(Seq(
+ testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga
+ client = Some(testchipip.serdes.SerialTLClientParams()), // bringup serial-tl acts only as a client
+ phyParams = testchipip.serdes.ExternalSyncSerialParams() // bringup serial-tl is sync'd to external clock
+ ),
+ testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip
+ client = Some(testchipip.serdes.SerialTLClientParams()), // chip-to-chip serial-tl acts as a client
+ manager = Some(testchipip.serdes.SerialTLManagerParams( // chip-to-chip serial-tl managers other chip's memory
+ memParams = Seq(testchipip.serdes.ManagerRAMParams(
+ address = 0,
+ size = 1L << 32,
+ )),
+ slaveWhere = OBUS
+ )),
+ phyParams = testchipip.serdes.SourceSyncSerialParams() // chip-to-chip serial-tl is symmetric source-sync'd
+ ))
+ ) ++
+ new testchipip.soc.WithOffchipBusClient(SBUS, // obus provides path to other chip's memory
+ blockRange = Seq(AddressSet(0, (1L << 32) - 1)), // The lower 4GB is mapped to this chip
+ replicationBase = Some(1L << 32) // The upper 4GB goes off-chip
+ ) ++
+ new testchipip.soc.WithOffchipBus ++
+ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+ new chipyard.config.AbstractConfig)
+
+// Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config
+class MultiSimSymmetricChipletRocketConfig extends Config(
+ new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
+ new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=1) ++
+ new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++
+ new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig)
+)
diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
index 16e6b313..8d6f1063 100644
--- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
@@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// DOC include start: FFTRocketConfig
class FFTRocketConfig extends Config(
- new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO: hack around dontTouch not working in SFC
+ new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO: hack around dontTouch not working in SFC
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
@@ -59,7 +59,7 @@ class LargeNVDLARocketConfig extends Config(
new chipyard.config.AbstractConfig)
class ManyMMIOAcceleratorRocketConfig extends Config(
- new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO: hack around dontTouch not working in SFC
+ new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO: hack around dontTouch not working in SFC
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
diff --git a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
new file mode 100644
index 00000000..c49f85ee
--- /dev/null
+++ b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
@@ -0,0 +1,41 @@
+package chipyard
+
+import org.chipsalliance.cde.config.{Config}
+import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+
+// ------------------------------------------------------------
+// Configs which demonstrate modifying the uncore memory system
+// ------------------------------------------------------------
+
+class SimAXIRocketConfig extends Config(
+ new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
+ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+ new chipyard.config.AbstractConfig)
+
+class GB1MemoryRocketConfig extends Config(
+ new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
+ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+ new chipyard.config.AbstractConfig)
+
+// DOC include start: mbusscratchpadrocket
+class MbusScratchpadOnlyRocketConfig extends Config(
+ new testchipip.soc.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
+ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
+ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+ new chipyard.config.AbstractConfig)
+// DOC include end: mbusscratchpadrocket
+
+class SbusScratchpadRocketConfig extends Config(
+ new testchipip.soc.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
+ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+ new chipyard.config.AbstractConfig)
+
+class SbusBypassRocketConfig extends Config(
+ new freechips.rocketchip.subsystem.WithExtMemSbusBypass ++ // Add bypass path to access DRAM incoherently through an address alias
+ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+ new chipyard.config.AbstractConfig)
+
+class QuadChannelRocketConfig extends Config(
+ new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++ // 4 AXI4 channels
+ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+ new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
index 0b6be558..4288fa84 100644
--- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
@@ -6,6 +6,7 @@ import freechips.rocketchip.subsystem.{SBUS, MBUS}
import constellation.channel._
import constellation.routing._
+import constellation.router._
import constellation.topology._
import constellation.noc._
import constellation.soc.{GlobalNoCParams}
@@ -45,7 +46,7 @@ import scala.collection.immutable.ListMap
* | SI:Core 2 | SO:system[0] | SO:system[1] | SI:Core 3 |
* |(0)___________|(1)___________|(2)___________|(3)___________|
* | FBus | Core 0 | Core 1 | Pbus |
- * | SI:serial-tl | SI:Core 0 | SI:Core 1 | SO:pbus |
+ * | SI:serial_tl | SI:Core 0 | SI:Core 1 | SO:pbus |
* |______________|______________|______________|______________|
*
* |(0)___________|(1)___________|(2)___________|(3)___________|
@@ -62,37 +63,37 @@ import scala.collection.immutable.ListMap
*/
// DOC include start: MultiNoCConfig
class MultiNoCConfig extends Config(
- new constellation.soc.WithCbusNoC(constellation.protocol.TLNoCParams(
+ new constellation.soc.WithCbusNoC(constellation.protocol.SimpleTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
- "serial-tl" -> 0),
+ "serial_tl" -> 0),
outNodeMapping = ListMap(
- "error" -> 1, "l2[0]" -> 2, "pbus" -> 3, "plic" -> 4,
+ "error" -> 1, "ctrls[0]" -> 2, "pbus" -> 3, "plic" -> 4,
"clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)),
NoCParams(
topology = TerminalRouter(BidirectionalLine(9)),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }),
routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1))
)) ++
- new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams(
+ new constellation.soc.WithMbusNoC(constellation.protocol.SimpleTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"L2 InclusiveCache[0]" -> 1, "L2 InclusiveCache[1]" -> 2,
"L2 InclusiveCache[2]" -> 5, "L2 InclusiveCache[3]" -> 6),
outNodeMapping = ListMap(
"system[0]" -> 0, "system[1]" -> 3, "system[2]" -> 4 , "system[3]" -> 7,
- "serdesser" -> 0)),
+ "serial_tl_0" -> 0)),
NoCParams(
topology = TerminalRouter(BidirectionalTorus1D(8)),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalTorus1DShortestRouting()), 5, 2))
)) ++
- new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
+ new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Core 0" -> 1, "Core 1" -> 2, "Core 2" -> 4 , "Core 3" -> 7,
"Core 4" -> 8, "Core 5" -> 11, "Core 6" -> 13, "Core 7" -> 14,
- "serial-tl" -> 0),
+ "serial_tl" -> 0),
outNodeMapping = ListMap(
"system[0]" -> 5, "system[1]" -> 6, "system[2]" -> 9, "system[3]" -> 10,
"pbus" -> 3)),
@@ -133,7 +134,7 @@ class MultiNoCConfig extends Config(
* Core 6 | SI | Core 6 | 16
* Core 7 | SI | Core 7 | 18
* Core 8 | SI | Core 8 | 19
- * fbus | SI | serial-tl | 9
+ * fbus | SI | serial_tl | 9
* pbus | SO | pbus | 4
* L2 0 | SO | system[0] | 0
* L2 1 | SO | system[1] | 2
@@ -145,7 +146,7 @@ class MultiNoCConfig extends Config(
* L2 3 | MI | Cache[3] | 6
* DRAM 0 | MO | system[0] | 3
* DRAM 1 | MO | system[1] | 5
- * extram | MO | serdesser | 9
+ * spad | MO | ram[0] | 9
*/
// DOC include start: SharedNoCConfig
class SharedNoCConfig extends Config(
@@ -162,24 +163,24 @@ class SharedNoCConfig extends Config(
BidirectionalLineRouting()))), 10, 2)
)
)) ++
- new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams(
+ new constellation.soc.WithMbusNoC(constellation.protocol.GlobalTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6),
outNodeMapping = ListMap(
"system[0]" -> 3, "system[1]" -> 5,
- "serdesser" -> 9))
- ), true) ++
- new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
+ "ram[0]" -> 9))
+ )) ++
+ new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
- "serial-tl" -> 9, "Core 0" -> 2,
+ "serial_tl" -> 9, "Core 0" -> 2,
"Core 1" -> 10, "Core 2" -> 11, "Core 3" -> 13, "Core 4" -> 14,
"Core 5" -> 15, "Core 6" -> 16, "Core 7" -> 18, "Core 8" -> 19),
outNodeMapping = ListMap(
"system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6,
"pbus" -> 4))
- ), true) ++
+ )) ++
new freechips.rocketchip.subsystem.WithNBigCores(8) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
@@ -187,8 +188,9 @@ class SharedNoCConfig extends Config(
)
// DOC include end: SharedNoCConfig
+// This Config implements a simple ring interconnect for the system bus
class SbusRingNoCConfig extends Config(
- new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
+ new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Core 0" -> 0,
@@ -199,19 +201,67 @@ class SbusRingNoCConfig extends Config(
"Core 5" -> 5,
"Core 6" -> 6,
"Core 7" -> 7,
- "serial-tl" -> 8),
+ "serial_tl" -> 8),
outNodeMapping = ListMap(
"system[0]" -> 9,
"system[1]" -> 10,
"system[2]" -> 11,
"system[3]" -> 12,
"pbus" -> 8)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
- NoCParams(
+ acdNoCParams = NoCParams(
topology = UnidirectionalTorus1D(13),
- channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
- routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2))
+ channelParamGen = (a, b) => UserChannelParams(Seq.fill(6) { UserVirtualChannelParams(4) }),
+ routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 3, 2)),
+ beNoCParams = NoCParams(
+ topology = UnidirectionalTorus1D(13),
+ channelParamGen = (a, b) => UserChannelParams(Seq.fill(4) { UserVirtualChannelParams(1) }),
+ routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 2, 2))
)) ++
new freechips.rocketchip.subsystem.WithNBigCores(8) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.AbstractConfig
)
+
+// This config integrates a mesh interconnect for the system bus, and divides the system bus
+// tilelink messages across two isolated interconnects
+class SbusMeshNoCConfig extends Config(
+ new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams(
+ constellation.protocol.DiplomaticNetworkNodeMapping(
+ inNodeMapping = ListMap(
+ "Core 0 " -> 0,
+ "Core 1 " -> 1,
+ "Core 2 " -> 2,
+ "Core 3 " -> 3,
+ "Core 4 " -> 4,
+ "Core 5 " -> 7,
+ "Core 6 " -> 8,
+ "Core 7 " -> 11,
+ "Core 8 " -> 12,
+ "Core 9 " -> 13,
+ "Core 10 " -> 14,
+ "Core 11 " -> 15,
+ "serial-tl" -> 0),
+ outNodeMapping = ListMap(
+ "system[0]" -> 5,
+ "system[1]" -> 6,
+ "system[2]" -> 9,
+ "system[3]" -> 10,
+ "pbus" -> 0)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
+ acdNoCParams = NoCParams(
+ topology = Mesh2D(4, 4),
+ channelParamGen = (a, b) => UserChannelParams(Seq.fill(3) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
+ routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
+ routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1)),
+ beNoCParams = NoCParams(
+ topology = Mesh2D(4, 4),
+ channelParamGen = (a, b) => UserChannelParams(Seq.fill(2) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
+ routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
+ routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1)),
+ beDivision = 4
+ )) ++
+ new freechips.rocketchip.subsystem.WithNBigCores(12) ++
+ new freechips.rocketchip.subsystem.WithNBanks(4) ++
+ new chipyard.config.WithSystemBusWidth(128) ++
+ new chipyard.config.AbstractConfig
+)
+
diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
index 19e9a7e0..6647e516 100644
--- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
@@ -4,8 +4,9 @@ import org.chipsalliance.cde.config.{Config}
// A empty config with no cores. Useful for testing
class NoCoresConfig extends Config(
- new testchipip.WithNoBootAddrReg ++
- new testchipip.WithNoCustomBootPin ++
+ new testchipip.soc.WithNoScratchpads ++
+ new testchipip.boot.WithNoBootAddrReg ++
+ new testchipip.boot.WithNoCustomBootPin ++
new chipyard.config.WithNoCLINT ++
new chipyard.config.WithNoBootROM ++
new chipyard.config.WithBroadcastManager ++
diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
index 7ad7a1ac..99400743 100644
--- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -22,13 +22,13 @@ class SmallSPIFlashRocketConfig extends Config(
class SimBlockDeviceRocketConfig extends Config(
new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
- new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
+ new testchipip.iceblk.WithBlockDevice ++ // add block-device module to peripherybus
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class BlockDeviceModelRocketConfig extends Config(
new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel
- new testchipip.WithBlockDevice ++ // add block-device module to periphery bus
+ new testchipip.iceblk.WithBlockDevice ++ // add block-device module to periphery bus
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
@@ -52,8 +52,11 @@ class MMIORocketConfig extends Config(
new chipyard.config.AbstractConfig)
class LBWIFRocketConfig extends Config(
- new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
- new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
+ new chipyard.config.WithOffchipBusFrequency(500) ++
+ new testchipip.soc.WithOffchipBusClient(MBUS) ++
+ new testchipip.soc.WithOffchipBus ++
+ new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
+ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
@@ -66,10 +69,10 @@ class dmiRocketConfig extends Config(
// DOC include end: DmiRocket
class ManyPeripheralsRocketConfig extends Config(
- new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
- new testchipip.WithOffchipBusClient(MBUS) ++ // OBUS provides backing memory to the MBUS
- new testchipip.WithOffchipBus ++ // OBUS must exist for serial-tl to master off-chip memory
- new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
+ new testchipip.iceblk.WithBlockDevice ++ // add block-device module to peripherybus
+ new testchipip.soc.WithOffchipBusClient(MBUS) ++ // OBUS provides backing memory to the MBUS
+ new testchipip.soc.WithOffchipBus ++ // OBUS must exist for serial-tl to master off-chip memory
+ new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
@@ -79,14 +82,9 @@ class ManyPeripheralsRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
-class QuadChannelRocketConfig extends Config(
- new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++ // 4 AXI4 channels
- new freechips.rocketchip.subsystem.WithNBigCores(1) ++
- new chipyard.config.AbstractConfig)
-
class UARTTSIRocketConfig extends Config(
new chipyard.harness.WithSerialTLTiedOff ++
- new testchipip.WithUARTTSIClient ++
+ new testchipip.tsi.WithUARTTSIClient ++
new chipyard.config.WithMemoryBusFrequency(10) ++
new chipyard.config.WithFrontBusFrequency(10) ++
new chipyard.config.WithPeripheryBusFrequency(10) ++
diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
index 4077fcbd..0796bade 100644
--- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
@@ -56,3 +56,9 @@ class HwachaLargeBoomConfig extends Config(
new boom.common.WithNLargeBooms(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
+
+class AES256ECBRocketConfig extends Config(
+ new aes.WithAES256ECBAccel ++ // use Caliptra AES 256 ECB accelerator
+ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+ new chipyard.config.WithSystemBusWidth(256) ++
+ new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index c45fb6f2..0ddb3737 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -2,6 +2,7 @@ package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+import freechips.rocketchip.subsystem.{InCluster}
// --------------
// Rocket Configs
@@ -12,18 +13,14 @@ class RocketConfig extends Config(
new chipyard.config.AbstractConfig)
class TinyRocketConfig extends Config(
- new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO FIX: Don't dontTouch the ports
+ new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO FIX: Don't dontTouch the ports
+ new testchipip.soc.WithNoScratchpads ++ // All memory is the Rocket TCMs
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core
new chipyard.config.AbstractConfig)
-class SimAXIRocketConfig extends Config(
- new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
- new freechips.rocketchip.subsystem.WithNBigCores(1) ++
- new chipyard.config.AbstractConfig)
-
class QuadRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles)
new chipyard.config.AbstractConfig)
@@ -38,14 +35,10 @@ class RV32RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
-class GB1MemoryRocketConfig extends Config(
- new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
- new freechips.rocketchip.subsystem.WithNBigCores(1) ++
- new chipyard.config.AbstractConfig)
-
// DOC include start: l1scratchpadrocket
class ScratchpadOnlyRocketConfig extends Config(
new chipyard.config.WithL2TLBs(0) ++
+ new testchipip.soc.WithNoScratchpads ++ // remove subsystem scratchpads, confusingly named, does not remove the L1D$ scratchpads
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem
@@ -65,26 +58,12 @@ class L1ScratchpadRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
-// DOC include start: mbusscratchpadrocket
-class MbusScratchpadOnlyRocketConfig extends Config(
- new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
- new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
- new freechips.rocketchip.subsystem.WithNBigCores(1) ++
- new chipyard.config.AbstractConfig)
-// DOC include end: mbusscratchpadrocket
-
-class SbusScratchpadRocketConfig extends Config(
- new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus backing scratchpad
- new freechips.rocketchip.subsystem.WithNBigCores(1) ++
- new chipyard.config.AbstractConfig)
-
-
class MulticlockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
// Frequency specifications
new chipyard.config.WithTileFrequency(1000.0) ++ // Matches the maximum frequency of U540
- new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit"), Nil),
+ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit", "clock_tap"), Nil),
("periphery", Seq("pbus", "fbus"), Nil)) ++
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Matches the maximum frequency of U540
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Matches the maximum frequency of U540
@@ -93,10 +72,10 @@ class MulticlockRocketConfig extends Config(
new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between FBUS and SBUS
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
- new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new chipyard.config.AbstractConfig)
class CustomIOChipTopRocketConfig extends Config(
+ new chipyard.example.WithBrokenOutUARTIO ++
new chipyard.example.WithCustomChipTop ++
new chipyard.example.WithCustomIOCells ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
@@ -110,3 +89,10 @@ class PrefetchingRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++ // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new chipyard.config.AbstractConfig)
+
+class ClusteredRocketConfig extends Config(
+ new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(1)) ++
+ new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(0)) ++
+ new freechips.rocketchip.subsystem.WithCluster(1) ++
+ new freechips.rocketchip.subsystem.WithCluster(0) ++
+ new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
index 4181083c..2edda3ce 100644
--- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
@@ -7,7 +7,8 @@ import org.chipsalliance.cde.config.{Config}
class Sodor1StageConfig extends Config(
// Create a Sodor 1-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
- new testchipip.WithSerialTLWidth(32) ++
+ new testchipip.soc.WithNoScratchpads ++ // No scratchpads
+ new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -16,7 +17,8 @@ class Sodor1StageConfig extends Config(
class Sodor2StageConfig extends Config(
// Create a Sodor 2-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
- new testchipip.WithSerialTLWidth(32) ++
+ new testchipip.soc.WithNoScratchpads ++ // No scratchpads
+ new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -25,7 +27,8 @@ class Sodor2StageConfig extends Config(
class Sodor3StageConfig extends Config(
// Create a Sodor 1-stage core with two ports
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
- new testchipip.WithSerialTLWidth(32) ++
+ new testchipip.soc.WithNoScratchpads ++ // No scratchpads
+ new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -34,7 +37,8 @@ class Sodor3StageConfig extends Config(
class Sodor3StageSinglePortConfig extends Config(
// Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
- new testchipip.WithSerialTLWidth(32) ++
+ new testchipip.soc.WithNoScratchpads ++ // No scratchpads
+ new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -43,7 +47,8 @@ class Sodor3StageSinglePortConfig extends Config(
class Sodor5StageConfig extends Config(
// Create a Sodor 5-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
- new testchipip.WithSerialTLWidth(32) ++
+ new testchipip.soc.WithNoScratchpads ++ // No scratchpads
+ new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -52,7 +57,8 @@ class Sodor5StageConfig extends Config(
class SodorUCodeConfig extends Config(
// Construct a Sodor microcode-based single-bus core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
- new testchipip.WithSerialTLWidth(32) ++
+ new testchipip.soc.WithNoScratchpads ++ // No scratchpads
+ new testchipip.serdes.WithSerialTLWidth(32) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++
diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
index 4c1fc303..6f4c6ab7 100644
--- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
@@ -43,7 +43,7 @@ class SpikeUltraFastDevicesConfig extends Config(
new chipyard.harness.WithSimBlockDevice ++
new chipyard.harness.WithLoopbackNIC ++
new icenet.WithIceNIC ++
- new testchipip.WithBlockDevice ++
+ new testchipip.iceblk.WithBlockDevice ++
new chipyard.WithSpikeTCM ++
new chipyard.WithNSpikeCores(1) ++
diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
index ab00ad24..c9db790d 100644
--- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -7,14 +7,16 @@ class AbstractTraceGenConfig extends Config(
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
new chipyard.harness.WithBlackBoxSimMem ++
new chipyard.harness.WithTraceGenSuccess ++
- new chipyard.harness.WithClockAndResetFromHarness ++
+ new chipyard.harness.WithClockFromHarness ++
+ new chipyard.harness.WithResetFromHarness ++
new chipyard.iobinders.WithAXI4MemPunchthrough ++
new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++
new chipyard.clocking.WithPassthroughClockGenerator ++
- new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++
+ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus"), Nil)) ++
new chipyard.config.WithTracegenSystem ++
- new chipyard.config.WithNoSubsystemDrivenClocks ++
+ new chipyard.config.WithNoSubsystemClockIO ++
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
+ new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
@@ -42,6 +44,6 @@ class NonBlockingTraceGenL2Config extends Config(
class NonBlockingTraceGenL2RingConfig extends Config(
new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
- new testchipip.WithRingSystemBus ++
+ new testchipip.soc.WithRingSystemBus ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new AbstractTraceGenConfig)
diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
index daa08265..cf93d0e4 100644
--- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
@@ -77,7 +77,7 @@ class TutorialSha3BlackBoxConfig extends Config(
// Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators
class TutorialNoCConfig extends Config(
- new chipyard.iobinders.WithDontTouchIOBinders(false) ++
+ new chipyard.harness.WithDontTouchChipTopPorts(false) ++
// Try changing the dimensions of the Mesh topology
new constellation.soc.WithGlobalNoC(constellation.soc.GlobalNoCParams(
NoCParams(
@@ -90,14 +90,14 @@ class TutorialNoCConfig extends Config(
// The inNodeMapping and outNodeMapping values are the physical identifiers of
// routers on the topology to map the agents to. Try changing these to any
// value within the range [0, topology.nNodes)
- new constellation.soc.WithPbusNoC(constellation.protocol.TLNoCParams(
+ new constellation.soc.WithPbusNoC(constellation.protocol.GlobalTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap("Core" -> 7),
outNodeMapping = ListMap(
"pbus" -> 8, "uart" -> 9, "control" -> 10, "gcd" -> 11,
"writeQueue[0]" -> 0, "writeQueue[1]" -> 1, "tailChain[0]" -> 2))
- ), true) ++
- new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
+ )) ++
+ new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Core 0" -> 0, "Core 1" -> 1,
@@ -105,7 +105,7 @@ class TutorialNoCConfig extends Config(
outNodeMapping = ListMap(
"system[0]" -> 3, "system[1]" -> 4, "system[2]" -> 5, "system[3]" -> 6,
"pbus" -> 7))
- ), true) ++
+ )) ++
new chipyard.example.WithGCD ++
new chipyard.harness.WithLoopbackNIC ++
new icenet.WithIceNIC ++
diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
index 2da9fbf2..8cf6ae67 100644
--- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -13,13 +13,14 @@ import freechips.rocketchip.tilelink.{HasTLBusParams}
import chipyard._
import chipyard.clocking._
+import testchipip.soc.{OffchipBusKey}
// The default RocketChip BaseSubsystem drives its diplomatic clock graph
// with the implicit clocks of Subsystem. Don't do that, instead we extend
// the diplomacy graph upwards into the ChipTop, where we connect it to
// our clock drivers
-class WithNoSubsystemDrivenClocks extends Config((site, here, up) => {
- case SubsystemDriveAsyncClockGroupsKey => None
+class WithNoSubsystemClockIO extends Config((site, here, up) => {
+ case SubsystemDriveClockGroupsFromIO => false
})
/**
@@ -103,18 +104,29 @@ class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) =>
class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
})
+class WithOffchipBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
+ case OffchipBusKey => up(OffchipBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+})
class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))
class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing())
+// Remove the tile clock gaters in this system
class WithNoTileClockGaters extends Config((site, here, up) => {
case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileClockGating = false)
})
+// Remove the tile reset control blocks in this system
class WithNoTileResetSetters extends Config((site, here, up) => {
case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileResetSetting = false)
})
+// Remove the global reset synchronizers in this system
class WithNoResetSynchronizers extends Config((site, here, up) => {
case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableResetSynchronizers = false)
})
+
+// Remove any ClockTap ports in this system
+class WithNoClockTap extends Config((site, here, up) => {
+ case ClockTapKey => false
+})
diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
index 8f52be74..51d31094 100644
--- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -29,7 +29,7 @@ import chipyard.{ExtTLMem}
* @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset
* @param contentFileName the path to the BootROM image
*/
-class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => {
+class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10000) extends Config((site, here, up) => {
case BootROMLocated(x) => up(BootROMLocated(x), site)
.map(_.copy(
address = address,
diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
index 4680eeeb..c9f7fcdb 100644
--- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
@@ -12,15 +12,15 @@ import gemmini._
import chipyard.{TestSuitesKey, TestSuiteHelper}
/**
- * Map from a hartId to a particular RoCC accelerator
+ * Map from a tileId to a particular RoCC accelerator
*/
case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])
/**
- * Config fragment to enable different RoCCs based on the hartId
+ * Config fragment to enable different RoCCs based on the tileId
*/
class WithMultiRoCC extends Config((site, here, up) => {
- case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil)
+ case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).tileId, Nil)
})
/**
@@ -39,7 +39,7 @@ class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) =>
*
* For ex:
* Core 0, 1, 2, 3 have been defined earlier
- * with hartIds of 0, 1, 2, 3 respectively
+ * with tileIds of 0, 1, 2, 3 respectively
* And you call WithMultiRoCCHwacha(0,1)
* Then Core 0 and 1 will get a Hwacha
*
diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
index 40f18d5d..b4971cba 100644
--- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
@@ -1,12 +1,17 @@
package chipyard.config
import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper}
+import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy.{DTSTimebase}
+import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
// Replaces the L2 with a broadcast manager for maintaining coherence
class WithBroadcastManager extends Config((site, here, up) => {
- case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
+ case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
+})
+
+class WithBroadcastParams(params: BroadcastParams) extends Config((site, here, up) => {
+ case BroadcastKey => params
})
class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
@@ -16,3 +21,13 @@ class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => {
case DTSTimebase => freqMHz
})
+
+// Adds buffers on the interior of the inclusive LLC, to improve PD
+class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
+ case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)
+})
+
+// Adds buffers on the exterior of the inclusive LLC, to improve PD
+class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
+ case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
+})
diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
index 17eaa3f0..392f1508 100644
--- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -11,7 +11,7 @@ import boom.common.{BoomTileAttachParams}
import cva6.{CVA6TileAttachParams}
import sodor.common.{SodorTileAttachParams}
import ibex.{IbexTileAttachParams}
-import testchipip._
+import testchipip.cosim.{TracePortKey, TracePortParams}
import barf.{TilePrefetchingMasterPortParams}
class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
@@ -66,10 +66,19 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
}
})
+class WithRocketCacheRowBits(rowBits: Int = 64) extends Config((site, here, up) => {
+ case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
+ case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+ dcache = tp.tileParams.dcache.map(_.copy(rowBits = rowBits)),
+ icache = tp.tileParams.icache.map(_.copy(rowBits = rowBits))
+ ))
+ }
+})
+
class WithRocketICacheScratchpad extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
- icache = tp.tileParams.icache.map(_.copy(itimAddr = Some(0x300000 + tp.tileParams.hartId * 0x10000)))
+ icache = tp.tileParams.icache.map(_.copy(itimAddr = Some(0x300000 + tp.tileParams.tileId * 0x10000)))
))
}
})
@@ -77,7 +86,7 @@ class WithRocketICacheScratchpad extends Config((site, here, up) => {
class WithRocketDCacheScratchpad extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
- dcache = tp.tileParams.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + tp.tileParams.hartId * 0x10000)))
+ dcache = tp.tileParams.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + tp.tileParams.tileId * 0x10000)))
))
}
})
@@ -85,14 +94,24 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
class WithTilePrefetchers extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
- master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+ master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
- master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+ master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
- master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+ master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
- master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+ master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
- master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+ master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
}
})
+
+// Adds boundary buffers to RocketTiles, which places buffers between the caches and the TileLink interface
+// This typically makes it easier to close timing
+class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {
+ case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
+ case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(
+ boundaryBuffers=buffers
+ ))
+ }
+})
diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala
index f2ebfc33..f710ccab 100644
--- a/generators/chipyard/src/main/scala/example/CustomChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala
@@ -5,9 +5,11 @@ import chipyard.iobinders._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy.{InModuleBody}
+import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations}
import barstools.iocell.chisel._
import chipyard._
import chipyard.harness.{BuildTop}
+import sifive.blocks.devices.uart._
// A "custom" IOCell with additional I/O
// The IO don't do anything here in this example
@@ -63,3 +65,21 @@ class WithCustomIOCells extends Config((site, here, up) => {
class WithCustomChipTop extends Config((site, here, up) => {
case BuildTop => (p: Parameters) => new CustomChipTop()(p)
})
+
+class WithBrokenOutUARTIO extends OverrideIOBinder({
+ (system: HasPeripheryUARTModuleImp) => {
+ val uart_txd = IO(Output(Bool()))
+ val uart_rxd = IO(Input(Bool()))
+ system.uart(0).rxd := uart_rxd
+ uart_txd := system.uart(0).txd
+ val where = PBUS // TODO fix
+ val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+ val freqMHz = bus.dtsFrequency.get / 1000000
+ (Seq(UARTPort(() => {
+ val uart_wire = Wire(new UARTPortIO(system.uart(0).c))
+ uart_wire.txd := uart_txd
+ uart_rxd := uart_wire.rxd
+ uart_wire
+ }, 0, freqMHz.toInt)), Nil)
+ }
+})
diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
index 96e21611..d4caa49b 100644
--- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
@@ -2,31 +2,34 @@ package chipyard.example
import chisel3._
-import org.chipsalliance.cde.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Config, Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util._
+import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations}
import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug}
import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter}
import chipyard.{BuildSystem, DigitalTop}
+import chipyard.harness.{BuildTop}
import chipyard.clocking._
-import chipyard.iobinders.{IOCellKey, JTAGChipIO}
+import chipyard.iobinders._
import barstools.iocell.chisel._
+import testchipip.serdes.{SerialTLKey}
+class WithFlatChipTop extends Config((site, here, up) => {
+ case BuildTop => (p: Parameters) => new FlatChipTop()(p)
+})
// This "FlatChipTop" uses no IOBinders, so all the IO have
// to be explicitly constructed.
// This only supports the base "DigitalTop"
-class FlatChipTop(implicit p: Parameters) extends LazyModule {
+class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPorts {
override lazy val desiredName = "ChipTop"
val system = LazyModule(p(BuildSystem)(p)).suggestName("system").asInstanceOf[DigitalTop]
//========================
// Diplomatic clock stuff
//========================
- val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
- system.connectImplicitClockSinkNode(implicitClockSinkNode)
-
val tlbus = system.locateTLBusWrapper(system.prciParams.slaveWhere)
val baseAddress = system.prciParams.baseAddress
val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) }
@@ -37,7 +40,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
- system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
+ system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
// Connect all other requested clocks
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
@@ -56,28 +59,26 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
debugClockSinkNode := system.locateTLBusWrapper(p(ExportDebug).slaveWhere).fixedClockNode
def debugClockBundle = debugClockSinkNode.in.head._1
+ var ports: Seq[Port[_]] = Nil
+
override lazy val module = new FlatChipTopImpl
class FlatChipTopImpl extends LazyRawModuleImp(this) {
//=========================
// Clock/reset
//=========================
- val implicit_clock = implicitClockSinkNode.in.head._1.clock
- val implicit_reset = implicitClockSinkNode.in.head._1.reset
- system.module match { case l: LazyModuleImp => {
- l.clock := implicit_clock
- l.reset := implicit_reset
- }}
-
- val clock_wire = Wire(Input(new ClockWithFreq(80)))
+ val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_pad, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_pad, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
slowClockSource.out.unzip._1.map { o =>
- o.clock := clock_wire.clock
+ o.clock := clock_wire
o.reset := reset_wire
}
+ ports = ports :+ ClockPort(() => clock_pad, 100.0)
+ ports = ports :+ ResetPort(() => reset_pad)
+
// For a real chip you should replace this ClockSourceAtFreqFromPlusArg
// with a blackbox of whatever PLL is being integrated
val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
@@ -93,11 +94,13 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
// Custom Boot
//=========================
val (custom_boot_pad, customBootIOCell) = IOCell.generateIOFromSignal(system.custom_boot_pin.get.getWrappedValue, "custom_boot", p(IOCellKey))
+ ports = ports :+ CustomBootPort(() => custom_boot_pad)
//=========================
// Serialized TileLink
//=========================
- val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey))
+ val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tls(0).getWrappedValue, "serial_tl", p(IOCellKey))
+ ports = ports :+ SerialTLPort(() => serial_tl_pad, p(SerialTLKey)(0), system.serdessers(0), 0)
//=========================
// JTAG/Debug
@@ -136,12 +139,17 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
}.get
+ ports = ports :+ JTAGPort(() => jtag_pad)
+
//==========================
// UART
//==========================
require(system.uarts.size == 1)
val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
-
+ val where = PBUS // TODO fix
+ val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+ val freqMHz = bus.dtsFrequency.get / 1000000
+ ports = ports :+ UARTPort(() => uart_pad, 0, freqMHz.toInt)
//==========================
// External interrupts (tie off)
diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
index 56bc9a78..9eeabecf 100644
--- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
+++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
@@ -11,7 +11,10 @@ import freechips.rocketchip.util.{PlusArg}
import freechips.rocketchip.subsystem.{CacheBlockBytes}
import freechips.rocketchip.devices.debug.{SimJTAG}
import freechips.rocketchip.jtag.{JTAGIO}
-import testchipip.{SerialTLKey, UARTAdapter, SimDRAM, TSIHarness, SimTSI}
+import testchipip.serdes._
+import testchipip.uart.{UARTAdapter}
+import testchipip.dram.{SimDRAM}
+import testchipip.tsi.{TSIHarness, SimTSI, SerialRAM}
import chipyard.harness.{BuildTop}
// A "flat" TestHarness that doesn't use IOBinders
@@ -30,7 +33,7 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
val clock_source = Module(new ClockSourceAtFreqFromPlusArg("slow_clk_freq_mhz"))
clock_source.io.power := true.B
clock_source.io.gate := false.B
- dut.clock_pad.clock := clock_source.io.clk
+ dut.clock_pad := clock_source.io.clk
// Reset
dut.reset_pad := reset.asAsyncReset
@@ -39,21 +42,32 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1)
// Serialized TL
- val sVal = p(SerialTLKey).get
- val serialTLManagerParams = sVal.serialTLManagerParams.get
+ val sVal = p(SerialTLKey)(0)
+ val serialTLManagerParams = sVal.manager.get
require(serialTLManagerParams.isMemoryDevice)
- withClockAndReset(clock, reset) {
- val serial_bits = dut.serial_tl_pad.bits
- if (DataMirror.directionOf(dut.serial_tl_pad.clock) == Direction.Input) {
- dut.serial_tl_pad.clock := clock
- }
- val harnessRAM = TSIHarness.connectRAM(
- lazyDut.system.serdesser.get,
- serial_bits,
- reset)
- io.success := SimTSI.connect(Some(harnessRAM.module.io.tsi), clock, reset)
+ // Figure out which clock drives the harness TLSerdes, based on the port type
+ val serial_ram_clock = dut.serial_tl_pad match {
+ case io: InternalSyncSerialIO => io.clock_out
+ case io: ExternalSyncSerialIO => clock
+ }
+ dut.serial_tl_pad match {
+ case io: ExternalSyncSerialIO => io.clock_in := clock
+ case io: InternalSyncSerialIO =>
+ }
+ dut.serial_tl_pad match {
+ case pad: DecoupledSerialIO => {
+ withClockAndReset(serial_ram_clock, reset) {
+ // SerialRAM implements the memory regions the chip expects
+ val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module)
+ ram.io.ser.in <> pad.out
+ pad.in <> ram.io.ser.out
+
+ // Allow TSI to master the chip
+ io.success := SimTSI.connect(ram.io.tsi, serial_ram_clock, reset)
+ }
+ }
}
// JTAG
diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala
index 5e6c5d67..1c1d2e2f 100644
--- a/generators/chipyard/src/main/scala/example/GCD.scala
+++ b/generators/chipyard/src/main/scala/example/GCD.scala
@@ -13,7 +13,7 @@ import freechips.rocketchip.util.UIntIsOneOf
// DOC include start: GCD params
case class GCDParams(
- address: BigInt = 0x1000,
+ address: BigInt = 0x4000,
width: Int = 32,
useAXI4: Boolean = false,
useBlackBox: Boolean = true)
@@ -185,7 +185,7 @@ trait CanHavePeripheryGCD { this: BaseSubsystem =>
// DOC include end: GCD lazy trait
// DOC include start: GCD imp trait
-trait CanHavePeripheryGCDModuleImp extends LazyModuleImp {
+trait CanHavePeripheryGCDModuleImp extends LazyRawModuleImp {
val outer: CanHavePeripheryGCD
val gcd_busy = outer.gcd match {
case Some(gcd) => {
diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
index 38c8577a..76b17273 100644
--- a/generators/chipyard/src/main/scala/example/TutorialTile.scala
+++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -82,7 +82,7 @@ case class MyTileAttachParams(
case class MyTileParams(
name: Option[String] = Some("my_tile"),
- hartId: Int = 0,
+ tileId: Int = 0,
trace: Boolean = false,
val core: MyCoreParams = MyCoreParams()
) extends InstantiableTileParams[MyTile]
@@ -94,9 +94,11 @@ case class MyTileParams(
val dcache: Option[DCacheParams] = Some(DCacheParams())
val icache: Option[ICacheParams] = Some(ICacheParams())
val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
- def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
+ def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
new MyTile(this, crossing, lookup)
}
+ val baseName = name.getOrElse("my_tile")
+ val uniqueName = s"${baseName}_$tileId"
}
// DOC include start: Tile class
@@ -111,11 +113,11 @@ class MyTile(
{
// Private constructor ensures altered LazyModule.p is used implicitly
- def this(params: MyTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
+ def this(params: MyTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)
// Require TileLink nodes
- val intOutwardNode = IntIdentityNode()
+ val intOutwardNode = None
val masterNode = visibilityNode
val slaveNode = TLIdentityNode()
@@ -135,7 +137,7 @@ class MyTile(
}
ResourceBinding {
- Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
+ Resource(cpuDevice, "reg").bind(ResourceAddress(tileId))
}
// TODO: Create TileLink nodes and connections here.
@@ -228,15 +230,15 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
}
// DOC include start: Config fragment
-class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
+class WithNMyCores(n: Int = 1) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
// Calculate the next available hart ID (since hart ID cannot be duplicated)
val prev = up(TilesLocated(InSubsystem), site)
- val idOffset = overrideIdOffset.getOrElse(prev.size)
+ val idOffset = up(NumTiles)
// Create TileAttachParams for every core to be instantiated
(0 until n).map { i =>
MyTileAttachParams(
- tileParams = MyTileParams(hartId = i + idOffset),
+ tileParams = MyTileParams(tileId = i + idOffset),
crossingParams = RocketCrossingParams()
)
} ++ prev
@@ -245,5 +247,6 @@ class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Con
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
// The # of instruction bits. Use maximum # of bits if your core supports both 32 and 64 bits.
case XLen => 64
+ case NumTiles => up(NumTiles) + n
})
// DOC include end: Config fragment
diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
index 01d72d24..df2ec35a 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
@@ -199,12 +199,13 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p
trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
val streamingFIR = p(GenericFIRKey) match {
case Some(params) => {
- val streamingFIR = LazyModule(new TLGenericFIRChain(
+ val domain = pbus.generateSynchronousDomain.suggestName("fir_domain")
+ val streamingFIR = domain { LazyModule(new TLGenericFIRChain(
genIn = FixedPoint(8.W, 3.BP),
genOut = FixedPoint(8.W, 3.BP),
coeffs = Seq(1.U.asFixedPoint(0.BP), 2.U.asFixedPoint(0.BP), 3.U.asFixedPoint(0.BP)),
- params = params))
- pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
+ params = params)) }
+ pbus.coupleTo("streamingFIR") { domain { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) } := _ }
Some(streamingFIR)
}
case None => None
diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
index 45e05fc2..a2259ab1 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
@@ -131,8 +131,9 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
val passthrough = p(StreamingPassthroughKey) match {
case Some(params) => {
- val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W)))
- pbus.coupleTo("streamingPassthrough") { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
+ val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain")
+ val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) }
+ pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ }
Some(streamingPassthroughChain)
}
case None => None
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index b670fd74..59d4110d 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -6,355 +6,313 @@ import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
-import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
-import freechips.rocketchip.devices.debug._
-import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.util._
-
-import sifive.blocks.devices.gpio._
-import sifive.blocks.devices.uart._
-import sifive.blocks.devices.spi._
-
+import freechips.rocketchip.jtag.{JTAGIO}
+import freechips.rocketchip.devices.debug.{SimJTAG}
import barstools.iocell.chisel._
-
-import testchipip._
-
+import testchipip.dram.{SimDRAM}
+import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO}
+import testchipip.soc.{TestchipSimDTM}
+import testchipip.spi.{SimSPIFlashModel}
+import testchipip.uart.{UARTAdapter, UARTToSerial}
+import testchipip.serdes._
+import testchipip.iceblk.{SimBlockDevice, BlockDeviceModel}
+import testchipip.cosim.{SpikeCosim}
+import icenet.{NicLoopback, SimNetwork}
import chipyard._
-import chipyard.clocking.{HasChipyardPRCI, ClockWithFreq}
-import chipyard.iobinders.{GetSystemParameters, JTAGChipIO}
+import chipyard.clocking.{HasChipyardPRCI}
+import chipyard.iobinders._
-import tracegen.{TraceGenSystemModuleImp}
-import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
-
-import scala.reflect.{ClassTag}
-
-case object HarnessBinders extends Field[HarnessBinderMap](HarnessBinderMapDefault)
+case object HarnessBinders extends Field[HarnessBinderFunction]({case _ => })
object ApplyHarnessBinders {
- def apply(th: HasHarnessInstantiators, sys: LazyModule, portMap: Map[String, Seq[Data]])(implicit p: Parameters): Unit = {
- val pm = portMap.withDefaultValue(Nil)
- p(HarnessBinders).foreach { case (s, f) =>
- f(sys, th, pm(s))
- f(sys.module, th, pm(s))
- }
+ def apply(th: HasHarnessInstantiators, ports: Seq[Port[_]], chipId: Int)(implicit p: Parameters): Unit = {
+ ports.foreach(port => p(HarnessBinders)(th, port, chipId))
}
}
-// The ClassTags here are necessary to overcome issues arising from type erasure
-class HarnessBinder[T, S <: HasHarnessInstantiators, U <: Data](composer: ((T, S, Seq[U]) => Unit) => (T, S, Seq[U]) => Unit)(implicit systemTag: ClassTag[T], harnessTag: ClassTag[S], portTag: ClassTag[U]) extends Config((site, here, up) => {
- case HarnessBinders => up(HarnessBinders, site) + (systemTag.runtimeClass.toString ->
- ((t: Any, th: HasHarnessInstantiators, ports: Seq[Data]) => {
- val pts = ports.collect({case p: U => p})
- require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${portTag}")
- val upfn = up(HarnessBinders, site)(systemTag.runtimeClass.toString)
- (th, t) match {
- case (th: S, system: T) => composer(upfn)(system, th, pts)
- case _ =>
- }
- })
- )
+class HarnessBinder[T <: HasHarnessInstantiators, S <: Port[_]](
+ fn: => HarnessBinderFunction
+) extends Config((site, here, up) => {
+ case HarnessBinders => fn orElse up(HarnessBinders)
})
-class OverrideHarnessBinder[T, S <: HasHarnessInstantiators, U <: Data](fn: => (T, S, Seq[U]) => Unit)
- (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U])
- extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Unit) => fn)
-class ComposeHarnessBinder[T, S <: HasHarnessInstantiators, U <: Data](fn: => (T, S, Seq[U]) => Unit)
- (implicit tag: ClassTag[T], thtag: ClassTag[S], ptag: ClassTag[U])
- extends HarnessBinder[T, S, U]((upfn: (T, S, Seq[U]) => Unit) => (t, th, p) => {
- upfn(t, th, p)
- fn(t, th, p)
- })
-
-
-class WithGPIOTiedOff extends OverrideHarnessBinder({
- (system: HasPeripheryGPIOModuleImp, th: HasHarnessInstantiators, ports: Seq[Analog]) => {
- ports.foreach { _ <> AnalogConst(0) }
+class WithGPIOTiedOff extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: GPIOPort, chipId: Int) => {
+ port.io <> AnalogConst(0)
}
})
// DOC include start: WithUARTAdapter
-class WithUARTAdapter extends OverrideHarnessBinder({
- (system: HasPeripheryUARTModuleImp, th: HasHarnessInstantiators, ports: Seq[UARTPortIO]) => {
- UARTAdapter.connect(ports)(system.p)
+class WithUARTAdapter extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => {
+ val div = (th.getHarnessBinderClockFreqMHz.toDouble * 1000000 / port.io.c.initBaudRate.toDouble).toInt
+ UARTAdapter.connect(Seq(port.io), div, false)
}
})
// DOC include end: WithUARTAdapter
-class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({
- (system: HasPeripherySPIFlashModuleImp, th: HasHarnessInstantiators, ports: Seq[SPIChipIO]) => {
- SimSPIFlashModel.connect(ports, th.harnessBinderReset, rdOnly)(system.p)
+class WithSimSPIFlashModel(rdOnly: Boolean = true) extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: SPIFlashPort, chipId: Int) => {
+ val spi_mem = Module(new SimSPIFlashModel(port.params.fSize, port.spiId, rdOnly)).suggestName(s"spi_mem${port.spiId}")
+ spi_mem.io.sck := port.io.sck
+ require(port.params.csWidth == 1, "I don't know what to do with your extra CS bits. Fix me please.")
+ spi_mem.io.cs(0) := port.io.cs(0)
+ spi_mem.io.dq.zip(port.io.dq).foreach { case (x, y) => x <> y }
+ spi_mem.io.reset := th.harnessBinderReset
}
})
-class WithSimBlockDevice extends OverrideHarnessBinder({
- (system: CanHavePeripheryBlockDevice, th: HasHarnessInstantiators, ports: Seq[ClockedIO[BlockDeviceIO]]) => {
- implicit val p: Parameters = GetSystemParameters(system)
- ports.map { b => SimBlockDevice.connect(b.clock, th.harnessBinderReset.asBool, Some(b.bits)) }
+class WithSimBlockDevice extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: BlockDevicePort, chipId: Int) => {
+ val sim_blkdev = Module(new SimBlockDevice(port.params))
+ sim_blkdev.io.bdev <> port.io.bits
+ sim_blkdev.io.clock := port.io.clock
+ sim_blkdev.io.reset := th.harnessBinderReset
}
})
-class WithBlockDeviceModel extends OverrideHarnessBinder({
- (system: CanHavePeripheryBlockDevice, th: HasHarnessInstantiators, ports: Seq[ClockedIO[BlockDeviceIO]]) => {
- implicit val p: Parameters = GetSystemParameters(system)
- ports.map { b => BlockDeviceModel.connect(Some(b.bits)) }
+class WithBlockDeviceModel extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: BlockDevicePort, chipId: Int) => {
+ val blkdev_model = Module(new BlockDeviceModel(16, port.params))
+ blkdev_model.io <> port.io.bits
+ blkdev_model.clock := port.io.clock
+ blkdev_model.reset := th.harnessBinderReset
}
})
-class WithLoopbackNIC extends OverrideHarnessBinder({
- (system: CanHavePeripheryIceNIC, th: HasHarnessInstantiators, ports: Seq[ClockedIO[NICIOvonly]]) => {
- implicit val p: Parameters = GetSystemParameters(system)
- ports.map { n => NicLoopback.connect(Some(n.bits), p(NICKey)) }
+class WithLoopbackNIC extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: NICPort, chipId: Int) => {
+ withClock(port.io.clock) { NicLoopback.connect(port.io.bits, port.params) }
}
})
-class WithSimNetwork extends OverrideHarnessBinder({
- (system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessInstantiators, ports: Seq[ClockedIO[NICIOvonly]]) => {
- implicit val p: Parameters = GetSystemParameters(system)
- ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.harnessBinderReset.asBool) }
+class WithSimNetwork extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: NICPort, chipId: Int) => {
+ withClock(port.io.clock) { SimNetwork.connect(Some(port.io.bits), port.io.clock, th.harnessBinderReset.asBool) }
}
})
-class WithSimAXIMem extends OverrideHarnessBinder({
- (system: CanHaveMasterAXI4MemPort, th: HasHarnessInstantiators, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
- val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
- (ports zip system.memAXI4Node.edges.in).map { case (port, edge) =>
- val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p))
- Module(mem.module).suggestName("mem")
- mem.io_axi4.head <> port.bits
+class WithSimAXIMem extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: AXI4MemPort, chipId: Int) => {
+ val mem = LazyModule(new SimAXIMem(port.edge, size=port.params.master.size)(Parameters.empty))
+ withClock(port.io.clock) { Module(mem.module) }
+ mem.io_axi4.head <> port.io.bits
+ }
+})
+
+class WithBlackBoxSimMem(additionalLatency: Int = 0) extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: AXI4MemPort, chipId: Int) => {
+ // TODO FIX: This currently makes each SimDRAM contain the entire memory space
+ val memSize = port.params.master.size
+ val memBase = port.params.master.base
+ val lineSize = 64 // cache block size
+ val clockFreq = port.clockFreqMHz
+ val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, port.edge.bundle, chipId)).suggestName("simdram")
+
+ mem.io.clock := port.io.clock
+ mem.io.reset := th.harnessBinderReset.asAsyncReset
+ mem.io.axi <> port.io.bits
+ // Bug in Chisel implementation. See https://github.com/chipsalliance/chisel3/pull/1781
+ def Decoupled[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = {
+ require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.")
+ val d = Wire(new DecoupledIO(chiselTypeOf(irr.bits)))
+ d.bits := irr.bits
+ d.valid := irr.valid
+ irr.ready := d.ready
+ d
+ }
+ if (additionalLatency > 0) {
+ withClock (port.io.clock) {
+ mem.io.axi.aw <> (0 until additionalLatency).foldLeft(Decoupled(port.io.bits.aw))((t, _) => Queue(t, 1, pipe=true))
+ mem.io.axi.w <> (0 until additionalLatency).foldLeft(Decoupled(port.io.bits.w ))((t, _) => Queue(t, 1, pipe=true))
+ port.io.bits.b <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.b ))((t, _) => Queue(t, 1, pipe=true))
+ mem.io.axi.ar <> (0 until additionalLatency).foldLeft(Decoupled(port.io.bits.ar))((t, _) => Queue(t, 1, pipe=true))
+ port.io.bits.r <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.r ))((t, _) => Queue(t, 1, pipe=true))
+ }
}
}
})
-class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBinder({
- (system: CanHaveMasterAXI4MemPort, th: HasHarnessInstantiators, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
- val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
- (ports zip system.memAXI4Node.edges.in).map { case (port, edge) =>
- // TODO FIX: This currently makes each SimDRAM contain the entire memory space
- val memSize = p(ExtMem).get.master.size
- val memBase = p(ExtMem).get.master.base
- val lineSize = p(CacheBlockBytes)
- val clockFreq = p(MemoryBusKey).dtsFrequency.get
- val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, edge.bundle)).suggestName("simdram")
- mem.io.axi <> port.bits
- // Bug in Chisel implementation. See https://github.com/chipsalliance/chisel3/pull/1781
- def Decoupled[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = {
- require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.")
- val d = Wire(new DecoupledIO(chiselTypeOf(irr.bits)))
- d.bits := irr.bits
- d.valid := irr.valid
- irr.ready := d.ready
- d
+class WithSimAXIMMIO extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: AXI4MMIOPort, chipId: Int) => {
+ val mmio_mem = LazyModule(new SimAXIMem(port.edge, size = port.params.size)(Parameters.empty))
+ withClock(port.io.clock) { Module(mmio_mem.module).suggestName("mmio_mem") }
+ mmio_mem.io_axi4.head <> port.io.bits
+ }
+})
+
+class WithTieOffInterrupts extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: ExtIntPort, chipId: Int) => {
+ port.io := 0.U
+ }
+})
+
+class WithTieOffL2FBusAXI extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: AXI4InPort, chipId: Int) => {
+ port.io := DontCare
+ port.io.bits.aw.valid := false.B
+ port.io.bits.w.valid := false.B
+ port.io.bits.b.ready := false.B
+ port.io.bits.ar.valid := false.B
+ port.io.bits.r.ready := false.B
+ }
+})
+
+class WithSimJTAGDebug extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => {
+ val dtm_success = WireInit(false.B)
+ when (dtm_success) { th.success := true.B }
+ val jtag_wire = Wire(new JTAGIO)
+ jtag_wire.TDO.data := port.io.TDO
+ jtag_wire.TDO.driven := true.B
+ port.io.TCK := jtag_wire.TCK
+ port.io.TMS := jtag_wire.TMS
+ port.io.TDI := jtag_wire.TDI
+ val jtag = Module(new SimJTAG(tickDelay=3))
+ jtag.connect(jtag_wire, th.harnessBinderClock, th.harnessBinderReset.asBool, ~(th.harnessBinderReset.asBool), dtm_success)
+ }
+})
+
+class WithSimDMI extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => {
+ val dtm_success = WireInit(false.B)
+ when (dtm_success) { th.success := true.B }
+ val dtm = Module(new TestchipSimDTM()(Parameters.empty)).connect(th.harnessBinderClock, th.harnessBinderReset.asBool, port.io, dtm_success)
+ }
+})
+
+class WithTiedOffJTAG extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => {
+ port.io.TCK := true.B.asClock
+ port.io.TMS := true.B
+ port.io.TDI := true.B
+ }
+})
+
+class WithTiedOffDMI extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => {
+ port.io.dmi.req.valid := false.B
+ port.io.dmi.req.bits := DontCare
+ port.io.dmi.resp.ready := true.B
+ port.io.dmiClock := false.B.asClock
+ port.io.dmiReset := true.B
+ }
+})
+
+// If tieoffs is specified, a list of serial portIds to tie off
+// If tieoffs is unspecified, ties off all serial ports
+class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => {
+ port.io match {
+ case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
+ case io: SourceSyncSerialIO => {
+ io.clock_in := false.B.asClock
+ io.reset_in := false.B.asAsyncReset
+ io.in := DontCare
+ io.credit_in := DontCare
}
- if (additionalLatency > 0) {
- withClockAndReset (port.clock, port.reset) {
- mem.io.axi.aw <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.aw))((t, _) => Queue(t, 1, pipe=true))
- mem.io.axi.w <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.w ))((t, _) => Queue(t, 1, pipe=true))
- port.bits.b <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.b))((t, _) => Queue(t, 1, pipe=true))
- mem.io.axi.ar <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.ar))((t, _) => Queue(t, 1, pipe=true))
- port.bits.r <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.r))((t, _) => Queue(t, 1, pipe=true))
+ }
+ port.io match {
+ case io: InternalSyncSerialIO =>
+ case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
+ case _ =>
+ }
+ }
+})
+
+class WithSimTSIOverSerialTL extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (port.portId == 0) => {
+ port.io match {
+ case io: InternalSyncSerialIO =>
+ case io: ExternalSyncSerialIO => io.clock_in := th.harnessBinderClock
+ }
+
+ port.io match {
+ case io: DecoupledSerialIO => {
+ // If the port is locally synchronous (provides a clock), drive everything with that clock
+ // Else, drive everything with the harnes clock
+ val clock = port.io match {
+ case io: InternalSyncSerialIO => io.clock_out
+ case io: ExternalSyncSerialIO => th.harnessBinderClock
+ }
+ withClock(clock) {
+ val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
+ ram.io.ser.in <> io.out
+ io.in <> ram.io.ser.out
+
+ val success = SimTSI.connect(ram.io.tsi, clock, th.harnessBinderReset, chipId)
+ when (success) { th.success := true.B }
}
}
- mem.io.clock := port.clock
- mem.io.reset := port.reset
}
}
})
-class WithSimAXIMMIO extends OverrideHarnessBinder({
- (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessInstantiators, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
- val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
- (ports zip system.mmioAXI4Node.edges.in).map { case (port, edge) =>
- val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p))
- withClockAndReset(port.clock, port.reset) {
- Module(mmio_mem.module).suggestName("mmio_mem")
- }
- mmio_mem.io_axi4.head <> port.bits
- }
+class WithDriveChipIdPin extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: ChipIdPort, chipId: Int) => {
+ require(chipId < math.pow(2, port.io.getWidth), "ID Pin is not wide enough")
+ port.io := chipId.U
}
})
-class WithTieOffInterrupts extends OverrideHarnessBinder({
- (system: HasExtInterruptsModuleImp, th: HasHarnessInstantiators, ports: Seq[UInt]) => {
- ports.foreach { _ := 0.U }
+class WithSimUARTToUARTTSI extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => {
+ UARTAdapter.connect(Seq(port.io),
+ baudrate=port.io.c.initBaudRate,
+ clockFrequency=th.getHarnessBinderClockFreqHz.toInt,
+ forcePty=true)
}
})
-class WithTieOffL2FBusAXI extends OverrideHarnessBinder({
- (system: CanHaveSlaveAXI4Port, th: HasHarnessInstantiators, ports: Seq[ClockedIO[AXI4Bundle]]) => {
- ports.foreach({ p =>
- p.bits := DontCare
- p.bits.aw.valid := false.B
- p.bits.w.valid := false.B
- p.bits.b.ready := false.B
- p.bits.ar.valid := false.B
- p.bits.r.ready := false.B
- })
+class WithSimTSIToUARTTSI extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
+ val freq = th.getHarnessBinderClockFreqHz.toInt
+ val uart_to_serial = Module(new UARTToSerial(freq, port.io.uart.c))
+ val serial_width_adapter = Module(new SerialWidthAdapter(8, TSI.WIDTH))
+ val success = SimTSI.connect(Some(TSIIO(serial_width_adapter.io.wide)), th.harnessBinderClock, th.harnessBinderReset)
+ when (success) { th.success := true.B }
+ assert(!uart_to_serial.io.dropped)
+ serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
+ uart_to_serial.io.uart.rxd := port.io.uart.txd
+ port.io.uart.rxd := uart_to_serial.io.uart.txd
}
})
-class WithSimDebug extends OverrideHarnessBinder({
- (system: HasPeripheryDebug, th: HasHarnessInstantiators, ports: Seq[Data]) => {
- implicit val p: Parameters = GetSystemParameters(system)
- ports.map {
- case d: ClockedDMIIO =>
- val dtm_success = WireInit(false.B)
- when (dtm_success) { th.success := true.B }
- val dtm = Module(new TestchipSimDTM).connect(th.harnessBinderClock, th.harnessBinderReset.asBool, d, dtm_success)
- case j: JTAGChipIO =>
- val dtm_success = WireInit(false.B)
- when (dtm_success) { th.success := true.B }
- val jtag_wire = Wire(new JTAGIO)
- jtag_wire.TDO.data := j.TDO
- jtag_wire.TDO.driven := true.B
- j.TCK := jtag_wire.TCK
- j.TMS := jtag_wire.TMS
- j.TDI := jtag_wire.TDI
- val jtag = Module(new SimJTAG(tickDelay=3))
- jtag.connect(jtag_wire, th.harnessBinderClock, th.harnessBinderReset.asBool, ~(th.harnessBinderReset.asBool), dtm_success)
- }
+class WithTraceGenSuccess extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: SuccessPort, chipId: Int) => {
+ when (port.io) { th.success := true.B }
}
})
-class WithTiedOffDebug extends OverrideHarnessBinder({
- (system: HasPeripheryDebug, th: HasHarnessInstantiators, ports: Seq[Data]) => {
- ports.map {
- case j: JTAGChipIO =>
- j.TCK := true.B.asClock
- j.TMS := true.B
- j.TDI := true.B
- case d: ClockedDMIIO =>
- d.dmi.req.valid := false.B
- d.dmi.req.bits := DontCare
- d.dmi.resp.ready := true.B
- d.dmiClock := false.B.asClock
- d.dmiReset := true.B
- case a: ClockedAPBBundle =>
- a.pready := false.B
- a.pslverr := false.B
- a.prdata := 0.U
- a.pduser := DontCare
- a.clock := false.B.asClock
- a.reset := true.B.asAsyncReset
- a.psel := false.B
- a.penable := false.B
- }
+class WithCospike extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: TracePort, chipId: Int) => {
+ port.io.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2, port.cosimCfg))
}
})
-class WithSerialTLTiedOff extends OverrideHarnessBinder({
- (system: CanHavePeripheryTLSerial, th: HasHarnessInstantiators, ports: Seq[ClockedIO[SerialIO]]) => {
- implicit val p = chipyard.iobinders.GetSystemParameters(system)
- ports.map({ port =>
- val bits = port.bits
- if (DataMirror.directionOf(port.clock) == Direction.Input) {
- port.clock := false.B.asClock
- }
- port.bits.out.ready := false.B
- port.bits.in.valid := false.B
- port.bits.in.bits := DontCare
- })
- }
-})
-
-class WithSimTSIOverSerialTL extends OverrideHarnessBinder({
- (system: CanHavePeripheryTLSerial, th: HasHarnessInstantiators, ports: Seq[ClockedIO[SerialIO]]) => {
- implicit val p = chipyard.iobinders.GetSystemParameters(system)
- ports.map({ port =>
- val bits = port.bits
- if (DataMirror.directionOf(port.clock) == Direction.Input) {
- port.clock := th.harnessBinderClock
- }
- val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.harnessBinderReset)
- val success = SimTSI.connect(Some(ram.module.io.tsi), th.harnessBinderClock, th.harnessBinderReset.asBool)
- when (success) { th.success := true.B }
- })
- }
-})
-
-class WithSimUARTToUARTTSI extends OverrideHarnessBinder({
- (system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTTSIIO]) => {
- implicit val p = chipyard.iobinders.GetSystemParameters(system)
- require(ports.size <= 1)
- ports.map { port => {
- UARTAdapter.connect(Seq(port.uart),
- baudrate=port.uartParams.initBaudRate,
- clockFrequency=th.getHarnessBinderClockFreqHz.toInt,
- forcePty=true)
- assert(!port.dropped)
- }}
- }
-})
-
-class WithSimTSIToUARTTSI extends OverrideHarnessBinder({
- (system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTTSIIO]) => {
- implicit val p = chipyard.iobinders.GetSystemParameters(system)
- require(ports.size <= 1)
- ports.map({ port =>
- val freq = th.getHarnessBinderClockFreqHz.toInt
- val uart_to_serial = Module(new UARTToSerial(freq, port.uartParams))
- val serial_width_adapter = Module(new SerialWidthAdapter(8, TSI.WIDTH))
- val success = SimTSI.connect(Some(TSIIO(serial_width_adapter.io.wide)), th.harnessBinderClock, th.harnessBinderReset)
- when (success) { th.success := true.B }
- assert(!uart_to_serial.io.dropped)
- serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
- uart_to_serial.io.uart.rxd := port.uart.txd
- port.uart.rxd := uart_to_serial.io.uart.txd
- })
- }
-})
-
-
-class WithTraceGenSuccess extends OverrideHarnessBinder({
- (system: TraceGenSystemModuleImp, th: HasHarnessInstantiators, ports: Seq[Bool]) => {
- ports.map { p => when (p) { th.success := true.B } }
- }
-})
-
-class WithCospike extends ComposeHarnessBinder({
- (system: CanHaveTraceIOModuleImp, th: HasHarnessInstantiators, ports: Seq[TraceOutputTop]) => {
- implicit val p = chipyard.iobinders.GetSystemParameters(system)
- val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem]
- val tiles = chipyardSystem.tiles
- val cfg = SpikeCosimConfig(
- isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
- vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0),
- priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
- mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
- mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
- pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
- nharts = tiles.size,
- bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
- has_dtm = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
- )
- ports.map { p => p.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2, cfg)) }
- }
-})
-
-
-class WithCustomBootPinPlusArg extends OverrideHarnessBinder({
- (system: CanHavePeripheryCustomBootPin, th: HasHarnessInstantiators, ports: Seq[Bool]) => {
+class WithCustomBootPinPlusArg extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: CustomBootPort, chipId: Int) => {
val pin = PlusArg("custom_boot_pin", width=1)
- ports.foreach(_ := pin)
+ port.io := pin
}
})
-
-class WithClockAndResetFromHarness extends OverrideHarnessBinder({
- (system: HasChipyardPRCI, th: HasHarnessInstantiators, ports: Seq[Data]) => {
- implicit val p = GetSystemParameters(system)
- val clocks = ports.collect { case c: ClockWithFreq => c }
+class WithClockFromHarness extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: ClockPort, chipId: Int) => {
// DOC include start: HarnessClockInstantiatorEx
- ports.map ({
- case c: ClockWithFreq => {
- val clock = th.harnessClockInstantiator.requestClockMHz(s"clock_${c.freqMHz.toInt}MHz", c.freqMHz)
- c.clock := clock
- }
- case r: AsyncReset => r := th.referenceReset.asAsyncReset
- })
+ port.io := th.harnessClockInstantiator.requestClockMHz(s"clock_${port.freqMHz}MHz", port.freqMHz)
// DOC include end: HarnessClockInstantiatorEx
}
})
+
+class WithResetFromHarness extends HarnessBinder({
+ case (th: HasHarnessInstantiators, port: ResetPort, chipId: Int) => {
+ port.io := th.referenceReset.asAsyncReset
+ }
+})
+
diff --git a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala
index 0f58f33b..cfc1cad4 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala
@@ -10,7 +10,6 @@ import freechips.rocketchip.util.{ResetCatchAndSync}
import freechips.rocketchip.prci._
import chipyard.harness.{ApplyHarnessBinders, HarnessBinders, HarnessClockInstantiatorKey}
-import chipyard.iobinders.HasIOBinders
import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
diff --git a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
index e79b6c4e..b8674623 100644
--- a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
+++ b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
@@ -5,12 +5,12 @@ import chisel3._
import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
import freechips.rocketchip.diplomacy.{LazyModule}
import org.chipsalliance.cde.config.{Field, Parameters, Config}
-import freechips.rocketchip.util.{ResetCatchAndSync}
+import freechips.rocketchip.util.{ResetCatchAndSync, DontTouch}
import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
import chipyard.stage.phases.TargetDirKey
import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
-import chipyard.iobinders.HasIOBinders
+import chipyard.iobinders.HasChipyardPorts
import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
import chipyard.{ChipTop}
@@ -24,6 +24,7 @@ case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) =>
case object HarnessClockInstantiatorKey extends Field[() => HarnessClockInstantiator]()
case object HarnessBinderClockFrequencyKey extends Field[Double](100.0) // MHz
case object MultiChipIdx extends Field[Int](0)
+case object DontTouchChipTopPorts extends Field[Boolean](true)
class WithMultiChip(id: Int, p: Parameters) extends Config((site, here, up) => {
case MultiChipParameters(`id`) => p
@@ -39,6 +40,10 @@ class WithHarnessBinderClockFreqMHz(freqMHz: Double) extends Config((site, here,
case HarnessBinderClockFrequencyKey => freqMHz
})
+class WithDontTouchChipTopPorts(b: Boolean = true) extends Config((site, here, up) => {
+ case DontTouchChipTopPorts => b
+})
+
// A TestHarness mixing this in will
// - use the HarnessClockInstantiator clock provide
trait HasHarnessInstantiators {
@@ -63,7 +68,7 @@ trait HasHarnessInstantiators {
val supportsMultiChip: Boolean = false
- private val chipParameters = p(MultiChipNChips) match {
+ val chipParameters = p(MultiChipNChips) match {
case Some(n) => (0 until n).map { i => p(MultiChipParameters(i)).alterPartial {
case TargetDirKey => p(TargetDirKey) // hacky fix
case MultiChipIdx => i
@@ -83,12 +88,20 @@ trait HasHarnessInstantiators {
withClockAndReset (harnessBinderClock, harnessBinderReset) {
lazyDuts.zipWithIndex.foreach {
- case (d: HasIOBinders, i: Int) => ApplyHarnessBinders(this, d.lazySystem, d.portMap)(chipParameters(i))
+ case (d: HasChipyardPorts, i: Int) => {
+ ApplyHarnessBinders(this, d.ports, i)(chipParameters(i))
+ }
case _ =>
}
ApplyMultiHarnessBinders(this, lazyDuts)
}
+ if (p(DontTouchChipTopPorts)) {
+ duts.map(_ match {
+ case d: DontTouch => d.dontTouchPorts()
+ })
+ }
+
val harnessBinderClk = harnessClockInstantiator.requestClockMHz("harnessbinder_clock", getHarnessBinderClockFreqMHz)
println(s"Harness binder clock is $harnessBinderClockFreq")
harnessBinderClock := harnessBinderClk
diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
index 1c057dff..4f32880e 100644
--- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
@@ -2,6 +2,7 @@ package chipyard.harness
import chisel3._
import chisel3.util._
+import chisel3.experimental.{DataMirror, Direction}
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
@@ -9,70 +10,75 @@ import freechips.rocketchip.devices.debug._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.util._
-import testchipip._
+import testchipip.serdes._
import chipyard._
-import chipyard.clocking.{HasChipyardPRCI, ClockWithFreq}
-import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, HasIOBinders}
+import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, HasChipyardPorts, Port, SerialTLPort}
import scala.reflect.{ClassTag}
-case class MultiHarnessBinders(c0: Int, c1: Int) extends Field[MultiHarnessBinderMap](MultiHarnessBinderMapDefault)
-
-class MultiHarnessBinder[T0, T1, S <: HasHarnessInstantiators, U0 <: Data, U1 <: Data]
- (chip0: Int, chip1: Int, fn: => (T0, T1, S, Seq[U0], Seq[U1]) => Unit)
- (implicit tag0: ClassTag[T0], tag1: ClassTag[T1], thtag: ClassTag[S], ptag0: ClassTag[U0], ptag1: ClassTag[U1])
- extends Config((site, here, up) => {
- // Override any HarnessBinders for chip0/chip1
- case MultiChipParameters(`chip0`) => new Config(
- new OverrideHarnessBinder[T0, S, U0]((system: T0, th: S, ports: Seq[U0]) => Nil) ++
- up(MultiChipParameters(chip0))
- )
- case MultiChipParameters(`chip1`) => new Config(
- new OverrideHarnessBinder[T1, S, U1]((system: T1, th: S, ports: Seq[U1]) => Nil) ++
- up(MultiChipParameters(chip1))
- )
- // Set the multiharnessbinder key
- case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) +
- ((tag0.runtimeClass.toString, tag1.runtimeClass.toString) ->
- ((c0: Any, c1: Any, th: HasHarnessInstantiators, ports0: Seq[Data], ports1: Seq[Data]) => {
- val pts0 = ports0.map(_.asInstanceOf[U0])
- val pts1 = ports1.map(_.asInstanceOf[U1])
- require(pts0.size == pts1.size)
- (c0, c1, th) match {
- case (c0: T0, c1: T1, th: S) => fn(c0, c1, th, pts0, pts1)
- case _ =>
- }
- })
- )
- })
+case class MultiHarnessBinders(chip0: Int, chip1: Int) extends Field[Seq[MultiHarnessBinderFunction]](Nil)
object ApplyMultiHarnessBinders {
def apply(th: HasHarnessInstantiators, chips: Seq[LazyModule])(implicit p: Parameters): Unit = {
Seq.tabulate(chips.size, chips.size) { case (i, j) => if (i != j) {
(chips(i), chips(j)) match {
- case (l0: HasIOBinders, l1: HasIOBinders) => p(MultiHarnessBinders(i, j)).foreach {
- case ((s0, s1), f) => {
- f(l0.lazySystem , l1.lazySystem , th, l0.portMap(s0), l1.portMap(s1))
- f(l0.lazySystem.module, l1.lazySystem.module, th, l0.portMap(s0), l1.portMap(s1))
- }
+ case (l0: HasChipyardPorts, l1: HasChipyardPorts) => p(MultiHarnessBinders(i, j)).foreach { f =>
+ f(th, l0.ports, l1.ports)
}
- case _ =>
}
}}
}
}
-class WithMultiChipSerialTL(chip0: Int, chip1: Int) extends MultiHarnessBinder(chip0, chip1, (
- (system0: CanHavePeripheryTLSerial, system1: CanHavePeripheryTLSerial,
- th: HasHarnessInstantiators,
- ports0: Seq[ClockedIO[SerialIO]], ports1: Seq[ClockedIO[SerialIO]]
- ) => {
- require(ports0.size == ports1.size)
- (ports0 zip ports1).map { case (l, r) =>
- l.clock <> r.clock
- require(l.bits.w == r.bits.w)
- l.bits.flipConnect(r.bits)
+class MultiHarnessBinder[T <: Port[_], S <: HasHarnessInstantiators](
+ chip0: Int, chip1: Int,
+ chip0portFn: T => Boolean, chip1portFn: T => Boolean,
+ connectFn: (S, T, T) => Unit
+)(implicit tag0: ClassTag[T], tag1: ClassTag[S]) extends Config((site, here, up) => {
+ // Override any HarnessBinders for chip0/chip1
+ case MultiChipParameters(`chip0`) => new Config(
+ new HarnessBinder({case (th: S, port: T, chipId: Int) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0))
+ )
+ case MultiChipParameters(`chip1`) => new Config(
+ new HarnessBinder({case (th: S, port: T, chipId: Int) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1))
+ )
+ // Set the multiharnessbinder key
+ case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) :+ {
+ ((th: S, chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => {
+ val chip0Port: Seq[T] = chip0Ports.collect { case (p: T) if chip0portFn(p) => p }
+ val chip1Port: Seq[T] = chip1Ports.collect { case (p: T) if chip1portFn(p) => p }
+ require(chip0Port.size == 1 && chip1Port.size == 1)
+ connectFn(th, chip0Port(0), chip1Port(0))
+ })
+ }
+ })
+
+
+class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder(
+ chip0, chip1,
+ (p0: SerialTLPort) => p0.portId == chip0portId,
+ (p1: SerialTLPort) => p1.portId == chip1portId,
+ (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
+ def connectDecoupledSyncSerialIO(clkSource: InternalSyncSerialIO, clkSink: ExternalSyncSerialIO) = {
+ clkSink.clock_in := clkSource.clock_out
+ clkSink.in <> clkSource.out
+ clkSource.in <> clkSink.out
+ }
+ def connectSourceSyncSerialIO(a: SourceSyncSerialIO, b: SourceSyncSerialIO) = {
+ a.clock_in := b.clock_out
+ b.clock_in := a.clock_out
+ a.reset_in := b.reset_out
+ b.reset_in := a.reset_out
+ a.in := b.out
+ b.in := a.out
+ a.credit_in := b.credit_out
+ b.credit_in := a.credit_out
+ }
+ (p0.io, p1.io) match {
+ case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1)
+ case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0)
+ case (io0: SourceSyncSerialIO , io1: SourceSyncSerialIO ) => connectSourceSyncSerialIO (io0, io1)
}
}
-))
+)
diff --git a/generators/chipyard/src/main/scala/harness/TestHarness.scala b/generators/chipyard/src/main/scala/harness/TestHarness.scala
index 459c6511..43bf2dd0 100644
--- a/generators/chipyard/src/main/scala/harness/TestHarness.scala
+++ b/generators/chipyard/src/main/scala/harness/TestHarness.scala
@@ -9,7 +9,6 @@ import freechips.rocketchip.util.{ResetCatchAndSync}
import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
-import chipyard.iobinders.HasIOBinders
import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
import chipyard.{ChipTop}
diff --git a/generators/chipyard/src/main/scala/harness/package.scala b/generators/chipyard/src/main/scala/harness/package.scala
index 789d1595..d49c1119 100644
--- a/generators/chipyard/src/main/scala/harness/package.scala
+++ b/generators/chipyard/src/main/scala/harness/package.scala
@@ -5,13 +5,7 @@ import scala.collection.immutable.ListMap
package object harness
{
- type HarnessBinderFunction = (Any, HasHarnessInstantiators, Seq[Data]) => Unit
- type HarnessBinderMap = Map[String, HarnessBinderFunction]
- def HarnessBinderMapDefault: HarnessBinderMap = (new ListMap[String, HarnessBinderFunction])
- .withDefaultValue((t: Any, th: HasHarnessInstantiators, d: Seq[Data]) => ())
-
- type MultiHarnessBinderFunction = (Any, Any, HasHarnessInstantiators, Seq[Data], Seq[Data]) => Unit
- type MultiHarnessBinderMap = Map[(String, String), MultiHarnessBinderFunction]
- def MultiHarnessBinderMapDefault: MultiHarnessBinderMap = (new ListMap[(String, String), MultiHarnessBinderFunction])
- .withDefaultValue((_: Any, _: Any, _: HasHarnessInstantiators, _: Seq[Data], _: Seq[Data]) => ())
+ import chipyard.iobinders.Port
+ type HarnessBinderFunction = PartialFunction[(HasHarnessInstantiators, Port[_], Int), Unit]
+ type MultiHarnessBinderFunction = (HasHarnessInstantiators, Seq[Port[_]], Seq[Port[_]]) => Unit
}
diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
similarity index 64%
rename from generators/chipyard/src/main/scala/IOBinders.scala
rename to generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index b74d8f0e..64b1296e 100644
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -1,7 +1,8 @@
package chipyard.iobinders
import chisel3._
-import chisel3.experimental.{Analog, IO, DataMirror}
+import chisel3.reflect.DataMirror
+import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
@@ -18,18 +19,26 @@ import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
+import sifive.blocks.devices.i2c._
import tracegen.{TraceGenSystemModuleImp}
import barstools.iocell.chisel._
-import testchipip._
+import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
+import testchipip.spi.{SPIChipIO}
+import testchipip.boot.{CanHavePeripheryCustomBootPin}
+import testchipip.soc.{CanHavePeripheryChipIdPin}
+import testchipip.util.{ClockedIO}
+import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO}
+import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
+import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
-import chipyard.{CanHaveMasterTLMemPort}
+import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
import scala.reflect.{ClassTag}
object IOBinderTypes {
- type IOBinderTuple = (Seq[Data], Seq[IOCell])
+ type IOBinderTuple = (Seq[Port[_]], Seq[IOCell])
type IOBinderFunction = (Boolean, => Any) => ModuleValue[IOBinderTuple]
}
import IOBinderTypes._
@@ -50,13 +59,7 @@ case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]](
Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil)
)
-case object DontTouchIOBindersPorts extends Field[Boolean](true)
-
-class WithDontTouchIOBinders(b: Boolean = true) extends Config((site, here, up) => {
- case DontTouchIOBindersPorts => b
-})
-
-abstract trait HasIOBinders { this: LazyModule =>
+abstract trait HasIOBinders extends HasChipyardPorts { this: LazyModule =>
val lazySystem: LazyModule
private val iobinders = p(IOBinders)
// Note: IOBinders cannot rely on the implicit clock/reset, as they may be called from the
@@ -80,11 +83,9 @@ abstract trait HasIOBinders { this: LazyModule =>
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop iocells
val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap }
- InModuleBody {
- if (p(DontTouchIOBindersPorts)) {
- portMap.values.foreach(_.foreach(dontTouch(_)))
- }
+ def ports = portMap.getWrappedValue.values.flatten.toSeq
+ InModuleBody {
println("IOCells generated by IOBinders:")
for ((k, v) <- iocellMap) {
if (!v.isEmpty) {
@@ -117,7 +118,10 @@ object GetSystemParameters {
}
class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
- case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> composer(up(IOBinders, site)(tag.runtimeClass.toString)))
+ case IOBinders => {
+ val upMap = up(IOBinders)
+ upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString)))
+ }
})
class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T](
@@ -171,29 +175,72 @@ class WithGPIOCells extends OverrideIOBinder({
iocell.io.ie := pin.o.ie
pin.i.ival := iocell.io.i
iocell.io.pad <> g
- (g, iocell)
+ (GPIOPort(() => g, i, j), iocell)
}).unzip
}).unzip
- val ports: Seq[Analog] = ports2d.flatten
- (ports, cells2d.flatten)
+ (ports2d.flatten, cells2d.flatten)
+ }
+})
+
+class WithGPIOPunchthrough extends OverrideIOBinder({
+ (system: HasPeripheryGPIOModuleImp) => {
+ val ports = system.gpio.zipWithIndex.map { case (gpio, i) =>
+ val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i")
+ io_gpio <> gpio
+ GPIOPinsPort(() => io_gpio, i)
+ }
+ (ports, Nil)
+ }
+})
+
+class WithI2CPunchthrough extends OverrideIOBinder({
+ (system: HasPeripheryI2CModuleImp) => {
+ val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
+ val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
+ io_i2c <> i2c
+ I2CPort(() => i2c)
+ }
+ (ports, Nil)
}
})
// DOC include start: WithUARTIOCells
class WithUARTIOCells extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp) => {
- val (ports: Seq[UARTPortIO], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
+ val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true)
- (port, ios)
+ val where = PBUS // TODO fix
+ val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+ val freqMHz = bus.dtsFrequency.get / 1000000
+ (UARTPort(() => port, i, freqMHz.toInt), ios)
}).unzip
(ports, cells2d.flatten)
}
})
// DOC include end: WithUARTIOCells
-class WithSPIIOCells extends OverrideIOBinder({
+class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
+ (system: HasPeripherySPI) => {
+ // attach resource to 1st SPI
+ if (system.tlSpiNodes.size > 0) ResourceBinding {
+ Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
+ }
+ InModuleBody {
+ val spi = system.asInstanceOf[BaseSubsystem].module.asInstanceOf[HasPeripherySPIBundle].spi
+ val ports = spi.zipWithIndex.map({ case (s, i) =>
+ val io_spi = IO(s.cloneType).suggestName(s"spi_$i")
+ io_spi <> s
+ SPIPort(() => io_spi)
+ })
+ (ports, Nil)
+ }
+ }
+})
+
+class WithSPIFlashIOCells extends OverrideIOBinder({
(system: HasPeripherySPIFlashModuleImp) => {
- val (ports: Seq[SPIChipIO], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
+ val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
+
val name = s"spi_${i}"
val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
val iocellBase = s"iocell_${name}"
@@ -213,7 +260,7 @@ class WithSPIIOCells extends OverrideIOBinder({
iocell
}
- (port, dqIOs ++ csIOs ++ sckIOs)
+ (SPIFlashPort(() => port, system.p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
}).unzip
(ports, cells2d.flatten)
}
@@ -223,7 +270,7 @@ class WithExtInterruptIOCells extends OverrideIOBinder({
(system: HasExtInterruptsModuleImp) => {
if (system.outer.nExtInterrupts > 0) {
val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true)
- (Seq(port), cells)
+ (Seq(ExtIntPort(() => port)), cells)
} else {
system.interrupts := DontCare // why do I have to drive this 0-wide wire???
(Nil, Nil)
@@ -239,7 +286,9 @@ class JTAGChipIO extends Bundle {
val TDO = Output(Bool())
}
-class WithDebugIOCells extends OverrideLazyIOBinder({
+// WARNING: Don't disable syncReset unless you are trying to
+// get around bugs in RTL simulators
+class WithDebugIOCells(syncReset: Boolean = true) extends OverrideLazyIOBinder({
(system: HasPeripheryDebug) => {
implicit val p = GetSystemParameters(system)
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere)
@@ -263,7 +312,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
d.disableDebug.foreach { d => d := false.B }
// Drive JTAG on-chip IOs
d.systemjtag.map { j =>
- j.reset := ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool)
+ j.reset := (if (syncReset) ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool) else clockBundle.reset.asBool)
j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
j.version := p(JtagDTMKey).idcodeVersion.U(4.W)
@@ -273,7 +322,8 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
// Add IOCells for the DMI/JTAG/APB ports
val dmiTuple = debug.clockeddmi.map { d =>
- IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = true)
+ val (port, cells) = IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = true)
+ (DMIPort(() => port), cells)
}
val jtagTuple = debug.systemjtag.map { j =>
@@ -282,14 +332,13 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
j.jtag.TMS := jtag_wire.TMS
j.jtag.TDI := jtag_wire.TDI
jtag_wire.TDO := j.jtag.TDO.data
- IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
+ val (port, cells) = IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
+ (JTAGPort(() => port), cells)
}
- val apbTuple = debug.apb.map { a =>
- IOCell.generateIOFromSignal(a, "apb", p(IOCellKey), abstractResetAsAsync = true)
- }
+ require(!debug.apb.isDefined)
- val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq
+ val allTuples = (dmiTuple ++ jtagTuple).toSeq
(allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq)
}).getOrElse((Nil, Nil))
}}}
@@ -297,20 +346,34 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
})
class WithSerialTLIOCells extends OverrideIOBinder({
- (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>
+ (system: CanHavePeripheryTLSerial) => {
+ val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
+ val sys = system.asInstanceOf[BaseSubsystem]
+ val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true)
+ (SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells)
+ }).unzip
+ (ports.toSeq, cells.flatten.toSeq)
+ }
+})
+
+class WithChipIdIOCells extends OverrideIOBinder({
+ (system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
- val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey), abstractResetAsAsync = true)
- (Seq(port), cells)
- }).getOrElse((Nil, Nil))
+ val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true)
+ (Seq(ChipIdPort(() => port)), cells)
+ }).getOrElse(Nil, Nil)
})
class WithSerialTLPunchthrough extends OverrideIOBinder({
- (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>
- val sys = system.asInstanceOf[BaseSubsystem]
- val port = IO(s.getWrappedValue.cloneType)
- port <> s.getWrappedValue
- (Seq(port), Nil)
- }).getOrElse((Nil, Nil))
+ (system: CanHavePeripheryTLSerial) => {
+ val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
+ val sys = system.asInstanceOf[BaseSubsystem]
+ val port = IO(chiselTypeOf(s.getWrappedValue))
+ port <> s.getWrappedValue
+ (SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil)
+ }).unzip
+ (ports.toSeq, cells.flatten.toSeq)
+ }
})
class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
@@ -321,12 +384,11 @@ class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
- val ports: Seq[ClockedAndResetIO[AXI4Bundle]] = system.mem_axi4.zipWithIndex.map({ case (m, i) =>
- val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}")
- p.bits <> m
- p.clock := clockBundle.clock
- p.reset := clockBundle.reset
- p
+ val ports: Seq[AXI4MemPort] = system.mem_axi4.zipWithIndex.map({ case (m, i) =>
+ val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}")
+ port.bits <> m
+ port.clock := clockBundle.clock
+ AXI4MemPort(() => port, p(ExtMem).get, system.memAXI4Node.edges.in(i), p(MemoryBusKey).dtsFrequency.get.toInt)
}).toSeq
(ports, Nil)
}
@@ -341,12 +403,11 @@ class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
- val ports: Seq[ClockedAndResetIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
- val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}")
- p.bits <> m
- p.clock := clockBundle.clock
- p.reset := clockBundle.reset
- p
+ val ports: Seq[AXI4MMIOPort] = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
+ val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}")
+ port.bits <> m
+ port.clock := clockBundle.clock
+ AXI4MMIOPort(() => port, p(ExtBus).get, system.mmioAXI4Node.edges.in(i))
}).toSeq
(ports, Nil)
}
@@ -361,11 +422,11 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
- val ports: Seq[ClockedIO[AXI4Bundle]] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>
- val p = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}")
- m <> p.bits
- p.clock := clockBundle.clock
- p
+ val ports: Seq[AXI4InPort] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>
+ val port = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}")
+ m <> port.bits
+ port.clock := clockBundle.clock
+ AXI4InPort(() => port, p(ExtIn).get)
}).toSeq
(ports, Nil)
}
@@ -374,10 +435,12 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryBlockDevice) => {
- val ports: Seq[ClockedIO[BlockDeviceIO]] = system.bdev.map({ bdev =>
- val p = IO(new ClockedIO(new BlockDeviceIO()(GetSystemParameters(system)))).suggestName("blockdev")
- p <> bdev
- p
+ val ports: Seq[BlockDevicePort] = system.bdev.map({ bdev =>
+ val p = GetSystemParameters(system)
+ val bdParams = p(BlockDeviceKey).get
+ val port = IO(new ClockedIO(new BlockDeviceIO(bdParams))).suggestName("blockdev")
+ port <> bdev
+ BlockDevicePort(() => port, bdParams)
}).toSeq
(ports, Nil)
}
@@ -385,10 +448,11 @@ class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({
class WithNICIOPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryIceNIC) => {
- val ports: Seq[ClockedIO[NICIOvonly]] = system.icenicOpt.map({ n =>
- val p = IO(new ClockedIO(new NICIOvonly)).suggestName("nic")
- p <> n
- p
+ val ports: Seq[NICPort] = system.icenicOpt.map({ n =>
+ val p = GetSystemParameters(system)
+ val port = IO(new ClockedIO(new NICIOvonly)).suggestName("nic")
+ port <> n
+ NICPort(() => port, p(NICKey).get)
}).toSeq
(ports, Nil)
}
@@ -398,16 +462,30 @@ class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({
(system: TraceGenSystemModuleImp) => {
val success: Bool = IO(Output(Bool())).suggestName("success")
success := system.success
- (Seq(success), Nil)
+ (Seq(SuccessPort(() => success)), Nil)
}
})
-class WithTraceIOPunchthrough extends OverrideIOBinder({
- (system: CanHaveTraceIOModuleImp) => {
- val ports: Option[TraceOutputTop] = system.traceIO.map { t =>
+class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
+ (system: CanHaveTraceIO) => InModuleBody {
+ val ports: Option[TracePort] = system.traceIO.map { t =>
val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace")
trace <> t
- trace
+ val p = GetSystemParameters(system)
+ val chipyardSystem = system.asInstanceOf[ChipyardSystem]
+ val tiles = chipyardSystem.totalTiles.values
+ val cfg = SpikeCosimConfig(
+ isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
+ vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0),
+ priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
+ mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
+ mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
+ pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
+ nharts = tiles.size,
+ bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
+ has_dtm = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
+ )
+ TracePort(() => trace, cfg)
}
(ports.toSeq, Nil)
}
@@ -417,7 +495,7 @@ class WithCustomBootPin extends OverrideIOBinder({
(system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, "custom_boot", sys.p(IOCellKey), abstractResetAsAsync = true)
- (Seq(port), cells)
+ (Seq(CustomBootPort(() => port)), cells)
}).getOrElse((Nil, Nil))
})
@@ -426,7 +504,7 @@ class WithUARTTSIPunchthrough extends OverrideIOBinder({
val sys = system.asInstanceOf[BaseSubsystem]
val uart_tsi = IO(new UARTTSIIO(p.uartParams))
uart_tsi <> p
- (Seq(uart_tsi), Nil)
+ (Seq(UARTTSIPort(() => uart_tsi)), Nil)
}).getOrElse((Nil, Nil))
})
@@ -434,7 +512,7 @@ class WithTLMemPunchthrough extends OverrideIOBinder({
(system: CanHaveMasterTLMemPort) => {
val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
io_tl_mem_pins_temp <> system.mem_tl
- (Seq(io_tl_mem_pins_temp), Nil)
+ (Seq(TLMemPort(() => io_tl_mem_pins_temp)), Nil)
}
})
@@ -444,8 +522,8 @@ class WithDontTouchPorts extends OverrideIOBinder({
})
class WithNMITiedOff extends ComposeIOBinder({
- (system: HasTilesModuleImp) => {
- system.nmi.flatten.foreach { nmi =>
+ (system: HasHierarchicalElementsRootContextModuleImp) => {
+ system.nmi.foreach { nmi =>
nmi.rnmi := false.B
nmi.rnmi_interrupt_vector := 0.U
nmi.rnmi_exception_vector := 0.U
diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala
new file mode 100644
index 00000000..6b327a18
--- /dev/null
+++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala
@@ -0,0 +1,111 @@
+package chipyard.iobinders
+
+import chisel3._
+import chisel3.experimental.{Analog}
+import sifive.blocks.devices.uart.{UARTPortIO}
+import sifive.blocks.devices.spi.{SPIFlashParams, SPIPortIO}
+import sifive.blocks.devices.gpio.{GPIOPortIO}
+import testchipip.util.{ClockedIO}
+import testchipip.serdes.{TLSerdesser, SerialIO, SerialTLParams}
+import testchipip.spi.{SPIChipIO}
+import testchipip.cosim.{TraceOutputTop, SpikeCosimConfig}
+import testchipip.iceblk.{BlockDeviceIO, BlockDeviceConfig}
+import testchipip.tsi.{UARTTSIIO}
+import icenet.{NICIOvonly, NICConfig}
+import org.chipsalliance.cde.config.{Parameters}
+import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters}
+import freechips.rocketchip.subsystem.{MemoryPortParams, MasterPortParams, SlavePortParams}
+import freechips.rocketchip.devices.debug.{ClockedDMIIO}
+import freechips.rocketchip.util.{HeterogeneousBag}
+import freechips.rocketchip.tilelink.{TLBundle}
+
+trait Port[T <: Data] {
+ val getIO: () => T
+ // port.io should only be called in the TestHarness context
+ lazy val io = getIO()
+}
+
+trait HasChipyardPorts {
+ def ports: Seq[Port[_]]
+}
+
+// These case classes are generated by IOBinders, and interpreted by HarnessBinders
+case class GPIOPort (val getIO: () => Analog, val gpioId: Int, val pinId: Int)
+ extends Port[Analog]
+
+case class GPIOPinsPort (val getIO: () => GPIOPortIO, val gpioId: Int)
+ extends Port[GPIOPortIO]
+
+case class I2CPort (val getIO: () => sifive.blocks.devices.i2c.I2CPort)
+ extends Port[sifive.blocks.devices.i2c.I2CPort]
+
+case class UARTPort (val getIO: () => UARTPortIO, val uartNo: Int, val freqMHz: Int)
+ extends Port[UARTPortIO]
+
+case class SPIFlashPort (val getIO: () => SPIChipIO, val params: SPIFlashParams, val spiId: Int)
+ extends Port[SPIChipIO]
+
+case class SPIPort (val getIO: () => SPIPortIO)
+ extends Port[SPIPortIO]
+
+case class BlockDevicePort (val getIO: () => ClockedIO[BlockDeviceIO], val params: BlockDeviceConfig)
+ extends Port[ClockedIO[BlockDeviceIO]]
+
+case class NICPort (val getIO: () => ClockedIO[NICIOvonly], val params: NICConfig)
+ extends Port[ClockedIO[NICIOvonly]]
+
+case class AXI4MemPort (val getIO: () => ClockedIO[AXI4Bundle], val params: MemoryPortParams, val edge: AXI4EdgeParameters, val clockFreqMHz: Int)
+ extends Port[ClockedIO[AXI4Bundle]]
+
+case class AXI4MMIOPort (val getIO: () => ClockedIO[AXI4Bundle], val params: MasterPortParams, val edge: AXI4EdgeParameters)
+ extends Port[ClockedIO[AXI4Bundle]]
+
+case class AXI4InPort (val getIO: () => ClockedIO[AXI4Bundle], val params: SlavePortParams)
+ extends Port[ClockedIO[AXI4Bundle]]
+
+case class ExtIntPort (val getIO: () => UInt)
+ extends Port[UInt]
+
+case class DMIPort (val getIO: () => ClockedDMIIO)
+ extends Port[ClockedDMIIO]
+
+case class JTAGPort (val getIO: () => JTAGChipIO)
+ extends Port[JTAGChipIO]
+
+// Lack of nice union types in scala-2 means we have to set this type as Data
+case class SerialTLPort (val getIO: () => Data, val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int)
+ extends Port[Data]
+
+case class ChipIdPort (val getIO: () => UInt)
+ extends Port[UInt]
+
+case class UARTTSIPort (val getIO: () => UARTTSIIO)
+ extends Port[UARTTSIIO]
+
+case class SuccessPort (val getIO: () => Bool)
+ extends Port[Bool]
+
+case class TracePort (val getIO: () => TraceOutputTop, val cosimCfg: SpikeCosimConfig)
+ extends Port[TraceOutputTop]
+
+case class CustomBootPort (val getIO: () => Bool)
+ extends Port[Bool]
+
+case class ClockPort (val getIO: () => Clock, val freqMHz: Double)
+ extends Port[Clock]
+
+case class ClockTapPort (val getIO: () => Clock)
+ extends Port[Clock]
+
+case class ResetPort (val getIO: () => AsyncReset)
+ extends Port[Reset]
+
+case class DebugResetPort (val getIO: () => Reset)
+ extends Port[Reset]
+
+case class JTAGResetPort (val getIO: () => Reset)
+ extends Port[Reset]
+
+case class TLMemPort (val getIO: () => HeterogeneousBag[TLBundle])
+ extends Port[HeterogeneousBag[TLBundle]]
+
diff --git a/generators/constellation b/generators/constellation
index 03ed9e4e..81f005ff 160000
--- a/generators/constellation
+++ b/generators/constellation
@@ -1 +1 @@
-Subproject commit 03ed9e4ecd31d71d4bd48f02b0e806bc2b8a7e6b
+Subproject commit 81f005ffeac998ebf0619e0bd7f0d212d68a82c5
diff --git a/generators/cva6 b/generators/cva6
index 46323fcd..9d1c1068 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit 46323fcd7407544c751b353f52e356eb8f33e9d1
+Subproject commit 9d1c106834824ddb8052b7f60574b2b544b40395
diff --git a/generators/fft-generator b/generators/fft-generator
index 811951b4..4e7e6cbb 160000
--- a/generators/fft-generator
+++ b/generators/fft-generator
@@ -1 +1 @@
-Subproject commit 811951b44a113f87710a6abaae4582120c1194ba
+Subproject commit 4e7e6cbbbc6ed96d27dbaeb2413764cd446c50b3
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index db6ec2fb..bd662a27 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -3,7 +3,6 @@
package firesim.firesim
import chisel3._
-import chisel3.experimental.annotate
import chisel3.experimental.{DataMirror, Direction}
import chisel3.util.experimental.BoringUtils
@@ -12,31 +11,29 @@ import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug, ExportDebug, DMI}
import freechips.rocketchip.amba.axi4.{AXI4Bundle}
import freechips.rocketchip.subsystem._
-import freechips.rocketchip.tile.{RocketTile}
import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
import freechips.rocketchip.util.{ResetCatchAndSync}
import sifive.blocks.devices.uart._
-import testchipip._
+import testchipip.serdes.{ExternalSyncSerialIO}
+import testchipip.tsi.{SerialRAM}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import junctions.{NastiKey, NastiParameters}
import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
-import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotation}
import firesim.bridges._
import firesim.configs.MemModelKey
import tracegen.{TraceGenSystemModuleImp}
import cva6.CVA6Tile
-import boom.common.{BoomTile}
import barstools.iocell.chisel._
-import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey}
+import chipyard.iobinders._
import chipyard._
import chipyard.harness._
object MainMemoryConsts {
val regionNamePrefix = "MainMemory"
- def globalName()(implicit p: Parameters) = s"${regionNamePrefix}_${p(MultiChipIdx)}"
+ def globalName(chipId: Int) = s"${regionNamePrefix}_$chipId"
}
trait Unsupported {
@@ -69,130 +66,73 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
case IOCellKey => FireSimIOCellParams()
})
-class WithTSIBridgeAndHarnessRAMOverSerialTL extends OverrideHarnessBinder({
- (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => {
- ports.map { port =>
- implicit val p = GetSystemParameters(system)
- val bits = port.bits
- port.clock := th.harnessBinderClock
- val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.harnessBinderReset)
- TSIBridge(th.harnessBinderClock, ram.module.io.tsi, p(ExtMem).map(_ => MainMemoryConsts.globalName), th.harnessBinderReset.asBool)
- }
- Nil
- }
-})
+class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
+ case (th: FireSim, port: SerialTLPort, chipId: Int) => {
+ port.io match {
+ case io: ExternalSyncSerialIO => {
+ io.clock_in := th.harnessBinderClock
+ val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
+ ram.io.ser.in <> io.out
+ io.in <> ram.io.ser.out
-class WithNICBridge extends OverrideHarnessBinder({
- (system: CanHavePeripheryIceNIC, th: FireSim, ports: Seq[ClockedIO[NICIOvonly]]) => {
- val p: Parameters = GetSystemParameters(system)
- ports.map { n => NICBridge(n.clock, n.bits)(p) }
- Nil
- }
-})
-
-class WithUARTBridge extends OverrideHarnessBinder({
- (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) =>
- val uartSyncClock = Wire(Clock())
- uartSyncClock := false.B.asClock
- val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode
- val pbusClock = pbusClockNode.in.head._1.clock
- BoringUtils.bore(pbusClock, Seq(uartSyncClock))
- ports.map { p => UARTBridge(uartSyncClock, p, th.harnessBinderReset.asBool)(system.p) }; Nil
-})
-
-class WithBlockDeviceBridge extends OverrideHarnessBinder({
- (system: CanHavePeripheryBlockDevice, th: FireSim, ports: Seq[ClockedIO[BlockDeviceIO]]) => {
- implicit val p: Parameters = GetSystemParameters(system)
- ports.map { b => BlockDevBridge(b.clock, b.bits, th.harnessBinderReset.asBool) }
- Nil
- }
-})
-
-
-class WithFASEDBridge extends OverrideHarnessBinder({
- (system: CanHaveMasterAXI4MemPort, th: FireSim, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
- implicit val p: Parameters = GetSystemParameters(system)
- (ports zip system.memAXI4Node.edges.in).map { case (axi4, edge) =>
- val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth,
- axi4.bits.ar.bits.addr.getWidth,
- axi4.bits.ar.bits.id.getWidth)
- system match {
- case s: BaseSubsystem => FASEDBridge(axi4.clock, axi4.bits, axi4.reset.asBool,
- CompleteConfig(p(firesim.configs.MemModelKey),
- nastiKey,
- Some(AXI4EdgeSummary(edge)),
- Some(MainMemoryConsts.globalName)))
- case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design")
+ // This assumes that:
+ // If ExtMem for the target is defined, then FASED bridge will be attached
+ // If FASED bridge is attached, loadmem widget is present
+ val hasMainMemory = th.chipParameters(chipId)(ExtMem).isDefined
+ val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(chipId))
+ TSIBridge(th.harnessBinderClock, ram.io.tsi.get, mainMemoryName, th.harnessBinderReset.asBool)(th.p)
}
}
- Nil
}
})
-class WithTracerVBridge extends ComposeHarnessBinder({
- (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => {
- ports.map { p => p.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p)) }
- Nil
+class WithNICBridge extends HarnessBinder({
+ case (th: FireSim, port: NICPort, chipId: Int) => {
+ NICBridge(port.io.clock, port.io.bits)(th.p)
}
})
-class WithCospikeBridge extends ComposeHarnessBinder({
- (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => {
- implicit val p = chipyard.iobinders.GetSystemParameters(system)
- val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem]
- val tiles = chipyardSystem.tiles
- val cfg = SpikeCosimConfig(
- isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
- vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0),
- priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
- mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
- mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
- pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
- nharts = tiles.size,
- bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
- has_dtm = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
- )
- ports.map { p => p.traces.zipWithIndex.map(t => CospikeBridge(t._1, t._2, cfg)) }
+class WithUARTBridge extends HarnessBinder({
+ case (th: FireSim, port: UARTPort, chipId: Int) =>
+ val uartSyncClock = th.harnessClockInstantiator.requestClockMHz("uart_clock", port.freqMHz)
+ UARTBridge(uartSyncClock, port.io, th.harnessBinderReset.asBool, port.freqMHz)(th.p)
+})
+
+class WithBlockDeviceBridge extends HarnessBinder({
+ case (th: FireSim, port: BlockDevicePort, chipId: Int) => {
+ BlockDevBridge(port.io.clock, port.io.bits, th.harnessBinderReset.asBool)
}
})
-class WithTraceGenBridge extends OverrideHarnessBinder({
- (system: TraceGenSystemModuleImp, th: FireSim, ports: Seq[Bool]) =>
- ports.map { p => GroundTestBridge(th.harnessBinderClock, p)(system.p) }; Nil
-})
-class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
- (system: HasTilesModuleImp) => {
- system.outer.tiles.map {
- case r: RocketTile => {
- annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
- r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
- }
- case b: BoomTile => {
- val core = b.module.core
- core.iregfile match {
- case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
- }
- if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
- case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
- }
- }
- case _ =>
- }
- (Nil, Nil)
+class WithFASEDBridge extends HarnessBinder({
+ case (th: FireSim, port: AXI4MemPort, chipId: Int) => {
+ val nastiKey = NastiParameters(port.io.bits.r.bits.data.getWidth,
+ port.io.bits.ar.bits.addr.getWidth,
+ port.io.bits.ar.bits.id.getWidth)
+ FASEDBridge(port.io.clock, port.io.bits, th.harnessBinderReset.asBool,
+ CompleteConfig(th.p(firesim.configs.MemModelKey),
+ nastiKey,
+ Some(AXI4EdgeSummary(port.edge)),
+ Some(MainMemoryConsts.globalName(chipId))))(th.p)
}
})
-class WithFireSimFAME5 extends ComposeIOBinder({
- (system: HasTilesModuleImp) => {
- system.outer.tiles.map {
- case b: BoomTile =>
- annotate(EnableModelMultiThreadingAnnotation(b.module))
- case r: RocketTile =>
- annotate(EnableModelMultiThreadingAnnotation(r.module))
- case _ => Nil
- }
- (Nil, Nil)
+class WithTracerVBridge extends HarnessBinder({
+ case (th: FireSim, port: TracePort, chipId: Int) => {
+ port.io.traces.map(tileTrace => TracerVBridge(tileTrace)(th.p))
+ }
+})
+
+class WithCospikeBridge extends HarnessBinder({
+ case (th: FireSim, port: TracePort, chipId: Int) => {
+ port.io.traces.zipWithIndex.map(t => CospikeBridge(t._1, t._2, port.cosimCfg))
+ }
+})
+
+class WithSuccessBridge extends HarnessBinder({
+ case (th: FireSim, port: SuccessPort, chipId: Int) => {
+ GroundTestBridge(th.harnessBinderClock, port.io)(th.p)
}
})
diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala
index c20abca1..599788bc 100644
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -5,21 +5,26 @@ package firesim.firesim
import scala.collection.mutable.{LinkedHashMap}
import chisel3._
-import chisel3.experimental.{IO}
+import chisel3.experimental.{IO, annotate}
import freechips.rocketchip.prci._
-import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
+import freechips.rocketchip.subsystem._
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
+import freechips.rocketchip.tile.{RocketTile}
+import boom.common.{BoomTile}
import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock, ResetPulseBridge, ResetPulseBridgeParameters}
-
+import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotation}
import chipyard._
import chipyard.harness._
import chipyard.iobinders._
import chipyard.clocking._
+case object FireSimMultiCycleRegFile extends Field[Boolean](false)
+case object FireSimFAME5 extends Field[Boolean](false)
+
/**
* Under FireSim's current multiclock implementation there can be only a
* single clock bridge. This requires, therefore, that it be instantiated in
@@ -85,11 +90,46 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
override val supportsMultiChip = true
- instantiateChipTops()
+ val chiptops = instantiateChipTops()
// Ensures FireSim-synthesized assertions and instrumentation is disabled
// while resetBridge.io.reset is asserted. This ensures assertions do not fire at
// time zero in the event their local reset is delayed (typically because it
// has been pipelined)
midas.targetutils.GlobalResetCondition(resetBridge.io.reset)
+
+
+ // FireSim multi-cycle regfile optimization
+ // FireSim ModelMultithreading
+ chiptops.foreach {
+ case c: ChipTop => c.lazySystem match {
+ case ls: InstantiatesHierarchicalElements => {
+ if (p(FireSimMultiCycleRegFile)) ls.totalTiles.values.map {
+ case r: RocketTile => {
+ annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
+ r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
+ }
+ case b: BoomTile => {
+ val core = b.module.core
+ core.iregfile match {
+ case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+ }
+ if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
+ case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
+ }
+ }
+ case _ =>
+ }
+ if (p(FireSimFAME5)) ls.totalTiles.values.map {
+ case b: BoomTile =>
+ annotate(EnableModelMultiThreadingAnnotation(b.module))
+ case r: RocketTile =>
+ annotate(EnableModelMultiThreadingAnnotation(r.module))
+ case _ => Nil
+ }
+ }
+ case _ =>
+ }
+ case _ =>
+ }
}
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index c08a028d..04bb26a4 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -13,7 +13,8 @@ import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing}
-import testchipip.{BlockDeviceKey, BlockDeviceConfig, TracePortKey, TracePortParams}
+import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
+import testchipip.cosim.{TracePortKey, TracePortParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import scala.math.{min, max}
@@ -55,6 +56,16 @@ class WithScalaTestFeatures extends Config((site, here, up) => {
case TracePortKey => up(TracePortKey, site).map(_.copy(print = true))
})
+// Multi-cycle regfile for rocket+boom
+class WithFireSimMultiCycleRegfile extends Config((site, here, up) => {
+ case FireSimMultiCycleRegFile => true
+})
+
+// Model multithreading optimization
+class WithFireSimFAME5 extends Config((site, here, up) => {
+ case FireSimFAME5 => true
+})
+
// FASED Config Aliases. This to enable config generation via "_" concatenation
// which requires that all config classes be defined in the same package
class DDR3FCFS extends FCFS16GBQuadRank
@@ -72,7 +83,9 @@ class WithMinimalFireSimDesignTweaks extends Config(
// Required*: Punch all clocks to FireSim's harness clock instantiator
new WithFireSimHarnessClockBridgeInstantiator ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(1000.0) ++
- new chipyard.harness.WithClockAndResetFromHarness ++
+ new chipyard.harness.WithClockFromHarness ++
+ new chipyard.harness.WithResetFromHarness ++
+ new chipyard.config.WithNoClockTap ++
new chipyard.clocking.WithPassthroughClockGenerator ++
// Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
new WithBootROM ++
@@ -87,18 +100,20 @@ class WithMinimalFireSimDesignTweaks extends Config(
// Non-frequency tweaks that are generally applied to all firesim configs
class WithFireSimDesignTweaks extends Config(
new WithMinimalFireSimDesignTweaks ++
+ // Required: Remove the debug clock tap, this breaks compilation of target-level sim in FireSim
+ new chipyard.config.WithNoClockTap ++
// Required: Bake in the default FASED memory model
new WithDefaultMemModel ++
// Optional: reduce the width of the Serial TL interface
- new testchipip.WithSerialTLWidth(4) ++
+ new testchipip.serdes.WithSerialTLWidth(4) ++
// Required*: Scale default baud rate with periphery bus frequency
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
// Optional: Adds IO to attach tracerV bridges
new chipyard.config.WithTraceIO ++
- // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
+ // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
// Optional: Removing this will require using an initramfs under linux
- new testchipip.WithBlockDevice
+ new testchipip.iceblk.WithBlockDevice
)
// Tweaks to modify target clock frequencies / crossings to legacy firesim defaults
@@ -110,16 +125,17 @@ class WithFireSimHighPerfClocking extends Config(
// This frequency selection matches FireSim's legacy selection and is required
// to support 200Gb NIC performance. You may select a smaller value.
new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
+ new chipyard.config.WithControlBusFrequency(3200.0) ++
new chipyard.config.WithSystemBusFrequency(3200.0) ++
new chipyard.config.WithFrontBusFrequency(3200.0) ++
+ new chipyard.config.WithControlBusFrequency(3200.0) ++
// Optional: These three configs put the DRAM memory system in it's own clock domain.
// Removing the first config will result in the FASED timing model running
// at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades.
// 1 GHz matches the FASED default, using some other frequency will require
// runnings the FASED runtime configuration generator to generate faithful DDR3 timing values.
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
- new chipyard.config.WithAsynchrousMemoryBusCrossing ++
- new testchipip.WithAsynchronousSerialSlaveCrossing
+ new chipyard.config.WithAsynchrousMemoryBusCrossing
)
// Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
@@ -128,8 +144,11 @@ class WithFireSimConfigTweaks extends Config(
// Using some other frequency will require runnings the FASED runtime configuration generator
// to generate faithful DDR3 timing values.
new chipyard.config.WithSystemBusFrequency(1000.0) ++
+ new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
+ new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
+ new chipyard.config.WithFrontBusFrequency(1000.0) ++
new WithFireSimDesignTweaks
)
@@ -138,7 +157,7 @@ class WithFireSimConfigTweaks extends Config(
class WithMinimalFireSimHighPerfConfigTweaks extends Config(
new WithFireSimHighPerfClocking ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
- new testchipip.WithMbusScratchpad ++
+ new testchipip.soc.WithMbusScratchpad ++
new WithMinimalFireSimDesignTweaks
)
@@ -148,8 +167,8 @@ class WithMinimalFireSimHighPerfConfigTweaks extends Config(
class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config(
new WithFireSimHighPerfClocking ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against
- new testchipip.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
- new testchipip.WithBlockDevice(true) ++ // add in block device
+ new testchipip.soc.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
+ new testchipip.iceblk.WithBlockDevice(true) ++ // add in block device
new WithMinimalFireSimDesignTweaks
)
@@ -175,13 +194,14 @@ class WithFireSimTestChipConfigTweaks extends Config(
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency
new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency
+ new chipyard.config.WithFrontBusFrequency(500.0) ++ // Match the sbus and fbus frequency
+ new chipyard.config.WithControlBusFrequency(500.0) ++ // Match the sbus and cbus frequency
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
// Crossing specifications
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
- new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new WithFireSimDesignTweaks
)
@@ -236,11 +256,18 @@ class FireSimSmallSystemConfig extends Config(
new WithDefaultMemModel ++
new WithBootROM ++
new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
+ new chipyard.config.WithControlBusFrequency(3200.0) ++
+ new chipyard.config.WithSystemBusFrequency(3200.0) ++
+ new chipyard.config.WithFrontBusFrequency(3200.0) ++
+ new chipyard.config.WithMemoryBusFrequency(3200.0) ++
new WithoutClockGating ++
new WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
- new testchipip.WithDefaultSerialTL ++
- new testchipip.WithBlockDevice ++
+ new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
+ client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)),
+ phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32)
+ ))) ++
+ new testchipip.iceblk.WithBlockDevice ++
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
new chipyard.RocketConfig)
@@ -289,6 +316,7 @@ class FireSimLeanGemminiPrintfRocketConfig extends Config(
//**********************************************************************************
class SupernodeFireSimRocketConfig extends Config(
new WithFireSimHarnessClockBridgeInstantiator ++
+ new WithDefaultMemModel ++ // this is a global for all the multi-chip configs
new chipyard.harness.WithHomogeneousMultiChip(n=4, new Config(
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8GB DRAM per node
new FireSimRocketConfig)))
@@ -317,7 +345,7 @@ class FireSim16LargeBoomConfig extends Config(
class FireSimNoMemPortConfig extends Config(
new WithDefaultFireSimBridges ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
- new testchipip.WithMbusScratchpad ++
+ new testchipip.soc.WithMbusScratchpad ++
new WithFireSimConfigTweaks ++
new chipyard.RocketConfig)
diff --git a/generators/ibex b/generators/ibex
index 66ec6e56..c2174aba 160000
--- a/generators/ibex
+++ b/generators/ibex
@@ -1 +1 @@
-Subproject commit 66ec6e56ed69df4e4af5383128cf21adf88b08fc
+Subproject commit c2174aba4fb304c7565c248f2a673f7151be896b
diff --git a/generators/icenet b/generators/icenet
index 68b4c7f3..d6a471f2 160000
--- a/generators/icenet
+++ b/generators/icenet
@@ -1 +1 @@
-Subproject commit 68b4c7f30f0119fe5cfab7ea99fb6927a563e112
+Subproject commit d6a471f2187c0671eea6567c7ba29e86e830e8d4
diff --git a/generators/nvdla b/generators/nvdla
index 730fad43..95697452 160000
--- a/generators/nvdla
+++ b/generators/nvdla
@@ -1 +1 @@
-Subproject commit 730fad4360e67b14b1a4656ac58aaa40cfd4fe6b
+Subproject commit 95697452e51ad56230a6e631bb02b3351c4293c6
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index c1c809eb..bbfc3c35 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit c1c809ebd5c9a76cd60d8c3169cea4bf4b2fa8fd
+Subproject commit bbfc3c35100329386314c49b62b49a7f42f65e87
diff --git a/generators/rocc-acc-utils b/generators/rocc-acc-utils
new file mode 160000
index 00000000..b001c888
--- /dev/null
+++ b/generators/rocc-acc-utils
@@ -0,0 +1 @@
+Subproject commit b001c888f9620189cd13d2c6ba19f1e28663a3cb
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 50adbdb3..749a3eae 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 50adbdb3e4e18c2b3de57693323f4174b60f9767
+Subproject commit 749a3eae9678bc70b029c5b9091fae33fad539c4
diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks
new file mode 160000
index 00000000..212c7b07
--- /dev/null
+++ b/generators/rocket-chip-blocks
@@ -0,0 +1 @@
+Subproject commit 212c7b070bc7132f31a26deec6b2bde9e0b1b612
diff --git a/generators/rocket-chip-inclusive-cache b/generators/rocket-chip-inclusive-cache
new file mode 160000
index 00000000..1332d226
--- /dev/null
+++ b/generators/rocket-chip-inclusive-cache
@@ -0,0 +1 @@
+Subproject commit 1332d2268ae01b2b311966d53a3ee0d930e83f07
diff --git a/generators/shuttle b/generators/shuttle
index e628836c..fd325d43 160000
--- a/generators/shuttle
+++ b/generators/shuttle
@@ -1 +1 @@
-Subproject commit e628836c3c4bfe29927cd9e1473801fab33dee6c
+Subproject commit fd325d43a162378dc1984e87297e6d710167db79
diff --git a/generators/sifive-blocks b/generators/sifive-blocks
deleted file mode 160000
index 5edd72e7..00000000
--- a/generators/sifive-blocks
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 5edd72e793ccb534b1395d0d8c1831754fd72fec
diff --git a/generators/sifive-cache b/generators/sifive-cache
deleted file mode 160000
index 51d400bd..00000000
--- a/generators/sifive-cache
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 51d400bd32131e8914c6713bfb71bef690f2fe70
diff --git a/generators/testchipip b/generators/testchipip
index e1d8ef10..d1f472ec 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit e1d8ef1012e74028b2920a27e1855f7c7600399c
+Subproject commit d1f472ecb1d3c14492bf4591bea6d1284e162d9a
diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala
index 5d4f0211..f51052c5 100644
--- a/generators/tracegen/src/main/scala/Configs.scala
+++ b/generators/tracegen/src/main/scala/Configs.scala
@@ -13,19 +13,18 @@ import scala.math.{max, min}
class WithTraceGen(
n: Int = 2,
- overrideIdOffset: Option[Int] = None,
overrideMemOffset: Option[BigInt] = None)(
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
nReqs: Int = 8192
) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
- val idOffset = overrideIdOffset.getOrElse(prev.size)
+ val idOffset = up(NumTiles)
val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
params.zipWithIndex.map { case (dcp, i) =>
TraceGenTileAttachParams(
tileParams = TraceGenParams(
- hartId = i + idOffset,
+ tileId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
@@ -48,23 +47,23 @@ class WithTraceGen(
)
} ++ prev
}
+ case NumTiles => up(NumTiles) + n
})
class WithBoomTraceGen(
n: Int = 2,
- overrideIdOffset: Option[Int] = None,
overrideMemOffset: Option[BigInt] = None)(
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
nReqs: Int = 8192
) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
- val idOffset = overrideIdOffset.getOrElse(prev.size)
+ val idOffset = up(NumTiles)
val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
params.zipWithIndex.map { case (dcp, i) =>
BoomTraceGenTileAttachParams(
tileParams = BoomTraceGenParams(
- hartId = i + idOffset,
+ tileId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
@@ -84,24 +83,24 @@ class WithBoomTraceGen(
)
} ++ prev
}
+ case NumTiles => up(NumTiles) + n
})
class WithL2TraceGen(
n: Int = 2,
- overrideIdOffset: Option[Int] = None,
overrideMemOffset: Option[BigInt] = None)(
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
nReqs: Int = 8192
) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
- val idOffset = overrideIdOffset.getOrElse(prev.size)
+ val idOffset = up(NumTiles)
val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
params.zipWithIndex.map { case (dcp, i) =>
TraceGenTileAttachParams(
tileParams = TraceGenParams(
- hartId = i + idOffset,
+ tileId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
@@ -126,4 +125,5 @@ class WithL2TraceGen(
)
} ++ prev
}
+ case NumTiles => up(NumTiles) + n
})
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
index 2a0ba3d5..488054d3 100644
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -9,15 +9,28 @@ import freechips.rocketchip.subsystem._
import boom.lsu.BoomTraceGenTile
class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
- with HasTiles
+ with InstantiatesHierarchicalElements
+ with HasTileNotificationSinks
+ with HasTileInputConstants
+ with HasHierarchicalElementsRootContext
+ with HasHierarchicalElements
with CanHaveMasterAXI4MemPort {
def coreMonitorBundles = Nil
- val tileStatusNodes = tiles.collect {
+
+ val tileStatusNodes = totalTiles.values.toSeq.collect {
case t: GroundTestTile => t.statusNode.makeSink()
case t: BoomTraceGenTile => t.statusNode.makeSink()
}
- lazy val debugNode = IntSyncXbar() := NullIntSyncSource()
+
+ lazy val fakeClockDomain = sbus.generateSynchronousDomain
+
+ lazy val clintOpt = None
+ lazy val debugOpt = None
+ lazy val plicOpt = None
+ lazy val clintDomainOpt = Some(fakeClockDomain)
+ lazy val plicDomainOpt = Some(fakeClockDomain)
+
override lazy val module = new TraceGenSystemModuleImp(this)
}
diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh
index c95056db..a55b10fd 100755
--- a/scripts/build-setup.sh
+++ b/scripts/build-setup.sh
@@ -29,7 +29,8 @@ usage() {
echo " 7. FireSim pre-compile sources"
echo " 8. FireMarshal"
echo " 9. FireMarshal pre-compile default buildroot Linux sources"
- echo " 10. Runs repository clean-up"
+ echo " 10. Install CIRCT"
+ echo " 11. Runs repository clean-up"
echo ""
echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**"
echo ""
@@ -37,12 +38,20 @@ usage() {
echo " --help -h : Display this message"
echo " --force -f : Skip all prompts and checks"
- echo " --skip-validate : DEPRECATED: Same functionality as --force"
echo " --verbose -v : Verbose printout"
echo " --use-unpinned-deps -ud : Use unpinned conda environment"
echo " --skip -s N : Skip step N in the list above. Use multiple times to skip multiple steps ('-s N -s M ...')."
+ echo " --skip-conda : Skip Conda initialization (step 1)"
+ echo " --skip-submodules : Skip submodule initialization (step 2)"
+ echo " --skip-toolchain : Skip toolchain collateral (step 3)"
+ echo " --skip-ctags : Skip ctags (step 4)"
+ echo " --skip-precompile : Skip precompiling sources (steps 5/7)"
+ echo " --skip-firesim : Skip Firesim initialization (steps 6/7)"
+ echo " --skip-marshal : Skip firemarshal initialization (steps 8/9)"
+ echo " --skip-circt : Skip CIRCT install (step 10)"
+ echo " --skip-clean : Skip repository clean-up (step 11)"
exit "$1"
}
@@ -72,6 +81,24 @@ do
--skip | -s)
shift
SKIP_LIST+=(${1}) ;;
+ --skip-conda)
+ SKIP_LIST+=(1) ;;
+ --skip-submodules)
+ SKIP_LIST+=(2) ;;
+ --skip-toolchain)
+ SKIP_LIST+=(3) ;;
+ --skip-ctags)
+ SKIP_LIST+=(4) ;;
+ --skip-precompile)
+ SKIP_LIST+=(5 6) ;;
+ --skip-firesim)
+ SKIP_LIST+=(6 7) ;;
+ --skip-marshal)
+ SKIP_LIST+=(8 9) ;;
+ --skip-circt)
+ SKIP_LIST+=(10) ;;
+ --skip-clean)
+ SKIP_LIST+=(11) ;;
* )
error "invalid option $1"
usage 1 ;;
@@ -109,8 +136,31 @@ if [ $TOOLCHAIN_TYPE == "esp-tools" ]; then
done
fi
+
+#######################################
+###### BEGIN STEP-BY-STEP SETUP #######
+#######################################
+
+# In order to run code on error, we must handle errors manually
+set +e;
+
+function begin_step
+{
+ thisStepNum=$1;
+ thisStepDesc=$2;
+ echo " ========== BEGINNING STEP $thisStepNum: $thisStepDesc =========="
+}
+function exit_if_last_command_failed
+{
+ local exitcode=$?;
+ if [ $exitcode -ne 0 ]; then
+ die "Build script failed with exit code $exitcode at step $thisStepNum: $thisStepDesc" $exitcode;
+ fi
+}
+
# setup and install conda environment
if run_step "1"; then
+ begin_step "1" "Conda environment setup"
# note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154
CONDA_REQS=$CYDIR/conda-reqs
CONDA_LOCK_REQS=$CONDA_REQS/conda-lock-reqs
@@ -120,13 +170,35 @@ if run_step "1"; then
if [ "$USE_UNPINNED_DEPS" = true ]; then
# auto-gen the lockfiles
$CYDIR/scripts/generate-conda-lockfiles.sh
+ exit_if_last_command_failed
fi
# use conda-lock to create env
- conda-lock install --conda $(which conda) -p $CYDIR/.conda-env $LOCKFILE
-
- source $CYDIR/.conda-env/etc/profile.d/conda.sh
+ conda-lock install --conda $(which conda) -p $CYDIR/.conda-env $LOCKFILE &&
+ source $CYDIR/.conda-env/etc/profile.d/conda.sh &&
conda activate $CYDIR/.conda-env
+ exit_if_last_command_failed
+
+ # Conda Setup
+ # Provide a sourceable snippet that can be used in subshells that may not have
+ # inhereted conda functions that would be brought in under a login shell that
+ # has run conda init (e.g., VSCode, CI)
+ read -r -d '\0' CONDA_ACTIVATE_PREAMBLE <<'END_CONDA_ACTIVATE'
+if ! type conda >& /dev/null; then
+ echo "::ERROR:: you must have conda in your environment first"
+ return 1 # don't want to exit here because this file is sourced
+fi
+
+# if we're sourcing this in a sub process that has conda in the PATH but not as a function, init it again
+conda activate --help >& /dev/null || source $(conda info --base)/etc/profile.d/conda.sh
+\0
+END_CONDA_ACTIVATE
+
+ replace_content env.sh build-setup-conda "# line auto-generated by $0
+$CONDA_ACTIVATE_PREAMBLE
+conda activate $CYDIR/.conda-env
+source $CYDIR/scripts/fix-open-files.sh"
+
fi
if [ -z "$FORCE_FLAG" ]; then
@@ -138,11 +210,14 @@ fi
# initialize all submodules (without the toolchain submodules)
if run_step "2"; then
+ begin_step "2" "Initializing Chipyard submodules"
$CYDIR/scripts/init-submodules-no-riscv-tools.sh $FORCE_FLAG
+ exit_if_last_command_failed
fi
# build extra toolchain collateral (i.e. spike, pk, riscv-tests, libgloss)
if run_step "3"; then
+ begin_step "3" "Building toolchain collateral"
if run_step "1"; then
PREFIX=$CONDA_PREFIX/$TOOLCHAIN_TYPE
else
@@ -153,64 +228,97 @@ if run_step "3"; then
PREFIX=$RISCV
fi
$CYDIR/scripts/build-toolchain-extra.sh $TOOLCHAIN_TYPE -p $PREFIX
+ exit_if_last_command_failed
fi
# run ctags for code navigation
if run_step "4"; then
+ begin_step "4" "Running ctags for code navigation"
$CYDIR/scripts/gen-tags.sh
+ exit_if_last_command_failed
fi
# precompile chipyard scala sources
if run_step "5"; then
- pushd $CYDIR/sims/verilator
- make launch-sbt SBT_COMMAND=";project chipyard; compile"
- make launch-sbt SBT_COMMAND=";project tapeout; compile"
+ begin_step "5" "Pre-compiling Chipyard Scala sources"
+ pushd $CYDIR/sims/verilator &&
+ make launch-sbt SBT_COMMAND=";project chipyard; compile" &&
+ make launch-sbt SBT_COMMAND=";project tapeout; compile" &&
popd
+ exit_if_last_command_failed
fi
# setup firesim
if run_step "6"; then
- $CYDIR/scripts/firesim-setup.sh
+ begin_step "6" "Setting up FireSim"
+ $CYDIR/scripts/firesim-setup.sh &&
$CYDIR/sims/firesim/gen-tags.sh
+ exit_if_last_command_failed
# precompile firesim scala sources
if run_step "7"; then
- pushd $CYDIR/sims/firesim
+ begin_step "7" "Pre-compiling Firesim Scala sources"
+ pushd $CYDIR/sims/firesim &&
(
+ set -e # Subshells un-set "set -e" so it must be re enabled
echo $CYDIR
source sourceme-manager.sh --skip-ssh-setup
pushd sim
make sbt SBT_COMMAND="project {file:$CYDIR}firechip; compile" TARGET_PROJECT=firesim
popd
)
+ exit_if_last_command_failed
popd
fi
fi
# setup firemarshal
if run_step "8"; then
- pushd $CYDIR/software/firemarshal
+ begin_step "8" "Setting up FireMarshal"
+ pushd $CYDIR/software/firemarshal &&
./init-submodules.sh
+ exit_if_last_command_failed
# precompile firemarshal buildroot sources
if run_step "9"; then
- source $CYDIR/scripts/fix-open-files.sh
- ./marshal $VERBOSE_FLAG build br-base.json
+ begin_step "9" "Pre-compiling FireMarshal buildroot sources"
+ source $CYDIR/scripts/fix-open-files.sh &&
+ ./marshal $VERBOSE_FLAG build br-base.json &&
./marshal $VERBOSE_FLAG clean br-base.json
+ exit_if_last_command_failed
fi
popd
fi
-# do misc. cleanup for a "clean" git status
if run_step "10"; then
- $CYDIR/scripts/repo-clean.sh
+ # install circt into conda
+ if run_step "1"; then
+ PREFIX=$CONDA_PREFIX/$TOOLCHAIN_TYPE
+ else
+ if [ -z "$RISCV" ] ; then
+ error "ERROR: If conda initialization skipped, \$RISCV variable must be defined."
+ exit 1
+ fi
+ PREFIX=$RISCV
+ fi
+
+ git submodule update --init $CYDIR/tools/install-circt &&
+ $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
+ -f circt-full-shared-linux-x64.tar.gz \
+ -i $PREFIX \
+ -v version-file \
+ -x $CYDIR/conda-reqs/circt.json \
+ -g null
+ exit_if_last_command_failed
fi
-cat <> env.sh
-# line auto-generated by $0
-conda activate $CYDIR/.conda-env
-source $CYDIR/scripts/fix-open-files.sh
-EOT
+
+# do misc. cleanup for a "clean" git status
+if run_step "11"; then
+ begin_step "10" "Cleaning up repository"
+ $CYDIR/scripts/repo-clean.sh
+ exit_if_last_command_failed
+fi
echo "Setup complete!"
diff --git a/scripts/build-toolchain-extra.sh b/scripts/build-toolchain-extra.sh
index 049e3424..28cc9dfa 100755
--- a/scripts/build-toolchain-extra.sh
+++ b/scripts/build-toolchain-extra.sh
@@ -118,4 +118,17 @@ cd tools/DRAMSim2
make libdramsim.so
cp libdramsim.so $RISCV/lib/
+echo '==> Installing uart_tsi bringup utility'
+cd $RDIR
+git submodule update --init generators/testchipip
+cd generators/testchipip/uart_tsi
+make
+cp uart_tsi $RISCV/bin
+
+echo '==> Installing spike-devices'
+cd $RDIR
+git submodule update --init toolchains/riscv-tools/riscv-spike-devices
+cd toolchains/riscv-tools/riscv-spike-devices
+make install
+
echo "Extra Toolchain Utilities/Tests Build Complete!"
diff --git a/scripts/generate-conda-lockfiles.sh b/scripts/generate-conda-lockfiles.sh
index f2e81106..544a8281 100755
--- a/scripts/generate-conda-lockfiles.sh
+++ b/scripts/generate-conda-lockfiles.sh
@@ -13,6 +13,13 @@ fi
for TOOLCHAIN_TYPE in riscv-tools esp-tools; do
# note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154
LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml
+ rm -rf $LOCKFILE
- conda-lock -f "$REQS_DIR/chipyard.yaml" -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" -p linux-64 --lockfile $LOCKFILE
+ conda-lock \
+ --no-mamba \
+ --no-micromamba \
+ -f "$REQS_DIR/chipyard.yaml" \
+ -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" \
+ -p linux-64 \
+ --lockfile $LOCKFILE
done
diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh
index d15498ea..aa921f0d 100755
--- a/scripts/init-submodules-no-riscv-tools-nolog.sh
+++ b/scripts/init-submodules-no-riscv-tools-nolog.sh
@@ -157,8 +157,6 @@ if [ ! -f ./software/firemarshal/marshal-config.yaml ]; then
echo "firesim-dir: '../../sims/firesim/'" > ./software/firemarshal/marshal-config.yaml
fi
-cat << EOT >> env.sh
-# line auto-generated by init-submodules-no-riscv-tools.sh
+replace_content env.sh init-submodules "# line auto-generated by init-submodules-no-riscv-tools.sh
__DIR="$RDIR"
-PATH=\$__DIR/software/firemarshal:\$PATH
-EOT
+PATH=\$__DIR/software/firemarshal:\$PATH"
diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py
index ed6fed73..8262c251 100755
--- a/scripts/insert-includes.py
+++ b/scripts/insert-includes.py
@@ -1,6 +1,7 @@
#!/usr/bin/env python
-# replaces a `include with the full include file
+# replaces a `include with the full include file.
+# recursively replaces `include's until none are left
#
# args
# $1 - file to remove includes from
@@ -12,6 +13,8 @@
import sys
import re
import os
+import tempfile
+import shutil
inVlog = sys.argv[1]
outVlog = sys.argv[2]
@@ -24,28 +27,52 @@ if inVlog == outVlog:
incDirs = sys.argv[3:]
print("[INFO] Searching following dirs for includes: " + str(incDirs))
-# open file
-with open(inVlog, 'r') as inFile:
- with open(outVlog, 'w') as outFile:
- # for each include found, search through all dirs and replace if found, error if not
- for num, line in enumerate(inFile, 1):
+def process(inF, outF):
+ # open file
+ with open(inF, 'r') as inFile:
+ with open(outF, 'w') as outFile:
+ # for each include found, search through all dirs and replace if found, error if not
+ for num, line in enumerate(inFile, 1):
+ match = re.match(r"^ *`include +\"(.*)\"", line)
+ if match:
+ # search for include and replace
+ found = False
+ for d in incDirs:
+ potentialIncFileName = d + "/" + match.group(1)
+ if os.path.exists(potentialIncFileName):
+ found = True
+ with open(potentialIncFileName, 'r') as incFile:
+ for iline in incFile:
+ outFile.write(iline)
+ break
+
+ # must find something to include with
+ if not found:
+ sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num))
+ else:
+ outFile.write(line)
+
+inF = inVlog
+
+while True:
+ # create a copy of the input
+ fd, temp_path = tempfile.mkstemp()
+ shutil.copy2(inF, temp_path)
+
+ with open(temp_path, 'r') as inFile:
+ anyIncludes = False
+ for line in inFile:
match = re.match(r"^ *`include +\"(.*)\"", line)
if match:
- # search for include and replace
- found = False
- for d in incDirs:
- potentialIncFileName = d + "/" + match.group(1)
- if os.path.exists(potentialIncFileName):
- found = True
- with open(potentialIncFileName, 'r') as incFile:
- for iline in incFile:
- outFile.write(iline)
- break
+ anyIncludes = True
+ break
- # must find something to include with
- if not found:
- sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num))
- else:
- outFile.write(line)
+ if anyIncludes:
+ process(temp_path, outVlog)
+ inF = outVlog
+ os.remove(temp_path)
+ else:
+ os.remove(temp_path)
+ break
print("[INFO] Success. Writing output to: " + str(outVlog))
diff --git a/scripts/replace-content.py b/scripts/replace-content.py
new file mode 100755
index 00000000..a20acaa8
--- /dev/null
+++ b/scripts/replace-content.py
@@ -0,0 +1,56 @@
+#!/usr/bin/env python3
+
+# Replace text in a file given a key identifying a block to replace.
+# If the file doesn't exist, create it.
+#
+# args
+# $1 - file to replace text in
+# $2 - key used to find block of text to replace
+# $3 - text to fill in block that is replaced
+
+import re
+import sys
+
+def CY_INITIALIZE_RE_BLOCK(k):
+ return (
+ r"^# >>> " + f"{k}" + r" initialize >>>(?:\n|\r\n)"
+ r"([\s\S]*?)"
+ r"# <<< " + f"{k}" + r" initialize <<<(?:\n|\r\n)?"
+ )
+
+def CY_INITIALIZE_START_TOKEN(k):
+ return "# >>> " + f"{k}" + " initialize >>>"
+
+def CY_INITIALIZE_END_TOKEN(k):
+ return "# <<< " + f"{k}" + " initialize <<<"
+
+# ------------------------------
+
+try:
+ with open(sys.argv[1]) as fh:
+ fh_content = fh.read()
+except FileNotFoundError:
+ fh_content = ""
+except:
+ raise
+
+initialize_comment_key = sys.argv[2]
+inner_contents = CY_INITIALIZE_START_TOKEN(initialize_comment_key) + "\n" + sys.argv[3] + "\n" + CY_INITIALIZE_END_TOKEN(initialize_comment_key) + "\n"
+
+# ------------------------------
+
+replace_str = "__CY_REPLACE_ME_123__"
+fh_content = re.sub(
+ CY_INITIALIZE_RE_BLOCK(initialize_comment_key),
+ replace_str,
+ fh_content,
+ flags=re.MULTILINE,
+)
+# TODO: maybe remove all but last of replace_str, if there's more than one occurrence
+fh_content = fh_content.replace(replace_str, inner_contents)
+
+if CY_INITIALIZE_START_TOKEN(initialize_comment_key) not in fh_content:
+ fh_content += "\n%s\n" % inner_contents
+
+with open(sys.argv[1], "w") as fh:
+ fh.write(fh_content)
diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch
index 1e766db9..b64d7a43 100644
--- a/scripts/tutorial-patches/build.sbt.patch
+++ b/scripts/tutorial-patches/build.sbt.patch
@@ -1,20 +1,20 @@
diff --git a/build.sbt b/build.sbt
-index 302d99e6..0aa0fcb4 100644
+index c3be6161..2a6d7160 100644
--- a/build.sbt
+++ b/build.sbt
-@@ -148,7 +148,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
-
+@@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
+
lazy val chipyard = (project in file("generators/chipyard"))
- .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+ .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
+ //sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, rocket_dsp_utils,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
- constellation, mempress, barf, shuttle)
-@@ -220,10 +220,10 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
+ constellation, mempress, barf, shuttle, caliptra_aes)
+@@ -219,10 +219,10 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
-
+
-lazy val sha3 = (project in file("generators/sha3"))
- .dependsOn(rocketchip, midasTargetUtils)
- .settings(libraryDependencies ++= rocketLibDeps.value)
@@ -23,6 +23,6 @@ index 302d99e6..0aa0fcb4 100644
+// .dependsOn(rocketchip, midasTargetUtils)
+// .settings(libraryDependencies ++= rocketLibDeps.value)
+// .settings(commonSettings)
-
+
lazy val gemmini = (project in file("generators/gemmini"))
.dependsOn(rocketchip)
diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py
index d53eb2f0..0ddea49f 100755
--- a/scripts/uniquify-module-names.py
+++ b/scripts/uniquify-module-names.py
@@ -21,6 +21,7 @@ parser.add_argument("--gcpath", type=str, required=True, help="Path to gen-colla
args = parser.parse_args()
MODEL_SFX=args.model + "_UNIQUIFIED"
+SED=os.environ.get("SED", "sed")
def bash(cmd):
@@ -109,7 +110,7 @@ def generate_copy(c, sfx):
new_file = os.path.join(args.gcpath, new_file)
shutil.copy(cur_file, new_file)
- bash(f"sed -i s/\"module {cur_name}\"/\"module {new_name}\"/ {new_file}")
+ bash(f"{SED} -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}")
return new_file
def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
@@ -136,7 +137,7 @@ def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
new_file = generate_copy(cur_file, MODEL_SFX)
if parent is not None and ((parent, mod) not in updated_submodule):
parent_file = os.path.join(args.gcpath, verilog_module_filename[parent])
- bash(f"sed -i s/\"{mod} \"/\"{mod}_{MODEL_SFX} \"/ {parent_file}")
+ bash(f"{SED} -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}")
updated_submodule.add((parent, mod))
# add the uniquified module to the verilog_modul_filename dict
diff --git a/scripts/utils.sh b/scripts/utils.sh
index 30d3e092..633be103 100755
--- a/scripts/utils.sh
+++ b/scripts/utils.sh
@@ -53,3 +53,27 @@ function restore_bash_options
{
set +vx; eval "$OLDSTATE"
}
+
+#######################################
+# Wrapper around replace-content.py.
+# For a file ($1), write out text ($3) into it
+# replacing any area designated by $2.
+#######################################
+function replace_content
+{
+ # On macOS, use GNU readlink from 'coreutils' package in Homebrew/MacPorts
+ if [ "$(uname -s)" = "Darwin" ] ; then
+ READLINK=greadlink
+ else
+ READLINK=readlink
+ fi
+
+ # If BASH_SOURCE is undefined, we may be running under zsh, in that case
+ # provide a zsh-compatible alternative
+ DIR="$(dirname "$($READLINK -f "${BASH_SOURCE[0]:-${(%):-%x}}")")"
+ file="$1"
+ shift
+ key="$1"
+ shift
+ $DIR/replace-content.py "$file" "$key" "$@"
+}
diff --git a/sims/firesim b/sims/firesim
index 08b565c8..d2501ec7 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 08b565c8c69f125a1de292eb8efe03ee08408d2e
+Subproject commit d2501ec790c3df9094cc729c33074b641c515b03
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index 73845bc2..e1cf31ef 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -163,8 +163,7 @@ VERILATOR_NONCC_OPTS = \
VERILATOR_CXXFLAGS = \
$(SIM_CXXFLAGS) \
$(RUNTIME_PROFILING_CFLAGS) \
- -DVERILATOR \
- -include $(build_dir)/$(long_name).plusArgs
+ -DVERILATOR
VERILATOR_LDFLAGS = $(SIM_LDFLAGS)
@@ -195,13 +194,13 @@ model_mk_debug = $(model_dir_debug)/V$(TB).mk
$(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
rm -rf $(model_dir)
mkdir -p $(model_dir)
- $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
+ $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
touch $@
$(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
rm -rf $(model_dir_debug)
mkdir -p $(model_dir_debug)
- $(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
+ $(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
touch $@
#########################################################################################
diff --git a/software/baremetal-ide b/software/baremetal-ide
new file mode 160000
index 00000000..f488090a
--- /dev/null
+++ b/software/baremetal-ide
@@ -0,0 +1 @@
+Subproject commit f488090a7f37da43610bd5017ee401526bf40fb2
diff --git a/software/firemarshal b/software/firemarshal
index 8b8eea35..97826983 160000
--- a/software/firemarshal
+++ b/software/firemarshal
@@ -1 +1 @@
-Subproject commit 8b8eea35f618b9418c850df7ed809a2285ee5d1c
+Subproject commit 97826983438427b8fc40d9b66af2674ce7046bac
diff --git a/tests/Makefile b/tests/Makefile
index 28976a6a..1c6df31b 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -2,14 +2,14 @@
# RISCV Toolchain
#################################
-PREFIX = riscv64-unknown-elf-
+TARGET = riscv64-unknown-elf
-GCC = $(PREFIX)gcc
-CXX = $(PREFIX)g++
-CP = $(PREFIX)objcopy
-OBJDUMP = $(PREFIX)objdump
-DG = $(PREFIX)gdb
-SIZE = $(PREFIX)size
+GCC = $(TARGET)-gcc
+CXX = $(TARGET)-g++
+CP = $(TARGET)-objcopy
+OBJDUMP = $(TARGET)-objdump
+DG = $(TARGET)-gdb
+SIZE = $(TARGET)-size
#################################
@@ -29,7 +29,7 @@ include libgloss.mk
PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \
streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd \
- hello mt-hello
+ hello mt-hello symmetric
.DEFAULT_GOAL := default
diff --git a/tests/blkdev.c b/tests/blkdev.c
index 994a341b..b740617c 100644
--- a/tests/blkdev.c
+++ b/tests/blkdev.c
@@ -59,8 +59,8 @@ void blkdev_write(unsigned long offset, void *addr, size_t nsectors)
#define TEST_NSECTORS 4
#define TEST_SIZE (TEST_NSECTORS * BLKDEV_SECTOR_SIZE / sizeof(int))
-unsigned int test_data[TEST_SIZE];
-unsigned int res_data[TEST_SIZE];
+unsigned int test_data[TEST_SIZE] __attribute__ ((aligned (64)));
+unsigned int res_data[TEST_SIZE] __attribute__ ((aligned (64)));
int main(void)
{
diff --git a/tests/gcd.c b/tests/gcd.c
index 1d8ee691..de28251d 100644
--- a/tests/gcd.c
+++ b/tests/gcd.c
@@ -1,9 +1,9 @@
#include "mmio.h"
-#define GCD_STATUS 0x1000
-#define GCD_X 0x1004
-#define GCD_Y 0x1008
-#define GCD_GCD 0x100C
+#define GCD_STATUS 0x4000
+#define GCD_X 0x4004
+#define GCD_Y 0x4008
+#define GCD_GCD 0x400C
unsigned int gcd_ref(unsigned int x, unsigned int y) {
while (y != 0) {
diff --git a/tests/libgloss.mk b/tests/libgloss.mk
index 2272df33..5553bdbd 100644
--- a/tests/libgloss.mk
+++ b/tests/libgloss.mk
@@ -5,6 +5,10 @@ ifndef GCC
$(error GCC is not defined)
endif
+ifndef TARGET
+$(error TARGET is not defined)
+endif
+
libgloss_specs := htif_nano.specs
# Test whether libgloss-htif is globally installed and usable
diff --git a/tests/symmetric.c b/tests/symmetric.c
new file mode 100644
index 00000000..a6d37627
--- /dev/null
+++ b/tests/symmetric.c
@@ -0,0 +1,30 @@
+#include
+#include
+#include
+#include "marchid.h"
+
+#define OBUS_OFFSET (0x1L << 32)
+
+char src[] = "This is a test string. It will be written into the off-chip memory address, then copied back.";
+char dest[4096];
+char test[4096];
+
+int main(void) {
+ size_t write_start = rdcycle();
+ memcpy(dest + OBUS_OFFSET, src, sizeof(src));
+ size_t write_end = rdcycle();
+
+ printf("Wrote %ld bytes in %ld cycles\n", sizeof(src), write_end - write_start);
+
+ size_t read_start = rdcycle();
+ memcpy(test, dest + OBUS_OFFSET, sizeof(src));
+ size_t read_end = rdcycle();
+
+ if (memcmp(src, test, sizeof(src))) {
+ printf("Remote write/read failed\n");
+ exit(1);
+ }
+ printf("Read %ld bytes in %ld cycles\n", sizeof(src), read_end - read_start);
+
+ return 0;
+}
diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim
index 015b4e92..4d8651be 160000
--- a/toolchains/riscv-tools/riscv-isa-sim
+++ b/toolchains/riscv-tools/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit 015b4e92e3a85f827a54590e00e716b79a2f8e9e
+Subproject commit 4d8651be943ea706eb8dcb3443add2e7ccc117a6
diff --git a/toolchains/riscv-tools/riscv-spike-devices b/toolchains/riscv-tools/riscv-spike-devices
new file mode 160000
index 00000000..8b4836db
--- /dev/null
+++ b/toolchains/riscv-tools/riscv-spike-devices
@@ -0,0 +1 @@
+Subproject commit 8b4836db0b5b4ed0a9bab34e7707fe40c7c014be
diff --git a/tools/barstools b/tools/barstools
index f5fe37c4..60a1be9b 160000
--- a/tools/barstools
+++ b/tools/barstools
@@ -1 +1 @@
-Subproject commit f5fe37c4bf0a37eb5033eeaf930c337895470607
+Subproject commit 60a1be9bfe344fccbddd4874524accb3c9d2ade9
diff --git a/tools/dsptools b/tools/dsptools
index 7bd039fb..8f433663 160000
--- a/tools/dsptools
+++ b/tools/dsptools
@@ -1 +1 @@
-Subproject commit 7bd039fb5f28ce2f31ed4420deb9a2220542838d
+Subproject commit 8f4336639578d2e2dbaf61e542ee1f0fa8d79e63
diff --git a/tools/fixedpoint b/tools/fixedpoint
index 35dda166..36ce43c9 160000
--- a/tools/fixedpoint
+++ b/tools/fixedpoint
@@ -1 +1 @@
-Subproject commit 35dda166f58f021cc32d00a2e76a5a33691c2b20
+Subproject commit 36ce43c90ce9cfc63e7698fa1e27fd122c878e9e
diff --git a/tools/install-circt b/tools/install-circt
new file mode 160000
index 00000000..3f8dda6e
--- /dev/null
+++ b/tools/install-circt
@@ -0,0 +1 @@
+Subproject commit 3f8dda6e1c1965537b5801a43c81c287bac4eae4
diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils
index 341e9198..19445522 160000
--- a/tools/rocket-dsp-utils
+++ b/tools/rocket-dsp-utils
@@ -1 +1 @@
-Subproject commit 341e91985fdda7cce7eb30566fe58482a6f5aa40
+Subproject commit 194455223aa75f400d2ac76bfd71e61e3c2a9533
diff --git a/variables.mk b/variables.mk
index 5d540ea4..705b8955 100644
--- a/variables.mk
+++ b/variables.mk
@@ -29,8 +29,7 @@ HELP_SIMULATION_VARIABLES = \
" LOADMEM = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \
" LOADARCH = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \
" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \
-" timeout_cycles = number of clock cycles before simulator times out, defaults to 10000000" \
-" bmark_timeout_cycles = number of clock cycles before benchmark simulator times out, defaults to 100000000"
+" TIMEOUT_CYCLES = number of clock cycles before simulator times out, defaults to 10000000"
# include default simulation rules
HELP_COMMANDS = \
@@ -97,7 +96,7 @@ ifeq ($(SUB_PROJECT),testchipip)
VLOG_MODEL ?= $(MODEL)
MODEL_PACKAGE ?= chipyard.unittest
CONFIG ?= TestChipUnitTestConfig
- CONFIG_PACKAGE ?= testchipip
+ CONFIG_PACKAGE ?= testchipip.test
GENERATOR_PACKAGE ?= chipyard
TB ?= TestDriver
TOP ?= UnitTestSuite
@@ -287,7 +286,7 @@ PERMISSIVE_ON=+permissive
PERMISSIVE_OFF=+permissive-off
BINARY ?=
BINARIES ?=
-override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles)
+override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(TIMEOUT_CYCLES)
VERBOSE_FLAGS ?= +verbose
# get_out_name is a function, 1st argument is the binary
get_out_name = $(subst $() $(),_,$(notdir $(basename $(1))))
@@ -305,14 +304,20 @@ endif
# build output directory for compilation
#########################################################################################
# output for all project builds
-gen_dir=$(sim_dir)/generated-src
+generated_src_name ?=generated-src
+gen_dir =$(sim_dir)/$(generated_src_name)
# per-project output directory
-build_dir=$(gen_dir)/$(long_name)
+build_dir =$(gen_dir)/$(long_name)
# final generated collateral per-project
-GEN_COLLATERAL_DIR ?= $(build_dir)/gen-collateral
+GEN_COLLATERAL_DIR ?=$(build_dir)/gen-collateral
#########################################################################################
-# assembly/benchmark variables
+# simulation variables
#########################################################################################
-timeout_cycles = 10000000
-bmark_timeout_cycles = 100000000
+TIMEOUT_CYCLES = 10000000
+
+# legacy timeout_cycles handling
+timeout_cycles ?=
+ifneq ($(timeout_cycles),)
+TIMEOUT_CYCLES=$(timeout_cycles)
+endif
diff --git a/vlsi/Makefile b/vlsi/Makefile
index b3901fe6..074ec66a 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -42,7 +42,7 @@ HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\
./example-vlsi-sky130,\
./example-vlsi)
VLSI_TOP ?= $(TOP)
-VLSI_MODEL_DUT_NAME ?= chiptop
+VLSI_MODEL_DUT_NAME ?= chiptop0
# If overriding, this should be relative to $(vlsi_dir)
VLSI_OBJ_DIR ?= build
ifneq ($(CUSTOM_VLOG),)
diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml
index c7300f9b..4a6b664c 100644
--- a/vlsi/example-designs/sky130-openroad-rockettile.yml
+++ b/vlsi/example-designs/sky130-openroad-rockettile.yml
@@ -22,27 +22,16 @@ vlsi.inputs.placement_constraints:
bottom: 10
# Place SRAM memory instances
- # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
- # data cache
- - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+ # data cache
+ - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 50
orientation: r90
- - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
+ - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
type: hardmacro
x: 50
- y: 450
- orientation: r90
- - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
- type: hardmacro
- x: 50
- y: 850
- orientation: r90
- - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
- type: hardmacro
- x: 50
- y: 1250
+ y: 800
orientation: r90
# tag array
@@ -53,7 +42,7 @@ vlsi.inputs.placement_constraints:
orientation: r90
# instruction cache
- - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
+ - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 2100
diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml
index 33f01cad..3b95d982 100644
--- a/vlsi/example-designs/sky130-openroad.yml
+++ b/vlsi/example-designs/sky130-openroad.yml
@@ -54,8 +54,6 @@ vlsi.inputs.placement_constraints:
bottom: 10
# Place SRAM memory instances
- # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
- # data cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml
index 1cd281f7..1e3faf1c 100644
--- a/vlsi/example-sky130.yml
+++ b/vlsi/example-sky130.yml
@@ -48,6 +48,11 @@ vlsi.inputs.placement_constraints:
x: 50
y: 50
orientation: r90
+ - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
+ type: hardmacro
+ x: 50
+ y: 800
+ orientation: r90
# tag array
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
diff --git a/vlsi/power.mk b/vlsi/power.mk
index ff1c1729..c006d338 100644
--- a/vlsi/power.mk
+++ b/vlsi/power.mk
@@ -23,7 +23,7 @@ endif
endif
echo " start_times: ['0ns']" >> $@
echo " end_times: [" >> $@
- echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
+ echo " '`bc <<< $(TIMEOUT_CYCLES)*$(CLOCK_PERIOD)`ns'" >> $@
echo " ]" >> $@
$(POWER_RTL_CONF): $(VLSI_RTL)
diff --git a/vlsi/sim.mk b/vlsi/sim.mk
index ea2c76d7..f5ff85ff 100644
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -51,7 +51,11 @@ $(SIM_DEBUG_CONF): $(sim_common_files) check-binary
mkdir -p $(dir $@)
mkdir -p $(output_dir)
echo "sim.inputs:" > $@
- echo " defines: ['DEBUG']" >> $@
+ echo " defines:" >> $@
+ echo " - 'DEBUG'" >> $@;
+ifndef USE_VPD
+ echo " - 'FSDB=1'" >> $@;
+endif
echo " defines_meta: 'append'" >> $@
echo " execution_flags:" >> $@
for x in $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$(BINARY))); do \
@@ -60,7 +64,7 @@ $(SIM_DEBUG_CONF): $(sim_common_files) check-binary
echo " execution_flags_meta: 'append'" >> $@
echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@
- echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
+ echo " saif.end_time: '`bc <<< $(TIMEOUT_CYCLES)*$(CLOCK_PERIOD)`ns'" >> $@
ifndef USE_VPD
echo " options:" >> $@
echo ' - "-kdb"' >> $@
diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk
index 6b970fcb..5e57455f 100644
--- a/vlsi/tutorial.mk
+++ b/vlsi/tutorial.mk
@@ -12,6 +12,7 @@ ifeq ($(tutorial),asap7)
TECH_CONF ?= example-asap7.yml
DESIGN_CONFS ?=
VLSI_OBJ_DIR ?= build-asap7-commercial
+ INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
endif
ifeq ($(tutorial),sky130-commercial)
@@ -23,6 +24,7 @@ ifeq ($(tutorial),sky130-commercial)
$(if $(filter $(VLSI_TOP),Rocket), \
example-designs/sky130-rocket.yml, )
VLSI_OBJ_DIR ?= build-sky130-commercial
+ INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
endif
ifeq ($(tutorial),sky130-openroad)
@@ -36,8 +38,7 @@ ifeq ($(tutorial),sky130-openroad)
$(if $(filter $(VLSI_TOP),RocketTile), \
example-designs/sky130-openroad-rockettile.yml, )
VLSI_OBJ_DIR ?= build-sky130-openroad
- # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
+ INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
+ # Yosys compatibility for CIRCT-generated Verilog
ENABLE_YOSYS_FLOW = 1
endif
-
-INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)