From 4956a93c2711e553d47c7d52ec613dd7a58b3124 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 16:56:05 -0800 Subject: [PATCH 1/4] changing clock to clock_clock [skip ci] --- vlsi/example-asap7.yml | 2 +- vlsi/example-design.yml | 2 +- vlsi/example-nangate45.yml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index 683edaae..213f0b90 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "1ns", uncertainty: "0.1ns"} + {name: "clock_clock", period: "1ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index 43f54997..3c11cd11 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "2ns", uncertainty: "0.1ns"} + {name: "clock_clock", period: "2ns", uncertainty: "0.1ns"} ] # Specify pin properties diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index c1c3ba63..5b4a59ea 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -22,7 +22,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "5ns", uncertainty: "0.5ns"} + {name: "clock_clock", period: "5ns", uncertainty: "0.5ns"} ] # Generate Make include to aid in flow From e9b1c4818c799b24ab3ff136f1810c41ea9fd2c7 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 16:56:41 -0800 Subject: [PATCH 2/4] removing extra space [skip ci] --- vlsi/example-vlsi | 1 - vlsi/example-vlsi-sky130 | 36 +----------------------------------- 2 files changed, 1 insertion(+), 36 deletions(-) diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index bf280f0f..73f73ffe 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -39,7 +39,6 @@ set_db route_design_top_routing_layer 7 class ExampleDriver(CLIDriver): def get_extra_par_hooks(self) -> List[HammerToolHookAction]: extra_hooks = [ - # Default set of steps can be found in the CAD tool plugin's __init__.py # make_pre_insertion_hook will execute the custom hook before the specified step diff --git a/vlsi/example-vlsi-sky130 b/vlsi/example-vlsi-sky130 index 73fba530..b3bf9467 100755 --- a/vlsi/example-vlsi-sky130 +++ b/vlsi/example-vlsi-sky130 @@ -32,35 +32,15 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here +# only route in met1 to met4 set_db route_design_bottom_routing_layer 2 set_db route_design_top_routing_layer 5 ''') return True -def drc_blackbox_openram_srams(x: hammer_vlsi.HammerTool) -> bool: - if x.get_setting("vlsi.core.technology") == "sky130": - drc_box = '' - for name in SKY130Tech().openram_sram_names(): - drc_box += f"\nEXCLUDE CELL {name}" - with open(x.drc_run_file, "a") as f: - f.write(drc_box) - return True - -def lvs_blackbox_openram_srams(x: hammer_vlsi.HammerTool) -> bool: - if x.get_setting("vlsi.core.technology") == "sky130": - lvs_box = '' - for name in SKY130Tech.openram_sram_names(): - lvs_box += f"\nLVS BOX {name}" - lvs_box += f"\nLVS FILTER {name} OPEN " - with open(x.lvs_run_file, "a") as f: - f.write(lvs_box) - return True - - class ExampleDriver(CLIDriver): def get_extra_par_hooks(self) -> List[HammerToolHookAction]: extra_hooks = [ - # Default set of steps can be found in the CAD tool plugin's __init__.py # make_pre_insertion_hook will execute the custom hook before the specified step @@ -79,20 +59,6 @@ class ExampleDriver(CLIDriver): # The target step in any of the above calls may be a default step or another one of your custom hooks ] return extra_hooks - - def get_extra_drc_hooks(self) -> List[HammerToolHookAction]: - extra_hooks = [ - # This is an example of a technology-supplied hook - hammer_vlsi.HammerTool.make_post_insertion_hook("generate_drc_run_file", drc_blackbox_openram_srams), - ] - return extra_hooks - - def get_extra_lvs_hooks(self) -> List[HammerToolHookAction]: - extra_hooks = [ - # This is an example of a technology-supplied hook - hammer_vlsi.HammerTool.make_post_insertion_hook("generate_lvs_run_file", lvs_blackbox_openram_srams), - ] - return extra_hooks if __name__ == '__main__': ExampleDriver().main() From dc17b85a396dbfa33cf507abbb946363e55fb529 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 16:57:17 -0800 Subject: [PATCH 3/4] bumping hammer cadence plugin to lastest master commit [skip ci] --- vlsi/hammer-cadence-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 84fe5968..998b2021 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 84fe59682ce326fba27624a383d8b5c3ba0716af +Subproject commit 998b2021b028bedf7c45f7a32915b1831f842c9b From 488e25c001663ed2794eeb5d10343d0889d15694 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 18:01:53 -0800 Subject: [PATCH 4/4] modified power straps and floorplan to improve PnR results [skip ci] --- vlsi/example-sky130.yml | 132 ++++++++++++++++++---------------------- 1 file changed, 58 insertions(+), 74 deletions(-) diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index f570b349..e8cae39a 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -7,14 +7,10 @@ vlsi.core.max_threads: 12 # Technology paths technology.sky130: sky130_pdk: "path-to-skywater-pdk/" - sky130_nda: "path-to-skywater-src-nda/" sky130A: "path-to-sky130A/" + sky130_nda: "path-to-skywater-src-nda/" openram_lib: "path-to-sky130_sram_macros/" -# Mentor environment variables -mentor.extra_env_vars: - - PDK_HOME: "path-to-skywater-src-nda/s8/V2.0.1" - # General Hammer Inputs # Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info @@ -23,7 +19,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "200ns", uncertainty: "10ns"} + {name: "clock_clock", period: "130ns", uncertainty: "1ns"} ] # Generate Make include to aid in flow @@ -33,21 +29,23 @@ vlsi.core.build_system: make par.power_straps_mode: generate par.generate_power_straps_method: by_tracks par.blockage_spacing: 2.0 +par.blockage_spacing_top_layer: met4 par.generate_power_straps_options: by_tracks: strap_layers: - - met2 - - met3 - met4 - met5 pin_layers: - met5 + blockage_spacing_met2: 4.0 track_width: 6 track_width_met5: 2 track_spacing: 1 track_start: 10 - power_utilization: 0.2 - power_utilization_met5: 1 + track_start_met5: 1 + power_utilization: 0.1 + power_utilization_met4: 0.3 + power_utilization_met5: 0.5 # Placement Constraints vlsi.inputs.placement_constraints: @@ -55,127 +53,113 @@ vlsi.inputs.placement_constraints: type: toplevel x: 0 y: 0 - width: 4000 - height: 3000 + width: 4500 + height: 2500 margins: left: 0 right: 0 top: 0 bottom: 0 + # Place data cache SRAM instances - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro - x: 30 - y: 2190 + x: 50 + y: 100 orientation: r0 - top_layer: "met4" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" type: hardmacro - x: 30 - y: 1530 - orientation: mx - top_layer: "met4" + x: 50 + y: 700 + orientation: r0 - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0" type: hardmacro - x: 30 - y: 1030 - orientation: mx - top_layer: "met4" + x: 50 + y: 1300 + orientation: r0 - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0" type: hardmacro - x: 30 - y: 530 - orientation: mx - top_layer: "met4" + x: 50 + y: 1900 + orientation: r0 - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0" type: hardmacro - x: 30 - y: 30 - orientation: mx - top_layer: "met4" + x: 1000 + y: 1900 + orientation: r0 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0" type: hardmacro - x: 1110 - y: 30 - orientation: mx - top_layer: "met4" + x: 1000 + y: 1300 + orientation: r0 - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0" type: hardmacro - x: 2150 - y: 30 - orientation: mx - top_layer: "met4" - + x: 1000 + y: 700 + orientation: r0 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0" type: hardmacro - x: 2150 - y: 530 - orientation: mx - top_layer: "met4" - - + x: 1000 + y: 100 + orientation: r0 + # Place instruction cache SRAM instances - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro - x: 2150 - y: 1550 - orientation: mx - top_layer: "met4" - + x: 3700 + y: 100 + orientation: r0 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0" type: hardmacro - x: 2150 - y: 1030 + x: 3700 + y: 700 orientation: r0 - top_layer: "met4" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" type: hardmacro - x: 2350 - y: 2200 + x: 3000 + y: 100 orientation: r0 - top_layer: "met4" - + + # Place L2 TLB SRAM instances - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" type: hardmacro - x: 3100 - y: 30 + x: 1900 + y: 1900 orientation: "r0" - top_layer: "met4" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1" type: hardmacro - x: 3100 - y: 530 + x: 2600 + y: 1900 orientation: "r0" - top_layer: "met4" - + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2" type: hardmacro - x: 3100 - y: 1030 + x: 3300 + y: 1900 orientation: "r0" - top_layer: "met4" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3" type: hardmacro - x: 3100 - y: 1530 + x: 3950 + y: 1900 orientation: "r0" - top_layer: "met4" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4" type: hardmacro - x: 3100 - y: 2190 + x: 3950 + y: 1300 orientation: "r0" - top_layer: "met4" # Pin placement constraints vlsi.inputs.pin_mode: generated