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spelling check | better heading for accelerators

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abejgonzalez
2019-05-27 19:07:55 -07:00
parent 3b14ac8706
commit c160f597b7
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docs/Getting-Started/Development-Ecosystem.rst
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@@ -13,7 +13,7 @@ Chisel/FIRRTL
One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language <https://chisel.eecs.berkeley.edu/>`__ and the `FIRRTL Compiler <https://freechipsproject.github.io/firrtl/>`__.
Chisel is an embedded language within Scala that provides a set of libraries to help hardware designers create highly parameterizable RTL.
FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimation, circuit analysis, connectivity checks, and much more!
FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more!
These two tools in combination allow quick design space exploration and development of new RTL.
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