diff --git a/fpga/fpga-shells b/fpga/fpga-shells index cdf3db20..2d36b0ab 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit cdf3db20f01abbb09937b77c992de1914f71956a +Subproject commit 2d36b0ab430fe3dc4cf378f378be21b925379110 diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index d9fc1322..5b766107 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -6,7 +6,8 @@ import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.diplomacy.{RegionType, AddressSet} +import freechips.rocketchip.resources.{DTSModel, DTSTimebase} import freechips.rocketchip.tile.{XLen} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index d9caa81d..afcbf7d4 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -6,7 +6,8 @@ import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.diplomacy.{RegionType, AddressSet} +import freechips.rocketchip.resources.{DTSModel, DTSTimebase} import freechips.rocketchip.tile.{XLen} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} diff --git a/generators/boom b/generators/boom index 41c8fc9b..6a3ad0a1 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 41c8fc9bdfe68d0e30295cbaf764f2e69c36dbb8 +Subproject commit 6a3ad0a1d9ae659aba5aea78978ef1a7cb5dd163 diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index 97866c50..6811be7a 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ -import freechips.rocketchip.prci.ClockSinkParameters +import freechips.rocketchip.prci._ case class SpikeCoreParams() extends CoreParams { val useVM = true diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala index fc6466ce..c1213d93 100644 --- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala @@ -1,7 +1,6 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // ------------------------------ // Configs with MMIO accelerators diff --git a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala index 1b351266..fe99d5f1 100644 --- a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala @@ -1,7 +1,6 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // ------------------------------------------------------------ // Configs which demonstrate modifying the uncore memory system diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index ac24d85c..ebd196c3 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -1,7 +1,6 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.subsystem.{SBUS, MBUS} import constellation.channel._ diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index fa74d9b8..c84427ad 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -1,7 +1,6 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.subsystem.{MBUS} // --------------------------------------------------------- diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 960872b1..a654d70f 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -1,7 +1,6 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // ------------------------------ // Configs with RoCC Accelerators diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 680129a3..c0ee4bba 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -1,7 +1,7 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} +import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.{InCluster} // -------------- diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 265be720..87229cb4 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -7,7 +7,7 @@ import chisel3.util.{log2Up} import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey} import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} +import freechips.rocketchip.prci.{AsynchronousCrossing} import chipyard.stage.phases.TargetDirKey import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen} diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index 8e16b26c..42899286 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -2,7 +2,7 @@ package chipyard.config import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy.{DTSTimebase} +import freechips.rocketchip.resources.{DTSTimebase} import sifive.blocks.inclusivecache.{InclusiveCachePortParameters} // Replaces the L2 with a broadcast manager for maintaining coherence diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 76b17273..f69ec864 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.prci.ClockSinkParameters +import freechips.rocketchip.prci._ // Example parameter class copied from CVA6, not included in documentation but for compile check only // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure diff --git a/generators/constellation b/generators/constellation index 6664839b..5c9d2735 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit 6664839b104a0d34adebfee13a0addc19efbde50 +Subproject commit 5c9d27359dcb2b144c99cc8e3e561979eb2bd905 diff --git a/generators/cva6 b/generators/cva6 index 9d1c1068..de4772f1 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 9d1c106834824ddb8052b7f60574b2b544b40395 +Subproject commit de4772f1d66cc6d4ef42e75f34c42eb7b941c8f0 diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 42f0b1d8..1793d32b 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -12,7 +12,8 @@ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} -import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.prci.{AsynchronousCrossing} import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig} import testchipip.cosim.{TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} @@ -383,4 +384,4 @@ class FireSimLargeBoomSV39CospikeConfig extends Config( new WithDefaultMemModel ++ new WithFireSimConfigTweaks++ new chipyard.config.WithSV39 ++ - new chipyard.LargeBoomV3Config) \ No newline at end of file + new chipyard.LargeBoomV3Config) diff --git a/generators/ibex b/generators/ibex index 89c19c2d..8a43aa70 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 89c19c2d7bc2523a0d9fb85e154bcaf2c1cc7665 +Subproject commit 8a43aa70da1c06f4d34ec8710a3d2ee7585948a5 diff --git a/generators/icenet b/generators/icenet index 969bc8f9..6fd35bf5 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 969bc8f9a00e4b11d243656f255761e04e10ccb9 +Subproject commit 6fd35bf5a28310c61671fce7309526b56d91e35d diff --git a/generators/riscv-sodor b/generators/riscv-sodor index ca043149..732cbe19 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit ca0431493ec35983388cb08bb203d5e12e9a32b2 +Subproject commit 732cbe1990e9ef55ba122664465b372744f2eaab diff --git a/generators/rocket-chip b/generators/rocket-chip index 3cec0f0d..4ac1529d 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 3cec0f0dee432d6bb2da5ce6aa1142474807ff86 +Subproject commit 4ac1529d982df90da6970c1425ec471e304ba4fb diff --git a/generators/shuttle b/generators/shuttle index 4792a1ab..799263c6 160000 --- a/generators/shuttle +++ b/generators/shuttle @@ -1 +1 @@ -Subproject commit 4792a1aba4e9f2d70e6f84587913f78c9e4c0340 +Subproject commit 799263c6180587670fe42de23f3338f1f218d87e diff --git a/generators/testchipip b/generators/testchipip index 7a30dc73..b85f5ac0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 7a30dc737d0d93e1e1926d56f7361d4b70ff5fe7 +Subproject commit b85f5ac0464d16706000c6b1ef5b0c8556f84133 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index c4c638da..6ee2309f 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit c4c638da02351c701ff31e73aadd987baa7a2acc +Subproject commit 6ee2309f80a54b404795f227793d2a54e1dfadf8