From c27c9d5d1882508640acd86682822a1d4da5e42e Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 15 Mar 2021 02:16:18 -0700
Subject: [PATCH] Add option to add async queues between chip-serialIO and
 harness serdes

---
 .../src/main/scala/HarnessBinders.scala       | 24 ++++++++++++++-----
 generators/testchipip                         |  2 +-
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala
index 643b2065..fe03f951 100644
--- a/generators/chipyard/src/main/scala/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/HarnessBinders.scala
@@ -238,23 +238,35 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
 })
 
 
-class WithSerialAdapterTiedOff extends OverrideHarnessBinder({
+class WithSerialAdapterTiedOff(asyncQueue: Boolean = false) extends OverrideHarnessBinder({
   (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
     ports.map({ port =>
-      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
+      val bits = if (asyncQueue) {
+        SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
+      } else {
+        port.bits
+      }
+      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
       SerialAdapter.tieoff(ram.module.io.tsi_ser)
     })
   }
 })
 
-class WithSimSerial extends OverrideHarnessBinder({
+class WithSimSerial(asyncQueue: Boolean = false) extends OverrideHarnessBinder({
   (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
     ports.map({ port =>
-      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
-      val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, port.clock, th.harnessReset.asBool)
-      when (success) { th.success := true.B }
+      val bits = if (asyncQueue) {
+        SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
+      } else {
+        port.bits
+      }
+      withClockAndReset(th.harnessClock, th.harnessReset) {
+        val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
+        val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.harnessClock, th.harnessReset.asBool)
+        when (success) { th.success := true.B }
+      }
     })
   }
 })
diff --git a/generators/testchipip b/generators/testchipip
index 282ca2e2..6e2db28a 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 282ca2e25e191e63051afafc8808561f6a54c695
+Subproject commit 6e2db28a165627f44b6e97d40930406bbfb6e3e3