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default to .gitignoring all files in verisim/vsim | read verilator.mk

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abejgonzalez
2019-03-08 18:11:10 -08:00
parent 4fd1bfbd56
commit c364869563
4 changed files with 51 additions and 5 deletions
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.gitignore vendored
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@@ -3,9 +3,6 @@ bootrom
target
*.jar
*.stamp
/sims/vsim
/sims/verisim
simv*
*.vcd
*.swp
.idea