From c472e22223ce229a313becdbc0f75b087f3f14d0 Mon Sep 17 00:00:00 2001
From: abejgonzalez <abe.j.gonza@gmail.com>
Date: Thu, 13 Oct 2022 17:52:58 -0700
Subject: [PATCH] Update FPGA makefile | Reorg firtool args

---
 common.mk     | 11 ++++++-----
 fpga/Makefile | 10 +++++-----
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/common.mk b/common.mk
index 3c67a5c7..474bf922 100644
--- a/common.mk
+++ b/common.mk
@@ -190,19 +190,20 @@ $(FIRTOOL_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
 		$(EXTRA_FIRRTL_OPTIONS))
 	$(if $(shell grep "Fixed<" $(FIRRTL_FILE)),mv $(SFC_FIRRTL_BASENAME).mid.fir $(SFC_FIRRTL_FILE),)
 	firtool \
+		--format=fir \
+		-O=release \
+		--dedup \
 		--export-module-hierarchy \
 		--emit-metadata \
-		--format=fir \
-		-warn-on-unprocessed-annotations \
-		-verify-each=false \
-		-dedup \
-		--annotation-file=$(SFC_ANNO_FILE) \
+		--verify-each=false \
 		--disable-annotation-classless \
 		--disable-annotation-unknown \
+		--warn-on-unprocessed-annotations \
 		--lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \
 		--repl-seq-mem \
 		--repl-seq-mem-circuit=$(MODEL) \
 		--repl-seq-mem-file=$(FIRTOOL_SMEMS_CONF) \
+		--annotation-file=$(SFC_ANNO_FILE) \
 		--split-verilog \
 		-o $(OUT_DIR) \
 		$(SFC_FIRRTL_FILE)
diff --git a/fpga/Makefile b/fpga/Makefile
index be059e65..d037833b 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -94,13 +94,13 @@ SIM_FILE_REQS += \
 	$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
 
 # copy files but ignore *.h files in *.f (match vcs)
-$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
-	cp -f $^ $(build_dir)
+$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR)
+	cp -f $^ $(OUT_DIR)
 	$(foreach file,\
 		$^,\
 		$(if $(filter %.h,$(file)),\
 			,\
-			echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
+			echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;))
 
 #########################################################################################
 # import other necessary rules and variables
@@ -111,8 +111,8 @@ include $(base_dir)/common.mk
 # copy from other directory
 #########################################################################################
 all_vsrcs := \
-	$(sim_vsrcs) \
-	$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v
+	$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \
+	$(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v
 
 #########################################################################################
 # vivado rules