diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala
index 39f389f8..8b91c3ea 100644
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -43,13 +43,13 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
 
   // place all clocks in the shell
   require(dp(ClockInputOverlayKey).size >= 1)
-  val sys_clk_placed = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput())
+  val sysClkNode = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()).overlayOutput.node
 
   /*** Connect/Generate clocks ***/
 
   // connect to the PLL that will generate multiple clocks
   val harnessSysPLL = dp(PLLFactoryKey)()
-  harnessSysPLL := sys_clk_placed.overlayOutput.node
+  harnessSysPLL := sysClkNode
 
   // create and connect to the dutClock
   val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey))
@@ -73,7 +73,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
 
   /*** DDR ***/
 
-  val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL))
+  val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr
 
   // connect 1 mem. channel to the FPGA DDR
   val inParams = topDesign match { case td: ChipTop =>
@@ -82,7 +82,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
     }
   }
   val ddrClient = TLClientNode(Seq(inParams.master))
-  ddrPlaced.overlayOutput.ddr := ddrClient
+  ddrNode := ddrClient
 
   // module implementation
   override lazy val module = new VCU118FPGATestHarnessImp(this)
@@ -96,10 +96,10 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
   _outer.xdc.addPackagePin(reset, "L19")
   _outer.xdc.addIOStandard(reset, "LVCMOS12")
 
-  val reset_ibuf = Module(new IBUF)
-  reset_ibuf.io.I := reset
+  val resetIBUF = Module(new IBUF)
+  resetIBUF.io.I := reset
 
-  val sysclk: Clock = _outer.sys_clk_placed.overlayOutput.node.out.head._1.clock
+  val sysclk: Clock = _outer.sysClkNode.out.head._1.clock
 
   val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
   _outer.sdc.addAsyncPath(Seq(powerOnReset))
@@ -109,7 +109,7 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
     case _ => false.B
   }
 
-  _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset)
+  _outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset)
 
   // reset setup
   val hReset = Wire(Reset())
diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
index 0fd51108..95025dc7 100644
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -72,10 +72,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
 
   // use the 2nd system clock for the 2nd DDR
   val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput()))
-  val sys_clk2_placed = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput())
+  val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node
 
   val ddr2PLL = dp(PLLFactoryKey)()
-  ddr2PLL := sys_clk2_placed.overlayOutput.node
+  ddr2PLL := sysClk2Node
 
   val ddrClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey))
   val ddrWrangler = LazyModule(new ResetWrangler)
@@ -85,7 +85,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
   val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput()))
 
   val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth)))
-  val tsiDdrPlaced = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb))
+  val tsiDdrNode = dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(ddrWrangler.node, ddr2PLL, dp(PeripheryTSIHostKey).head, io_tsi_serial_bb)).overlayOutput.ddr
 
   // connect 1 mem. channel to the FPGA DDR
   val inTsiParams = topDesign match { case td: ChipTop =>
@@ -94,7 +94,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
     }
   }
   val tsiDdrClient = TLClientNode(Seq(inTsiParams.master))
-  (tsiDdrPlaced.overlayOutput.ddr
+  (tsiDdrNode
     := TLFragmenter(8,64,holdFirstDeny=true)
     := TLCacheCork()
     := TLAtomicAutomata(passthrough=false)