Merge branch 'local-fpga-temp' into local-fpga-support

generators/chipyard/src/main/scala/ChipTop.scala

@@ -7,7 +7,7 @@ import scala.collection.mutable.{ArrayBuffer}
 import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
 import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
 import freechips.rocketchip.config.{Parameters, Field}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import chipyard.iobinders._
 
@@ -23,7 +23,7 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters)
  * drive clock and reset generation
  */
 
-class ChipTop(implicit p: Parameters) extends LazyModule
+class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
     with HasTestHarnessFunctions with HasIOBinders {
   // The system module specified by BuildSystem
   lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -20,12 +20,16 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
   with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
   with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
+  with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI
+  with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
+  with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
   with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
   with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
   with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
   with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
   with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
   with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
+  with CanHaveMasterTLMemPort
 {
   override lazy val module = new DigitalTopModule(this)
 }
@@ -35,6 +39,48 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
   with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
   with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
   with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
+  with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
+  with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
+  with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
   with chipyard.example.CanHavePeripheryGCDModuleImp
   with freechips.rocketchip.util.DontTouch
 // DOC include end: DigitalTop
+
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+/** Adds a TileLink port to the system intended to master an MMIO device bus */
+trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
+  private val memPortParamsOpt = p(ExtMem)
+  private val portName = "tl_mem"
+  private val device = new MemoryDevice
+  private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
+
+  val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) =>
+    Seq.tabulate(nMemoryChannels) { channel =>
+      val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
+      val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
+
+      TLSlavePortParameters.v1(
+        managers = Seq(TLSlaveParameters.v1(
+          address            = base.flatMap(_.intersect(filter)),
+          resources          = device.reg,
+          regionType         = RegionType.UNCACHED, // cacheable
+          executable         = true,
+          supportsGet        = TransferSizes(1, mbus.blockBytes),
+          supportsPutFull    = TransferSizes(1, mbus.blockBytes),
+          supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
+        beatBytes = memPortParams.beatBytes)
+    }
+  }).toList.flatten)
+
+  mbus.coupleTo(s"memory_controller_port_named_$portName") {
+    (memTLNode
+      :*= TLBuffer()
+      :*= TLSourceShrinker(1 << idBits)
+      :*= TLWidthWidget(mbus.beatBytes)
+      :*= _)
+  }
+
+  val mem_tl = InModuleBody { memTLNode.makeIOs() }
+}

generators/chipyard/src/main/scala/System.scala

@@ -23,7 +23,6 @@ import freechips.rocketchip.util.{DontTouch}
  */
 class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
   with HasAsyncExtInterrupts
-  with CanHaveMasterAXI4MemPort
   with CanHaveMasterAXI4MMIOPort
   with CanHaveSlaveAXI4Port
 {

generators/utilities/src/main/scala/Simulator.scala

@@ -11,6 +11,7 @@ case class GenerateSimConfig(
 sealed trait Simulator
 object VerilatorSimulator extends Simulator
 object VCSSimulator extends Simulator
+object NotSimulator extends Simulator
 
 trait HasGenerateSimConfig {
   val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") {
@@ -22,15 +23,16 @@ trait HasGenerateSimConfig {
       .action((x, c) => x match {
         case "verilator" => c.copy(simulator = VerilatorSimulator)
         case "vcs" => c.copy(simulator = VCSSimulator)
+        case "none" => c.copy(simulator = NotSimulator)
         case _ => throw new Exception(s"Unrecognized simulator $x")
       })
-      .text("Name of simulator to generate files for (verilator, vcs)")
+      .text("Name of simulator to generate files for (verilator, vcs, none)")
 
     opt[String]("target-dir")
       .abbr("td")
       .valueName("<target-directory>")
       .action((x, c) => c.copy(targetDir = x))
-      .text("Target director to put files")
+      .text("Target directory to put files")
 
     opt[String]("dotFName")
       .abbr("df")
@@ -50,6 +52,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
         case VerilatorSimulator => s"-FI ${fname}"
         // vcs pulls headers in with +incdir, doesn't have anything like verilator.h
         case VCSSimulator => ""
+        case _ => ""
       }
     } else { // do nothing otherwise
       fname
@@ -95,15 +98,30 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
     "/csrc/remote_bitbang.h",
     "/csrc/remote_bitbang.cc",
     "/vsrc/EICG_wrapper.v",
-  ) ++ (sim match { // simulator specific files to include
-    case VerilatorSimulator => Seq(
-      "/csrc/emulator.cc",
-      "/csrc/verilator.h",
-    )
-    case VCSSimulator => Seq(
-      "/vsrc/TestDriver.v",
-    )
-  })
+    ) ++ (sim match {
+      case NotSimulator => Seq()
+      case _ => Seq(
+        "/testchipip/csrc/SimSerial.cc",
+        "/testchipip/csrc/SimDRAM.cc",
+        "/testchipip/csrc/mm.h",
+        "/testchipip/csrc/mm.cc",
+        "/testchipip/csrc/mm_dramsim2.h",
+        "/testchipip/csrc/mm_dramsim2.cc",
+        "/csrc/SimDTM.cc",
+        "/csrc/SimJTAG.cc",
+        "/csrc/remote_bitbang.h",
+        "/csrc/remote_bitbang.cc",
+      )
+    }) ++ (sim match { // simulator specific files to include
+      case VerilatorSimulator => Seq(
+        "/csrc/emulator.cc",
+        "/csrc/verilator.h",
+      )
+      case VCSSimulator => Seq(
+        "/vsrc/TestDriver.v",
+      )
+      case _ => Seq()
+    })
 
   def writeBootrom(): Unit = {
     firrtl.FileUtils.makeDirectory("./bootrom/")