diff --git a/generators/testchipip b/generators/testchipip
index efaa073f..e830ecf6 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit efaa073f5b7cd1d6e976a67591243b3d6298d0af
+Subproject commit e830ecf6ca591370ae818a6a8aa139d0676b801a
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index d48da28e..96f37237 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -60,7 +60,8 @@ SIM_FILE_REQS += \
 	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \
 	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \
 	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \
-	$(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \
+	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_dtm.cc \
+	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_dtm.h \
 	$(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \
 	$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \
 	$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc