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David Biancolin
2019-10-12 05:36:06 +00:00
parent 989332a6dc 5e7875f080
commit ca3eff022e
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docs/Tools/Chisel.rst
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Chisel
===========================
`Chisel <https://chisel.eecs.berkeley.edu/>`__ is an open-source hardware description language embedded in Scala.
`Chisel <https://chisel-lang.org/>`__ is an open-source hardware description language embedded in Scala.
It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM.
After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog.
@@ -16,4 +16,4 @@ However, if that passes, the output of the generator gives you an FIRRTL file an
See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog.
For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp <https://github.com/freechipsproject/chisel-bootcamp>`__.
Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel.eecs.berkeley.edu/>`__.
Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel-lang.org/>`__.

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docs/Tools/FIRRTL.rst
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An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
Once the transformations are done, a Verilog file is emitted and the build process is done.
For more information on please visit their `website <https://freechipsproject.github.io/firrtl/>`__.
For more information on please visit their `website <https://chisel-lang.org/firrtl/>`__.