From cd48271b5314d0605bea01223a3f97b091ef63b8 Mon Sep 17 00:00:00 2001
From: abejgonzalez <abe.j.gonza@gmail.com>
Date: Thu, 1 Aug 2019 22:33:21 -0700
Subject: [PATCH] Added DTM docs | bumped BOOM

---
 docs/Advanced-Usage/DTM-Debugging.rst | 48 +++++++++++++++++++++++++++
 docs/Advanced-Usage/index.rst         |  1 +
 generators/boom                       |  2 +-
 3 files changed, 50 insertions(+), 1 deletion(-)
 create mode 100644 docs/Advanced-Usage/DTM-Debugging.rst

diff --git a/docs/Advanced-Usage/DTM-Debugging.rst b/docs/Advanced-Usage/DTM-Debugging.rst
new file mode 100644
index 00000000..953e9cbd
--- /dev/null
+++ b/docs/Advanced-Usage/DTM-Debugging.rst
@@ -0,0 +1,48 @@
+Debugging with DTM/JTAG
+===============================
+
+By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core.
+Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation).
+However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system.
+
+Creating a DTM/JTAG Config
+-------------------------------------------
+
+First, a DTM config must be created for the system that you want to create.
+This involves specifying the SoC top-level to add a DTM as well as configuring that DTM to use JTAG.
+
+.. code-block:: scala
+
+    class DTMBoomConfig extends Config(
+      new WithDTMBoomRocketTop ++
+      new WithBootROM ++
+      new WithJtagDTM ++
+      new boom.common.SmallBoomConfig)
+
+In this example, the ``WithDTMBoomRocketTop`` mixin specifies that the top-level SoC will instantiate a DTM.
+The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup).
+The rest of the mixins specify the rest of the system (cores, accelerators, etc).
+
+Starting the DTM Simulation
+-------------------------------------------
+
+After creating the config, call the ``make`` command like the following:
+
+.. code-block:: bash
+
+    cd sims/verilator
+    # or
+    cd sims/vcs
+
+    make CONFIG=DTMBoomConfig TOP=BoomRocketTopWithDTM MODEL=TestHarnessWithDTM
+
+In this example, this will use the config that you previously specified, as well as set the other parameters that are needed to satisfy the build system.
+After that point, you should have a JTAG enabled simulation that you can attach to using OpenOCD and GDB!
+
+Debugging with JTAG
+-------------------------------------------------------
+
+Please refer to the following resources on how to debug with JTAG.
+
+* https://github.com/chipsalliance/rocket-chip#-debugging-with-gdb
+* https://github.com/riscv/riscv-isa-sim#debugging-with-gdb
diff --git a/docs/Advanced-Usage/index.rst b/docs/Advanced-Usage/index.rst
index 62dd11aa..1f313e60 100644
--- a/docs/Advanced-Usage/index.rst
+++ b/docs/Advanced-Usage/index.rst
@@ -9,3 +9,4 @@ They expect you to know about Chisel, Parameters, Configs, etc.
    :caption: Getting Started:
 
    Heterogeneous-SoCs
+   DTM-Debugging
diff --git a/generators/boom b/generators/boom
index 3a06403d..609cf36e 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 3a06403df71d46f2c42f9baac134a3b2997595e5
+Subproject commit 609cf36eea7da73aad9f7abf379320615ae7e554