From 8c28f03ba188dba9fe9c58d66469e8987349c75f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 13 Oct 2019 14:08:05 -0400 Subject: [PATCH 1/7] [FireChip] Remove by3 clock division FASED config --- generators/firechip/src/main/scala/TargetConfigs.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 27af7548..9839c14f 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -89,7 +89,6 @@ class WithScalaTestFeatures extends Config((site, here, up) => { // FASED Config Aliases. This to enable config generation via "_" concatenation // which requires that all config classes be defined in the same package class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB -class DDR3FRFCFSLLC4MB3Div extends FRFCFS16GBQuadRankLLC4MB3Div // L2 Config Aliases. For use with "_" concatenation class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache From 2e5f29031e75e82440c9a816feeb0c738d3aff8f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 13 Oct 2019 14:08:48 -0400 Subject: [PATCH 2/7] [CI] Remove clock-division based FC tests --- .circleci/config.yml | 56 ------------------------------------------- .circleci/defaults.sh | 1 - 2 files changed, 57 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 3f7b35c6..01bd8e9d 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -346,35 +346,6 @@ jobs: key: fireboom-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - prepare-firesim-clockdiv: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb - steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building FireSim MIDAS simulator using Verilator - command: .circleci/do-firesim-build.sh firesim-clockdiv - no_output_timeout: 120m - - save_cache: - key: firesim-clockdiv-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" midasexamples-run-tests: docker: - image: riscvboom/riscvboom-images:0.0.12 @@ -571,33 +542,6 @@ jobs: name: Run FireSim tests command: .circleci/run-firesim-tests.sh fireboom no_output_timeout: 20m - firesim-clockdiv-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb - steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - firesim-clockdiv-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - extra-tests-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run FireSim tests - command: .circleci/run-firesim-tests.sh firesim-clockdiv # Order and dependencies of jobs to run diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 855ca4a5..884592f1 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -49,4 +49,3 @@ mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketCo mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha" mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config" -mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" From 46289ec284abf75efa3df186b69ae57b1dad386b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 13 Oct 2019 14:16:04 -0400 Subject: [PATCH 3/7] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 7f36976c..afad1b6a 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7f36976cde51309834851ff4f246a2fe007ce324 +Subproject commit afad1b6accfaba5efbc0cfeea66372abae5ab2eb From 84611fed8aa463b2d62bdca44b26bd35a61b2cfd Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 13 Oct 2019 15:22:49 -0700 Subject: [PATCH 4/7] [CI] Completely remove the clockdiv tests --- .circleci/config.yml | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 01bd8e9d..e1738732 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -615,11 +615,6 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-firesim-clockdiv: - requires: - - install-riscv-toolchain - - install-verilator - # Run the respective tests # Run midasexamples test @@ -659,8 +654,3 @@ workflows: requires: - prepare-fireboom - build-extra-tests - - - firesim-clockdiv-run-tests: - requires: - - prepare-firesim-clockdiv - - build-extra-tests From 7e908b4964fb3b085b35676bfb2b90529fe54e7a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 14 Oct 2019 13:27:58 -0700 Subject: [PATCH 5/7] update ci to exit at the end instead of partway through | fix flattened toolchain repos --- .circleci/check-commit.sh | 47 ++++++++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 18a7b649..3183d07c 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -21,29 +21,66 @@ git config submodule.vlsi/hammer-synopsys-plugins.update none git submodule update --init status=$(git submodule status) +all_names=() + search () { for submodule in "${submodules[@]}" do echo "Running check on submodule $submodule in $dir" - hash=$(echo "$status" | grep $submodule | awk '{print$1}' | grep -o "[[:alnum:]]*") - echo "Searching for $hash in origin/master of $submodule" - git -C $dir/$submodule branch -r --contains "$hash" | grep "origin/master" # needs init'ed submodules + hash=$(echo "$status" | grep "$dir.*$submodule " | awk '{print$1}' | grep -o "[[:alnum:]]*") + echo "Searching for $hash in origin/$branch of $submodule" + (git -C $dir/$submodule branch -r --contains "$hash" | grep "origin/$branch") && true # needs init'ed submodules + all_names+=("$dir/$submodule $hash $?") done } submodules=("boom" "hwacha" "icenet" "rocket-chip" "sifive-blocks" "sifive-cache" "testchipip") dir="generators" +branch="master" search -submodules=("esp-tools" "riscv-tools") -dir="toolchains" +submodules=("riscv-gnu-toolchain" "riscv-isa-sim" "riscv-pk" "riscv-tests") +dir="toolchains/esp-tools" +branch="master" + +search + + +submodules=("riscv-gnu-toolchain" "riscv-isa-sim" "riscv-pk" "riscv-tests" "riscv-gnu-toolchain-prebuilt") +dir="toolchains/riscv-tools" +branch="master" + +search + +# riscv-openocd doesn't use its master branch +submodules=("riscv-openocd") +dir="toolchains/riscv-tools" +branch="riscv" search submodules=("barstools" "chisel3" "firrtl" "torture") dir="tools" +branch="master" search +# turn off verbose printing to make this easier to read +set +x + +# print all result strings +for str in "${all_names[@]}"; +do + echo "$str" +done + +# check if there was a non-zero return code +for str in "${all_names[@]}"; +do + if [ ! 0 = $(echo "$str" | awk '{print$3}') ]; then + exit 1 + fi +done + echo "Done checking all submodules" From f0fa623000668fd2e8d9354921fa6117151497bd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 15 Oct 2019 10:31:09 -0700 Subject: [PATCH 6/7] also check firesim --- .circleci/check-commit.sh | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 3183d07c..ad7be185 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -66,6 +66,12 @@ branch="master" search +submodules=("firesim") +dir="sims" +branch="master" + +search + # turn off verbose printing to make this easier to read set +x From c87b69fcbf1bcd799192e6b773d0faa39775de6e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 15 Oct 2019 21:14:27 -0700 Subject: [PATCH 7/7] fix spacing in init-submodules-no-riscv-tools.sh --- scripts/init-submodules-no-riscv-tools.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 0ce30475..d8842050 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -50,7 +50,7 @@ git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update if [ $NO_FIRESIM = false ]; then -echo "initializing firesim" + echo "initializing firesim" # Renable firesim and init only the required submodules to provide # all required scala deps, without doing a full build-setup git config --unset submodule.sims/firesim.update