diff --git a/.circleci/README.md b/.circleci/README.md
index 83fd3264..a50fc44a 100644
--- a/.circleci/README.md
+++ b/.circleci/README.md
@@ -16,9 +16,8 @@ For example:
     - prepare-rocketchip:
         requires:
             - install-riscv-toolchain
-            - install-verilator
 
-This specifies that the `prepare-rocketchip` job needs the `install-riscv-toolchain` and `install-verilator` steps to run before it can run.
+This specifies that the `prepare-rocketchip` job needs the `install-riscv-toolchain` steps to run before it can run.
 
 All jobs in the CI workflow are specified at the top of `config.yml`
 They specify a docker image to use (in this case a riscv-boom image since that is already available and works nicely) and an environment.
@@ -36,7 +35,6 @@ This directory contains all the collateral for the Chipyard CI to work.
 The following is included:
 
     `build-toolchains.sh` # build either riscv-tools or esp-tools
-    `build-verilator.sh`  # build verilator (remotely)
     `create-hash.sh`      # create hashes of riscv-tools/esp-tools so circleci caching can work
     `do-rtl-build.sh`     # use verilator to build a sim executable (remotely)
     `config.yml`          # main circleci config script to enumerate jobs/workflows
@@ -48,11 +46,10 @@ How things are setup for Chipyard
 The steps for CI to run are as follows.
 1st, build the toolchains in parallel (note: `esp-tools` is currently not used in the run).
 The docker image sets up the `PATH` and `RISCV` variable so that `riscv-tools` is the default (currently the `env.sh` script that is created at tool build is unused).
-2nd, install verilator using the `*.mk` to cache unique versions of verilator (mainly for if verilator is bumped).
-3rd, create the simulator binary.
+2nd, create the simulator binary.
 This requires the `riscv-tools` for `fesvr` and `verilator` to be able to build the binary.
 This stores all collateral for the tests (srcs, generated-srcs, sim binary, etc) to run "out of the gate" in the next job (make needs everything or else it will run again).
-4th, finally run the tests that were wanted.
+3rd, finally run the desired tests.
 
 Other CI Setup
 --------------
diff --git a/.circleci/build-verilator.sh b/.circleci/build-verilator.sh
deleted file mode 100755
index a6780d1c..00000000
--- a/.circleci/build-verilator.sh
+++ /dev/null
@@ -1,35 +0,0 @@
-#!/bin/bash
-
-# build verilator
-
-# turn echo on and error on earliest command
-set -ex
-
-# get shared variables
-SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
-source $SCRIPT_DIR/defaults.sh
-
-# call clean on exit
-trap clean EXIT
-
-run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR
-
-if [ ! -d "$LOCAL_VERILATOR_DIR" ]; then
-    # set stricthostkeychecking to no (must happen before rsync)
-    run "echo \"Ping $SERVER\""
-
-    clean
-
-    run "mkdir -p $REMOTE_CHIPYARD_DIR"
-    copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR
-
-    run "make -j$NPROC -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR verilator_install"
-
-    # copy so that circleci can cache
-    mkdir -p $LOCAL_CHIPYARD_DIR
-    mkdir -p $LOCAL_VERILATOR_DIR
-    copy $SERVER:$REMOTE_CHIPYARD_DIR/  $LOCAL_CHIPYARD_DIR
-    copy $SERVER:$REMOTE_VERILATOR_DIR/ $LOCAL_VERILATOR_DIR
-
-    cp -r $LOCAL_VERILATOR_DIR/install/bin/* $LOCAL_VERILATOR_DIR/install/share/verilator/bin/.
-fi
diff --git a/.circleci/config.yml b/.circleci/config.yml
index a1e67f18..5fdc774d 100644
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -4,9 +4,6 @@
 version: 2.1
 
 parameters:
-    verilator-cache-version:
-        type: string
-        default: "v3"
     tools-cache-version:
         type: string
         default: "v4"
@@ -15,7 +12,7 @@ parameters:
 executors:
     main-env:
         docker:
-            - image: riscvboom/riscvboom-images:0.0.12
+            - image: riscvboom/riscvboom-images:0.0.13
         environment:
             JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
 
@@ -54,8 +51,8 @@ commands:
                     - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e"
             - checkout
 
-    setup-tools-verilator:
-        description: "Get toolchain and verilator"
+    setup-tools:
+        description: "Get toolchain"
         parameters:
             tools-version:
                 type: string
@@ -69,9 +66,6 @@ commands:
             - restore_cache:
                 keys:
                     - << parameters.tools-version >>-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../<< parameters.tools-version >>.hash" }}
-            - restore_cache:
-                keys:
-                    - verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }}
 
     prepare-rtl:
         description: "Run the prepare step of RTL"
@@ -88,7 +82,7 @@ commands:
                 type: string
                 default: "do-rtl-build.sh"
         steps:
-            - setup-tools-verilator:
+            - setup-tools:
                 tools-version: "<< parameters.tools-version >>"
             - run:
                 name: Building << parameters.project-key >> subproject using Verilator
@@ -117,7 +111,7 @@ commands:
                 type: string
                 default: "10m"
         steps:
-            - setup-tools-verilator:
+            - setup-tools:
                 tools-version: "<< parameters.tools-version >>"
             - restore_cache:
                 keys:
@@ -166,18 +160,10 @@ jobs:
         executor: main-env
         steps:
             - ssh-checkout
-            - restore_cache:
-                keys:
-                    - verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }}
             - run:
-                name: Build Verilator
+                name: Install Verilator to remote
                 command: |
-                    .circleci/build-verilator.sh
-                no_output_timeout: 120m
-            - save_cache:
-                key: verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }}
-                paths:
-                    - "/home/riscvuser/verilator"
+                    .circleci/install-verilator.sh
     build-extra-tests:
         executor: main-env
         steps:
@@ -262,9 +248,11 @@ jobs:
             - prepare-rtl:
                 project-key: "fireboom"
                 build-script: "do-firesim-build.sh"
-
-
-
+    prepare-chipyard-ariane:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                project-key: "chipyard-ariane"
     chipyard-rocket-run-tests:
         executor: main-env
         steps:
@@ -327,14 +315,19 @@ jobs:
                 project-key: "fireboom"
                 run-script: "run-firesim-tests.sh"
                 timeout: "30m"
-
     midasexamples-run-tests:
         executor: main-env
         steps:
-            - setup-tools-verilator
+            - setup-tools
             - run:
                 name: Run midasexamples tests
                 command: .circleci/run-midasexamples-tests.sh
+    chipyard-ariane-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                project-key: "chipyard-ariane"
+
 # Order and dependencies of jobs to run
 workflows:
     version: 2
@@ -357,7 +350,6 @@ workflows:
 
             - install-esp-toolchain
 
-            # Build verilator
             - install-verilator
 
             - commit-on-master-check
@@ -431,13 +423,17 @@ workflows:
                     - install-riscv-toolchain
                     - install-verilator
 
+            - prepare-chipyard-ariane:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
             # Run the respective tests
 
             # Run midasexamples test
             - midasexamples-run-tests:
                 requires:
                     - install-riscv-toolchain
-                    - install-verilator
 
             # Run the example tests
             - chipyard-rocket-run-tests:
@@ -486,3 +482,7 @@ workflows:
                 requires:
                     - prepare-fireboom
                     - build-extra-tests
+
+            - chipyard-ariane-run-tests:
+                requires:
+                    - prepare-chipyard-ariane
diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh
index 7fa7c68c..552ac1db 100755
--- a/.circleci/defaults.sh
+++ b/.circleci/defaults.sh
@@ -20,22 +20,24 @@ clean () {
 # make parallelism
 NPROC=8
 
+# verilator version
+VERILATOR_VERSION=v4.028
+
 # remote variables
 REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB
 REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install
 REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install
 REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard
-REMOTE_VERILATOR_DIR=$REMOTE_WORK_DIR/verilator
 REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator
 REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim
 REMOTE_JAVA_ARGS="-Xmx8G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
+REMOTE_VERILATOR_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-verilator-install
 
 # local variables (aka within the docker container)
 LOCAL_CHECKOUT_DIR=$HOME/project
 LOCAL_RISCV_DIR=$HOME/riscv-tools-install
 LOCAL_ESP_DIR=$HOME/esp-tools-install
 LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR
-LOCAL_VERILATOR_DIR=$HOME/verilator
 LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator
 LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
 
@@ -53,3 +55,5 @@ mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP
 mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem"
 mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig PLATFORM_CONFIG=BaseF1Config"
 mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig PLATFORM_CONFIG=BaseF1Config"
+mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig"
+mapping["fireariane"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig PLATFORM_CONFIG=BaseF1Config"
diff --git a/.circleci/do-firesim-build.sh b/.circleci/do-firesim-build.sh
index 709f3d0b..7d86c779 100755
--- a/.circleci/do-firesim-build.sh
+++ b/.circleci/do-firesim-build.sh
@@ -28,18 +28,15 @@ run "echo \"Ping $SERVER\""
 
 clean
 
-# copy over riscv/esp-tools, verilator, and chipyard to remote
+# copy over riscv/esp-tools, and chipyard to remote
 run "mkdir -p $REMOTE_CHIPYARD_DIR"
-run "mkdir -p $REMOTE_VERILATOR_DIR"
 copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR
-copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR
 
 run "cp -r ~/.ivy2 $REMOTE_WORK_DIR"
 run "cp -r ~/.sbt  $REMOTE_WORK_DIR"
 
 TOOLS_DIR=$REMOTE_RISCV_DIR
 LD_LIB_DIR=$REMOTE_RISCV_DIR/lib
-VERILATOR_BIN_DIR=$REMOTE_VERILATOR_DIR/install/bin
 
 if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then
     TOOLS_DIR=$REMOTE_ESP_DIR
@@ -54,9 +51,11 @@ fi
 # Build MIDAS-level verilator sim
 FIRESIM_VARS="${mapping[$1]}"
 run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean"
-run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
-     export PATH=\"$VERILATOR_BIN_DIR:\$PATH\"; export FIRESIM_ENV_SOURCED=1; \
-     export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; \
+run "export RISCV=\"$TOOLS_DIR\"; \
+     export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
+     export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
+     export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
+     export FIRESIM_ENV_SOURCED=1; \
      make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" $FIRESIM_VARS verilator"
 run "rm -rf $REMOTE_CHIPYARD_DIR/project"
 
diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh
index 5276080f..52c920f5 100755
--- a/.circleci/do-rtl-build.sh
+++ b/.circleci/do-rtl-build.sh
@@ -21,11 +21,9 @@ run "echo \"Ping $SERVER\""
 
 clean
 
-# copy over riscv/esp-tools, verilator, and chipyard to remote
+# copy over riscv/esp-tools, and chipyard to remote
 run "mkdir -p $REMOTE_CHIPYARD_DIR"
-run "mkdir -p $REMOTE_VERILATOR_DIR"
 copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR
-copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR
 
 run "cp -r ~/.ivy2 $REMOTE_WORK_DIR"
 run "cp -r ~/.sbt  $REMOTE_WORK_DIR"
@@ -56,9 +54,11 @@ fi
 
 # enter the verilator directory and build the specific config on remote server
 run "make -C $REMOTE_SIM_DIR clean"
-run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
-     export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; \
-     make -j$NPROC -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}"
+run "export RISCV=\"$TOOLS_DIR\"; \
+     export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
+     export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
+     export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
+     make -j$NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}"
 run "rm -rf $REMOTE_CHIPYARD_DIR/project"
 
 # copy back the final build
diff --git a/.circleci/install-verilator.sh b/.circleci/install-verilator.sh
new file mode 100755
index 00000000..86d1ae04
--- /dev/null
+++ b/.circleci/install-verilator.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+# move verilator to the remote server
+
+# turn echo on and error on earliest command
+set -ex
+
+# get shared variables
+SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
+source $SCRIPT_DIR/defaults.sh
+
+run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR
+
+# set stricthostkeychecking to no (must happen before rsync)
+run "echo \"Ping $SERVER\""
+
+run "git clone http://git.veripool.org/git/verilator $REMOTE_VERILATOR_DIR; \
+     cd $REMOTE_VERILATOR_DIR; \
+     git checkout $VERILATOR_VERSION; \
+     autoconf; \
+     export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR; \
+     ./configure; \
+     make -j$NPROC;"
diff --git a/.circleci/run-firesim-tests.sh b/.circleci/run-firesim-tests.sh
index 8cdf9e81..d1111e60 100755
--- a/.circleci/run-firesim-tests.sh
+++ b/.circleci/run-firesim-tests.sh
@@ -7,7 +7,6 @@ set -ex
 SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
 source $SCRIPT_DIR/defaults.sh
 
-export PATH=$LOCAL_VERILATOR_DIR/install/bin:$PATH
 export FIRESIM_ENV_SOURCED=1
 
 SIMULATION_ARGS="${mapping[$1]}"
diff --git a/.circleci/run-midasexamples-tests.sh b/.circleci/run-midasexamples-tests.sh
index 7d31ac11..467dc0e9 100755
--- a/.circleci/run-midasexamples-tests.sh
+++ b/.circleci/run-midasexamples-tests.sh
@@ -19,13 +19,11 @@ run "echo \"Ping $SERVER\""
 
 clean
 
-# copy over riscv-tools, verilator, and chipyard to remote
+# copy over riscv-tools, and chipyard to remote
 run "mkdir -p $REMOTE_CHIPYARD_DIR"
-run "mkdir -p $REMOTE_VERILATOR_DIR"
 run "mkdir -p $REMOTE_RISCV_DIR"
 
 copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR
-copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR
 copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR
 
 # Copy ivy2 and sbt directories
@@ -35,12 +33,13 @@ run "cp -r ~/.sbt  $REMOTE_WORK_DIR"
 
 TOOLS_DIR=$REMOTE_RISCV_DIR
 LD_LIB_DIR=$REMOTE_RISCV_DIR/lib
-VERILATOR_BIN_DIR=$REMOTE_VERILATOR_DIR/install/bin
 
 # Run midasexamples test
 
 run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean"
-run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
-     export PATH=\"$VERILATOR_BIN_DIR:\$PATH\"; export FIRESIM_ENV_SOURCED=1; \
-     export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; \
+run "export RISCV=\"$TOOLS_DIR\"; \
+     export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
+     export FIRESIM_ENV_SOURCED=1; \
+     export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
+     export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
      make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" TARGET_PROJECT=midasexamples test"
diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh
index ac63ff15..480908c9 100755
--- a/.circleci/run-tests.sh
+++ b/.circleci/run-tests.sh
@@ -9,14 +9,12 @@ set -ex
 SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
 source $SCRIPT_DIR/defaults.sh
 
-export VERILATOR_ROOT=$LOCAL_VERILATOR_DIR/install/share/verilator
-
 run_bmark () {
-    make run-bmark-tests-fast -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@
+    make run-bmark-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@
 }
 
 run_asm () {
-    make run-asm-tests-fast -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@
+    make run-asm-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@
 }
 
 run_both () {
@@ -25,7 +23,7 @@ run_both () {
 }
 
 run_tracegen () {
-    make tracegen -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@
+    make tracegen -C $LOCAL_SIM_DIR $@
 }
 
 # TODO BUG: the run-binary command forces a rebuild of the simulator in CI
@@ -47,7 +45,7 @@ case $1 in
         export RISCV=$LOCAL_ESP_DIR
         export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib
         export PATH=$RISCV/bin:$PATH
-        make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]}
+        make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR ${mapping[$1]}
         ;;
     chipyard-gemmini)
         export RISCV=$LOCAL_ESP_DIR
@@ -70,6 +68,9 @@ case $1 in
     tracegen-boom)
         run_tracegen ${mapping[$1]}
         ;;
+    chipyard-ariane)
+        make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
+        ;;
     *)
         echo "No set of tests for $1. Did you spell it right?"
         exit 1
diff --git a/.gitmodules b/.gitmodules
index 88096baf..34846d61 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -113,6 +113,9 @@
 [submodule "software/firemarshal"]
 	path = software/firemarshal
 	url = https://github.com/firesim/FireMarshal.git
+[submodule "generators/ariane"]
+	path = generators/ariane
+	url = https://github.com/ucb-bar/ariane-wrapper.git
 [submodule "tools/DRAMSim2"]
 	path = tools/DRAMSim2
 	url = https://github.com/firesim/DRAMSim2.git
diff --git a/README.md b/README.md
index 26f32cf5..0eec2d87 100644
--- a/README.md
+++ b/README.md
@@ -10,14 +10,14 @@ To get started using Chipyard, see the documentation on the Chipyard documentati
 
 Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
 It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
-Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom]), accelerators ([Hwacha][hwacha]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
+Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
 Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
 Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
 
 ## Resources
 
 * Chipyard Documentation: https://chipyard.readthedocs.io/
-* Chipyard Basics slides: https://fires.im/micro19-slides-pdf/02_chipyard_basics.pdf 
+* Chipyard Basics slides: https://fires.im/micro19-slides-pdf/02_chipyard_basics.pdf
 * Chipyard Tutorial Exercise slides: https://fires.im/micro19-slides-pdf/03_building_custom_socs.pdf
 
 ## Need help?
@@ -63,3 +63,4 @@ These publications cover many of the internal components used in Chipyard. Howev
 [rocket-chip]: https://github.com/freechipsproject/rocket-chip
 [boom]: https://github.com/ucb-bar/riscv-boom
 [firemarshal]: https://github.com/firesim/FireMarshal/
+[ariane]: https://github.com/pulp-platform/ariane/
diff --git a/build.sbt b/build.sbt
index 52fc3cb5..a633066f 100644
--- a/build.sbt
+++ b/build.sbt
@@ -125,7 +125,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
 lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
   .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
-    gemmini, icenet, tracegen)
+    gemmini, icenet, tracegen, ariane)
   .settings(commonSettings)
 
 lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
@@ -147,6 +147,10 @@ lazy val boom = (project in file("generators/boom"))
   .dependsOn(rocketchip)
   .settings(commonSettings)
 
+lazy val ariane = (project in file("generators/ariane"))
+  .dependsOn(rocketchip)
+  .settings(commonSettings)
+
 lazy val sha3 = (project in file("generators/sha3"))
   .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
   .settings(commonSettings)
@@ -196,12 +200,9 @@ lazy val sifive_cache = (project in file("generators/sifive-cache")).settings(
 lazy val midas      = ProjectRef(firesimDir, "midas")
 lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
 
-lazy val firechip = (project in file("generators/firechip"))
-  .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache,
-    sha3, // On separate line to allow for cleaner tutorial-setup patches
-    utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
+lazy val firechip = conditionalDependsOn(project in file("generators/firechip"))
+  .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
   .settings(
     commonSettings,
     testGrouping in Test := isolateAllTests( (definedTests in Test).value )
   )
-
diff --git a/common.mk b/common.mk
index 839e7b54..bf40e602 100644
--- a/common.mk
+++ b/common.mk
@@ -6,10 +6,12 @@ SHELL=/bin/bash
 #########################################################################################
 # variables to get all *.scala files
 #########################################################################################
-lookup_scala_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.scala" -print 2> /dev/null)
+lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null)
 
-SOURCE_DIRS=$(addprefix $(base_dir)/,generators sims/firesim/sim)
-SCALA_SOURCES=$(call lookup_scala_srcs,$(SOURCE_DIRS))
+SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim)
+SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala)
+VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v)
+ARIANE_VLOG_SOURCES = $(call lookup_srcs,$(base_dir)/generators/ariane,sv) $(call lookup_srcs,$(base_dir)/generators/ariane,v)
 
 #########################################################################################
 # rocket and testchipip classes
@@ -42,7 +44,8 @@ $(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main
 $(FIRRTL_FILE) $(ANNO_FILE): generator_temp
 	@echo "" > /dev/null
 
-generator_temp: $(SCALA_SOURCES) $(sim_files)
+# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile
+generator_temp: $(SCALA_SOURCES) $(ARIANE_VLOG_SOURCES) $(sim_files)
 	mkdir -p $(build_dir)
 	cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)"
 
@@ -64,7 +67,7 @@ HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNES
 $(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp
 	@echo "" > /dev/null
 
-firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE)
+firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
 	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTopAndHarness -o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)" && touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
 # DOC include end: FirrtlCompiler
 
@@ -89,7 +92,7 @@ harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp
 # remove duplicate files and headers in list of simulation file inputs
 ########################################################################################
 $(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes)
-	awk '{print $1;}' $^ | sort -u | grep -v '.*\.h$$' > $@
+	awk '{print $1;}' $^ | sort -u | grep -v '.*\.\(svh\|h\)$$' > $@
 
 #########################################################################################
 # helper rule to just make verilog files
diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst
index cbca299f..d3ec9a95 100644
--- a/docs/Chipyard-Basics/Chipyard-Components.rst
+++ b/docs/Chipyard-Basics/Chipyard-Components.rst
@@ -20,6 +20,10 @@ Processor Cores
   An out-of-order RISC-V core.
   See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information.
 
+**Ariane Core**
+  An in-order RISC-V core written in System Verilog.
+  See :ref:`Ariane Core` for more information.
+
 Accelerators
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
diff --git a/docs/Generators/Ariane.rst b/docs/Generators/Ariane.rst
new file mode 100644
index 00000000..e58f9dfc
--- /dev/null
+++ b/docs/Generators/Ariane.rst
@@ -0,0 +1,14 @@
+Ariane Core
+====================================
+
+`Ariane <https://github.com/pulp-platform/ariane>`__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
+The `Ariane core` is wrapped in an `Ariane tile` so it can be used as a component within the `Rocket Chip SoC generator`.
+The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
+
+.. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface).
+
+While the core itself is not a generator, we expose the same parameterization that the Ariane core provides (i.e. change branch prediction parameters).
+
+.. Warning::  This target does not support Verilator simulation at this time. Please use VCS.
+
+For more information, please refer to the `GitHub repository <https://github.com/pulp-platform/ariane>`__.
diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst
index 90db4ae8..675318d9 100644
--- a/docs/Generators/index.rst
+++ b/docs/Generators/index.rst
@@ -27,4 +27,5 @@ so changes to the generators themselves will automatically be used when building
    TestChipIP
    SiFive-Generators
    SHA3
+   Ariane
 
diff --git a/generators/ariane b/generators/ariane
new file mode 160000
index 00000000..145b5ed1
--- /dev/null
+++ b/generators/ariane
@@ -0,0 +1 @@
+Subproject commit 145b5ed106efd0b22c2105c20722ab303fa4039b
diff --git a/generators/chipyard/src/main/scala/ArianeConfigs.scala b/generators/chipyard/src/main/scala/ArianeConfigs.scala
new file mode 100644
index 00000000..e0cb771e
--- /dev/null
+++ b/generators/chipyard/src/main/scala/ArianeConfigs.scala
@@ -0,0 +1,42 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// Ariane Configs
+// ---------------------
+
+class ArianeConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.iobinders.WithSimAXIMem ++                        // drive the master AXI4 memory with a SimAXIMem
+  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
+  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
+  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new chipyard.config.WithNoGPIO ++                              // no top-level GPIO pins (overrides default set in sifive-blocks)
+  new chipyard.config.WithBootROM ++                             // use default bootrom
+  new chipyard.config.WithUART ++                                // add a UART
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+  new ariane.WithNArianeCores(1) ++                              // single Ariane core
+  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
+
+class dmiArianeConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithTiedOffSerial ++
+  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new ariane.WithNArianeCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
diff --git a/generators/chipyard/src/main/scala/Generator.scala b/generators/chipyard/src/main/scala/Generator.scala
index 32619f29..4baba357 100644
--- a/generators/chipyard/src/main/scala/Generator.scala
+++ b/generators/chipyard/src/main/scala/Generator.scala
@@ -14,6 +14,7 @@ object Generator extends GeneratorApp {
     implicit val p: Parameters = params
     TestSuiteHelper.addRocketTestSuites
     TestSuiteHelper.addBoomTestSuites
+    TestSuiteHelper.addArianeTestSuites
 
     // if hwacha parameter exists then generate its tests
     // TODO: find a more elegant way to do this. either through
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index d8635cd5..96443a9f 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -22,24 +22,26 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.amba.axi4._
 
 import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
+import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
 
-
-trait HasBoomAndRocketTiles extends HasTiles
+trait HasChipyardTiles extends HasTiles
   with CanHavePeripheryPLIC
   with CanHavePeripheryCLINT
   with HasPeripheryDebug
 { this: BaseSubsystem =>
 
-  val module: HasBoomAndRocketTilesModuleImp
+  val module: HasChipyardTilesModuleImp
 
   protected val rocketTileParams = p(RocketTilesKey)
   protected val boomTileParams = p(BoomTilesKey)
+  protected val arianeTileParams = p(ArianeTilesKey)
 
   // crossing can either be per tile or global (aka only 1 crossing specified)
   private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
   private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
+  private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size)
 
-  val allTilesInfo = (rocketTileParams ++ boomTileParams) zip (rocketCrossings ++ boomCrossings)
+  val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings)
 
   // Make a tile and wire its nodes into the system,
   // according to the specified type of clock crossing.
@@ -59,6 +61,10 @@ trait HasBoomAndRocketTiles extends HasTiles
           val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
           (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
         }
+        case a: ArianeTileParams => {
+          val t = LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
+          (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
+        }
       }
       connectMasterPortsToSBus(tile, crossing)
       connectSlavePortsToCBus(tile, crossing)
@@ -79,14 +85,14 @@ trait HasBoomAndRocketTiles extends HasTiles
   }.toList
 }
 
-trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
+trait HasChipyardTilesModuleImp extends HasTilesModuleImp
   with HasPeripheryDebugModuleImp
 {
-  val outer: HasBoomAndRocketTiles
+  val outer: HasChipyardTiles
 }
 
 class Subsystem(implicit p: Parameters) extends BaseSubsystem
-  with HasBoomAndRocketTiles
+  with HasChipyardTiles
 {
   override lazy val module = new SubsystemModuleImp(this)
 
@@ -95,7 +101,7 @@ class Subsystem(implicit p: Parameters) extends BaseSubsystem
 
 class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
   with HasResetVectorWire
-  with HasBoomAndRocketTilesModuleImp
+  with HasChipyardTilesModuleImp
 {
   tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
     wire.hartid := i.U
diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala
index 05c4bf6e..7d901c62 100644
--- a/generators/chipyard/src/main/scala/TestSuites.scala
+++ b/generators/chipyard/src/main/scala/TestSuites.scala
@@ -9,6 +9,7 @@ import freechips.rocketchip.util.{GeneratorApp}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
 
 import boom.common.{BoomTilesKey}
+import ariane.{ArianeTilesKey}
 
 /**
  * A set of pre-chosen regression tests
@@ -139,4 +140,44 @@ object TestSuiteHelper
       TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
     }
   }
+
+  /**
+  * Add Ariane tests (asm, bmark, regression)
+  */
+  def addArianeTestSuites(implicit p: Parameters) = {
+    val xlen = p(XLen)
+    p(ArianeTilesKey).find(_.hartId == 0).map { tileParams =>
+      val coreParams = tileParams.core
+      val vm = coreParams.useVM
+      val env = if (vm) List("p","v") else List("p")
+      coreParams.fpu foreach { case cfg =>
+        if (xlen == 32) {
+          TestGeneration.addSuites(env.map(rv32uf))
+          if (cfg.fLen >= 64)
+            TestGeneration.addSuites(env.map(rv32ud))
+        } else {
+          TestGeneration.addSuite(rv32udBenchmarks)
+          TestGeneration.addSuites(env.map(rv64uf))
+          if (cfg.fLen >= 64)
+            TestGeneration.addSuites(env.map(rv64ud))
+        }
+      }
+      if (coreParams.useAtomics) {
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+        else
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
+      }
+      if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      val (rvi, rvu) =
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
+
+      TestGeneration.addSuites(rvi.map(_("p")))
+      TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      TestGeneration.addSuite(benchmarks)
+      TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+    }
+  }
+
 }
diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
index 3804b97f..35934eab 100644
--- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
@@ -6,7 +6,6 @@ import freechips.rocketchip.config.{Config}
 // BOOM Configs
 // ---------------------
 
-
 class SmallBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
   new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
@@ -26,7 +25,6 @@ class SmallBoomConfig extends Config(
   new boom.common.WithNBoomCores(1) ++                           // single-core boom
   new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
 
-
 class MediumBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index 9a19e6ef..cfa1a873 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -21,11 +21,12 @@ import midas.targetutils.{MemModelAnnotation}
 import firesim.bridges._
 import firesim.configs.MemModelKey
 import tracegen.HasTraceGenTilesModuleImp
+import ariane.ArianeTile
 
 import boom.common.{BoomTile}
 
 import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
-import chipyard.HasBoomAndRocketTilesModuleImp
+import chipyard.HasChipyardTilesModuleImp
 
 class WithSerialBridge extends OverrideIOBinder({
   (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq
@@ -67,7 +68,7 @@ class WithTraceGenBridge extends OverrideIOBinder({
 })
 
 class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
-  (c, r, s, target: HasBoomAndRocketTilesModuleImp) => {
+  (c, r, s, target: HasChipyardTilesModuleImp) => {
     target.outer.tiles.map {
       case r: RocketTile => {
         annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
@@ -84,6 +85,7 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
           case _ => Nil
         }
       }
+      case a: ArianeTile => Nil
     }
     Nil
   }
diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala
index 11598719..18aeefc8 100644
--- a/generators/firechip/src/main/scala/Generator.scala
+++ b/generators/firechip/src/main/scala/Generator.scala
@@ -26,6 +26,7 @@ trait HasTestSuites {
   def addTestSuites(targetName: String, params: Parameters) {
     TestSuiteHelper.addRocketTestSuites(params)
     TestSuiteHelper.addBoomTestSuites(params)
+    TestSuiteHelper.addArianeTestSuites(params)
     TestGeneration.addSuite(FastBlockdevTests)
     TestGeneration.addSuite(SlowBlockdevTests)
     if (!targetName.contains("NoNIC"))
@@ -61,7 +62,7 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike {
   override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   lazy val generatorArgs = GeneratorArgs(args)
   lazy val genDir = new File(names.targetDir)
-  // The only reason this is not generateFirrtl; generateAnno is that we need to use a different 
+  // The only reason this is not generateFirrtl; generateAnno is that we need to use a different
   // JsonProtocol to properly write out the annotations. Fix once the generated are unified
   elaborate
   generateTestSuiteMakefrags
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index d13ba0a2..e07a73a6 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -19,6 +19,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import scala.math.{min, max}
 import tracegen.TraceGenKey
 import icenet._
+import ariane.ArianeTilesKey
 import testchipip.WithRingSystemBus
 
 import firesim.bridges._
@@ -76,6 +77,7 @@ class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
 // Enables tracing on all cores
 class WithTraceIO extends Config((site, here, up) => {
   case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+  case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
   case TracePortKey => Some(TracePortParams())
 })
 
@@ -165,3 +167,12 @@ class SupernodeFireSimRocketConfig extends Config(
   new WithNumNodes(4) ++
   new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB
   new FireSimRocketConfig)
+
+//**********************************************************************************
+//* Ariane Configurations
+//*********************************************************************************/
+class FireSimArianeConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.ArianeConfig)
diff --git a/scripts/centos-req.sh b/scripts/centos-req.sh
index 8fac61af..30b9fe70 100755
--- a/scripts/centos-req.sh
+++ b/scripts/centos-req.sh
@@ -1,5 +1,7 @@
 #!/bin/bash
 
+set -ex
+
 sudo yum groupinstall -y "Development tools"
 sudo yum install -y gmp-devel mpfr-devel libmpc-devel zlib-devel vim git java java-devel
 curl https://bintray.com/sbt/rpm/rpm | sudo tee /etc/yum.repos.d/bintray-sbt-rpm.repo
@@ -16,3 +18,9 @@ sudo yum install -y centos-release-scl
 sudo yum install -y devtoolset-8-make
 # install DTC
 sudo yum install -y dtc
+
+# install verilator
+git clone http://git.veripool.org/git/verilator
+cd verilator
+git checkout v4.028
+autoconf && ./configure && make -j16 && sudo make install
diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch
index b5eb87bf..422c59c8 100644
--- a/scripts/tutorial-patches/build.sbt.patch
+++ b/scripts/tutorial-patches/build.sbt.patch
@@ -1,5 +1,5 @@
 diff --git a/build.sbt b/build.sbt
-index 52fc3cb..875e3b4 100644
+index a633066..3df8b74 100644
 --- a/build.sbt
 +++ b/build.sbt
 @@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
@@ -8,28 +8,19 @@ index 52fc3cb..875e3b4 100644
    .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities,
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
-     gemmini, icenet, tracegen)
+     gemmini, icenet, tracegen, ariane)
    .settings(commonSettings)
  
-@@ -147,9 +147,9 @@ lazy val boom = (project in file("generators/boom"))
+@@ -151,9 +151,9 @@ lazy val ariane = (project in file("generators/ariane"))
    .dependsOn(rocketchip)
    .settings(commonSettings)
  
 -lazy val sha3 = (project in file("generators/sha3"))
 -  .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
 -  .settings(commonSettings)
-+// lazy val sha3 = (project in file("generators/sha3"))
-+//   .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
-+//   .settings(commonSettings)
++//lazy val sha3 = (project in file("generators/sha3"))
++//  .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
++//  .settings(commonSettings)
  
  lazy val gemmini = (project in file("generators/gemmini"))
    .dependsOn(rocketchip, chisel_testers, testchipip)
-@@ -198,7 +198,7 @@ lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
- 
- lazy val firechip = (project in file("generators/firechip"))
-   .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache,
--    sha3, // On separate line to allow for cleaner tutorial-setup patches
-+//    sha3, // On separate line to allow for cleaner tutorial-setup patches
-     utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
-   .settings(
-     commonSettings,
diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh
index 1858c3a4..da626052 100755
--- a/scripts/ubuntu-req.sh
+++ b/scripts/ubuntu-req.sh
@@ -1,5 +1,7 @@
 #!/bin/bash
 
+set -ex
+
 sudo apt-get install -y build-essential bison flex
 sudo apt-get install -y libgmp-dev libmpfr-dev libmpc-dev zlib1g-dev vim git default-jdk default-jre
 # install sbt: https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html
@@ -17,3 +19,9 @@ sudo apt-get install -y libgtk-3-dev
 sudo apt-get install -y python3-pip python3.6-dev rsync libguestfs-tools expat ctags
 # install DTC
 sudo apt-get install -y device-tree-compiler
+
+# install verilator
+git clone http://git.veripool.org/git/verilator
+cd verilator
+git checkout v4.028
+autoconf && ./configure && make -j16 && sudo make install
diff --git a/sims/firesim b/sims/firesim
index 2f033c21..9f970576 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 2f033c2101612097fa27cf1768a280c980125b39
+Subproject commit 9f9705762a7e19b1e9ff77a92f7f4413ffe83265
diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile
index e5c6e1be..e829047c 100644
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -62,20 +62,25 @@ VCS_NONCC_OPTS = \
 	+v2k \
 	+vcs+lic+wait \
 	+vc+list \
-	-f $(sim_common_files) \
+	-error=noZMMCM \
+	-assert svaext \
 	-sverilog \
+	+libext+.v \
 	+incdir+$(build_dir) \
+	-f $(sim_common_files) \
+	$(sim_vsrcs)
+
+VCS_DEFINES = \
+	+define+VCS \
 	+define+CLOCK_PERIOD=1.0 \
-	$(sim_vsrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
 	+define+STOP_COND=!$(TB).reset \
 	+define+RANDOMIZE_MEM_INIT \
 	+define+RANDOMIZE_REG_INIT \
 	+define+RANDOMIZE_GARBAGE_ASSIGN \
-	+define+RANDOMIZE_INVALID_ASSIGN \
-	+libext+.v
+	+define+RANDOMIZE_INVALID_ASSIGN
 
-VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS)
+VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES)
 
 #########################################################################################
 # vcs simulator rules
@@ -84,9 +89,10 @@ $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	-debug_pp
 
-$(sim_debug) : $(sim_vsrcs) $(sim_common_files) $(dramsim_lib)
+$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
-	+define+DEBUG -debug_pp
+	+define+DEBUG \
+	-debug_pp
 
 #########################################################################################
 # create a vcs vpd rule
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index 140f54fd..13e7d201 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -1,6 +1,9 @@
 #########################################################################################
 # verilator makefile
 #########################################################################################
+ifeq ($(shell which verilator),)
+$(error Did not find Verilator in PATH. Make sure all requirements are installed)
+endif
 
 #########################################################################################
 # general path variables
@@ -38,12 +41,11 @@ debug: $(sim_debug)
 # import other necessary rules and variables
 #########################################################################################
 include $(base_dir)/common.mk
-include $(sim_dir)/verilator.mk
 
 #########################################################################################
 # verilator binary and flags
 #########################################################################################
-VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
+VERILATOR := verilator --cc --exe
 
 CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -I$(dramsim_dir) -D__STDC_FORMAT_MACROS
 LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(dramsim_dir) -Wl,-rpath,$(dramsim_dir) -L$(sim_dir) -lfesvr -lpthread -ldramsim
@@ -54,17 +56,38 @@ VERILATOR_CC_OPTS = \
 	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \
 	-LDFLAGS "$(LDFLAGS)"
 
+# default flags added for ariane
+ARIANE_VERILATOR_FLAGS = \
+	--unroll-count 256 \
+	-Werror-PINMISSING \
+	-Werror-IMPLICIT \
+	-Wno-fatal \
+	-Wno-PINCONNECTEMPTY \
+	-Wno-ASSIGNDLY \
+	-Wno-DECLFILENAME \
+	-Wno-UNUSED \
+	-Wno-UNOPTFLAT \
+	-Wno-BLKANDNBLK \
+	-Wno-style \
+	-Wall
+
+# normal flags used for chipyard builds (that are incompatible with ariane)
+CHIPYARD_VERILATOR_FLAGS = \
+	--assert
+
 VERILATOR_NONCC_OPTS = \
 	--top-module $(VLOG_MODEL) \
-	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
-	+define+STOP_COND=\$$c\(\"done_reset\"\) \
-	--assert \
+	$(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \
 	--output-split 10000 \
 	--output-split-cfuncs 100 \
-	$(sim_vsrcs) \
-	-f $(sim_common_files)
+	-f $(sim_common_files) \
+	$(sim_vsrcs)
 
-VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS)
+VERILATOR_DEFINES = \
+	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+	+define+STOP_COND=\$$c\(\"done_reset\"\)
+
+VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES)
 
 #########################################################################################
 # verilator build paths and file names
@@ -81,14 +104,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
 #########################################################################################
 # build makefile fragment that builds the verilator sim rules
 #########################################################################################
-
-$(model_mk): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR)
+$(model_mk): $(sim_vsrcs) $(sim_common_files)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name)
 	$(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
 	touch $@
 
-$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR)
+$(model_mk_debug): $(sim_vsrcs) $(sim_common_files)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name).debug
 	$(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
diff --git a/sims/verilator/verilator.mk b/sims/verilator/verilator.mk
deleted file mode 100644
index 12ab165d..00000000
--- a/sims/verilator/verilator.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-#########################################################################################
-# verilator installation makefrag
-#########################################################################################
-
-#########################################################################################
-# verilator version, binary, and path
-#########################################################################################
-VERILATOR_VERSION      = 4.016
-VERILATOR_INSTALL_DIR ?= verilator_install
-VERILATOR_SRCDIR       = $(VERILATOR_INSTALL_DIR)/src/verilator-$(VERILATOR_VERSION)
-INSTALLED_VERILATOR    = $(abspath $(VERILATOR_INSTALL_DIR)/install/bin/verilator)
-
-#########################################################################################
-# build and install our own verilator to work around versioning issues
-#########################################################################################
-$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator
-	$(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata
-	touch $@
-
-.PHONY:
-verilator_install: $(INSTALLED_VERILATOR)
-
-$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile
-	$(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin
-	touch $@
-
-$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure
-	mkdir -p $(dir $@)
-	cd $(dir $@) && ./configure --prefix=$(abspath $(VERILATOR_INSTALL_DIR)/install)
-
-$(VERILATOR_SRCDIR)/configure: $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz
-	rm -rf $(dir $@)
-	mkdir -p $(dir $@)
-	cat $^ | tar -xz --strip-components=1 -C $(dir $@)
-	touch $@
-
-$(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz:
-	mkdir -p $(dir $@)
-	wget https://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
diff --git a/variables.mk b/variables.mk
index d124fed6..8a1bb1df 100644
--- a/variables.mk
+++ b/variables.mk
@@ -114,11 +114,11 @@ HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf
 HARNESS_SMEMS_FIR  ?= $(build_dir)/$(long_name).harness.mems.fir
 
 # files that contain lists of files needed for VCS or Verilator simulation
-sim_files                  ?= $(build_dir)/sim_files.f
-sim_top_blackboxes         ?= $(build_dir)/firrtl_black_box_resource_files.top.f
-sim_harness_blackboxes     ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
+sim_files              ?= $(build_dir)/sim_files.f
+sim_top_blackboxes     ?= $(build_dir)/firrtl_black_box_resource_files.top.f
+sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
 # single file that contains all files needed for VCS or Verilator simulation (unique and without .h's)
-sim_common_files           ?= $(build_dir)/sim_files.common.f
+sim_common_files       ?= $(build_dir)/sim_files.common.f
 
 #########################################################################################
 # java arguments used in sbt