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alonamid
2021-01-08 20:18:52 -08:00
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4
docs/Chipyard-Basics/Chipyard-Components.rst
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@@ -130,8 +130,8 @@ Prototyping
**FPGA Prototyping**
FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``.
Some examples of FPGAs supported are the Xilinx Arty 35T and VCU118 boards.
For a fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform.
See :ref:`Prototyping Flow` for more information on FPGA prototypes.
For a fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`Simulation/FPGA-Accelerated-Simulation:FireSim` platform.
See :ref:`Prototyping/index:Prototyping Flow` for more information on FPGA prototypes.
VLSI
-------------------------------------------

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docs/Prototyping/General.rst
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@@ -18,7 +18,7 @@ Generating a Bitstream
----------------------
Generating a bitstream for any FPGA target using Vivado is similar to building RTL for a software RTL simulation.
Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado:
Similar to a software RTL simulation (:ref:`Simulation/Software-RTL-Simulation:Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado:
.. code-block:: shell
@@ -67,4 +67,4 @@ For example, running the bitstream build for an added ILA for a BOOM config.:
make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream
.. IMPORTANT:: For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform.
.. IMPORTANT:: For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`Simulation/FPGA-Accelerated-Simulation:FireSim` platform.

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docs/Prototyping/VCU118.rst
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@@ -45,7 +45,7 @@ For ease of use, you can change the ``FPGAFrequencyKey`` to change the default c
After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs.
This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``).
For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`.
For more information on harness binders and io binders, refer to :ref:`Customization/IOBinders:IOBinders and HarnessBinders`.
Introduction to the Bringup Platform
------------------------------------
@@ -57,4 +57,4 @@ The TSI Host Widget is used to interact with the DUT from the prototype over a S
.. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation.
For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``.
See :ref:`Generating a Bitstream` for information on the various make variables.
See :ref:`Prototyping/General:Generating a Bitstream` for information on the various make variables.