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Merge pull request #747 from ucb-bar/local-fpga-support

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Local FPGA Support - Arty/VCU118
This commit is contained in:
Abraham Gonzalez
2021-01-08 17:51:57 -08:00
committed by GitHub
parent 6d8627f36d 5505aef30f
commit d1d7bb8f52
69 changed files with 3309 additions and 46 deletions
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18
.circleci/README.md
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@@ -34,11 +34,19 @@ Here the key is built from a string where the `checksum` portion converts the fi
This directory contains all the collateral for the Chipyard CI to work. This directory contains all the collateral for the Chipyard CI to work.
The following is included: The following is included:
`build-toolchains.sh` # build either riscv-tools or esp-tools `build-toolchains.sh` # build either riscv-tools or esp-tools
`create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work
`do-rtl-build.sh` # use verilator to build a sim executable (remotely) `do-rtl-build.sh` # use verilator to build a sim executable (remotely)
`config.yml` # main circleci config script to enumerate jobs/workflows `config.yml` # main circleci config script to enumerate jobs/workflows
`defaults.sh` # default variables used `defaults.sh` # default variables used
`check-commit.sh` # check that submodule commits are valid
`build-extra-tests.sh` # build default chipyard tests located in tests/
`clean-old-files.sh` # clean up build server files
`do-fpga-rtl-build.sh` # similar to `do-rtl-build` but using fpga/
`install-verilator.sh` # install verilator on build server
`run-firesim-scala-tests.sh` # run firesim scala tests
`run-tests.sh # run tests for a specific set of designs
`images/` # docker image used in CI
How things are setup for Chipyard How things are setup for Chipyard
--------------------------------- ---------------------------------

4
.circleci/check-commit.sh
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@@ -120,6 +120,10 @@ dir="vlsi"
branches=("master") branches=("master")
search search
submodules=("fpga-shells")
dir="fpga"
branches=("master")
search
# turn off verbose printing to make this easier to read # turn off verbose printing to make this easier to read
set +x set +x

15
.circleci/config.yml
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@@ -82,12 +82,15 @@ commands:
build-script: build-script:
type: string type: string
default: "do-rtl-build.sh" default: "do-rtl-build.sh"
build-type:
type: string
default: "sim"
steps: steps:
- setup-tools: - setup-tools:
tools-version: "<< parameters.tools-version >>" tools-version: "<< parameters.tools-version >>"
- run: - run:
name: Building << parameters.group-key >> subproject using Verilator name: Building << parameters.group-key >> subproject using Verilator
command: .circleci/<< parameters.build-script >> << parameters.group-key >> command: .circleci/<< parameters.build-script >> << parameters.group-key >> << parameters.build-type >>
no_output_timeout: << parameters.timeout >> no_output_timeout: << parameters.timeout >>
- save_cache: - save_cache:
key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }} key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }}
@@ -368,6 +371,12 @@ jobs:
project-key: "firesim-multiclock" project-key: "firesim-multiclock"
run-script: "run-firesim-scala-tests.sh" run-script: "run-firesim-scala-tests.sh"
timeout: "20m" timeout: "20m"
prepare-chipyard-fpga:
executor: main-env
steps:
- prepare-rtl:
group-key: "group-fpga"
build-type: "fpga"
# Order and dependencies of jobs to run # Order and dependencies of jobs to run
workflows: workflows:
@@ -507,4 +516,8 @@ workflows:
- install-verilator - install-verilator
- build-extra-tests - build-extra-tests
# Prepare the fpga builds (just Verilog)
- prepare-chipyard-fpga:
requires:
- install-riscv-toolchain

5
.circleci/defaults.sh
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@@ -33,6 +33,7 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install
REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard
REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator
REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim
REMOTE_FPGA_DIR=$REMOTE_CHIPYARD_DIR/fpga
REMOTE_JAVA_OPTS="-Xmx10G -Xss8M" REMOTE_JAVA_OPTS="-Xmx10G -Xss8M"
# Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI
REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
@@ -53,6 +54,7 @@ grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spifl
grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
grouping["group-tracegen"]="tracegen tracegen-boom" grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-other"]="icenet testchipip" grouping["group-other"]="icenet testchipip"
grouping["group-fpga"]="arty vcu118"
# key value store to get the build strings # key value store to get the build strings
declare -A mapping declare -A mapping
@@ -83,3 +85,6 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test
mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
mapping["icenet"]="SUB_PROJECT=icenet" mapping["icenet"]="SUB_PROJECT=icenet"
mapping["testchipip"]="SUB_PROJECT=testchipip" mapping["testchipip"]="SUB_PROJECT=testchipip"
mapping["arty"]="SUB_PROJECT=arty verilog"
mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"

30
.circleci/do-rtl-build.sh
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@@ -1,7 +1,11 @@
#!/bin/bash #!/bin/bash
# create the different verilator builds # create the different verilator builds
# argument is the make command string # usage:
# do-rtl-build.sh <make command string> sim
# run rtl build for simulations and copy back results
# do-rtl-build.sh <make command string> fpga
# run rtl build for fpga and don't copy back results
# turn echo on and error on earliest command # turn echo on and error on earliest command
set -ex set -ex
@@ -15,6 +19,7 @@ trap clean EXIT
cd $LOCAL_CHIPYARD_DIR cd $LOCAL_CHIPYARD_DIR
./scripts/init-submodules-no-riscv-tools.sh ./scripts/init-submodules-no-riscv-tools.sh
./scripts/init-fpga.sh
# set stricthostkeychecking to no (must happen before rsync) # set stricthostkeychecking to no (must happen before rsync)
run "echo \"Ping $SERVER\"" run "echo \"Ping $SERVER\""
@@ -50,9 +55,19 @@ else
copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR
fi fi
# choose what make dir to use
case $2 in
"sim")
REMOTE_MAKE_DIR=$REMOTE_SIM_DIR
;;
"fpga")
REMOTE_MAKE_DIR=$REMOTE_FPGA_DIR
;;
esac
# enter the verilator directory and build the specific config on remote server # enter the verilator directory and build the specific config on remote server
run "export RISCV=\"$TOOLS_DIR\"; \ run "export RISCV=\"$TOOLS_DIR\"; \
make -C $REMOTE_SIM_DIR clean;" make -C $REMOTE_MAKE_DIR clean;"
read -a keys <<< ${grouping[$1]} read -a keys <<< ${grouping[$1]}
@@ -64,11 +79,14 @@ do
export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$key]}" make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$key]}"
done done
run "rm -rf $REMOTE_CHIPYARD_DIR/project" run "rm -rf $REMOTE_CHIPYARD_DIR/project"
# copy back the final build # choose to copy back results
mkdir -p $LOCAL_CHIPYARD_DIR if [ $2 = "sim" ]; then
copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR # copy back the final build
mkdir -p $LOCAL_CHIPYARD_DIR
copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR
fi

3
.gitmodules vendored
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@@ -131,3 +131,6 @@
[submodule "generators/riscv-sodor"] [submodule "generators/riscv-sodor"]
path = generators/riscv-sodor path = generators/riscv-sodor
url = https://github.com/ucb-bar/riscv-sodor.git url = https://github.com/ucb-bar/riscv-sodor.git
[submodule "fpga/fpga-shells"]
path = fpga/fpga-shells
url = https://github.com/sifive/fpga-shells.git

202
LICENSE.SiFive Normal file
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@@ -0,0 +1,202 @@
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8
build.sbt
View File

@@ -311,3 +311,11 @@ lazy val firechip = (project in file("generators/firechip"))
testGrouping in Test := isolateAllTests( (definedTests in Test).value ), testGrouping in Test := isolateAllTests( (definedTests in Test).value ),
testOptions in Test += Tests.Argument("-oF") testOptions in Test += Tests.Argument("-oF")
) )
lazy val fpga_shells = (project in file("./fpga/fpga-shells"))
.dependsOn(rocketchip, sifive_blocks)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val fpga_platforms = (project in file("./fpga"))
.dependsOn(chipyard, fpga_shells)
.settings(commonSettings)

2
common.mk
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@@ -61,7 +61,7 @@ include $(base_dir)/tools/dromajo/dromajo.mk
# Returns a list of files in directory $1 with file extension $2. # Returns a list of files in directory $1 with file extension $2.
lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null)
SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell) SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga/fpga-shells fpga/src)
SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala)
VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v)
# This assumes no SBT meta-build sources # This assumes no SBT meta-build sources

13
docs/Chipyard-Basics/Chipyard-Components.rst
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@@ -106,12 +106,12 @@ Software
Sims Sims
------------------------------------------- -------------------------------------------
**verilator (Verilator wrapper)** **Verilator**
Verilator is an open source Verilog simulator. Verilator is an open source Verilog simulator.
The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files).
See :ref:`Verilator (Open-Source)` for more information. See :ref:`Verilator (Open-Source)` for more information.
**vcs (VCS wrapper)** **VCS**
VCS is a proprietary Verilog simulator. VCS is a proprietary Verilog simulator.
Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files).
See :ref:`Synopsys VCS (License Required)` for more information. See :ref:`Synopsys VCS (License Required)` for more information.
@@ -124,6 +124,15 @@ Sims
In order to use FireSim, the repository must be cloned and executed on AWS instances. In order to use FireSim, the repository must be cloned and executed on AWS instances.
See :ref:`FireSim` for more information. See :ref:`FireSim` for more information.
Prototyping
-------------------------------------------
**FPGA Prototyping**
FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``.
Some examples of FPGAs supported are the Xilinx Arty 35T and VCU118 boards.
For a fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform.
See :ref:`Prototyping Flow` for more information on FPGA prototypes.
VLSI VLSI
------------------------------------------- -------------------------------------------

26
docs/Prototyping/Arty.rst Normal file
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@@ -0,0 +1,26 @@
Running a Design on Arty
========================
Basic Arty Design
-----------------
The default Xilinx Arty 35T harness is setup to have JTAG available over the board's PMOD pins, and UART available over its FTDI serial USB adapter. The pin mappings for JTAG signals are identical to those described in the `SiFive Freedom E310 Arty 35T Getting Started Guide <https://static.dev.sifive.com/SiFive-E310-arty-gettingstarted-v1.0.6.pdf>`__.
The JTAG interface allows a user to connect to the core via OpenOCD, run bare-metal applications, and debug these applications with gdb. UART allows a user to communicate with the core over a USB connection and serial console running on a PC.
To extend this design, a user may create their own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``.
Adding this config. fragment will enable and connect the JTAG and UART interfaces to your Chipyard design.
.. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala
:language: scala
:start-after: DOC include start: AbstractArty and Rocket
:end-before: DOC include end: AbstractArty and Rocket
Future peripherals to be supported include the Arty 35T SPI Flash EEPROM, and I2C/PWM/SPI over the Arty 35T GPIO pins. These peripherals are available as part of sifive-blocks.
Brief Implementation Description and Guidance for Adding/Changing Xilinx Collateral
-----------------------------------------------------------------------------------
Like the VCU118, the basis for the Arty 35T design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design.
This is done with the ``ArtyTestHarness`` in the basic default Arty 35T target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``.
Unlike the VCU118 and other more complicated test harnesses, the Arty 35T Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``.
If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinders`` and ``IOBinders``.
Examples of a simple ``IOBinder`` and ``HarnessBinder`` for routing signals (in this case the debug and JTAG resets) from the core to the test harness are the ``WithResetPassthrough`` and ``WithArtyResetHarnessBinder``.

70
docs/Prototyping/General.rst Normal file
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@@ -0,0 +1,70 @@
General Setup and Usage
==============================
Sources and Submodule Setup
---------------------------
All FPGA prototyping-related collateral and sources are located in the ``fpga`` top-level Chipyard directory.
This includes the ``fpga-shells`` submodule and the ``src`` directory that hold both Scala, TCL and other collateral.
However, the ``fpga-shells`` submodule repository is not initialized by default.
To initialize the ``fpga-shells`` submodule repository, run the included initialization script from the Chipyard top-level directory:
.. code-block:: shell
# in the chipyard top level folder
./scripts/init-fpga.sh
Generating a Bitstream
----------------------
Generating a bitstream for any FPGA target using Vivado is similar to building RTL for a software RTL simulation.
Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado:
.. code-block:: shell
make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... FPGA_BRAND=... bitstream
# or
make SUB_PROJECT=<sub_project> bitstream
The ``SUB_PROJECT`` make variable is a way to meta make variable that sets all of the other make variables to a specific default.
For example:
.. code-block:: shell
make SUB_PROJECT=vcu118 bitstream
# converts to
make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream
Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``.
These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system.
Like a software RTL simulation make invocation, all of the make variables can be overridden with user specific values (ex. include the ``SUB_PROJECT`` with a ``CONFIG`` and ``CONFIG_PACKAGE`` override).
In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to.
For example, building the BOOM configuration on the VCU118:
.. code-block:: shell
make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bitstream
That command will build the RTL and generate a bitstream using Vivado.
The generated bitstream will be located in your designs specific build folder (``generated-src/<LONG_NAME>/obj``).
However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL.
Debugging with ILAs on Supported FPGAs
--------------------------------------
ILA (integrated logic analyzers) can be added to certain designs for debugging relevant signals.
First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``).
Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA).
This can be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``.
This will create a new bitstream called ``top.bit`` in a folder named ``generated-src/<LONG_NAME>/debug_obj/``.
For example, running the bitstream build for an added ILA for a BOOM config.:
.. code-block:: shell
make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream
.. IMPORTANT:: For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform.

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Running a Design on VCU118
==========================
Basic VCU118 Design
-------------------
The default Xilinx VCU118 harness is setup to have UART, a SPI SDCard, and DDR backing memory.
This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118).
To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``.
Adding this config fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config.
.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala
:language: scala
:start-after: DOC include start: AbstractVCU118 and Rocket
:end-before: DOC include end: AbstractVCU118 and Rocket
Brief Implementation Description + More Complicated Designs
-----------------------------------------------------------
The basis for a VCU118 design revolves around creating a special test harness to connect the external IOs to your Chipyard design.
This is done with the ``VCU118TestHarness`` in the basic default VCU118 FPGA target.
The ``VCU118TestHarness`` (located in ``fpga/src/main/scala/vcu118/TestHarness.scala``) uses ``Overlays`` that connect to the VCU118 external IOs.
Generally, the ``Overlays`` take an IO from the ``ChipTop`` (labeled as ``topDesign`` in the file) when "placed" and connect it to the external IO and generate necessary Vivado collateral.
For example, the following shows a UART ``Overlay`` being "placed" into the design with a IO input called ``io_uart_bb``.
.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala
:language: scala
:start-after: DOC include start: UartOverlay
:end-before: DOC include end: UartOverlay
Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART.
The ``UARTDesignInput`` is used to pass in the UART IO from the ``ChipTop``/``topDesign`` to the ``Overlay``.
Note that the ``BundleBridgeSource`` can be viewed as a glorified wire (that is defined in the ``LazyModule`` scope).
This pattern is similar for all other ``Overlays`` in the test harness.
They must be "placed" and given a set of inputs (IOs, parameters).
The main exception to this pattern is the ``Overlay`` used to generate the clock(s) for the FPGA.
.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala
:language: scala
:start-after: DOC include start: ClockOverlay
:end-before: DOC include end: ClockOverlay
Without going into too much detail, the clocks overlay is placed in the harness and a PLL node (``harnessSysPLL``) generates the necessary clocks specified by ``ClockSinkNodes``.
For ease of use, you can change the ``FPGAFrequencyKey`` to change the default clock frequency of the FPGA design.
After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs.
This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``).
For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`.
Introduction to the Bringup Platform
------------------------------------
An example of a more complicated design used for Chipyard test chips can be viewed in ``fpga/src/main/scala/vcu118/bringup/``.
This example extends the default test harness and creates new ``Overlays`` to connect to a DUT (connected to the FMC port).
Extensions include another UART (connected over FMC), I2C (connected over FMC), miscellaneous GPIOS (can be connected to anything), and a TSI Host Widget.
The TSI Host Widget is used to interact with the DUT from the prototype over a SerDes link (sometimes called the Low BandWidth InterFace - LBWIF) and provide access to a channel of the FPGA's DRAM.
.. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation.
For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``.
See :ref:`Generating a Bitstream` for information on the various make variables.

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Prototyping Flow
================
Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells <https://github.com/sifive/fpga-shells>`__.
This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty 35T board.
.. Note:: While ``fpga-shells`` provides harnesses for other FPGA development boards such as the Xilinx VC707 and some MicroSemi PolarFire, only harnesses for the Xilinx VCU118 and Xilinx Arty 35T boards are currently supported in Chipyard.
However, the VCU118 and Arty 35T examples demonstrate how a user may implement support for other harnesses provided by fpga-shells.
.. toctree::
:maxdepth: 2
:caption: Prototyping Flow:
General
VCU118
Arty

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@@ -3,14 +3,14 @@ Simulation
Chipyard supports two classes of simulation: Chipyard supports two classes of simulation:
#. Software RTL simulation using commercial or open-source (Verilator) RTL simulators #. Software RTL simulation using commercial or open-source (Verilator) RTL simulators
#. FPGA-accelerated full-system simulation using FireSim #. FPGA-accelerated full-system simulation using FireSim
Software RTL simulators of Chipyard designs run at O(1 KHz), but compile Software RTL simulators of Chipyard designs run at O(1 KHz), but compile
quickly and provide full waveforms. Conversly, FPGA-accelerated simulators run quickly and provide full waveforms. Conversely, FPGA-accelerated simulators run
at O(100 MHz), making them appropriate for booting an operating system and at O(100 MHz), making them appropriate for booting an operating system and
running a complete workload, but have multi-hour compile times and poorer debug running a complete workload, but have multi-hour compile times and poorer debug
visability. visibility.
Click next to see how to run a simulation. Click next to see how to run a simulation.
@@ -20,4 +20,3 @@ Click next to see how to run a simulation.
Software-RTL-Simulation Software-RTL-Simulation
FPGA-Accelerated-Simulation FPGA-Accelerated-Simulation

2
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TileLink-Diplomacy-Reference/index TileLink-Diplomacy-Reference/index
Prototyping/index
Indices and tables Indices and tables
================== ==================

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generated-src

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#########################################################################################
# fpga prototype makefile
#########################################################################################
#########################################################################################
# general path variables
#########################################################################################
base_dir=$(abspath ..)
sim_dir=$(abspath .)
# do not generate simulation files
sim_name := none
#########################################################################################
# include shared variables
#########################################################################################
SUB_PROJECT ?= vcu118
ifeq ($(SUB_PROJECT),vcu118)
SBT_PROJECT ?= fpga_platforms
MODEL ?= VCU118FPGATestHarness
VLOG_MODEL ?= VCU118FPGATestHarness
MODEL_PACKAGE ?= chipyard.fpga.vcu118
CONFIG ?= RocketVCU118Config
CONFIG_PACKAGE ?= chipyard.fpga.vcu118
GENERATOR_PACKAGE ?= chipyard
TB ?= none # unused
TOP ?= ChipTop
BOARD ?= vcu118
FPGA_BRAND ?= xilinx
endif
ifeq ($(SUB_PROJECT),bringup)
SBT_PROJECT ?= fpga_platforms
MODEL ?= BringupVCU118FPGATestHarness
VLOG_MODEL ?= BringupVCU118FPGATestHarness
MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup
CONFIG ?= RocketBringupConfig
CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup
GENERATOR_PACKAGE ?= chipyard
TB ?= none # unused
TOP ?= ChipTop
BOARD ?= vcu118
FPGA_BRAND ?= xilinx
endif
ifeq ($(SUB_PROJECT),arty)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
MODEL ?= ArtyFPGATestHarness
VLOG_MODEL ?= ArtyFPGATestHarness
MODEL_PACKAGE ?= chipyard.fpga.arty
CONFIG ?= TinyRocketArtyConfig
CONFIG_PACKAGE ?= chipyard.fpga.arty
GENERATOR_PACKAGE ?= chipyard
TB ?= none # unused
TOP ?= ChipTop
BOARD ?= arty
FPGA_BRAND ?= xilinx
endif
include $(base_dir)/variables.mk
# default variables to build the arty example
# setup the board to use
.PHONY: default
default: $(mcs)
#########################################################################################
# misc. directories
#########################################################################################
fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND)
fpga_common_script_dir := $(fpga_dir)/common/tcl
#########################################################################################
# import other necessary rules and variables
#########################################################################################
include $(base_dir)/common.mk
#########################################################################################
# copy from other directory
#########################################################################################
all_vsrcs := \
$(sim_vsrcs) \
$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \
$(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v
#########################################################################################
# vivado rules
#########################################################################################
# combine all sources into single .f
synth_list_f := $(build_dir)/$(long_name).vsrcs.f
$(synth_list_f): $(sim_common_files) $(all_vsrcs)
$(foreach file,$(all_vsrcs),echo "$(file)" >> $@;)
cat $(sim_common_files) >> $@
BIT_FILE := $(build_dir)/obj/$(MODEL).bit
$(BIT_FILE): $(synth_list_f)
cd $(build_dir); vivado \
-nojournal -mode batch \
-source $(fpga_common_script_dir)/vivado.tcl \
-tclargs \
-top-module "$(MODEL)" \
-F "$(synth_list_f)" \
-ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \
-board "$(BOARD)"
.PHONY: bitstream
bitstream: $(BIT_FILE)
.PHONY: debug-bitstream
debug-bitstream: $(build_dir)/obj/post_synth.dcp
cd $(build_dir); vivado \
-nojournal -mode batch \
-source $(sim_dir)/scripts/run_impl_bitstream.tcl \
-tclargs \
$(build_dir)/obj/post_synth.dcp \
$(BOARD) \
$(build_dir)/debug_obj \
$(fpga_common_script_dir)
#########################################################################################
# general cleanup rules
#########################################################################################
.PHONY: clean
clean:
rm -rf $(gen_dir)

1
fpga/fpga-shells Submodule

Submodule fpga/fpga-shells added at f9fb9fd338

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#### Command line arguments to this script
# argv[0] = absolute path to post_synth checkpoint file
# argv[1] = part
# argv[2] = output directory
# argv[3] = common fpga brand tcl
set synth_checkpoint_file [lindex $argv 0]
set board [lindex $argv 1]
set wrkdir [lindex $argv 2]
set scriptdir [lindex $argv 3]
# Set the variable for all the common files
set commondir [file dirname $scriptdir]
# Set the variable that points to board specific files
set boarddir [file join [file dirname $commondir] $board]
source [file join $boarddir tcl board.tcl]
# Set the project part to the part passed into this script
set_part $part_fpga
# Create output directories if they doesn't exist
file mkdir $wrkdir
set rptdir [file join $wrkdir report]
file mkdir $rptdir
# Load synthesis checkpoint
open_checkpoint $synth_checkpoint_file
# opt
opt_design
write_checkpoint -force [file join $wrkdir post_opt]
# place
place_design
phys_opt_design
write_checkpoint -force [file join $wrkdir post_place]
report_timing_summary -file [file join $rptdir post_place_timing_summary.rpt]
report_drc -file [file join $rptdir post_place_drc.rpt]
# route
route_design
write_checkpoint -force [file join $wrkdir post_route]
report_timing_summary -file [file join $rptdir post_route_timing_summary.rpt]
report_timing -sort_by group -max_paths 100 -path_type summary -file [file join $rptdir post_route_timing.rpt]
report_clock_utilization -file [file join $rptdir post_route_clock_utilization.rpt]
report_utilization -file [file join $rptdir post_route_utilization.rpt]
report_drc -file [file join $rptdir post_route_drc.rpt]
report_cdc -details -file [file join $rptdir post_route_cdc.rpt]
report_clock_interaction -file [file join $rptdir post_route_clock_interaction.rpt]
report_bus_skew -file [file join $rptdir post_route_bus_skew.rpt]
report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file [file join $rptdir post_route_timing_violations.rpt]
# bitstream
write_verilog -force [file join $wrkdir post_route.v]
write_xdc -no_fixed_only -force [file join $wrkdir post_route.xdc]
write_bitstream -force [file join $wrkdir top.bit]
write_debug_probes -force [file join $wrkdir debug_nets.ltx]

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build

42
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# RISCV environment variable must be set
ROOT_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
BUILD_DIR := $(ROOT_DIR)/build
CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
OBJDUMP=$(RISCV)/bin/riscv64-unknown-elf-objdump
CFLAGS=-march=rv64ima -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles
CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0
CFLAGS+= -I $(ROOT_DIR)/include -I.
LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T sdboot.elf.lds
PBUS_CLK ?= 1000000 # default to 1MHz but really should be overridden
default: elf bin dump
elf := $(BUILD_DIR)/sdboot.elf
$(elf): head.S kprintf.c sd.c
mkdir -p $(BUILD_DIR)
$(CC) $(CFLAGS) -DTL_CLK="$(PBUS_CLK)UL" $(LFLAGS) -o $@ head.S sd.c kprintf.c
.PHONY: elf
elf: $(elf)
bin := $(BUILD_DIR)/sdboot.bin
$(bin): $(elf)
mkdir -p $(BUILD_DIR)
$(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@
.PHONY: bin
bin: $(bin)
dump := $(BUILD_DIR)/sdboot.dump
$(dump): $(elf)
$(OBJDUMP) -D -S $< > $@
.PHONY: dump
dump: $(dump)
.PHONY: clean
clean::
rm -rf $(BUILD_DIR)

10
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@@ -0,0 +1,10 @@
// See LICENSE.Sifive for license details.
#ifndef _SDBOOT_COMMON_H
#define _SDBOOT_COMMON_H
#ifndef PAYLOAD_DEST
#define PAYLOAD_DEST MEMORY_MEM_ADDR
#endif
#endif

21
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// See LICENSE.Sifive for license details.
#include <platform.h>
#include <smp.h>
#include "common.h"
.section .text.init
.option norvc
.globl _prog_start
_prog_start:
smp_pause(s1, s2)
li sp, (PAYLOAD_DEST + 0xffff000)
call main
smp_resume(s1, s2)
csrr a0, mhartid // hartid for next level bootloader
la a1, dtb // dtb address for next level bootloader
li s1, PAYLOAD_DEST
jr s1
.section .dtb
.align 3
dtb:

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// See LICENSE.Sifive for license details.
#ifndef _RISCV_BITS_H
#define _RISCV_BITS_H
#define likely(x) __builtin_expect((x), 1)
#define unlikely(x) __builtin_expect((x), 0)
#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
#define ROUNDDOWN(a, b) ((a)/(b)*(b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
#define STR(x) XSTR(x)
#define XSTR(x) #x
#if __riscv_xlen == 64
# define SLL32 sllw
# define STORE sd
# define LOAD ld
# define LWU lwu
# define LOG_REGBYTES 3
#else
# define SLL32 sll
# define STORE sw
# define LOAD lw
# define LWU lw
# define LOG_REGBYTES 2
#endif
#define REGBYTES (1 << LOG_REGBYTES)
#endif

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@@ -0,0 +1,18 @@
// See LICENSE.Sifive for license details.
/* Derived from <linux/const.h> */
#ifndef _SIFIVE_CONST_H
#define _SIFIVE_CONST_H
#ifdef __ASSEMBLER__
#define _AC(X,Y) X
#define _AT(T,X) X
#else
#define _AC(X,Y) (X##Y)
#define _AT(T,X) ((T)(X))
#endif /* !__ASSEMBLER__*/
#define _BITUL(x) (_AC(1,UL) << (x))
#define _BITULL(x) (_AC(1,ULL) << (x))
#endif /* _SIFIVE_CONST_H */

14
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@@ -0,0 +1,14 @@
// See LICENSE.Sifive for license details.
#ifndef _SIFIVE_CLINT_H
#define _SIFIVE_CLINT_H
#define CLINT_MSIP 0x0000
#define CLINT_MSIP_size 0x4
#define CLINT_MTIMECMP 0x4000
#define CLINT_MTIMECMP_size 0x8
#define CLINT_MTIME 0xBFF8
#define CLINT_MTIME_size 0x8
#endif /* _SIFIVE_CLINT_H */

24
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@@ -0,0 +1,24 @@
// See LICENSE.Sifive for license details.
#ifndef _SIFIVE_GPIO_H
#define _SIFIVE_GPIO_H
#define GPIO_INPUT_VAL (0x00)
#define GPIO_INPUT_EN (0x04)
#define GPIO_OUTPUT_EN (0x08)
#define GPIO_OUTPUT_VAL (0x0C)
#define GPIO_PULLUP_EN (0x10)
#define GPIO_DRIVE (0x14)
#define GPIO_RISE_IE (0x18)
#define GPIO_RISE_IP (0x1C)
#define GPIO_FALL_IE (0x20)
#define GPIO_FALL_IP (0x24)
#define GPIO_HIGH_IE (0x28)
#define GPIO_HIGH_IP (0x2C)
#define GPIO_LOW_IE (0x30)
#define GPIO_LOW_IP (0x34)
#define GPIO_IOF_EN (0x38)
#define GPIO_IOF_SEL (0x3C)
#define GPIO_OUTPUT_XOR (0x40)
#endif /* _SIFIVE_GPIO_H */

31
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// See LICENSE.Sifive for license details.
#ifndef PLIC_H
#define PLIC_H
#include <const.h>
// 32 bits per source
#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
// 1 bit per source (1 address)
#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
#define PLIC_PENDING_SHIFT_PER_SOURCE 0
//0x80 per target
#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
#define PLIC_ENABLE_SHIFT_PER_TARGET 7
#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
#define PLIC_CLAIM_SHIFT_PER_TARGET 12
#define PLIC_MAX_SOURCE 1023
#define PLIC_SOURCE_MASK 0x3FF
#define PLIC_MAX_TARGET 15871
#define PLIC_TARGET_MASK 0x3FFF
#endif /* PLIC_H */

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// See LICENSE.Sifive for license details.
#ifndef _SIFIVE_SPI_H
#define _SIFIVE_SPI_H
/* Register offsets */
#define SPI_REG_SCKDIV 0x00
#define SPI_REG_SCKMODE 0x04
#define SPI_REG_CSID 0x10
#define SPI_REG_CSDEF 0x14
#define SPI_REG_CSMODE 0x18
#define SPI_REG_DCSSCK 0x28
#define SPI_REG_DSCKCS 0x2a
#define SPI_REG_DINTERCS 0x2c
#define SPI_REG_DINTERXFR 0x2e
#define SPI_REG_FMT 0x40
#define SPI_REG_TXFIFO 0x48
#define SPI_REG_RXFIFO 0x4c
#define SPI_REG_TXCTRL 0x50
#define SPI_REG_RXCTRL 0x54
#define SPI_REG_FCTRL 0x60
#define SPI_REG_FFMT 0x64
#define SPI_REG_IE 0x70
#define SPI_REG_IP 0x74
/* Fields */
#define SPI_SCK_POL 0x1
#define SPI_SCK_PHA 0x2
#define SPI_FMT_PROTO(x) ((x) & 0x3)
#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
/* TXCTRL register */
#define SPI_TXWM(x) ((x) & 0xffff)
/* RXCTRL register */
#define SPI_RXWM(x) ((x) & 0xffff)
#define SPI_IP_TXWM 0x1
#define SPI_IP_RXWM 0x2
#define SPI_FCTRL_EN 0x1
#define SPI_INSN_CMD_EN 0x1
#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
#define SPI_TXFIFO_FULL (1 << 31)
#define SPI_RXFIFO_EMPTY (1 << 31)
/* Values */
#define SPI_CSMODE_AUTO 0
#define SPI_CSMODE_HOLD 2
#define SPI_CSMODE_OFF 3
#define SPI_DIR_RX 0
#define SPI_DIR_TX 1
#define SPI_PROTO_S 0
#define SPI_PROTO_D 1
#define SPI_PROTO_Q 2
#define SPI_ENDIAN_MSB 0
#define SPI_ENDIAN_LSB 1
#endif /* _SIFIVE_SPI_H */

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// See LICENSE.Sifive for license details.
#ifndef _SIFIVE_UART_H
#define _SIFIVE_UART_H
/* Register offsets */
#define UART_REG_TXFIFO 0x00
#define UART_REG_RXFIFO 0x04
#define UART_REG_TXCTRL 0x08
#define UART_REG_RXCTRL 0x0c
#define UART_REG_IE 0x10
#define UART_REG_IP 0x14
#define UART_REG_DIV 0x18
/* TXCTRL register */
#define UART_TXEN 0x1
#define UART_TXNSTOP 0x2
#define UART_TXWM(x) (((x) & 0xffff) << 16)
/* RXCTRL register */
#define UART_RXEN 0x1
#define UART_RXWM(x) (((x) & 0xffff) << 16)
/* IP register */
#define UART_IP_TXWM 0x1
#define UART_IP_RXWM 0x2
#endif /* _SIFIVE_UART_H */

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// See LICENSE for license details.
#ifndef _CHIPYARD_PLATFORM_H
#define _CHIPYARD_PLATFORM_H
#include "const.h"
#include "devices/clint.h"
#include "devices/gpio.h"
#include "devices/plic.h"
#include "devices/spi.h"
#include "devices/uart.h"
// Some things missing from the official encoding.h
#if __riscv_xlen == 32
#define MCAUSE_INT 0x80000000UL
#define MCAUSE_CAUSE 0x7FFFFFFFUL
#else
#define MCAUSE_INT 0x8000000000000000UL
#define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL
#endif
/****************************************************************************
* Platform definitions
*****************************************************************************/
// CPU info
#define NUM_CORES 1
#define GLOBAL_INT_SIZE 38
#define GLOBAL_INT_MAX_PRIORITY 7
// Memory map
#define CLINT_CTRL_ADDR _AC(0x2000000,UL)
#define CLINT_CTRL_SIZE _AC(0x10000,UL)
#define DEBUG_CTRL_ADDR _AC(0x0,UL)
#define DEBUG_CTRL_SIZE _AC(0x1000,UL)
#define ERROR_MEM_ADDR _AC(0x3000,UL)
#define ERROR_MEM_SIZE _AC(0x1000,UL)
#define GPIO_CTRL_ADDR _AC(0x64002000,UL)
#define GPIO_CTRL_SIZE _AC(0x1000,UL)
#define MASKROM_MEM_ADDR _AC(0x10000,UL)
#define MASKROM_MEM_SIZE _AC(0x10000,UL)
#define MEMORY_MEM_ADDR _AC(0x80000000,UL)
#define MEMORY_MEM_SIZE _AC(0x10000000,UL)
#define PLIC_CTRL_ADDR _AC(0xc000000,UL)
#define PLIC_CTRL_SIZE _AC(0x4000000,UL)
#define SPI_CTRL_ADDR _AC(0x64001000,UL)
#define SPI_CTRL_SIZE _AC(0x1000,UL)
#define SPI1_CTRL_ADDR _AC(0x64004000,UL)
#define SPI1_CTRL_SIZE _AC(0x1000,UL)
#define TEST_CTRL_ADDR _AC(0x4000,UL)
#define TEST_CTRL_SIZE _AC(0x1000,UL)
#define UART_CTRL_ADDR _AC(0x64000000,UL)
#define UART_CTRL_SIZE _AC(0x1000,UL)
#define UART1_CTRL_ADDR _AC(0x64003000,UL)
#define UART1_CTRL_SIZE _AC(0x1000,UL)
#define I2C_CTRL_ADDR _AC(0x64005000,UL)
#define I2C_CTRL_SIZE _AC(0x1000,UL)
// IOF masks
// Interrupt numbers
#define UART_INT_BASE 1
#define UART1_INT_BASE 2
#define I2C_INT_BASE 3
#define GPIO_INT_BASE 4
#define SPI_INT_BASE 36
#define SPI1_INT_BASE 37
// Helper functions
#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
// Bulk set bits in `reg` to either 0 or 1.
// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7
// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7
#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
#define AXI_PCIE_HOST_1_00_A_REG(offset) _REG32(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset)
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
#define DEBUG_REG(offset) _REG32(DEBUG_CTRL_ADDR, offset)
#define ERROR_REG(offset) _REG32(ERROR_CTRL_ADDR, offset)
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
#define MASKROM_REG(offset) _REG32(MASKROM_CTRL_ADDR, offset)
#define MEMORY_REG(offset) _REG32(MEMORY_CTRL_ADDR, offset)
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
#define SPI_REG(offset) _REG32(SPI_CTRL_ADDR, offset)
#define TEST_REG(offset) _REG32(TEST_CTRL_ADDR, offset)
#define UART_REG(offset) _REG32(UART_CTRL_ADDR, offset)
#define AXI_PCIE_HOST_1_00_A_REG64(offset) _REG64(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset)
#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset)
#define DEBUG_REG64(offset) _REG64(DEBUG_CTRL_ADDR, offset)
#define ERROR_REG64(offset) _REG64(ERROR_CTRL_ADDR, offset)
#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
#define MASKROM_REG64(offset) _REG64(MASKROM_CTRL_ADDR, offset)
#define MEMORY_REG64(offset) _REG64(MEMORY_CTRL_ADDR, offset)
#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset)
#define SPI_REG64(offset) _REG64(SPI_CTRL_ADDR, offset)
#define SPI1_REG64(offset) _REG64(SPI1_CTRL_ADDR, offset)
#define TEST_REG64(offset) _REG64(TEST_CTRL_ADDR, offset)
#define UART_REG64(offset) _REG64(UART_CTRL_ADDR, offset)
#define UART1_REG64(offset) _REG64(UART1_CTRL_ADDR, offset)
#define I2C_REG64(offset) _REG64(I2C_CTRL_ADDR, offset)
// Misc
#endif /* _CHIPYARD_PLATFORM_H */

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// See LICENSE.Sifive for license details.
#ifndef _SECTIONS_H
#define _SECTIONS_H
extern unsigned char _rom[];
extern unsigned char _rom_end[];
extern unsigned char _ram[];
extern unsigned char _ram_end[];
extern unsigned char _ftext[];
extern unsigned char _etext[];
extern unsigned char _fbss[];
extern unsigned char _ebss[];
extern unsigned char _end[];
#endif /* _SECTIONS_H */

143
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// See LICENSE.Sifive for license details.
#ifndef SIFIVE_SMP
#define SIFIVE_SMP
#include "platform.h"
// The maximum number of HARTs this code supports
#ifndef MAX_HARTS
#define MAX_HARTS 32
#endif
#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
#define CLINT1_END_HART_IPI CLINT1_CTRL_ADDR + (MAX_HARTS*4)
// The hart that non-SMP tests should run on
#ifndef NONSMP_HART
#define NONSMP_HART 0
#endif
/* If your test cannot handle multiple-threads, use this:
* smp_disable(reg1)
*/
#define smp_disable(reg1, reg2) \
csrr reg1, mhartid ;\
li reg2, NONSMP_HART ;\
beq reg1, reg2, hart0_entry ;\
42: ;\
wfi ;\
j 42b ;\
hart0_entry:
/* If your test needs to temporarily block multiple-threads, do this:
* smp_pause(reg1, reg2)
* ... single-threaded work ...
* smp_resume(reg1, reg2)
* ... multi-threaded work ...
*/
#define smp_pause(reg1, reg2) \
li reg2, 0x8 ;\
csrw mie, reg2 ;\
li reg1, NONSMP_HART ;\
csrr reg2, mhartid ;\
bne reg1, reg2, 42f
#ifdef CLINT1_CTRL_ADDR
// If a second CLINT exists, then make sure we:
// 1) Trigger a software interrupt on all harts of both CLINTs.
// 2) Locate your own hart's software interrupt pending register and clear it.
// 3) Wait for all harts on both CLINTs to clear their software interrupt
// pending register.
// WARNING: This code makes these assumptions, which are only true for Fadu as
// of now:
// 1) hart0 uses CLINT0 at offset 0
// 2) hart2 uses CLINT1 at offset 0
// 3) hart3 uses CLINT1 at offset 1
// 4) There are no other harts or CLINTs in the system.
#define smp_resume(reg1, reg2) \
/* Trigger software interrupt on CLINT0 */ \
li reg1, CLINT_CTRL_ADDR ;\
41: ;\
li reg2, 1 ;\
sw reg2, 0(reg1) ;\
addi reg1, reg1, 4 ;\
li reg2, CLINT_END_HART_IPI ;\
blt reg1, reg2, 41b ;\
/* Trigger software interrupt on CLINT1 */ \
li reg1, CLINT1_CTRL_ADDR ;\
41: ;\
li reg2, 1 ;\
sw reg2, 0(reg1) ;\
addi reg1, reg1, 4 ;\
li reg2, CLINT1_END_HART_IPI ;\
blt reg1, reg2, 41b ;\
/* Wait to receive software interrupt */ \
42: ;\
wfi ;\
csrr reg2, mip ;\
andi reg2, reg2, 0x8 ;\
beqz reg2, 42b ;\
/* Clear own software interrupt bit */ \
csrr reg2, mhartid ;\
bnez reg2, 41f; \
/* hart0 case: Use CLINT0 */ \
li reg1, CLINT_CTRL_ADDR ;\
slli reg2, reg2, 2 ;\
add reg2, reg2, reg1 ;\
sw zero, 0(reg2) ;\
j 42f; \
41: \
/* hart 2, 3 case: Use CLINT1 and remap hart IDs to 0 and 1 */ \
li reg1, CLINT1_CTRL_ADDR ;\
addi reg2, reg2, -2; \
slli reg2, reg2, 2 ;\
add reg2, reg2, reg1 ;\
sw zero, 0(reg2) ; \
42: \
/* Wait for all software interrupt bits to be cleared on CLINT0 */ \
li reg1, CLINT_CTRL_ADDR ;\
41: ;\
lw reg2, 0(reg1) ;\
bnez reg2, 41b ;\
addi reg1, reg1, 4 ;\
li reg2, CLINT_END_HART_IPI ;\
blt reg1, reg2, 41b; \
/* Wait for all software interrupt bits to be cleared on CLINT1 */ \
li reg1, CLINT1_CTRL_ADDR ;\
41: ;\
lw reg2, 0(reg1) ;\
bnez reg2, 41b ;\
addi reg1, reg1, 4 ;\
li reg2, CLINT1_END_HART_IPI ;\
blt reg1, reg2, 41b; \
/* End smp_resume() */
#else
#define smp_resume(reg1, reg2) \
li reg1, CLINT_CTRL_ADDR ;\
41: ;\
li reg2, 1 ;\
sw reg2, 0(reg1) ;\
addi reg1, reg1, 4 ;\
li reg2, CLINT_END_HART_IPI ;\
blt reg1, reg2, 41b ;\
42: ;\
wfi ;\
csrr reg2, mip ;\
andi reg2, reg2, 0x8 ;\
beqz reg2, 42b ;\
li reg1, CLINT_CTRL_ADDR ;\
csrr reg2, mhartid ;\
slli reg2, reg2, 2 ;\
add reg2, reg2, reg1 ;\
sw zero, 0(reg2) ;\
41: ;\
lw reg2, 0(reg1) ;\
bnez reg2, 41b ;\
addi reg1, reg1, 4 ;\
li reg2, CLINT_END_HART_IPI ;\
blt reg1, reg2, 41b
#endif /* ifdef CLINT1_CTRL_ADDR */
#endif

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// See LICENSE.Sifive for license details.
#include <stdarg.h>
#include <stdint.h>
#include <stdbool.h>
#include "kprintf.h"
static inline void _kputs(const char *s)
{
char c;
for (; (c = *s) != '\0'; s++)
kputc(c);
}
void kputs(const char *s)
{
_kputs(s);
kputc('\r');
kputc('\n');
}
void kprintf(const char *fmt, ...)
{
va_list vl;
bool is_format, is_long, is_char;
char c;
va_start(vl, fmt);
is_format = false;
is_long = false;
is_char = false;
while ((c = *fmt++) != '\0') {
if (is_format) {
switch (c) {
case 'l':
is_long = true;
continue;
case 'h':
is_char = true;
continue;
case 'x': {
unsigned long n;
long i;
if (is_long) {
n = va_arg(vl, unsigned long);
i = (sizeof(unsigned long) << 3) - 4;
} else {
n = va_arg(vl, unsigned int);
i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4;
}
for (; i >= 0; i -= 4) {
long d;
d = (n >> i) & 0xF;
kputc(d < 10 ? '0' + d : 'a' + d - 10);
}
break;
}
case 's':
_kputs(va_arg(vl, const char *));
break;
case 'c':
kputc(va_arg(vl, int));
break;
}
is_format = false;
is_long = false;
is_char = false;
} else if (c == '%') {
is_format = true;
} else {
kputc(c);
}
}
va_end(vl);
}

49
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// See LICENSE.Sifive for license details.
#ifndef _SDBOOT_KPRINTF_H
#define _SDBOOT_KPRINTF_H
#include <platform.h>
#include <stdint.h>
#define REG32(p, i) ((p)[(i) >> 2])
#ifndef UART_CTRL_ADDR
#ifndef UART_NUM
#define UART_NUM 0
#endif
#define _CONCAT3(A, B, C) A ## B ## C
#define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR)
#define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM)
#endif
static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR);
static inline void kputc(char c)
{
volatile uint32_t *tx = &REG32(uart, UART_REG_TXFIFO);
#ifdef __riscv_atomic
int32_t r;
do {
__asm__ __volatile__ (
"amoor.w %0, %2, %1\n"
: "=r" (r), "+A" (*tx)
: "r" (c));
} while (r < 0);
#else
while ((int32_t)(*tx) < 0);
*tx = c;
#endif
}
extern void kputs(const char *);
extern void kprintf(const char *, ...);
#ifdef DEBUG
#define dprintf(s, ...) kprintf((s), ##__VA_ARGS__)
#define dputs(s) kputs((s))
#else
#define dprintf(s, ...) do { } while (0)
#define dputs(s) do { } while (0)
#endif
#endif /* _SDBOOT_KPRINTF_H */

5
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MEMORY
{
bootrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x2000
memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x40000000
}

80
fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds Normal file
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OUTPUT_ARCH("riscv")
ENTRY(_prog_start)
INCLUDE memory.lds
PHDRS
{
text PT_LOAD;
data PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
PROVIDE(_ram = ORIGIN(memory_mem));
PROVIDE(_ram_end = _ram + LENGTH(memory_mem));
.text ALIGN((ORIGIN(bootrom_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(bootrom_mem) + 0x0), 8)) {
PROVIDE(_ftext = .);
*(.text.init)
*(.text.unlikely .text.unlikely.*)
*(.text .text.* .gnu.linkonce.t.*)
PROVIDE(_etext = .);
. += 0x40; /* to create a gap between .text and .data b/c ifetch can fetch ahead from .data */
} >bootrom_mem :text
.eh_frame ALIGN((ADDR(.text) + SIZEOF(.text)), 8) : AT(ALIGN((LOADADDR(.text) + SIZEOF(.text)), 8)) {
*(.eh_frame)
} >bootrom_mem :text
.srodata ALIGN((ADDR(.eh_frame) + SIZEOF(.eh_frame)), 8) : AT(ALIGN((LOADADDR(.eh_frame) + SIZEOF(.eh_frame)), 8)) ALIGN_WITH_INPUT {
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata.*)
} >bootrom_mem :data
.data ALIGN((ADDR(.srodata) + SIZEOF(.srodata)), 8) : AT(ALIGN((LOADADDR(.srodata) + SIZEOF(.srodata)), 8)) ALIGN_WITH_INPUT {
*(.data .data.* .gnu.linkonce.d.*)
*(.tohost) /* TODO: Support sections that aren't explicitly listed in this linker script */
} >bootrom_mem :data
.sdata ALIGN((ADDR(.data) + SIZEOF(.data)), 8) : AT(ALIGN((LOADADDR(.data) + SIZEOF(.data)), 8)) ALIGN_WITH_INPUT {
*(.sdata .sdata.* .gnu.linkonce.s.*)
} >bootrom_mem :data
.rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT {
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.dtb) /* Must be last if this code is added to RC's BootROM */
} >bootrom_mem :data
PROVIDE(_data = ADDR(.rodata));
PROVIDE(_data_lma = LOADADDR(.rodata));
PROVIDE(_edata = .);
.bss ALIGN((ORIGIN(memory_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(memory_mem) + 0x0), 8)) ALIGN(8) {
PROVIDE(_fbss = .);
PROVIDE(__global_pointer$ = . + 0x7C0);
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.bss .bss.* .gnu.linkonce.b.*)
. = ALIGN(8);
PROVIDE(_ebss = .);
} >memory_mem :bss
PROVIDE(_end = .);
/*
* heap_stack_region_usable_end: (ORIGIN(memory_mem) + LENGTH(memory_mem))
* heap_stack_min_size: 4096
* heap_stack_max_size: 1048576
*/
PROVIDE(_sp = ALIGN(MIN((ORIGIN(memory_mem) + LENGTH(memory_mem)), _ebss + 1048576) - 7, 8));
PROVIDE(_heap_end = _sp - 2048);
/* This section is a noop and is only used for the ASSERT */
.stack : {
ASSERT(_sp >= (_ebss + 4096), "Error: No room left for the heap and stack");
}
}

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// See LICENSE.Sifive for license details.
#include <stdint.h>
#include <platform.h>
#include "common.h"
#define DEBUG
#include "kprintf.h"
#define MAX_CORES 8
// A sector is 512 bytes, so ((1 << 11) * 512) = 1 MiB
#define PAYLOAD_SIZE (16 << 11)
// The sector at which the BBL partition starts
#define BBL_PARTITION_START_SECTOR 34
#ifndef TL_CLK
#error Must define TL_CLK
#endif
#define F_CLK TL_CLK
static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
static inline uint8_t spi_xfer(uint8_t d)
{
int32_t r;
REG32(spi, SPI_REG_TXFIFO) = d;
do {
r = REG32(spi, SPI_REG_RXFIFO);
} while (r < 0);
return r;
}
static inline uint8_t sd_dummy(void)
{
return spi_xfer(0xFF);
}
static uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc)
{
unsigned long n;
uint8_t r;
REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
sd_dummy();
spi_xfer(cmd);
spi_xfer(arg >> 24);
spi_xfer(arg >> 16);
spi_xfer(arg >> 8);
spi_xfer(arg);
spi_xfer(crc);
n = 1000;
do {
r = sd_dummy();
if (!(r & 0x80)) {
// dprintf("sd:cmd: %hx\r\n", r);
goto done;
}
} while (--n > 0);
kputs("sd_cmd: timeout");
done:
return r;
}
static inline void sd_cmd_end(void)
{
sd_dummy();
REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
}
static void sd_poweron(void)
{
long i;
REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL);
REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF;
for (i = 10; i > 0; i--) {
sd_dummy();
}
REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
}
static int sd_cmd0(void)
{
int rc;
dputs("CMD0");
rc = (sd_cmd(0x40, 0, 0x95) != 0x01);
sd_cmd_end();
return rc;
}
static int sd_cmd8(void)
{
int rc;
dputs("CMD8");
rc = (sd_cmd(0x48, 0x000001AA, 0x87) != 0x01);
sd_dummy(); /* command version; reserved */
sd_dummy(); /* reserved */
rc |= ((sd_dummy() & 0xF) != 0x1); /* voltage */
rc |= (sd_dummy() != 0xAA); /* check pattern */
sd_cmd_end();
return rc;
}
static void sd_cmd55(void)
{
sd_cmd(0x77, 0, 0x65);
sd_cmd_end();
}
static int sd_acmd41(void)
{
uint8_t r;
dputs("ACMD41");
do {
sd_cmd55();
r = sd_cmd(0x69, 0x40000000, 0x77); /* HCS = 1 */
} while (r == 0x01);
return (r != 0x00);
}
static int sd_cmd58(void)
{
int rc;
dputs("CMD58");
rc = (sd_cmd(0x7A, 0, 0xFD) != 0x00);
rc |= ((sd_dummy() & 0x80) != 0x80); /* Power up status */
sd_dummy();
sd_dummy();
sd_dummy();
sd_cmd_end();
return rc;
}
static int sd_cmd16(void)
{
int rc;
dputs("CMD16");
rc = (sd_cmd(0x50, 0x200, 0x15) != 0x00);
sd_cmd_end();
return rc;
}
static uint16_t crc16_round(uint16_t crc, uint8_t data) {
crc = (uint8_t)(crc >> 8) | (crc << 8);
crc ^= data;
crc ^= (uint8_t)(crc >> 4) & 0xf;
crc ^= crc << 12;
crc ^= (crc & 0xff) << 5;
return crc;
}
#define SPIN_SHIFT 6
#define SPIN_UPDATE(i) (!((i) & ((1 << SPIN_SHIFT)-1)))
#define SPIN_INDEX(i) (((i) >> SPIN_SHIFT) & 0x3)
static const char spinner[] = { '-', '/', '|', '\\' };
static int copy(void)
{
volatile uint8_t *p = (void *)(PAYLOAD_DEST);
long i = PAYLOAD_SIZE;
int rc = 0;
dputs("CMD18");
kprintf("LOADING ");
// John: Let's go slow until we get this working
//REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL);
REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL);
if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) {
sd_cmd_end();
return 1;
}
do {
uint16_t crc, crc_exp;
long n;
crc = 0;
n = 512;
while (sd_dummy() != 0xFE);
do {
uint8_t x = sd_dummy();
*p++ = x;
crc = crc16_round(crc, x);
} while (--n > 0);
crc_exp = ((uint16_t)sd_dummy() << 8);
crc_exp |= sd_dummy();
if (crc != crc_exp) {
kputs("\b- CRC mismatch ");
rc = 1;
break;
}
if (SPIN_UPDATE(i)) {
kputc('\b');
kputc(spinner[SPIN_INDEX(i)]);
}
} while (--i > 0);
sd_cmd_end();
sd_cmd(0x4C, 0, 0x01);
sd_cmd_end();
kputs("\b ");
return rc;
}
int main(void)
{
REG32(uart, UART_REG_TXCTRL) = UART_TXEN;
kputs("INIT");
sd_poweron();
if (sd_cmd0() ||
sd_cmd8() ||
sd_acmd41() ||
sd_cmd58() ||
sd_cmd16() ||
copy()) {
kputs("ERROR");
return 1;
}
kputs("BOOT");
__asm__ __volatile__ ("fence.i" : : : "memory");
return 0;
}

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// See LICENSE for license details.
package chipyard.fpga.arty
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
import freechips.rocketchip.system._
import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
import testchipip.{SerialTLKey}
import chipyard.{BuildSystem}
class WithDefaultPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(
UARTParams(address = 0x10013000))
case DTSTimebase => BigInt(32768)
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2,
idcodePartNum = 0x000,
idcodeManufId = 0x489,
debugIdleCycles = 5)
case SerialTLKey => None // remove serialized tl port
})
// DOC include start: AbstractArty and Rocket
class WithArtyTweaks extends Config(
new WithArtyJTAGHarnessBinder ++
new WithArtyUARTHarnessBinder ++
new WithArtyResetHarnessBinder ++
new WithDebugResetPassthrough ++
new WithDefaultPeripherals ++
new freechips.rocketchip.subsystem.WithNBreakpoints(2))
class TinyRocketArtyConfig extends Config(
new WithArtyTweaks ++
new chipyard.TinyRocketConfig)
// DOC include end: AbstractArty and Rocket

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package chipyard.fpga.arty
import chisel3._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.jtag._
import sifive.blocks.devices.pinctrl._
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
require(ports.size == 2)
withClockAndReset(th.clock_32MHz, th.ck_rst) {
// Debug module reset
th.dut_ndreset := ports(0)
// JTAG reset
ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
}
}
})
class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
ports.map {
case j: JTAGIO =>
withClockAndReset(th.harnessClock, th.hReset) {
val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
JTAGPinsFromPort(io_jtag, j)
io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool
IOBUF(th.jd_5, io_jtag.TMS)
PULLUP(th.jd_5)
IOBUF(th.jd_4, io_jtag.TDI)
PULLUP(th.jd_4)
IOBUF(th.jd_0, io_jtag.TDO)
// mimic putting a pullup on this line (part of reset vote)
th.SRST_n := IOBUF(th.jd_6)
PULLUP(th.jd_6)
// ignore the po input
io_jtag.TCK.i.po.map(_ := DontCare)
io_jtag.TDI.i.po.map(_ := DontCare)
io_jtag.TMS.i.po.map(_ := DontCare)
io_jtag.TDO.i.po.map(_ := DontCare)
}
}
}
})
class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_txd_in, ports.head.txd)
ports.head.rxd := IOBUF(th.uart_rxd_out)
}
}
})

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package chipyard.fpga.arty
import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.util._
import freechips.rocketchip.devices.debug._
import chipyard.iobinders.{ComposeIOBinder}
class WithDebugResetPassthrough extends ComposeIOBinder({
(system: HasPeripheryDebugModuleImp) => {
// Debug module reset
val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset")
io_ndreset := system.debug.get.ndreset
// JTAG reset
val sjtag = system.debug.get.systemjtag.get
val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
sjtag.reset := io_sjtag_reset
(Seq(io_ndreset, io_sjtag_reset), Nil)
}
})

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fpga/src/main/scala/arty/TestHarness.scala Normal file
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package chipyard.fpga.arty
import chisel3._
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions}
import chipyard.harness.{ApplyHarnessBinders}
import chipyard.iobinders.{HasIOBinders}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
// Convert harness resets from Bool to Reset type.
val hReset = Wire(Reset())
hReset := ck_rst
val dReset = Wire(AsyncReset())
dReset := reset_core.asAsyncReset
// default to 32MHz clock
withClockAndReset(clock_32MHz, hReset) {
val dut = Module(lazyDut.module)
}
val harnessClock = clock_32MHz
val harnessReset = hReset
val success = false.B
val dutReset = dReset
// must be after HasHarnessSignalReferences assignments
lazyDut match { case d: HasTestHarnessFunctions =>
d.harnessFunctions.foreach(_(this))
}
lazyDut match { case d: HasIOBinders =>
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}
}

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fpga/src/main/scala/vcu118/Configs.scala Normal file
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package chipyard.fpga.vcu118
import sys.process._
import freechips.rocketchip.config.{Config, Parameters}
import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet}
import freechips.rocketchip.tile.{XLen}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import testchipip.{SerialTLKey}
import chipyard.{BuildSystem, ExtTLMem}
class WithDefaultPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))
case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L)))
case VCU118ShellPMOD => "SDIO"
})
class WithSystemModifications extends Config((site, here, up) => {
case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000))
case DTSTimebase => BigInt(1000000)
case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
// invoke makefile for sdboot
val freqMHz = site(FPGAFrequencyKey).toInt * 1000000
val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin"
require (make.! == 0, "Failed to build bootrom")
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
}
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size
case SerialTLKey => None // remove serialized tl port
})
// DOC include start: AbstractVCU118 and Rocket
class WithVCU118Tweaks extends Config(
new WithUART ++
new WithSPISDCard ++
new WithDDRMem ++
new WithUARTIOPassthrough ++
new WithSPIIOPassthrough ++
new WithTLIOPassthrough ++
new WithDefaultPeripherals ++
new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
new chipyard.config.WithNoDebug ++ // remove debug module
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1))
class RocketVCU118Config extends Config(
new WithVCU118Tweaks ++
new chipyard.RocketConfig)
// DOC include end: AbstractVCU118 and Rocket
class BoomVCU118Config extends Config(
new WithFPGAFrequency(50) ++
new WithVCU118Tweaks ++
new chipyard.MegaBoomConfig)
class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => {
case FPGAFrequencyKey => MHz
})
class WithFPGAFreq25MHz extends WithFPGAFrequency(25)
class WithFPGAFreq50MHz extends WithFPGAFrequency(50)
class WithFPGAFreq75MHz extends WithFPGAFrequency(75)
class WithFPGAFreq100MHz extends WithFPGAFrequency(100)

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package chipyard.fpga.vcu118
import chisel3._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
import sifive.fpgashells.shell._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.clocks._
import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
class SysClock2VCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput)
extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput)
{
val node = shell { ClockSourceNode(freqMHz = 250, jitterPS = 50)(ValName(name)) }
shell { InModuleBody {
shell.xdc.addPackagePin(io.p, "AW26")
shell.xdc.addPackagePin(io.n, "AW27")
shell.xdc.addIOStandard(io.p, "DIFF_SSTL12")
shell.xdc.addIOStandard(io.n, "DIFF_SSTL12")
} }
}
class SysClock2VCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName)
extends ClockInputShellPlacer[VCU118ShellBasicOverlays]
{
def place(designInput: ClockInputDesignInput) = new SysClock2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
}
case object VCU118DDR2Size extends Field[BigInt](0x40000000L * 2) // 2GB
class DDR2VCU118PlacedOverlay(val shell: VCU118FPGATestHarness, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput)
extends DDRPlacedOverlay[XilinxVCU118MIGPads](name, designInput, shellInput)
{
val size = p(VCU118DDRSize)
val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(di.baseAddress, size))
val mig = LazyModule(new XilinxVCU118MIG(migParams))
val ioNode = BundleBridgeSource(() => mig.module.io.cloneType)
val topIONode = shell { ioNode.makeSink() }
val ddrUI = shell { ClockSourceNode(freqMHz = 200) }
val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) }
areset := designInput.wrangler := ddrUI
// since this uses a separate clk/rst need to put an async crossing
val asyncSink = LazyModule(new TLAsyncCrossingSink())
val migClkRstNode = BundleBridgeSource(() => new Bundle {
val clock = Output(Clock())
val reset = Output(Bool())
})
val topMigClkRstIONode = shell { migClkRstNode.makeSink() }
def overlayOutput = DDROverlayOutput(ddr = mig.node)
def ioFactory = new XilinxVCU118MIGPads(size)
InModuleBody {
ioNode.bundle <> mig.module.io
// setup async crossing
asyncSink.module.clock := migClkRstNode.bundle.clock
asyncSink.module.reset := migClkRstNode.bundle.reset
}
shell { InModuleBody {
require (shell.sys_clock2.get.isDefined, "Use of DDRVCU118Overlay depends on SysClock2VCU118Overlay")
val (sys, _) = shell.sys_clock2.get.get.overlayOutput.node.out(0)
val (ui, _) = ddrUI.out(0)
val (ar, _) = areset.in(0)
// connect the async fifo sync to sys_clock2
topMigClkRstIONode.bundle.clock := sys.clock
topMigClkRstIONode.bundle.reset := sys.reset
val port = topIONode.bundle.port
io <> port
ui.clock := port.c0_ddr4_ui_clk
ui.reset := /*!port.mmcm_locked ||*/ port.c0_ddr4_ui_clk_sync_rst
port.c0_sys_clk_i := sys.clock.asUInt
port.sys_rst := sys.reset // pllReset
port.c0_ddr4_aresetn := !ar.reset
// This was just copied from the SiFive example, but it's hard to follow.
// The pins are emitted in the following order:
// adr[0->13], we_n, cas_n, ras_n, bg, ba[0->1], reset_n, act_n, ck_c, ck_t, cke, cs_n, odt, dq[0->63], dqs_c[0->7], dqs_t[0->7], dm_dbi_n[0->7]
val allddrpins = Seq(
"AM27", "AL27", "AP26", "AP25", "AN28", "AM28", "AP28", "AP27", "AN26", "AM26", "AR28", "AR27", "AV25", "AT25", // adr[0->13]
"AV28", "AU26", "AV26", "AU27", // we_n, cas_n, ras_n, bg
"AR25", "AU28", // ba[0->1]
"BD35", "AN25", "AT27", "AT26", "AW28", "AY29", "BB29", // reset_n, act_n, ck_c, ck_t, cke, cs_n, odt
"BD30", "BE30", "BD32", "BE33", "BC33", "BD33", "BC31", "BD31", "BA32", "BB33", "BA30", "BA31", "AW31", "AW32", "AY32", "AY33", // dq[0->15]
"AV30", "AW30", "AU33", "AU34", "AT31", "AU32", "AU31", "AV31", "AR33", "AT34", "AT29", "AT30", "AP30", "AR30", "AN30", "AN31", // dq[16->31]
"BE34", "BF34", "BC35", "BC36", "BD36", "BE37", "BF36", "BF37", "BD37", "BE38", "BC39", "BD40", "BB38", "BB39", "BC38", "BD38", // dq[32->47]
"BB36", "BB37", "BA39", "BA40", "AW40", "AY40", "AY38", "AY39", "AW35", "AW36", "AU40", "AV40", "AU38", "AU39", "AV38", "AV39", // dq[48->63]
"BF31", "BA34", "AV29", "AP32", "BF35", "BF39", "BA36", "AW38", // dqs_c[0->7]
"BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7]
"BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7]
(IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) }
} }
shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk))
}
class DDR2VCU118ShellPlacer(shell: VCU118FPGATestHarness, val shellInput: DDRShellInput)(implicit val valName: ValName)
extends DDRShellPlacer[VCU118FPGATestHarness] {
def place(designInput: DDRDesignInput) = new DDR2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
}

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package chipyard.fpga.vcu118
import scala.collection.immutable.HashMap
// TODO: was typed by hand, so this needs a once-over before it can be considered trustworthy
object FMCMap {
// Take an FMC pin name and return the VCU118 package pin
// See https://www.xilinx.com/support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf
// Pages 97-98
// Omitted pins are not connected to a GPIO
def apply(fmcPin: String): String = HashMap(
"C10" -> "BD13",
"C11" -> "BE13",
"C14" -> "BB13",
"C15" -> "BB12",
"C18" -> "AW8",
"C19" -> "AW7",
"C22" -> "AP12",
"C23" -> "AR12",
"C26" -> "AL14",
"C27" -> "AM14",
"D1" -> "AK35",
"D8" -> "BF10",
"D9" -> "BF9",
"D11" -> "BE14",
"D12" -> "BF14",
"D14" -> "BA14",
"D15" -> "BB14",
"D17" -> "AY8",
"D18" -> "AY7",
"D20" -> "AR14",
"D21" -> "AT14",
"D23" -> "AN16",
"D24" -> "AP16",
"D26" -> "AK15",
"D27" -> "AL15",
"F1" -> "BA7",
"G2" -> "AV14",
"G3" -> "AV13",
"G6" -> "AY9",
"G7" -> "BA9",
"G9" -> "BD12",
"G10" -> "BE12",
"G12" -> "BE15",
"G13" -> "BF15",
"G15" -> "BC14",
"G16" -> "BC13",
"G18" -> "AV9",
"G19" -> "AV8",
"G21" -> "AW11",
"G22" -> "AY10",
"G24" -> "AW13",
"G25" -> "AY13",
"G27" -> "AT12",
"G28" -> "AU12",
"G30" -> "AN15",
"G31" -> "AP15",
"G33" -> "AM13",
"G34" -> "AM12",
"G36" -> "AK14",
"G37" -> "AK13",
"H2" -> "BB7",
"H4" -> "BC9",
"H5" -> "BC8",
"H7" -> "BC11",
"H8" -> "BD11",
"H10" -> "BF12",
"H11" -> "BF11",
"H13" -> "BC15",
"H14" -> "BD15",
"H16" -> "BA16",
"H17" -> "BA15",
"H19" -> "BB16",
"H20" -> "BC16",
"H22" -> "AW12",
"H23" -> "AY12",
"H25" -> "AU11",
"H26" -> "AV11",
"H28" -> "AP13",
"H29" -> "AR13",
"H31" -> "AV10",
"H32" -> "AW10",
"H34" -> "AK12",
"H35" -> "AL12",
"H37" -> "AJ13",
"H38" -> "AJ12"
)(fmcPin)
}
object FMCPMap {
// Take an FMC+ pin name and return the VCU118 package pin
// See https://www.xilinx.com/support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf
// Pages 100-106
// Omitted pins are not connected to a GPIO
def apply(fmcpPin: String): String = HashMap(
"A2" -> "AN45",
"A3" -> "AN46",
"A6" -> "AL45",
"A7" -> "AL45",
"A10" -> "AJ45",
"A11" -> "AJ46",
"A14" -> "W45",
"A15" -> "W46",
"A18" -> "U45",
"A19" -> "U46",
"A22" -> "AP42",
"A23" -> "AP43",
"A26" -> "AM42",
"A27" -> "AM43",
"A30" -> "AL40",
"A31" -> "AL41",
"A34" -> "T42",
"A35" -> "T43",
"A38" -> "P42",
"A39" -> "P43",
"B4" -> "AF43",
"B5" -> "AF44",
"B8" -> "AG45",
"B9" -> "AG46",
"B12" -> "N45",
"B13" -> "N46",
"B16" -> "R45",
"B17" -> "R46",
"B24" -> "AJ40",
"B25" -> "AJ41",
"B28" -> "AK42",
"B29" -> "AK43",
"B32" -> "K42",
"B33" -> "K43",
"B36" -> "M42",
"B37" -> "M43",
"C2" -> "AT42",
"C3" -> "AT43",
"C6" -> "AR45",
"C7" -> "AR46",
"C10" -> "AT35",
"C11" -> "AT36",
"C14" -> "AP35",
"C15" -> "AR35",
"C18" -> "AG31",
"C19" -> "AH31",
"C22" -> "R31",
"C23" -> "P31",
"C26" -> "V33",
"C27" -> "V34",
"D1" -> "AK35",
"D8" -> "AL30",
"D9" -> "AL31",
"D11" -> "AP38",
"D12" -> "AR38",
"D14" -> "AJ33",
"D15" -> "AK33",
"D17" -> "AJ35",
"D18" -> "AJ36",
"D20" -> "R34",
"D21" -> "P34",
"D23" -> "Y32",
"D24" -> "W32",
"D26" -> "V32",
"D27" -> "U33",
"E2" -> "V15",
"E3" -> "U15",
"E6" -> "R14",
"E7" -> "P14",
"E9" -> "W14",
"E10" -> "V14",
"E12" -> "V13",
"E13" -> "U12",
"E15" -> "T14",
"E16" -> "R13",
"E18" -> "M15",
"E19" -> "L15",
"F1" -> "AM34",
"F4" -> "N14",
"F5" -> "N13",
"F7" -> "AA13",
"F8" -> "Y13",
"F10" -> "U11",
"F11" -> "T11",
"F13" -> "T16",
"F14" -> "T15",
"F16" -> "M13",
"F17" -> "M12",
"F19" -> "L14",
"F20" -> "L13",
"G2" -> "P35",
"G3" -> "P36",
"G6" -> "AL35",
"G7" -> "AL36",
"G9" -> "AT39",
"G10" -> "AT40",
"G12" -> "AK29",
"G13" -> "AK30",
"G15" -> "AH33",
"G16" -> "AH34",
"G18" -> "AG34",
"G19" -> "AH35",
"G21" -> "N32",
"G22" -> "M32",
"G24" -> "N34",
"G25" -> "N35",
"G27" -> "Y34",
"G28" -> "W34",
"G30" -> "U35",
"G31" -> "T36",
"G33" -> "P37",
"G34" -> "N37",
"G36" -> "L34",
"G37" -> "K34",
"H2" -> "AM33",
"H4" -> "AL32",
"H5" -> "AM32",
"H7" -> "AJ32",
"H8" -> "AK32",
"H10" -> "AR37",
"H11" -> "AT37",
"H13" -> "AP36",
"H14" -> "AP37",
"H16" -> "AJ30",
"H17" -> "AJ31",
"H19" -> "AG32",
"H20" -> "AG33",
"H22" -> "N33",
"H23" -> "M33",
"H25" -> "M35",
"H26" -> "L35",
"H28" -> "T34",
"H29" -> "T35",
"H31" -> "M36",
"H32" -> "L36",
"H34" -> "N38",
"H35" -> "M38",
"H37" -> "L33",
"H38" -> "K33",
"J6" -> "W12",
"J7" -> "V12",
"J9" -> "AA14",
"J10" -> "Y14",
"J12" -> "R12",
"J13" -> "P12",
"J15" -> "M11",
"J16" -> "L11",
"J18" -> "P15",
"J19" -> "N15",
"J21" -> "K12",
"J22" -> "J12",
"K7" -> "AA12",
"K8" -> "Y12",
"K10" -> "U13",
"K11" -> "T13",
"K13" -> "V16",
"K14" -> "U16",
"K16" -> "R11",
"K17" -> "P11",
"K19" -> "K14",
"K20" -> "K13",
"K22" -> "K11",
"K23" -> "J11",
"L4" -> "R40",
"L5" -> "R41",
"L8" -> "AB38",
"L9" -> "AB39",
"L12" -> "AF38",
"L13" -> "AF39",
"L16" -> "AN34",
"L17" -> "AN35",
"L20" -> "AN33",
"L21" -> "AP33",
"L24" -> "AK34",
"L25" -> "AL34",
"L28" -> "AM36",
"L29" -> "AN36",
"M2" -> "AU45",
"M3" -> "AU46",
"M6" -> "AW45",
"M7" -> "AW46",
"M10" -> "BA45",
"M11" -> "BA46",
"M14" -> "BC45",
"M15" -> "BC46",
"M18" -> "W40",
"M19" -> "W41",
"M22" -> "U40",
"M23" -> "U41",
"M26" -> "H42",
"M27" -> "H43",
"M30" -> "F42",
"M31" -> "F43",
"M34" -> "D42",
"M35" -> "D43",
"M38" -> "B42",
"M39" -> "B43",
"Y2" -> "AV42",
"Y3" -> "AV43",
"Y6" -> "BB42",
"Y7" -> "BB43",
"Y10" -> "AE45",
"Y11" -> "AE46",
"Y14" -> "AC45",
"Y15" -> "AC46",
"Y18" -> "AA45",
"Y19" -> "AA46",
"Y22" -> "Y43",
"Y23" -> "Y44",
"Y26" -> "AE40",
"Y27" -> "AE41",
"Y30" -> "AA40",
"Y31" -> "AA41",
"Y34" -> "J45",
"Y35" -> "J46",
"Y38" -> "E45",
"Y39" -> "E46",
"Z1" -> "AM29",
"Z4" -> "AY42",
"Z5" -> "AY43",
"Z8" -> "BD42",
"Z9" -> "BD43",
"Z12" -> "AD43",
"Z13" -> "AD44",
"Z16" -> "AB43",
"Z17" -> "AB44",
"Z20" -> "AN40",
"Z21" -> "AN41",
"Z24" -> "AG40",
"Z25" -> "AG41",
"Z28" -> "AC40",
"Z29" -> "AC41",
"Z32" -> "L45",
"Z33" -> "L46",
"Z36" -> "G45",
"Z37" -> "G46"
)(fmcpPin)
}

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fpga/src/main/scala/vcu118/HarnessBinders.scala Normal file
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package chipyard.fpga.vcu118
import chisel3._
import chisel3.experimental.{BaseModule}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort}
import chipyard.harness.{OverrideHarnessBinder}
/*** UART ***/
class WithUART extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
th match { case vcu118th: VCU118FPGATestHarnessImp => {
vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head
} }
}
})
/*** SPI ***/
class WithSPISDCard extends OverrideHarnessBinder({
(system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {
th match { case vcu118th: VCU118FPGATestHarnessImp => {
vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head
} }
}
})
/*** Experimental DDR ***/
class WithDDRMem extends OverrideHarnessBinder({
(system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
th match { case vcu118th: VCU118FPGATestHarnessImp => {
require(ports.size == 1)
val bundles = vcu118th.vcu118Outer.ddrClient.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
ddrClientBundle <> ports.head
} }
}
})

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fpga/src/main/scala/vcu118/IOBinders.scala Normal file
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package chipyard.fpga.vcu118
import chisel3._
import chisel3.experimental.{IO, DataMirror}
import freechips.rocketchip.diplomacy.{ResourceBinding, Resource, ResourceAddress, InModuleBody}
import freechips.rocketchip.subsystem.{BaseSubsystem}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp}
import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice}
import chipyard.{CanHaveMasterTLMemPort}
import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder}
class WithUARTIOPassthrough extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp) => {
val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") }
(io_uart_pins_temp zip system.uart).map { case (io, sysio) =>
io <> sysio
}
(io_uart_pins_temp, Nil)
}
})
class WithSPIIOPassthrough extends OverrideLazyIOBinder({
(system: HasPeripherySPI) => {
// attach resource to 1st SPI
ResourceBinding {
Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
}
InModuleBody {
system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => {
val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") }
(io_spi_pins_temp zip system.spi).map { case (io, sysio) =>
io <> sysio
}
(io_spi_pins_temp, Nil)
} }
}
}
})
class WithTLIOPassthrough extends OverrideIOBinder({
(system: CanHaveMasterTLMemPort) => {
val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
io_tl_mem_pins_temp <> system.mem_tl
(Seq(io_tl_mem_pins_temp), Nil)
}
})

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fpga/src/main/scala/vcu118/TestHarness.scala Normal file
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package chipyard.fpga.vcu118
import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell._
import sifive.fpgashells.clocks._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.gpio._
import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort}
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness.{ApplyHarnessBinders}
case object FPGAFrequencyKey extends Field[Double](100.0)
class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays {
def dp = designParameters
val pmod_is_sdio = p(VCU118ShellPMOD) == "SDIO"
val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52")
// Order matters; ddr depends on sys_clock
val uart = Overlay(UARTOverlayKey, new UARTVCU118ShellPlacer(this, UARTShellInput()))
val sdio = if (pmod_is_sdio) Some(Overlay(SPIOverlayKey, new SDIOVCU118ShellPlacer(this, SPIShellInput()))) else None
val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVCU118ShellPlacer(this, JTAGDebugShellInput(location = jtag_location)))
val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVCU118ShellPlacer(this, cJTAGDebugShellInput()))
val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput()))
val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput()))
val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput()))
val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput()))
val ddr2 = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput()))
val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
// DOC include start: ClockOverlay
// place all clocks in the shell
require(dp(ClockInputOverlayKey).size >= 1)
val sysClkNode = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()).overlayOutput.node
/*** Connect/Generate clocks ***/
// connect to the PLL that will generate multiple clocks
val harnessSysPLL = dp(PLLFactoryKey)()
harnessSysPLL := sysClkNode
// create and connect to the dutClock
val dutClock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey))
val dutWrangler = LazyModule(new ResetWrangler)
val dutGroup = ClockGroup()
dutClock := dutWrangler.node := dutGroup := harnessSysPLL
// DOC include end: ClockOverlay
/*** UART ***/
// DOC include start: UartOverlay
// 1st UART goes to the VCU118 dedicated UART
val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head)))
dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
// DOC include end: UartOverlay
/*** SPI ***/
// 1st SPI goes to the VCU118 SDIO port
val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head)))
dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb))
/*** DDR ***/
val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr
// connect 1 mem. channel to the FPGA DDR
val inParams = topDesign match { case td: ChipTop =>
td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
lsys.memTLNode.edges.in(0)
}
}
val ddrClient = TLClientNode(Seq(inParams.master))
ddrNode := ddrClient
// module implementation
override lazy val module = new VCU118FPGATestHarnessImp(this)
}
class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
val vcu118Outer = _outer
val reset = IO(Input(Bool()))
_outer.xdc.addPackagePin(reset, "L19")
_outer.xdc.addIOStandard(reset, "LVCMOS12")
val resetIBUF = Module(new IBUF)
resetIBUF.io.I := reset
val sysclk: Clock = _outer.sysClkNode.out.head._1.clock
val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
_outer.sdc.addAsyncPath(Seq(powerOnReset))
val ereset: Bool = _outer.chiplink.get() match {
case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n
case _ => false.B
}
_outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset)
// reset setup
val hReset = Wire(Reset())
hReset := _outer.dutClock.in.head._1.reset
val harnessClock = _outer.dutClock.in.head._1.clock
val harnessReset = WireInit(hReset)
val dutReset = hReset.asAsyncReset
val success = false.B
childClock := harnessClock
childReset := harnessReset
// harness binders are non-lazy
_outer.topDesign match { case d: HasTestHarnessFunctions =>
d.harnessFunctions.foreach(_(this))
}
_outer.topDesign match { case d: HasIOBinders =>
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}
}

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fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala Normal file
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package chipyard.fpga.vcu118.bringup
import scala.collection.mutable.{LinkedHashMap}
object BringupGPIOs {
// map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD)
val pinMapping = LinkedHashMap(
// these connect to LEDs and switches on the VCU118 (and use 1.2V)
"led0" -> ("AT32", "LVCMOS12"), // 0
"led1" -> ("AV34", "LVCMOS12"), // 1
"led2" -> ("AY30", "LVCMOS12"), // 2
"led3" -> ("BB32", "LVCMOS12"), // 3
"led4" -> ("BF32", "LVCMOS12"), // 4
"led5" -> ("AU37", "LVCMOS12"), // 5
"led6" -> ("AV36", "LVCMOS12"), // 6
"led7" -> ("BA37", "LVCMOS12"), // 7
"sw0" -> ("B17", "LVCMOS12"), // 8
"sw1" -> ("G16", "LVCMOS12"), // 9
"sw2" -> ("J16", "LVCMOS12"), // 10
"sw3" -> ("D21", "LVCMOS12") // 11
)
// return list of names (ordered)
def names: Seq[String] = pinMapping.keys.toSeq
// return number of GPIOs
def width: Int = pinMapping.size
}

97
fpga/src/main/scala/vcu118/bringup/Configs.scala Normal file
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package chipyard.fpga.vcu118.bringup
import math.min
import freechips.rocketchip.config.{Config, Parameters}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{MasterPortParams}
import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams}
import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
import chipyard.{BuildSystem}
import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size}
class WithBringupPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L)))
case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L)))
case PeripheryGPIOKey => {
if (BringupGPIOs.width > 0) {
require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more)
val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000))
val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32)
List.tabulate(((BringupGPIOs.width - 1)/maxGPIOSupport) + 1)(n => {
GPIOParams(address = gpioAddrs(n), width = min(BringupGPIOs.width - maxGPIOSupport*n, maxGPIOSupport))
})
}
else {
List.empty[GPIOParams]
}
}
case TSIClockMaxFrequencyKey => 100
case PeripheryTSIHostKey => List(
TSIHostParams(
offchipSerialIfWidth = 4,
mmioBaseAddress = BigInt(0x64006000),
mmioSourceId = 1 << 13, // manager source
serdesParams = TSIHostSerdesParams(
clientPortParams = TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
name = "tl-tsi-host-serdes",
sourceId = IdRange(0, (1 << 13))))),
managerPortParams = TLSlavePortParameters.v1(
managers = Seq(TLSlaveParameters.v1(
address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), // access everything on chip
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(1, 64),
supportsPutFull = TransferSizes(1, 64),
supportsPutPartial = TransferSizes(1, 64),
supportsAcquireT = TransferSizes(1, 64),
supportsAcquireB = TransferSizes(1, 64),
supportsArithmetic = TransferSizes(1, 64),
supportsLogical = TransferSizes(1, 64))),
endSinkId = 1 << 6, // manager sink
beatBytes = 8)),
targetMasterPortParams = MasterPortParams(
base = BigInt("80000000", 16),
size = site(VCU118DDR2Size),
beatBytes = 8, // comes from test chip
idBits = 4) // comes from VCU118 idBits in XilinxVCU118MIG
))
})
class WithBringupVCU118System extends Config((site, here, up) => {
case BuildSystem => (p: Parameters) => new BringupVCU118DigitalTop()(p) // use the VCU118-extended bringup digital top
})
class WithBringupAdditions extends Config(
new WithBringupUART ++
new WithBringupI2C ++
new WithBringupGPIO ++
new WithBringupTSIHost ++
new WithTSITLIOPassthrough ++
new WithI2CIOPassthrough ++
new WithGPIOIOPassthrough ++
new WithBringupPeripherals ++
new WithBringupVCU118System)
class RocketBringupConfig extends Config(
new WithBringupAdditions ++
new WithVCU118Tweaks ++
new chipyard.RocketConfig)
class BoomBringupConfig extends Config(
new WithFPGAFrequency(50) ++
new WithBringupAdditions ++
new WithVCU118Tweaks ++
new chipyard.MegaBoomConfig)

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fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala Normal file
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package chipyard.fpga.vcu118.bringup
import chisel3._
import chisel3.experimental.{attach}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
import sifive.fpgashells.shell._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.clocks._
import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
import testchipip.{TSIHostWidgetIO}
import chipyard.fpga.vcu118.{FMCPMap}
/* Connect the I2C to certain FMC pins */
class BringupI2CVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput)
extends I2CXilinxPlacedOverlay(name, designInput, shellInput)
{
shell { InModuleBody {
require(shellInput.index == 0) // only support 1 I2C <-> FMC connection
val i2cLocations = List(List(FMCPMap("K11"), FMCPMap("E2")))
val packagePinsWithPackageIOs = Seq((i2cLocations(shellInput.index)(0), IOPin(io.scl)),
(i2cLocations(shellInput.index)(1), IOPin(io.sda)))
packagePinsWithPackageIOs foreach { case (pin, io) => {
shell.xdc.addPackagePin(io, pin)
shell.xdc.addIOStandard(io, "LVCMOS18")
shell.xdc.addIOB(io)
} }
} }
}
class BringupI2CVCU118ShellPlacer(val shell: VCU118ShellBasicOverlays, val shellInput: I2CShellInput)(implicit val valName: ValName)
extends I2CShellPlacer[VCU118ShellBasicOverlays]
{
def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
}
/* Connect the UART to certain FMC pins */
class BringupUARTVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput)
extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true)
{
shell { InModuleBody {
val packagePinsWithPackageIOs = Seq((FMCPMap("E9"), IOPin(io.ctsn.get)), // unused
(FMCPMap("E10"), IOPin(io.rtsn.get)), // unused
(FMCPMap("C15"), IOPin(io.rxd)),
(FMCPMap("C14"), IOPin(io.txd)))
packagePinsWithPackageIOs foreach { case (pin, io) => {
shell.xdc.addPackagePin(io, pin)
shell.xdc.addIOStandard(io, "LVCMOS18")
shell.xdc.addIOB(io)
} }
// add pullup on ctsn (ctsn is an input that is not used or driven)
packagePinsWithPackageIOs take 1 foreach { case (pin, io) => {
shell.xdc.addPullup(io)
} }
} }
}
class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: UARTShellInput)(implicit val valName: ValName)
extends UARTShellPlacer[VCU118ShellBasicOverlays] {
def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
}
/* Connect GPIOs to FPGA I/Os */
abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput)
extends GPIOPlacedOverlay(name, di, si)
{
def shell: XilinxShell
shell { InModuleBody {
(io.gpio zip tlgpioSink.bundle.pins).map { case (ioPin, sinkPin) =>
val iobuf = Module(new IOBUF)
iobuf.suggestName(s"gpio_iobuf")
attach(ioPin, iobuf.io.IO)
sinkPin.i.ival := iobuf.io.O
iobuf.io.T := !sinkPin.o.oe
iobuf.io.I := sinkPin.o.oval
}
} }
}
class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String])
extends GPIOXilinxPlacedOverlay(name, designInput, shellInput)
{
shell { InModuleBody {
require(gpioNames.length == io.gpio.length)
val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) =>
val (pin, iostd) = BringupGPIOs.pinMapping(name)
(pin, iostd, IOPin(io))
}
packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, io) => {
shell.xdc.addPackagePin(io, pin)
shell.xdc.addIOStandard(io, iostd)
if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") }
} }
} }
}
class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName)
extends GPIOShellPlacer[VCU118ShellBasicOverlays] {
def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames)
}
case class TSIHostShellInput()
case class TSIHostDesignInput(
serialIfWidth: Int,
node: BundleBridgeSource[TSIHostWidgetIO]
)(
implicit val p: Parameters)
case class TSIHostOverlayOutput()
trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]
case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil)
abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput)
extends IOPlacedOverlay[IO, TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]
{
implicit val p = di.p
}
case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB
class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput)
extends TSIHostPlacedOverlay[TSIHostWidgetIO](name, designInput, shellInput)
{
val tlTsiSerialSink = di.node.makeSink()
val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.serialIfWidth))
val topTSIIONode = shell { tsiIoNode.makeSink() }
def overlayOutput = TSIHostOverlayOutput()
def ioFactory = new TSIHostWidgetIO(di.serialIfWidth)
InModuleBody {
// connect TSI serial
val tsiSourcePort = tsiIoNode.bundle
val tsiSinkPort = tlTsiSerialSink.bundle
tsiSinkPort.serial_clock := tsiSourcePort.serial_clock
tsiSourcePort.serial.out.bits := tsiSinkPort.serial.out.bits
tsiSourcePort.serial.out.valid := tsiSinkPort.serial.out.valid
tsiSinkPort.serial.out.ready := tsiSourcePort.serial.out.ready
tsiSinkPort.serial.in.bits := tsiSourcePort.serial.in.bits
tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid
tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready
}
}
case object TSIClockMaxFrequencyKey extends Field[Int](50) // in MHz
class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput)
extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput)
{
// connect the TSI port
shell { InModuleBody {
// connect TSI signals
val tsiPort = topTSIIONode.bundle
io <> tsiPort
require(di.serialIfWidth == 4)
val clkIo = IOPin(io.serial_clock)
val packagePinsWithPackageIOs = Seq(
(FMCPMap("D8"), clkIo),
(FMCPMap("D17"), IOPin(io.serial.out.ready)),
(FMCPMap("D18"), IOPin(io.serial.out.valid)),
(FMCPMap("D11"), IOPin(io.serial.out.bits, 0)),
(FMCPMap("D12"), IOPin(io.serial.out.bits, 1)),
(FMCPMap("D14"), IOPin(io.serial.out.bits, 2)),
(FMCPMap("D15"), IOPin(io.serial.out.bits, 3)),
(FMCPMap("D26"), IOPin(io.serial.in.ready)),
(FMCPMap("D27"), IOPin(io.serial.in.valid)),
(FMCPMap("D20"), IOPin(io.serial.in.bits, 0)),
(FMCPMap("D21"), IOPin(io.serial.in.bits, 1)),
(FMCPMap("D23"), IOPin(io.serial.in.bits, 2)),
(FMCPMap("D24"), IOPin(io.serial.in.bits, 3)))
packagePinsWithPackageIOs foreach { case (pin, io) => {
shell.xdc.addPackagePin(io, pin)
shell.xdc.addIOStandard(io, "LVCMOS18")
} }
// Don't add an IOB to the clock
(packagePinsWithPackageIOs take 1) foreach { case (pin, io) => {
shell.xdc.addIOB(io)
} }
shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequencyKey))
shell.sdc.addGroup(pins = Seq(clkIo))
shell.xdc.clockDedicatedRouteFalse(clkIo)
} }
}
class BringupTSIHostVCU118ShellPlacer(shell: BringupVCU118FPGATestHarness, val shellInput: TSIHostShellInput)(implicit val valName: ValName)
extends TSIHostShellPlacer[BringupVCU118FPGATestHarness] {
def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
}

26
fpga/src/main/scala/vcu118/bringup/DigitalTop.scala Normal file
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@@ -0,0 +1,26 @@
package chipyard.fpga.vcu118.bringup
import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import chipyard.{DigitalTop, DigitalTopModule}
// ------------------------------------
// Bringup VCU118 DigitalTop
// ------------------------------------
class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop
with sifive.blocks.devices.i2c.HasPeripheryI2C
with testchipip.HasPeripheryTSIHostWidget
{
override lazy val module = new BringupVCU118DigitalTopModule(this)
}
class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends DigitalTopModule(l)
with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp

70
fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala Normal file
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@@ -0,0 +1,70 @@
package chipyard.fpga.vcu118.bringup
import chisel3._
import chisel3.experimental.{Analog, IO, BaseModule}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort}
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.{HasHarnessSignalReferences}
import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
/*** UART ***/
class WithBringupUART extends ComposeHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
require(ports.size == 2)
vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last
} }
}
})
/*** I2C ***/
class WithBringupI2C extends OverrideHarnessBinder({
(system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
require(ports.size == 1)
vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head
} }
}
})
/*** GPIO ***/
class WithBringupGPIO extends OverrideHarnessBinder({
(system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
(vcu118th.bringupOuter.io_gpio_bb zip ports).map { case (bb_io, dut_io) =>
bb_io.bundle <> dut_io
}
} }
}
})
/*** TSI Host Widget ***/
class WithBringupTSIHost extends OverrideHarnessBinder({
(system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
require(ports.size == 2) // 1st goes to the TL mem, 2nd goes to the serial link
ports.head match { case tlPort: HeterogeneousBag[TLBundle] =>
val tsiBundles = vcu118th.bringupOuter.tsiDdrClient.out.map(_._1)
val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
tsiDdrClientBundle <> tlPort
}
ports.last match { case serialPort: TSIHostWidgetIO =>
vcu118th.bringupOuter.io_tsi_serial_bb.bundle <> serialPort
}
} }
}
})

47
fpga/src/main/scala/vcu118/bringup/IOBinders.scala Normal file
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@@ -0,0 +1,47 @@
package chipyard.fpga.vcu118.bringup
import chisel3._
import chisel3.experimental.{IO, DataMirror}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.iobinders.{OverrideIOBinder}
class WithGPIOIOPassthrough extends OverrideIOBinder({
(system: HasPeripheryGPIOModuleImp) => {
val io_gpio_pins_temp = system.gpio.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"gpio_$i") }
(io_gpio_pins_temp zip system.gpio).map { case (io, sysio) =>
io <> sysio
}
(io_gpio_pins_temp, Nil)
}
})
class WithI2CIOPassthrough extends OverrideIOBinder({
(system: HasPeripheryI2CModuleImp) => {
val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") }
(io_i2c_pins_temp zip system.i2c).map { case (io, sysio) =>
io <> sysio
}
(io_i2c_pins_temp, Nil)
}
})
class WithTSITLIOPassthrough extends OverrideIOBinder({
(system: HasPeripheryTSIHostWidget) => {
require(system.tsiTLMem.size == 1)
val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiTLMem.head)).suggestName("tsi_tl_slave")
io_tsi_tl_mem_pins_temp <> system.tsiTLMem.head
require(system.tsiSerial.size == 1)
val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial")
io_tsi_serial_pins_temp <> system.tsiSerial.head
(Seq(io_tsi_tl_mem_pins_temp, io_tsi_serial_pins_temp), Nil)
}
})

100
fpga/src/main/scala/vcu118/bringup/TestHarness.scala Normal file
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@@ -0,0 +1,100 @@
package chipyard.fpga.vcu118.bringup
import chisel3._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell._
import sifive.fpgashells.clocks._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.gpio._
import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter}
import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}
import chipyard.{ChipTop}
class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness {
/*** UART ***/
require(dp(PeripheryUARTKey).size == 2)
// 2nd UART goes to the FMC UART
val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput()))
val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last)))
dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb))
/*** I2C ***/
val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput()))
val io_i2c_bb = BundleBridgeSource(() => (new I2CPort))
dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb))
/*** GPIO ***/
val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => {
val maxGPIOSupport = 32 // max gpio per gpio chip
val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1))
Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names))
})
val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) }
(dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) =>
placer.place(GPIODesignInput(params, io_gpio_bb(i)))
}
/*** TSI Host Widget ***/
require(dp(PeripheryTSIHostKey).size == 1)
// use the 2nd system clock for the 2nd DDR
val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node
val ddr2PLL = dp(PLLFactoryKey)()
ddr2PLL := sysClk2Node
val ddr2Clock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey))
val ddr2Wrangler = LazyModule(new ResetWrangler)
val ddr2Group = ClockGroup()
ddr2Clock := ddr2Wrangler.node := ddr2Group := ddr2PLL
val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput()))
val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetMasterPortParams.base, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr
val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth)))
dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb))
// connect 1 mem. channel to the FPGA DDR
val inTsiParams = topDesign match { case td: ChipTop =>
td.lazySystem match { case lsys: HasPeripheryTSIHostWidget =>
lsys.tsiMemTLNodes.head.edges.in(0)
}
}
val tsiDdrClient = TLClientNode(Seq(inTsiParams.master))
(ddr2Node
:= TLFragmenter(8,64,holdFirstDeny=true)
:= TLCacheCork()
:= TLAtomicAutomata(passthrough=false)
:= TLSinkSetter(64)
:= tsiDdrClient)
// module implementation
override lazy val module = new BringupVCU118FPGATestHarnessImp(this)
}
class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) {
lazy val bringupOuter = _outer
}

4
generators/chipyard/src/main/scala/ChipTop.scala
View File

@@ -7,7 +7,7 @@ import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
import freechips.rocketchip.util.{ResetCatchAndSync} import freechips.rocketchip.util.{ResetCatchAndSync}
import chipyard.iobinders._ import chipyard.iobinders._
@@ -23,7 +23,7 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters)
* drive clock and reset generation * drive clock and reset generation
*/ */
class ChipTop(implicit p: Parameters) extends LazyModule class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
with HasTestHarnessFunctions with HasIOBinders { with HasTestHarnessFunctions with HasIOBinders {
// The system module specified by BuildSystem // The system module specified by BuildSystem
lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")

9
generators/chipyard/src/main/scala/ConfigFragments.scala
View File

@@ -184,6 +184,15 @@ class WithNoDebug extends Config((site, here, up) => {
case DebugModuleKey => None case DebugModuleKey => None
}) })
class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => {
case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
})
class WithTLBackingMemory extends Config((site, here, up) => {
case ExtMem => None // disable AXI backing memory
case ExtTLMem => up(ExtMem, site) // enable TL backing memory
})
class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)
class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {

10
generators/chipyard/src/main/scala/CustomBusTopologies.scala
View File

@@ -70,3 +70,13 @@ class WithMulticlockCoherentBusTopology extends Config((site, here, up) => {
l2 = site(BankedL2Key), l2 = site(BankedL2Key),
sbusToMbusXType = site(SbusToMbusXTypeKey))) sbusToMbusXType = site(SbusToMbusXTypeKey)))
}) })
class WithMulticlockIncoherentBusTopology extends Config((site, here, up) => {
case TLNetworkTopologyLocated(InSubsystem) => List(
JustOneBusTopologyParams(sbus = site(SystemBusKey)),
HierarchicalMulticlockBusTopologyParams(
pbus = site(PeripheryBusKey),
fbus = site(FrontBusKey),
cbus = site(ControlBusKey),
xTypes = SubsystemCrossingParams()))
})

2
generators/chipyard/src/main/scala/DigitalTop.scala
View File

@@ -20,6 +20,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
@@ -35,6 +36,7 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
with chipyard.example.CanHavePeripheryGCDModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp
with freechips.rocketchip.util.DontTouch with freechips.rocketchip.util.DontTouch
// DOC include end: DigitalTop // DOC include end: DigitalTop

4
generators/chipyard/src/main/scala/Subsystem.scala
View File

@@ -11,7 +11,7 @@ import chisel3.internal.sourceinfo.{SourceInfo}
import freechips.rocketchip.prci._ import freechips.rocketchip.prci._
import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug} import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
@@ -31,7 +31,7 @@ trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr // Advertise HTIF if system can communicate with fesvr
if (this match { if (this match {
case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true
case _: HasPeripheryDebug if p(ExportDebug).dmi => true case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true
case _ => false case _ => false
}) { }) {
ResourceBinding { ResourceBinding {

52
generators/chipyard/src/main/scala/System.scala
View File

@@ -7,7 +7,7 @@ package chipyard
import chisel3._ import chisel3._
import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.tilelink._
@@ -23,7 +23,8 @@ import freechips.rocketchip.util.{DontTouch}
*/ */
class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
with HasAsyncExtInterrupts with HasAsyncExtInterrupts
with CanHaveMasterAXI4MemPort with CanHaveMasterTLMemPort // export TL port for outer memory
with CanHaveMasterAXI4MemPort // expose AXI port for outer mem
with CanHaveMasterAXI4MMIOPort with CanHaveMasterAXI4MMIOPort
with CanHaveSlaveAXI4Port with CanHaveSlaveAXI4Port
{ {
@@ -40,3 +41,50 @@ class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubs
with HasRTCModuleImp with HasRTCModuleImp
with HasExtInterruptsModuleImp with HasExtInterruptsModuleImp
with DontTouch with DontTouch
// ------------------------------------
// TL Mem Port Mixin
// ------------------------------------
// Similar to ExtMem but instantiates a TL mem port
case object ExtTLMem extends Field[Option[MemoryPortParams]](None)
/** Adds a port to the system intended to master an TL DRAM controller. */
trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
require(!(p(ExtTLMem).nonEmpty && p(ExtMem).nonEmpty),
"Can only have 1 backing memory port. Use ExtTLMem for a TL memory port or ExtMem for an AXI memory port.")
private val memPortParamsOpt = p(ExtTLMem)
private val portName = "tl_mem"
private val device = new MemoryDevice
private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) =>
Seq.tabulate(nMemoryChannels) { channel =>
val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
TLSlavePortParameters.v1(
managers = Seq(TLSlaveParameters.v1(
address = base.flatMap(_.intersect(filter)),
resources = device.reg,
regionType = RegionType.UNCACHED, // cacheable
executable = true,
supportsGet = TransferSizes(1, mbus.blockBytes),
supportsPutFull = TransferSizes(1, mbus.blockBytes),
supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
beatBytes = memPortParams.beatBytes)
}
}).toList.flatten)
mbus.coupleTo(s"memory_controller_port_named_$portName") {
(memTLNode
:*= TLBuffer()
:*= TLSourceShrinker(1 << idBits)
:*= TLWidthWidget(mbus.beatBytes)
:*= _)
}
val mem_tl = InModuleBody { memTLNode.makeIOs() }
}

2
generators/chipyard/src/main/scala/config/AbstractConfig.scala
View File

@@ -50,6 +50,6 @@ class AbstractConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system

12
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -11,6 +11,16 @@ class RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
class TinyRocketConfig extends Config(
new chipyard.config.WithTLSerialLocation(
freechips.rocketchip.subsystem.FBUS,
freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses
new chipyard.WithMulticlockIncoherentBusTopology ++ // use incoherent bus topology
new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core
new chipyard.config.AbstractConfig)
class HwachaRocketConfig extends Config( class HwachaRocketConfig extends Config(
new chipyard.config.WithHwachaTest ++ new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
@@ -179,7 +189,7 @@ class MMIORocketConfig extends Config(
class MulticlockRocketConfig extends Config( class MulticlockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
// Frequency specifications // Frequency specifications
new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540
new chipyard.config.WithSystemBusFrequency(800.0) ++ // Ditto new chipyard.config.WithSystemBusFrequency(800.0) ++ // Ditto
new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus)
new chipyard.config.WithPeripheryBusFrequency(100) ++ // Retains the default pbus frequency new chipyard.config.WithPeripheryBusFrequency(100) ++ // Retains the default pbus frequency

2
generators/sifive-blocks

Submodule generators/sifive-blocks updated: 612ed01df3...545a396f34

2
generators/testchipip

Submodule generators/testchipip updated: ca67a843bd...39ed56be3e

51
generators/utilities/src/main/scala/Simulator.scala
View File

@@ -5,7 +5,7 @@ import java.io.File
case class GenerateSimConfig( case class GenerateSimConfig(
targetDir: String = ".", targetDir: String = ".",
dotFName: String = "sim_files.f", dotFName: String = "sim_files.f",
simulator: Simulator = VerilatorSimulator, simulator: Option[Simulator] = Some(VerilatorSimulator)
) )
sealed trait Simulator sealed trait Simulator
@@ -20,17 +20,18 @@ trait HasGenerateSimConfig {
.abbr("sim") .abbr("sim")
.valueName("<simulator-name>") .valueName("<simulator-name>")
.action((x, c) => x match { .action((x, c) => x match {
case "verilator" => c.copy(simulator = VerilatorSimulator) case "verilator" => c.copy(simulator = Some(VerilatorSimulator))
case "vcs" => c.copy(simulator = VCSSimulator) case "vcs" => c.copy(simulator = Some(VCSSimulator))
case "none" => c.copy(simulator = None)
case _ => throw new Exception(s"Unrecognized simulator $x") case _ => throw new Exception(s"Unrecognized simulator $x")
}) })
.text("Name of simulator to generate files for (verilator, vcs)") .text("Name of simulator to generate files for (verilator, vcs, none)")
opt[String]("target-dir") opt[String]("target-dir")
.abbr("td") .abbr("td")
.valueName("<target-directory>") .valueName("<target-directory>")
.action((x, c) => c.copy(targetDir = x)) .action((x, c) => c.copy(targetDir = x))
.text("Target director to put files") .text("Target directory to put files")
opt[String]("dotFName") opt[String]("dotFName")
.abbr("df") .abbr("df")
@@ -47,9 +48,10 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
if (fname.takeRight(2) == ".h") { if (fname.takeRight(2) == ".h") {
cfg.simulator match { cfg.simulator match {
// verilator needs to explicitly include verilator.h, so use the -FI option // verilator needs to explicitly include verilator.h, so use the -FI option
case VerilatorSimulator => s"-FI ${fname}" case Some(VerilatorSimulator) => s"-FI ${fname}"
// vcs pulls headers in with +incdir, doesn't have anything like verilator.h // vcs pulls headers in with +incdir, doesn't have anything like verilator.h
case VCSSimulator => "" case Some(VCSSimulator) => ""
case None => ""
} }
} else { // do nothing otherwise } else { // do nothing otherwise
fname fname
@@ -81,7 +83,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
out.write(text) out.write(text)
out.close() out.close()
} }
def resources(sim: Simulator): Seq[String] = Seq( def resources(sim: Option[Simulator]): Seq[String] = Seq(
"/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/SimSerial.cc",
"/testchipip/csrc/testchip_tsi.cc", "/testchipip/csrc/testchip_tsi.cc",
"/testchipip/csrc/testchip_tsi.h", "/testchipip/csrc/testchip_tsi.h",
@@ -95,15 +97,30 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
"/csrc/remote_bitbang.h", "/csrc/remote_bitbang.h",
"/csrc/remote_bitbang.cc", "/csrc/remote_bitbang.cc",
"/vsrc/EICG_wrapper.v", "/vsrc/EICG_wrapper.v",
) ++ (sim match { // simulator specific files to include ) ++ (sim match {
case VerilatorSimulator => Seq( case None => Seq()
"/csrc/emulator.cc", case _ => Seq(
"/csrc/verilator.h", "/testchipip/csrc/SimSerial.cc",
) "/testchipip/csrc/SimDRAM.cc",
case VCSSimulator => Seq( "/testchipip/csrc/mm.h",
"/vsrc/TestDriver.v", "/testchipip/csrc/mm.cc",
) "/testchipip/csrc/mm_dramsim2.h",
}) "/testchipip/csrc/mm_dramsim2.cc",
"/csrc/SimDTM.cc",
"/csrc/SimJTAG.cc",
"/csrc/remote_bitbang.h",
"/csrc/remote_bitbang.cc",
)
}) ++ (sim match { // simulator specific files to include
case Some(VerilatorSimulator) => Seq(
"/csrc/emulator.cc",
"/csrc/verilator.h",
)
case Some(VCSSimulator) => Seq(
"/vsrc/TestDriver.v",
)
case None => Seq()
})
def writeBootrom(): Unit = { def writeBootrom(): Unit = {
firrtl.FileUtils.makeDirectory("./bootrom/") firrtl.FileUtils.makeDirectory("./bootrom/")

11
scripts/init-fpga.sh Executable file
View File

@@ -0,0 +1,11 @@
#!/usr/bin/env bash
# exit script if any command fails
set -e
set -o pipefail
# Enable submodule update for FPGA tools.
git config --unset submodule.fpga/fpga-shells.update
# Initialize local FPGA tools.
git submodule update --init --recursive fpga/fpga-shells
# Disable submodule update for FPGA tools.
git config submodule.fpga/fpga-shells.update none

2
scripts/init-submodules-no-riscv-tools-nolog.sh
View File

@@ -39,6 +39,8 @@ git config submodule.vlsi/hammer-cadence-plugins.update none
git config submodule.vlsi/hammer-synopsys-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none
git config submodule.vlsi/hammer-mentor-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none
git config submodule.software/firemarshal.update none git config submodule.software/firemarshal.update none
# Disable update to fpga-shells
git config submodule.fpga/fpga-shells.update none
git submodule update --init --recursive #--jobs 8 git submodule update --init --recursive #--jobs 8
# Un-ignore toolchain submodules # Un-ignore toolchain submodules