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Merge pull request #1495 from ucb-bar/shuttle

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Add dual-issue in-order "shuttle" core
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Jerry Zhao
2023-06-13 15:29:39 -07:00
committed by GitHub
parent fa6d77237e 309bfde21e
commit d287fed654
12 changed files with 182 additions and 28 deletions
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docs/Generators/Shuttle.rst Normal file
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Shuttle RISC-V Core
===================
Shuttle is a Rocket-based superscalar in-order RISC-V core, supporting the base RV64IMAFDC instruction set with supervisor and user-mode. Shuttle is a 6-stage core that can be configured to be dual, three, or quad-issue, although dual-issue is the most sensible design point. Shuttle is not designed to meet any power, performance, or area targets. It exists purely as a demonstrative example of another RISC-V CPU design point.
The superscalar microarchitecture presents the most advantages for 1) floating-point kernels and 2) RoCC accelerator kernels, as scalar control code can execute concurrently with floating point or RoCC instructions, maintaining high utilization of those units.
Shuttle is tape-out proven, and has similar physical design complexity as Rocket.

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docs/Generators/index.rst
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fft
NVDLA
Sodor
Shuttle
Mempress
Prefetchers