From 863f723708f39304293e6aba52bca2d47e130c85 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 30 Jun 2020 12:26:26 -0700 Subject: [PATCH 1/2] Pipe through AXI4 MMIO and Slave ports to ChipTop | IOBinders fix * Fixes bug with AXI4 MMIO ports not being generated properly due to IOBinders issue. Additionally adds IOCells to AXI4 ports so that they appear in ChipTop * Change IOBinders to also require passing p: Parameters to child functions. Serialization of type targets via ClassTags fails for compound types, so we cannot use `BaseSubsystem with HasSomeTrait` as the type target in OverrideIOBinders. --- .circleci/config.yml | 9 ++ .circleci/defaults.sh | 32 ++--- .../chipyard/src/main/scala/ChipTop.scala | 3 +- .../chipyard/src/main/scala/IOBinders.scala | 117 ++++++++++-------- .../src/main/scala/config/RocketConfigs.scala | 18 +++ .../src/main/scala/BridgeBinders.scala | 39 +++--- tools/barstools | 2 +- 7 files changed, 132 insertions(+), 88 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index ab123661..b6556850 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -287,6 +287,11 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-spiflashread" + prepare-chipyard-mmios: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-mmios" chipyard-rocket-run-tests: executor: main-env steps: @@ -531,6 +536,10 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-mmios: + requires: + - install-riscv-toolchain + # Run the respective tests # Run the example tests diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index b9aeeb3b..7cb8c1e2 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,23 +47,25 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build strings declare -A mapping -mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" -mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" -mapping["chipyard-streaming-fir"]="SUB_PROJECT=chipyard CONFIG=StreamingFIRRocketConfig" -mapping["chipyard-streaming-passthrough"]="SUB_PROJECT=chipyard CONFIG=StreamingPassthroughRocketConfig" -mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" -mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" -mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" -mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" -mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" -mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" -mapping["chipyard-spiflashread"]="SUB_PROJECT=chipyard CONFIG=LargeSPIFlashROMRocketConfig" -mapping["chipyard-spiflashwrite"]="SUB_PROJECT=chipyard CONFIG=SmallSPIFlashRocketConfig" -mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" -mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" -mapping["chipyard-nvdla"]="SUB_PROJECT=chipyard CONFIG=SmallNVDLARocketConfig" +mapping["chipyard-rocket"]="" +mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" +mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig" +mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig" +mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" +mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig" +mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig" +mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" +mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" +mapping["chipyard-ariane"]=" CONFIG=ArianeConfig" +mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig" +mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig" +mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" +mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" +mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" +mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" + diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index d0b4df02..ea0c804d 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -70,12 +70,13 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with val lSystem = p(BuildSystem)(p).suggestName("system") val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) } + // Call all of the IOBinders and provide them with a default clock and reset withClockAndReset(systemClock, systemReset) { // Call each IOBinder on both the lazyModule instance and the module // instance. Generally, an IOBinder PF should only be defined on one, so // this should not lead to two invocations. - val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3 + val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem, p) ++ f(system, p)).unzip3 // We ignore _ports for now... iocells ++= _iocells.flatten harnessFunctions ++= _harnessFunctions.flatten diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 1a366d19..2b7cd41c 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} -import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters} +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} import freechips.rocketchip.util._ import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} @@ -48,17 +48,17 @@ type TestHarnessFunction = (chipyard.TestHarness) => Seq[Any] // 3. An optional function to call inside the test harness (e.g. to connect the IOs) type IOBinderTuple = (Seq[Data], Seq[IOCell], Option[TestHarnessFunction]) -case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]]( - Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil) +case object IOBinders extends Field[Map[String, (Any, Parameters) => Seq[IOBinderTuple]]]( + Map[String, (Any, Parameters) => Seq[IOBinderTuple]]().withDefaultValue((Any, Parameters) => Nil) ) // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any) => { + ((t: Any, p: Parameters) => { t match { - case system: T => fn(system) + case system: T => fn(system, p) case _ => Nil } }) @@ -67,12 +67,12 @@ class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassT // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any) => { + ((t: Any, p: Parameters) => { t match { - case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system) - ++ fn(system)) + case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system, p) + ++ fn(system, p)) case _ => Nil } }) @@ -185,10 +185,19 @@ object AddIOCells { (port, ios) } - def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { + def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { io.zip(node.in).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => { - val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_mem_axi4_${i}")) - port.suggestName(s"mem_axi4_${i}") + val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_slave_${i}")) + port.suggestName(s"${name}_axi4_slave_${i}") + (port, edge, ios) + }} + } + def axi4(io: Seq[AXI4Bundle], node: AXI4MasterNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { + io.zip(node.out).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => { + //val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_master_${i}")) + val port = IO(Flipped(AXI4Bundle(edge.bundle))) + val ios = IOCell.generateFromSignal(mem_axi4, port, Some(s"iocell_${name}_axi4_master_${i}")) + port.suggestName(s"${name}_axi4_master_${i}") (port, edge, ios) }} } @@ -202,7 +211,7 @@ object AddIOCells { // DOC include start: WithGPIOTiedOff class WithGPIOTiedOff extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp) => { + (system: HasPeripheryGPIOModuleImp, p) => { val (ports2d, ioCells2d) = AddIOCells.gpio(system.gpio) val harnessFn = (th: chipyard.TestHarness) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } Seq((ports2d.flatten, ioCells2d.flatten, Some(harnessFn))) @@ -211,7 +220,7 @@ class WithGPIOTiedOff extends OverrideIOBinder({ // DOC include end: WithGPIOTiedOff class WithUARTAdapter extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => { + (system: HasPeripheryUARTModuleImp, p) => { val (ports, ioCells2d) = AddIOCells.uart(system.uart) val harnessFn = (th: chipyard.TestHarness) => { UARTAdapter.connect(ports)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) @@ -219,7 +228,7 @@ class WithUARTAdapter extends OverrideIOBinder({ }) class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ - (system: HasPeripherySPIFlashModuleImp) => { + (system: HasPeripherySPIFlashModuleImp, p) => { val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi") val harnessFn = (th: chipyard.TestHarness) => { SimSPIFlashModel.connect(ports, th.reset, rdOnly)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) @@ -227,7 +236,7 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ }) class WithSimBlockDevice extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => + (system: CanHavePeripheryBlockDeviceModuleImp, p) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) val harnessFn = (th: chipyard.TestHarness) => { SimBlockDevice.connect(th.clock, th.reset.asBool, Some(port))(system.p) @@ -238,7 +247,7 @@ class WithSimBlockDevice extends OverrideIOBinder({ }) class WithBlockDeviceModel extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => + (system: CanHavePeripheryBlockDeviceModuleImp, p) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) val harnessFn = (th: chipyard.TestHarness) => { BlockDeviceModel.connect(Some(port))(system.p) @@ -249,11 +258,11 @@ class WithBlockDeviceModel extends OverrideIOBinder({ }) class WithLoopbackNIC extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => system.connectNicLoopback(); Nil + (system: CanHavePeripheryIceNICModuleImp, p) => system.connectNicLoopback(); Nil }) class WithSimNIC extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil + (system: CanHavePeripheryIceNICModuleImp, p) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil }) // Note: The parameters instance is accessible only through the BaseSubsystem @@ -262,16 +271,16 @@ class WithSimNIC extends OverrideIOBinder({ // accessible to the IOBinder // DOC include start: WithSimAXIMem class WithSimAXIMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { - val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node) + (system: CanHaveMasterAXI4MemPort, p) => { + val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") // TODO: we are inlining the connectMem method of SimAXIMem because // it takes in a dut rather than seq of axi4 ports val harnessFn = (th: chipyard.TestHarness) => { peiTuples.map { case (port, edge, ios) => - val mem = LazyModule(new SimAXIMem(edge, size = system.p(ExtMem).get.master.size)(system.p)) + val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)(p)) Module(mem.module).suggestName("mem") mem.io_axi4.head <> port - } + } Nil } Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) @@ -280,12 +289,12 @@ class WithSimAXIMem extends OverrideIOBinder({ // DOC include end: WithSimAXIMem class WithBlackBoxSimMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { - val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node) + (system: CanHaveMasterAXI4MemPort, p) => { + val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") val harnessFn = (th: chipyard.TestHarness) => { peiTuples.map { case (port, edge, ios) => - val memSize = system.p(ExtMem).get.master.size - val lineSize = system.p(CacheBlockBytes) + val memSize = p(ExtMem).get.master.size + val lineSize = p(CacheBlockBytes) val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) mem.io.axi <> port mem.io.clock := th.clock @@ -298,15 +307,26 @@ class WithBlackBoxSimMem extends OverrideIOBinder({ }) class WithSimAXIMMIO extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MMIOPort with BaseSubsystem) => SimAXIMem.connectMMIO(system)(system.p); Nil + (system: CanHaveMasterAXI4MMIOPort, p) => { + val peiTuples = AddIOCells.axi4(system.mmio_axi4, system.mmioAXI4Node, "mmio_mem") + val harnessFn = (th: chipyard.TestHarness) => { + peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => + val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)(p)) + Module(mmio_mem.module).suggestName(s"mmio_mem_${i}") + mmio_mem.io_axi4.head <> port + } + Nil + } + Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) + } }) class WithDontTouchPorts extends OverrideIOBinder({ - (system: DontTouch) => system.dontTouchPorts(); Nil + (system: DontTouch, p) => system.dontTouchPorts(); Nil }) class WithTieOffInterrupts extends OverrideIOBinder({ - (system: HasExtInterruptsModuleImp) => { + (system: HasExtInterruptsModuleImp, p) => { val (port, ioCells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts")) port.suggestName("interrupts") val harnessFn = (th: chipyard.TestHarness) => { port := 0.U; Nil } @@ -315,26 +335,21 @@ class WithTieOffInterrupts extends OverrideIOBinder({ }) class WithTieOffL2FBusAXI extends OverrideIOBinder({ - (system: CanHaveSlaveAXI4Port with BaseSubsystem) => { - system.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - case _ => throw new Exception("Unknown AXI port direction") + (system: CanHaveSlaveAXI4Port, p) => { + val peiTuples = AddIOCells.axi4(system.l2_frontend_bus_axi4, system.l2FrontendAXI4Node, "l2_fbus") + val harnessFn = (th: chipyard.TestHarness) => { + peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => + port := DontCare // tieoff doesn't completely tie-off, for some reason + port.tieoff() } - }) - Nil + Nil + } + Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) } }) class WithTiedOffDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp) => { + (system: HasPeripheryDebugModuleImp, p) => { val (psdPort, resetctrlOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { @@ -352,7 +367,7 @@ class WithTiedOffDebug extends OverrideIOBinder({ }) class WithSimDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp) => { + (system: HasPeripheryDebugModuleImp, p) => { val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { @@ -367,7 +382,7 @@ class WithSimDebug extends OverrideIOBinder({ }) class WithTiedOffSerial extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => + (system: CanHavePeripherySerialModuleImp, p) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) val harnessFn = (th: chipyard.TestHarness) => { SerialAdapter.tieoff(port) @@ -378,7 +393,7 @@ class WithTiedOffSerial extends OverrideIOBinder({ }) class WithSimSerial extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => + (system: CanHavePeripherySerialModuleImp, p) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) val harnessFn = (th: chipyard.TestHarness) => { val ser_success = SerialAdapter.connectSimSerial(port, th.clock, th.harnessReset) @@ -390,7 +405,7 @@ class WithSimSerial extends OverrideIOBinder({ }) class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (system: TraceGenSystemModuleImp) => { + (system: TraceGenSystemModuleImp, p) => { val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) successPort.suggestName("success") val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } @@ -399,7 +414,7 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({ }) class WithSimDromajoBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp) => { + (system: CanHaveTraceIOModuleImp, p) => { system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } Nil } diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 06257c7b..3dc7d22d 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -542,3 +542,21 @@ class LargeNVDLARocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) + +class MMIORocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithTieOffL2FBusAXI ++ // Tie-off the incoming MMIO port + new chipyard.iobinders.WithSimAXIMMIO ++ // Attach a simulated memory to the outwards MMIO port + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index eeb19559..6af7bd0a 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -35,29 +35,28 @@ object MainMemoryConsts { } class WithSerialBridge extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp) => - system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(system.p)); Nil + (system: CanHavePeripherySerialModuleImp, p) => + system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(p)); Nil }) class WithNICBridge extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => - system.net.foreach(n => NICBridge(system.clock, n)(system.p)); Nil + (system: CanHavePeripheryIceNICModuleImp, p) => + system.net.foreach(n => NICBridge(system.clock, n)(p)); Nil }) class WithUARTBridge extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => - system.uart.foreach(u => UARTBridge(system.clock, u)(system.p)); Nil + (system: HasPeripheryUARTModuleImp, p) => + system.uart.foreach(u => UARTBridge(system.clock, u)(p)); Nil }) class WithBlockDeviceBridge extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => - system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(system.p)); Nil + (system: CanHavePeripheryBlockDeviceModuleImp, p) => + system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(p)); Nil }) class WithFASEDBridge extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { - implicit val p = system.p + (system: CanHaveMasterAXI4MemPort, p) => { (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) => val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, axi4.ar.bits.addr.getWidth, @@ -73,26 +72,26 @@ class WithFASEDBridge extends OverrideIOBinder({ }) class WithTracerVBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp) => - system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil + (system: CanHaveTraceIOModuleImp, p) => + system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(p))); Nil }) class WithDromajoBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp) => { - system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil + (system: CanHaveTraceIOModuleImp, p) => { + system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(p))); Nil } }) class WithTraceGenBridge extends OverrideIOBinder({ - (system: TraceGenSystemModuleImp) => + (system: TraceGenSystemModuleImp, p) => GroundTestBridge(system.clock, system.success)(system.p); Nil }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ - (system: HasTilesModuleImp) => { + (system: HasTilesModuleImp, p) => { system.outer.tiles.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) @@ -116,13 +115,13 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ }) class WithTiedOffSystemGPIO extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp) => + (system: HasPeripheryGPIOModuleImp, p) => system.gpio.foreach(_.pins.foreach(_.i.ival := false.B)); Nil }) class WithTiedOffSystemDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp) => { - Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p) + (system: HasPeripheryDebugModuleImp, p) => { + Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(p) // tieoffDebug doesn't actually tie everything off :/ system.debug.foreach { d => d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) @@ -133,7 +132,7 @@ class WithTiedOffSystemDebug extends OverrideIOBinder({ }) class WithTiedOffSystemInterrupts extends OverrideIOBinder({ - (system: HasExtInterruptsModuleImp) => + (system: HasExtInterruptsModuleImp, p) => system.interrupts := 0.U; Nil }) diff --git a/tools/barstools b/tools/barstools index 7e6e19b8..aa1c90c4 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 7e6e19b8adf3b625b31b09173ecae5f634c83e1b +Subproject commit aa1c90c4ccb73c2c379550f3296892cc81e8a195 From a7047c4ba2e7b9c4a2433a3e8ff0346bc3a67ab5 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 1 Jul 2020 12:21:51 -0700 Subject: [PATCH 2/2] Fix FireChip BridgeBinders --- .../chipyard/src/main/scala/ChipTop.scala | 3 +- .../chipyard/src/main/scala/IOBinders.scala | 84 +++++++++++-------- .../src/main/scala/BridgeBinders.scala | 54 ++++++------ 3 files changed, 79 insertions(+), 62 deletions(-) diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index ea0c804d..d0b4df02 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -70,13 +70,12 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with val lSystem = p(BuildSystem)(p).suggestName("system") val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) } - // Call all of the IOBinders and provide them with a default clock and reset withClockAndReset(systemClock, systemReset) { // Call each IOBinder on both the lazyModule instance and the module // instance. Generally, an IOBinder PF should only be defined on one, so // this should not lead to two invocations. - val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem, p) ++ f(system, p)).unzip3 + val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3 // We ignore _ports for now... iocells ++= _iocells.flatten harnessFunctions ++= _harnessFunctions.flatten diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 2b7cd41c..115723ab 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -5,7 +5,7 @@ import chisel3._ import chisel3.experimental.{Analog, IO} import freechips.rocketchip.config.{Field, Config, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} @@ -48,17 +48,32 @@ type TestHarnessFunction = (chipyard.TestHarness) => Seq[Any] // 3. An optional function to call inside the test harness (e.g. to connect the IOs) type IOBinderTuple = (Seq[Data], Seq[IOCell], Option[TestHarnessFunction]) -case object IOBinders extends Field[Map[String, (Any, Parameters) => Seq[IOBinderTuple]]]( - Map[String, (Any, Parameters) => Seq[IOBinderTuple]]().withDefaultValue((Any, Parameters) => Nil) +case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]]( + Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil) ) +// Note: The parameters instance is accessible only through LazyModule +// or LazyModuleImpLike. The self-type requirement in traits like +// CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder +// As a result, IOBinders only work on Modules which inherit LazyModule or +// or LazyModuleImpLike +object GetSystemParameters { + def apply(s: Any): Parameters = { + s match { + case s: LazyModule => s.p + case s: LazyModuleImpLike => s.p + case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike") + } + } +} + // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any, p: Parameters) => { + ((t: Any) => { t match { - case system: T => fn(system, p) + case system: T => fn(system) case _ => Nil } }) @@ -67,12 +82,12 @@ class OverrideIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((t: Any, p: Parameters) => { + ((t: Any) => { t match { - case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system, p) - ++ fn(system, p)) + case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system) + ++ fn(system)) case _ => Nil } }) @@ -211,7 +226,7 @@ object AddIOCells { // DOC include start: WithGPIOTiedOff class WithGPIOTiedOff extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp, p) => { + (system: HasPeripheryGPIOModuleImp) => { val (ports2d, ioCells2d) = AddIOCells.gpio(system.gpio) val harnessFn = (th: chipyard.TestHarness) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } Seq((ports2d.flatten, ioCells2d.flatten, Some(harnessFn))) @@ -220,7 +235,7 @@ class WithGPIOTiedOff extends OverrideIOBinder({ // DOC include end: WithGPIOTiedOff class WithUARTAdapter extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp, p) => { + (system: HasPeripheryUARTModuleImp) => { val (ports, ioCells2d) = AddIOCells.uart(system.uart) val harnessFn = (th: chipyard.TestHarness) => { UARTAdapter.connect(ports)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) @@ -228,7 +243,7 @@ class WithUARTAdapter extends OverrideIOBinder({ }) class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ - (system: HasPeripherySPIFlashModuleImp, p) => { + (system: HasPeripherySPIFlashModuleImp) => { val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi") val harnessFn = (th: chipyard.TestHarness) => { SimSPIFlashModel.connect(ports, th.reset, rdOnly)(system.p); Nil } Seq((ports, ioCells2d.flatten, Some(harnessFn))) @@ -236,7 +251,7 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ }) class WithSimBlockDevice extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, p) => system.bdev.map { bdev => + (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) val harnessFn = (th: chipyard.TestHarness) => { SimBlockDevice.connect(th.clock, th.reset.asBool, Some(port))(system.p) @@ -247,7 +262,7 @@ class WithSimBlockDevice extends OverrideIOBinder({ }) class WithBlockDeviceModel extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, p) => system.bdev.map { bdev => + (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => val (port, ios) = AddIOCells.blockDev(bdev) val harnessFn = (th: chipyard.TestHarness) => { BlockDeviceModel.connect(Some(port))(system.p) @@ -258,26 +273,23 @@ class WithBlockDeviceModel extends OverrideIOBinder({ }) class WithLoopbackNIC extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp, p) => system.connectNicLoopback(); Nil + (system: CanHavePeripheryIceNICModuleImp) => system.connectNicLoopback(); Nil }) class WithSimNIC extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp, p) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil + (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil }) -// Note: The parameters instance is accessible only through the BaseSubsystem -// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The -// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it -// accessible to the IOBinder // DOC include start: WithSimAXIMem class WithSimAXIMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort, p) => { + (system: CanHaveMasterAXI4MemPort) => { + implicit val p: Parameters = GetSystemParameters(system) val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") // TODO: we are inlining the connectMem method of SimAXIMem because // it takes in a dut rather than seq of axi4 ports val harnessFn = (th: chipyard.TestHarness) => { peiTuples.map { case (port, edge, ios) => - val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)(p)) + val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)) Module(mem.module).suggestName("mem") mem.io_axi4.head <> port } @@ -289,7 +301,8 @@ class WithSimAXIMem extends OverrideIOBinder({ // DOC include end: WithSimAXIMem class WithBlackBoxSimMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort, p) => { + (system: CanHaveMasterAXI4MemPort) => { + implicit val p: Parameters = GetSystemParameters(system) val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem") val harnessFn = (th: chipyard.TestHarness) => { peiTuples.map { case (port, edge, ios) => @@ -307,11 +320,12 @@ class WithBlackBoxSimMem extends OverrideIOBinder({ }) class WithSimAXIMMIO extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MMIOPort, p) => { + (system: CanHaveMasterAXI4MMIOPort) => { + implicit val p: Parameters = GetSystemParameters(system) val peiTuples = AddIOCells.axi4(system.mmio_axi4, system.mmioAXI4Node, "mmio_mem") val harnessFn = (th: chipyard.TestHarness) => { peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => - val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)(p)) + val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)) Module(mmio_mem.module).suggestName(s"mmio_mem_${i}") mmio_mem.io_axi4.head <> port } @@ -322,11 +336,11 @@ class WithSimAXIMMIO extends OverrideIOBinder({ }) class WithDontTouchPorts extends OverrideIOBinder({ - (system: DontTouch, p) => system.dontTouchPorts(); Nil + (system: DontTouch) => system.dontTouchPorts(); Nil }) class WithTieOffInterrupts extends OverrideIOBinder({ - (system: HasExtInterruptsModuleImp, p) => { + (system: HasExtInterruptsModuleImp) => { val (port, ioCells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts")) port.suggestName("interrupts") val harnessFn = (th: chipyard.TestHarness) => { port := 0.U; Nil } @@ -335,7 +349,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({ }) class WithTieOffL2FBusAXI extends OverrideIOBinder({ - (system: CanHaveSlaveAXI4Port, p) => { + (system: CanHaveSlaveAXI4Port) => { val peiTuples = AddIOCells.axi4(system.l2_frontend_bus_axi4, system.l2FrontendAXI4Node, "l2_fbus") val harnessFn = (th: chipyard.TestHarness) => { peiTuples.zipWithIndex.map { case ((port, edge, ios), i) => @@ -349,7 +363,7 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({ }) class WithTiedOffDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp, p) => { + (system: HasPeripheryDebugModuleImp) => { val (psdPort, resetctrlOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { @@ -367,7 +381,7 @@ class WithTiedOffDebug extends OverrideIOBinder({ }) class WithSimDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp, p) => { + (system: HasPeripheryDebugModuleImp) => { val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { @@ -382,7 +396,7 @@ class WithSimDebug extends OverrideIOBinder({ }) class WithTiedOffSerial extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp, p) => system.serial.map({ serial => + (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) val harnessFn = (th: chipyard.TestHarness) => { SerialAdapter.tieoff(port) @@ -393,7 +407,7 @@ class WithTiedOffSerial extends OverrideIOBinder({ }) class WithSimSerial extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp, p) => system.serial.map({ serial => + (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => val (port, ioCells) = AddIOCells.serial(serial) val harnessFn = (th: chipyard.TestHarness) => { val ser_success = SerialAdapter.connectSimSerial(port, th.clock, th.harnessReset) @@ -405,7 +419,7 @@ class WithSimSerial extends OverrideIOBinder({ }) class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (system: TraceGenSystemModuleImp, p) => { + (system: TraceGenSystemModuleImp) => { val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) successPort.suggestName("success") val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } @@ -414,7 +428,7 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({ }) class WithSimDromajoBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp, p) => { + (system: CanHaveTraceIOModuleImp) => { system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } Nil } diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 6af7bd0a..eba57451 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -26,7 +26,7 @@ import ariane.ArianeTile import boom.common.{BoomTile} -import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} +import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters} import testchipip.{CanHaveTraceIOModuleImp} object MainMemoryConsts { @@ -35,63 +35,67 @@ object MainMemoryConsts { } class WithSerialBridge extends OverrideIOBinder({ - (system: CanHavePeripherySerialModuleImp, p) => - system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(p)); Nil + (system: CanHavePeripherySerialModuleImp) => + system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(system.p)); Nil }) class WithNICBridge extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp, p) => - system.net.foreach(n => NICBridge(system.clock, n)(p)); Nil + (system: CanHavePeripheryIceNICModuleImp) => + system.net.foreach(n => NICBridge(system.clock, n)(system.p)); Nil }) class WithUARTBridge extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp, p) => - system.uart.foreach(u => UARTBridge(system.clock, u)(p)); Nil + (system: HasPeripheryUARTModuleImp) => + system.uart.foreach(u => UARTBridge(system.clock, u)(system.p)); Nil }) class WithBlockDeviceBridge extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, p) => - system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(p)); Nil + (system: CanHavePeripheryBlockDeviceModuleImp) => + system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(system.p)); Nil }) class WithFASEDBridge extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort, p) => { + (system: CanHaveMasterAXI4MemPort) => { + implicit val p: Parameters = GetSystemParameters(system) (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) => val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, axi4.ar.bits.addr.getWidth, axi4.ar.bits.id.getWidth) - FASEDBridge(system.module.clock, axi4, system.module.reset.toBool, - CompleteConfig(p(firesim.configs.MemModelKey), - nastiKey, - Some(AXI4EdgeSummary(edge)), - Some(MainMemoryConsts.globalName))) + system match { + case s: BaseSubsystem => FASEDBridge(s.module.clock, axi4, s.module.reset.toBool, + CompleteConfig(p(firesim.configs.MemModelKey), + nastiKey, + Some(AXI4EdgeSummary(edge)), + Some(MainMemoryConsts.globalName))) + case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design") + } }) Nil } }) class WithTracerVBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp, p) => - system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(p))); Nil + (system: CanHaveTraceIOModuleImp) => + system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil }) class WithDromajoBridge extends ComposeIOBinder({ - (system: CanHaveTraceIOModuleImp, p) => { - system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(p))); Nil + (system: CanHaveTraceIOModuleImp) => { + system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil } }) class WithTraceGenBridge extends OverrideIOBinder({ - (system: TraceGenSystemModuleImp, p) => + (system: TraceGenSystemModuleImp) => GroundTestBridge(system.clock, system.success)(system.p); Nil }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ - (system: HasTilesModuleImp, p) => { + (system: HasTilesModuleImp) => { system.outer.tiles.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) @@ -115,13 +119,13 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ }) class WithTiedOffSystemGPIO extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp, p) => + (system: HasPeripheryGPIOModuleImp) => system.gpio.foreach(_.pins.foreach(_.i.ival := false.B)); Nil }) class WithTiedOffSystemDebug extends OverrideIOBinder({ - (system: HasPeripheryDebugModuleImp, p) => { - Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(p) + (system: HasPeripheryDebugModuleImp) => { + Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p) // tieoffDebug doesn't actually tie everything off :/ system.debug.foreach { d => d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) @@ -132,7 +136,7 @@ class WithTiedOffSystemDebug extends OverrideIOBinder({ }) class WithTiedOffSystemInterrupts extends OverrideIOBinder({ - (system: HasExtInterruptsModuleImp, p) => + (system: HasExtInterruptsModuleImp) => system.interrupts := 0.U; Nil })