Merge remote-tracking branch 'origin/main' into clusters

fpga/Makefile

@@ -137,7 +137,7 @@ include $(base_dir)/common.mk
 # copy from other directory
 #########################################################################################
 all_vsrcs := \
-	$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v
+	$(base_dir)/generators/rocket-chip-blocks/vsrc/SRLatch.v
 
 #########################################################################################
 # vivado rules

fpga/src/main/resources/vcu118/sdboot/sd.c

@@ -22,7 +22,16 @@
 #error Must define TL_CLK
 #endif
 
-#define F_CLK TL_CLK
+#define F_CLK 		(TL_CLK)
+
+// SPI SCLK frequency, in kHz
+// We are using the 25MHz High Speed mode. If this speed is not supported by the
+// SD card, consider changing to the Default Speed mode (12.5 MHz).
+#define SPI_CLK 	25000
+
+// SPI clock divisor value
+// @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi
+#define SPI_DIV 	(((F_CLK * 1000) / SPI_CLK) / 2 - 1)
 
 static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
 
@@ -79,7 +88,9 @@ static inline void sd_cmd_end(void)
 static void sd_poweron(void)
 {
 	long i;
-	REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL);
+	// HACK: frequency change
+
+	REG32(spi, SPI_REG_SCKDIV) = SPI_DIV;
 	REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF;
 	for (i = 10; i > 0; i--) {
 		sd_dummy();
@@ -171,12 +182,10 @@ static int copy(void)
 
 	dputs("CMD18");
 
-	kprintf("LOADING 0x%xB PAYLOAD\r\n", PAYLOAD_SIZE_B);
+	kprintf("LOADING 0x%x B PAYLOAD\r\n", PAYLOAD_SIZE_B);
 	kprintf("LOADING  ");
 
-	// TODO: Speed up SPI freq. (breaks between these two values)
-	//REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL);
-	REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL);
+	REG32(spi, SPI_REG_SCKDIV) = SPI_DIV;
 	if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) {
 		sd_cmd_end();
 		return 1;

fpga/src/main/scala/arty/Configs.scala

@@ -11,7 +11,7 @@ import freechips.rocketchip.tile._
 
 import sifive.blocks.devices.uart._
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem}
 
@@ -31,7 +31,8 @@ class WithArtyTweaks extends Config(
   new chipyard.config.WithControlBusFrequency(32) ++
   new chipyard.config.WithPeripheryBusFrequency(32) ++
   new chipyard.config.WithControlBusFrequency(32) ++
-  new testchipip.WithNoSerialTL
+  new testchipip.serdes.WithNoSerialTL ++
+  new testchipip.soc.WithNoScratchpads
 )
 
 class TinyRocketArtyConfig extends Config(

fpga/src/main/scala/arty100t/Configs.scala

@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
 import sifive.blocks.devices.uart._
 import sifive.fpgashells.shell.{DesignKey}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem}
 
@@ -21,11 +21,15 @@ class WithNoDesignKey extends Config((site, here, up) => {
   case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
 })
 
+// By default, this uses the on-board USB-UART for the TSI-over-UART link
+// The PMODUART HarnessBinder maps the actual UART device to JD pin
 class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
+  new WithArty100TPMODUART ++
   new WithArty100TUARTTSI ++
   new WithArty100TDDRTL ++
+  new WithArty100TJTAG ++
   new WithNoDesignKey ++
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
   new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
   new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
@@ -36,8 +40,6 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
   new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.config.WithNoDebug ++ // no jtag
-  new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
   new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
   new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
   new freechips.rocketchip.subsystem.WithoutTLMonitors)
@@ -56,5 +58,5 @@ class NoCoresArty100TConfig extends Config(
 class BringupArty100TConfig extends Config(
   new WithArty100TSerialTLToGPIO ++
   new WithArty100TTweaks(freqMHz = 50) ++
-  new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
+  new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
   new chipyard.ChipBringupHostConfig)

fpga/src/main/scala/arty100t/Harness.scala

@@ -33,9 +33,6 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
 
   harnessSysPLLNode := clockOverlay.overlayOutput.node
 
-  val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
-  val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
-
   val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
   val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
     name = "chip_ddr",
@@ -79,6 +76,9 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
     def referenceReset = dutClock.in.head._1.reset
     def success = { require(false, "Unused"); false.B }
 
+    childClock := harnessBinderClock
+    childReset := harnessBinderReset
+
     ddrOverlay.mig.module.clock := harnessBinderClock
     ddrOverlay.mig.module.reset := harnessBinderReset
     ddrBlockDuringReset.module.clock := harnessBinderClock

fpga/src/main/scala/arty100t/HarnessBinders.scala

@@ -20,12 +20,20 @@ import chipyard._
 import chipyard.harness._
 import chipyard.iobinders._
 
-import testchipip._
-
 class WithArty100TUARTTSI extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
-    ath.io_uart_bb.bundle <> port.io.uart
+    val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi")
+    harnessIO <> port.io.uart
+    val packagePinsWithPackageIOs = Seq(
+      ("A9" , IOPin(harnessIO.rxd)),
+      ("D10", IOPin(harnessIO.txd)))
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      ath.xdc.addPackagePin(io, pin)
+      ath.xdc.addIOStandard(io, "LVCMOS33")
+      ath.xdc.addIOB(io)
+    } }
+
     ath.other_leds(1) := port.io.dropped
     ath.other_leds(9) := port.io.tsi2tl_state(0)
     ath.other_leds(10) := port.io.tsi2tl_state(1)
@@ -34,6 +42,7 @@ class WithArty100TUARTTSI extends HarnessBinder({
   }
 })
 
+
 class WithArty100TDDRTL extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: TLMemPort) => {
     val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
@@ -83,3 +92,46 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
     artyTh.xdc.clockDedicatedRouteFalse(clkIO)
   }
 })
+
+// Maps the UART device to the on-board USB-UART
+class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: UARTPort) => {
+    val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
+    harnessIO <> port.io
+    val packagePinsWithPackageIOs = Seq(
+      (rxdPin, IOPin(harnessIO.rxd)),
+      (txdPin, IOPin(harnessIO.txd)))
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      ath.xdc.addPackagePin(io, pin)
+      ath.xdc.addIOStandard(io, "LVCMOS33")
+      ath.xdc.addIOB(io)
+    } }
+  }
+})
+
+// Maps the UART device to PMOD JD pins 3/7
+class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
+
+class WithArty100TJTAG extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: JTAGPort) => {
+    val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
+    harnessIO <> port.io
+
+    ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
+    ath.sdc.addGroup(clocks = Seq("JTCK"))
+    ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK))
+    val packagePinsWithPackageIOs = Seq(
+      ("F4", IOPin(harnessIO.TCK)),
+      ("D2", IOPin(harnessIO.TMS)),
+      ("E2", IOPin(harnessIO.TDI)),
+      ("D4", IOPin(harnessIO.TDO))
+    )
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      ath.xdc.addPackagePin(io, pin)
+      ath.xdc.addIOStandard(io, "LVCMOS33")
+      ath.xdc.addPullup(io)
+    } }
+  }
+})

fpga/src/main/scala/nexysvideo/Configs.scala

@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
 import sifive.blocks.devices.uart._
 import sifive.fpgashells.shell.{DesignKey}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem}
 
@@ -26,7 +26,7 @@ class WithNexysVideoTweaks extends Config(
   new WithNexysVideoUARTTSI ++
   new WithNexysVideoDDRTL ++
   new WithNoDesignKey ++
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
   new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
   new chipyard.config.WithMemoryBusFrequency(50.0) ++
@@ -53,7 +53,7 @@ class WithTinyNexysVideoTweaks extends Config(
   new WithNexysVideoUARTTSI ++
   new WithNoDesignKey ++
   new sifive.fpgashells.shell.xilinx.WithNoNexysVideoShellDDR ++ // no DDR
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
   new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
   new chipyard.config.WithMemoryBusFrequency(50.0) ++

fpga/src/main/scala/nexysvideo/HarnessBinders.scala

@@ -12,8 +12,6 @@ import sifive.blocks.devices.uart.{UARTParams}
 
 import chipyard._
 import chipyard.harness._
-
-import testchipip._
 import chipyard.iobinders._
 
 class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({

fpga/src/main/scala/vc707/Configs.scala

@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem, ExtTLMem}
 import chipyard.harness._

fpga/src/main/scala/vcu118/Configs.scala

@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard._
 import chipyard.harness._

fpga/src/main/scala/vcu118/bringup/Configs.scala

@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
 
-import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
+import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
 
 import chipyard.{BuildSystem}
 

fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala

@@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.clocks._
 import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
 
-import testchipip.{TSIHostWidgetIO}
+import testchipip.tsi.{TSIHostWidgetIO}
 
 import chipyard.fpga.vcu118.{FMCPMap}
 

fpga/src/main/scala/vcu118/bringup/DigitalTop.scala

@@ -17,7 +17,7 @@ import chipyard.{DigitalTop, DigitalTopModule}
 
 class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop
   with sifive.blocks.devices.i2c.HasPeripheryI2C
-  with testchipip.HasPeripheryTSIHostWidget
+  with testchipip.tsi.HasPeripheryTSIHostWidget
 {
   override lazy val module = new BringupVCU118DigitalTopModule(this)
 }

fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala

@@ -11,7 +11,7 @@ import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
 import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort}
 import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
 
-import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
 
 import chipyard.harness._
 import chipyard.iobinders._

fpga/src/main/scala/vcu118/bringup/IOBinders.scala

@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle}
 import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
 import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
 
-import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
 
 import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
 

fpga/src/main/scala/vcu118/bringup/TestHarness.scala

@@ -16,7 +16,8 @@ import sifive.blocks.devices.spi._
 import sifive.blocks.devices.i2c._
 import sifive.blocks.devices.gpio._
 
-import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO}
+import testchipip.util.{TLSinkSetter}
 
 import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}