diff --git a/docs/Customization/Firrtl-Transforms.rst b/docs/Customization/Firrtl-Transforms.rst
index c089357b..1113bde6 100644
--- a/docs/Customization/Firrtl-Transforms.rst
+++ b/docs/Customization/Firrtl-Transforms.rst
@@ -10,11 +10,13 @@ Transforms are a powerful tool to take in the FIRRTL IR that is emitted from Chi
 
 The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler
 ------------------------------------------------------
-In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler(SFC) and the MLIR FIRRTL compiler(MFC).
-They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster. In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will
-compile CHIRRTL into Verilog(as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value,
+In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler (SFC) and the MLIR FIRRTL compiler (MFC).
+They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster (the generated Verilog will be different). In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will
+compile CHIRRTL into Verilog (as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value,
 we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied.
 
+For more information on MLIR FIRRTL Compiler, please visit https://mlir.llvm.org/ and https://circt.llvm.org/.
+
 Where to add transforms
 -----------------------
 
diff --git a/docs/Tools/FIRRTL.rst b/docs/Tools/FIRRTL.rst
index 268d7728..67adde2d 100644
--- a/docs/Tools/FIRRTL.rst
+++ b/docs/Tools/FIRRTL.rst
@@ -7,4 +7,6 @@ Without going into too much detail, FIRRTL is consumed by FIRRTL compilers which
 An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
 Once the transformations are done, a Verilog file is emitted and the build process is done.
 
-For more information on please visit their `website <https://chisel-lang.org/firrtl/>`__.
+To see how FIRRTL is transformed to Verilog in Chipyard, please visit the :ref:`Customization/Firrtl-Transforms` section.
+
+For more information on FIRRTL, please visit their `website <https://chisel-lang.org/firrtl/>`__.