From 5145b126957ed53f184281ef648c823d14ed36aa Mon Sep 17 00:00:00 2001 From: Santos <34815293+sant0s12@users.noreply.github.com> Date: Fri, 15 Jul 2022 20:11:37 +0200 Subject: [PATCH 1/4] Fix frequency rounding --- .../src/main/scala/config/fragments/ClockingFragments.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index c4172a7a..0c79f6dc 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -38,17 +38,17 @@ class WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends ClockN fMHz) class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { - case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble + case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get.toDouble / (1000 * 1000)) }) class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => { - case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toDouble + case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get.toDouble / (1000 * 1000)) }) class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => { case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++ Seq((cName: String) => site(key).dtsFrequency.flatMap { f => - re.findFirstIn(cName).map {_ => (f / (1000 * 1000)).toDouble } + re.findFirstIn(cName).map {_ => (f.toDouble / (1000 * 1000)) } }) }) From 439ba9731e3b1db274bb4d112ac1c9397807b594 Mon Sep 17 00:00:00 2001 From: michael-etzkorn Date: Sun, 14 Aug 2022 12:21:45 -0500 Subject: [PATCH 2/4] Update SiFive submodules to CHIPS fork --- .gitmodules | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index 11ca0d5a..cb7319f3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -15,7 +15,7 @@ url = https://github.com/riscv-boom/riscv-boom.git [submodule "generators/sifive-blocks"] path = generators/sifive-blocks - url = https://github.com/sifive/sifive-blocks.git + url = https://github.com/chipsalliance/rocket-chip-blocks.git [submodule "generators/hwacha"] path = generators/hwacha url = https://github.com/ucb-bar/hwacha.git @@ -27,7 +27,7 @@ url = https://github.com/firesim/icenet.git [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache - url = https://github.com/sifive/block-inclusivecache-sifive.git + url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git [submodule "toolchains/riscv-tools/riscv-gnu-toolchain"] path = toolchains/riscv-tools/riscv-gnu-toolchain url = https://github.com/riscv/riscv-gnu-toolchain.git @@ -121,7 +121,7 @@ url = https://github.com/ucb-bar/riscv-sodor.git [submodule "fpga/fpga-shells"] path = fpga/fpga-shells - url = https://github.com/sifive/fpga-shells.git + url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git [submodule "tools/api-config-chipsalliance"] path = tools/api-config-chipsalliance url = https://github.com/chipsalliance/api-config-chipsalliance.git From 8ee949af94d84c57e505db8b0b5e5b278e5d6713 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 26 Aug 2022 04:55:48 +0000 Subject: [PATCH 3/4] Bump testchipip for full-width strb fix in mm --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 03535f56..eea390af 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 03535f56a6318236ab6abf5342d78eecf453984d +Subproject commit eea390af19a05b9d6874c3ec51903d89c5520bf2 From e5052022dfc24f9ccdc0eab6131931b97aeab85d Mon Sep 17 00:00:00 2001 From: michael-etzkorn Date: Tue, 30 Aug 2022 18:37:46 +0800 Subject: [PATCH 4/4] CI check commit: fpga-shells now points to main --- .github/scripts/check-commit.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 27abacd4..756b7a3c 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -101,7 +101,7 @@ search submodules=("fpga-shells") dir="fpga" -branches=("master") +branches=("main") search # turn off verbose printing to make this easier to read