diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index b15c571d..40e7d19d 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,7 +45,7 @@ search () { done } -submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle") +submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat") dir="generators" branches=("master" "main" "dev") search @@ -81,14 +81,20 @@ dir="toolchains" branches=("master") search +submodules=("firesim") +dir="sims" +branches=("main") +search + + submodules=("coremark" "firemarshal" "nvdla-workload" "spec2017") dir="software" branches=("master" "dev") search -submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture") +submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde") dir="tools" -branches=("master" "dev") +branches=("master" "dev" "main") search submodules=("fpga-shells") diff --git a/README.md b/README.md index 0d68cf77..8bb2e3e3 100644 --- a/README.md +++ b/README.md @@ -85,7 +85,7 @@ These additional publications cover many of the internal components used in Chip ## Acknowledgements -This work is supported by the NSF CCRI ENS Chipyard Award #201662. +This work is supported by the NSF CCRI ENS Chipyard Award #2016662. [hwacha]:https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.pdf [hammer]:https://github.com/ucb-bar/hammer diff --git a/docs/Customization/Boot-Process.rst b/docs/Customization/Boot-Process.rst index a84c4e99..52ea32c1 100644 --- a/docs/Customization/Boot-Process.rst +++ b/docs/Customization/Boot-Process.rst @@ -12,7 +12,7 @@ Device Tree Binary (dtb) which details the components of the system. The assembly for the BootROM code is located in `generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.S `_. The BootROM address space starts at ``0x10000`` (determined by the ``BootROMParams`` key in the configuration) and execution starts at address -``0x10040`` (given by the linker script and reset vector in the ``BootROMParams``), which is marked by the ``_hang`` label in the BootROM assembly. +``0x10000`` (given by the linker script and reset vector in the ``BootROMParams``), which is marked by the ``_hang`` label in the BootROM assembly. The Chisel generator encodes the assembled instructions into the BootROM hardware at elaboration time, so if you want to change the BootROM code, you diff --git a/docs/Prototyping/Arty.rst b/docs/Prototyping/Arty.rst index 0575d811..843c05f5 100644 --- a/docs/Prototyping/Arty.rst +++ b/docs/Prototyping/Arty.rst @@ -34,7 +34,7 @@ Probe an address on the target system: .. code-block:: shell - ./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10040 none + ./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10000 none Write some address before running a program: diff --git a/docs/Prototyping/NexysVideo.rst b/docs/Prototyping/NexysVideo.rst index 773084b9..5256261f 100644 --- a/docs/Prototyping/NexysVideo.rst +++ b/docs/Prototyping/NexysVideo.rst @@ -34,7 +34,7 @@ Probe an address on the target system: .. code-block:: shell - ./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10040 none + ./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10000 none Write some address before running a program: diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 8f52be74..51d31094 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -29,7 +29,7 @@ import chipyard.{ExtTLMem} * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset * @param contentFileName the path to the BootROM image */ -class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => { +class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10000) extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site) .map(_.copy( address = address, diff --git a/generators/testchipip b/generators/testchipip index 6436959d..c4c0774f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6436959d997d0bb578790d95078648b478ca049b +Subproject commit c4c0774f5ff7a407dd81e5f0b4289a2fdd9e8d63 diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index d53eb2f0..237054f2 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -109,7 +109,7 @@ def generate_copy(c, sfx): new_file = os.path.join(args.gcpath, new_file) shutil.copy(cur_file, new_file) - bash(f"sed -i s/\"module {cur_name}\"/\"module {new_name}\"/ {new_file}") + bash(f"sed -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}") return new_file def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename): @@ -136,7 +136,7 @@ def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename): new_file = generate_copy(cur_file, MODEL_SFX) if parent is not None and ((parent, mod) not in updated_submodule): parent_file = os.path.join(args.gcpath, verilog_module_filename[parent]) - bash(f"sed -i s/\"{mod} \"/\"{mod}_{MODEL_SFX} \"/ {parent_file}") + bash(f"sed -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}") updated_submodule.add((parent, mod)) # add the uniquified module to the verilog_modul_filename dict