From d94a8efd4368763d141e6ee342c509a1fe19759d Mon Sep 17 00:00:00 2001
From: abejgonzalez <abe.j.gonza@gmail.com>
Date: Sun, 15 Nov 2020 15:44:38 -0800
Subject: [PATCH] Fix TLMemPort comment | Use Option instead of NoSimulator

---
 fpga/src/main/scala/vcu118/DigitalTop.scala   |  2 +-
 .../utilities/src/main/scala/Simulator.scala  | 25 +++++++++----------
 2 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/fpga/src/main/scala/vcu118/DigitalTop.scala b/fpga/src/main/scala/vcu118/DigitalTop.scala
index 9fe42bc8..d5c747fa 100644
--- a/fpga/src/main/scala/vcu118/DigitalTop.scala
+++ b/fpga/src/main/scala/vcu118/DigitalTop.scala
@@ -69,7 +69,7 @@ class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends
 // VCU118 Mem Port Mixin
 // ------------------------------------
 
-/** Adds a TileLink port to the system intended to master an MMIO device bus */
+/** Adds a port to the system intended to master an TL DRAM controller. */
 trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
   private val memPortParamsOpt = p(ExtMem)
   private val portName = "tl_mem"
diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala
index d7f4d007..fa157a36 100644
--- a/generators/utilities/src/main/scala/Simulator.scala
+++ b/generators/utilities/src/main/scala/Simulator.scala
@@ -5,13 +5,12 @@ import java.io.File
 case class GenerateSimConfig(
   targetDir: String = ".",
   dotFName: String = "sim_files.f",
-  simulator: Simulator = VerilatorSimulator,
+  simulator: Option[Simulator] = Some(VerilatorSimulator)
 )
 
 sealed trait Simulator
 object VerilatorSimulator extends Simulator
 object VCSSimulator extends Simulator
-object NoSimulator extends Simulator
 
 trait HasGenerateSimConfig {
   val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") {
@@ -21,9 +20,9 @@ trait HasGenerateSimConfig {
       .abbr("sim")
       .valueName("<simulator-name>")
       .action((x, c) => x match {
-        case "verilator" => c.copy(simulator = VerilatorSimulator)
-        case "vcs" => c.copy(simulator = VCSSimulator)
-        case "none" => c.copy(simulator = NoSimulator)
+        case "verilator" => c.copy(simulator = Some(VerilatorSimulator))
+        case "vcs" => c.copy(simulator = Some(VCSSimulator))
+        case "none" => c.copy(simulator = None)
         case _ => throw new Exception(s"Unrecognized simulator $x")
       })
       .text("Name of simulator to generate files for (verilator, vcs, none)")
@@ -49,10 +48,10 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
     if (fname.takeRight(2) == ".h") {
       cfg.simulator match {
         // verilator needs to explicitly include verilator.h, so use the -FI option
-        case VerilatorSimulator => s"-FI ${fname}"
+        case Some(VerilatorSimulator) => s"-FI ${fname}"
         // vcs pulls headers in with +incdir, doesn't have anything like verilator.h
-        case VCSSimulator => ""
-        case NoSimulator => ""
+        case Some(VCSSimulator) => ""
+        case None => ""
       }
     } else { // do nothing otherwise
       fname
@@ -84,7 +83,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
     out.write(text)
     out.close()
   }
-  def resources(sim: Simulator): Seq[String] = Seq(
+  def resources(sim: Option[Simulator]): Seq[String] = Seq(
     "/testchipip/csrc/SimSerial.cc",
     "/testchipip/csrc/testchip_tsi.cc",
     "/testchipip/csrc/testchip_tsi.h",
@@ -99,7 +98,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
     "/csrc/remote_bitbang.cc",
     "/vsrc/EICG_wrapper.v",
     ) ++ (sim match {
-      case NoSimulator => Seq()
+      case None => Seq()
       case _ => Seq(
         "/testchipip/csrc/SimSerial.cc",
         "/testchipip/csrc/SimDRAM.cc",
@@ -113,14 +112,14 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
         "/csrc/remote_bitbang.cc",
       )
     }) ++ (sim match { // simulator specific files to include
-      case VerilatorSimulator => Seq(
+      case Some(VerilatorSimulator) => Seq(
         "/csrc/emulator.cc",
         "/csrc/verilator.h",
       )
-      case VCSSimulator => Seq(
+      case Some(VCSSimulator) => Seq(
         "/vsrc/TestDriver.v",
       )
-      case NoSimulator => Seq()
+      case None => Seq()
     })
 
   def writeBootrom(): Unit = {