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Fixes UART portmap for Arty.

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Duy-Hieu Bui
2021-09-03 05:02:36 +07:00
parent 9d055fdac6
commit d9858c1dc8
1 changed files with 2 additions and 2 deletions
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4
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -72,8 +72,8 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) { withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_txd_in, ports.head.txd) IOBUF(th.uart_rxd_out, ports.head.txd)
ports.head.rxd := IOBUF(th.uart_rxd_out) ports.head.rxd := IOBUF(th.uart_txd_in)
} }
} }
}) })