Fast rocket config

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -81,7 +81,6 @@ class AbstractConfig extends Config(
   new chipyard.config.WithL2TLBs(1024) ++                           // use L2 TLBs
   new chipyard.config.WithNoSubsystemClockIO ++                     // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
   new chipyard.config.WithInheritBusFrequencyAssignments ++         // Unspecified clocks within a bus will receive the bus frequency if set
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++           // Don't add TL Monitors in the default configuration
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++      // Default 1 memory channels
   new freechips.rocketchip.subsystem.WithClockGateModel ++          // add default EICG_wrapper clock gate model
   new freechips.rocketchip.subsystem.WithJtagDTM ++                 // set the debug module to expose a JTAG port

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -97,6 +97,6 @@ class ClusteredRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithCluster(0) ++
   new chipyard.config.AbstractConfig)
 
-class TLMonitorRocketConfig extends Config(
-  new chipyard.config.WithTLMonitors ++
+class FastRTLSimRocketConfig extends Config(
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new chipyard.RocketConfig)

generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala

@@ -2,7 +2,7 @@ package chipyard.config
 
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.diplomacy.{DTSTimebase, MonitorsEnabled}
+import freechips.rocketchip.diplomacy.{DTSTimebase}
 import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
 
 // Replaces the L2 with a broadcast manager for maintaining coherence
@@ -31,7 +31,3 @@ class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = In
 class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
   case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
 })
-
-class WithTLMonitors extends Config((site, here, up) => {
-  case MonitorsEnabled => true
-})