Fast rocket config

docs/Simulation/Software-RTL-Simulation.rst

@@ -225,27 +225,26 @@ By enabling this, you will use Chipyard's ``numa_prefix`` wrapper, which is a si
 Note that both these flags are mutually exclusive, you can use either independently (though it makes sense to use ``NUMACTL`` just with ``VERILATOR_THREADS=8`` during a Verilator simulation).
 
 
-When the SoC Hangs Due to Bad Tilelink Messages
+Speeding up your RTL Simulation by 2x!
 -----------------------------------------------
 
 There are many cases when your custom module interfaces with Tilelink (e.g., when you write a custom accelerator).
 Wrong interfaces with Tilelink can cause the SoC to hang and can be tricky to debug.
 To help deal with these situations, you can add hardware modules called Tilelink monitors into
 your SoC that will fire assertions when wrong Tilelink messages are sent.
+However, these modules can significantly slow down the speed of your RTL simulation.
 
-You can simply add these modules into your SoC by adding the below line into your config.
+You can simply remove these modules by adding the below line into your config.
 
 .. code-block:: scala
 
-  new chipyard.config.WithTLMonitors ++
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
 
 
 For instance:
 
 .. code-block:: scala
 
-  class TLMonitorRocketConfig extends Config(
+  class FastRTLSimRocketConfig extends Config(
-    new chipyard.config.WithTLMonitors ++
+    new freechips.rocketchip.subsystem.WithoutTLMonitors ++
     new chipyard.RocketConfig)
-
-One caveat is that adding these modules can slow down your RTL simulation by around 2x.

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -81,7 +81,6 @@ class AbstractConfig extends Config(
   new chipyard.config.WithL2TLBs(1024) ++                           // use L2 TLBs
   new chipyard.config.WithNoSubsystemClockIO ++                     // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
   new chipyard.config.WithInheritBusFrequencyAssignments ++         // Unspecified clocks within a bus will receive the bus frequency if set
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++           // Don't add TL Monitors in the default configuration
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++      // Default 1 memory channels
   new freechips.rocketchip.subsystem.WithClockGateModel ++          // add default EICG_wrapper clock gate model
   new freechips.rocketchip.subsystem.WithJtagDTM ++                 // set the debug module to expose a JTAG port

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -97,6 +97,6 @@ class ClusteredRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithCluster(0) ++
   new chipyard.config.AbstractConfig)
 
-class TLMonitorRocketConfig extends Config(
+class FastRTLSimRocketConfig extends Config(
-  new chipyard.config.WithTLMonitors ++
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new chipyard.RocketConfig)

generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala

@@ -2,7 +2,7 @@ package chipyard.config
 
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.diplomacy.{DTSTimebase, MonitorsEnabled}
+import freechips.rocketchip.diplomacy.{DTSTimebase}
 import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
 
 // Replaces the L2 with a broadcast manager for maintaining coherence
@@ -31,7 +31,3 @@ class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = In
 class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
   case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
 })
-
-class WithTLMonitors extends Config((site, here, up) => {
-  case MonitorsEnabled => true
-})