From dab5720445dfec99c95a596ffc01080225c97d76 Mon Sep 17 00:00:00 2001 From: Haoan Li Date: Tue, 13 Dec 2022 16:53:31 +0900 Subject: [PATCH] expose functional pins and ports --- fpga/src/main/scala/vc707/IOBinders.scala | 2 +- fpga/src/main/scala/vc707/TestHarness.scala | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/fpga/src/main/scala/vc707/IOBinders.scala b/fpga/src/main/scala/vc707/IOBinders.scala index 6978e3c3..ad485571 100644 --- a/fpga/src/main/scala/vc707/IOBinders.scala +++ b/fpga/src/main/scala/vc707/IOBinders.scala @@ -25,7 +25,7 @@ class WithUARTIOPassthrough extends OverrideIOBinder({ } }) -class WithSPIIOPassthrough extends OverrideLazyIOBinder({ +class WithSPIIOPassthrough extends OverrideLazyIOBinder({ (system: HasPeripherySPI) => { // attach resource to 1st SPI ResourceBinding { diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index a7f571c8..bb2fa0b5 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLClientNode} import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay} import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} -import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, SPIOverlayKey, SPIDesignInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput} +import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, LEDOverlayKey, LEDDesignInput, SwitchOverlayKey, SwitchDesignInput, ButtonOverlayKey, ButtonDesignInput, SPIOverlayKey, SPIDesignInput, ChipLinkOverlayKey, ChipLinkDesignInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput, JTAGDebugOverlayKey, JTAGDebugDesignInput} import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler} import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO} @@ -31,7 +31,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She // place all clocks in the shell require(dp(ClockInputOverlayKey).size >= 1) - val sysClkNode = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()).overlayOutput.node + val sysClkNode = dp(ClockInputOverlayKey).head.place(ClockInputDesignInput()).overlayOutput.node /*** Connect/Generate clocks ***/ @@ -46,6 +46,18 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She val dutGroup = ClockGroup() dutClock := dutWrangler.node := dutGroup := harnessSysPLL + /*** LED ***/ + val ledModule = dp(LEDOverlayKey).map(_.place(LEDDesignInput()).overlayOutput.led) + + /*** Switch ***/ + val switchModule = dp(SwitchOverlayKey).map(_.place(SwitchDesignInput()).overlayOutput.sw) + + /*** Button ***/ + val buttonModule = dp(ButtonOverlayKey).map(_.place(ButtonDesignInput()).overlayOutput.but) + + /*** JTAG ***/ + val jtagModule = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput()).overlayOutput.jtag + /*** UART ***/ // 1st UART goes to the VC707 dedicated UART