wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Sync docs with CIRCT changes (#1312)

Browse Source
This commit is contained in:
joonho hwangbo
2023-01-17 16:14:09 -08:00
committed by GitHub
parent 749f84418e
commit db31427079
2 changed files with 12 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
docs/Simulation/Software-RTL-Simulation.rst
View File

@@ -144,8 +144,8 @@ All ``make`` targets that can be applied to the default example, can also be app
make SUB_PROJECT=hwacha run-asm-tests
Finally, in the ``generated-src/<...>-<package>-<config>/`` directory resides all of the collateral and Verilog source files for the build/simulation.
Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``.
Finally, in the ``generated-src/<...>-<package>-<config>/`` directory resides all of the collateral while the generated Verilog source files resides in ``generated-src/<...>-<package>-<config>/gen-collateral`` for the build/simulation.
Specifically, for ``CONFIG=RocketConfig`` the SoC top-level (``TOP``) Verilog file is ``ChipTop.sv`` while the (``Model``) file is ``TestHarness.sv``.
Fast Memory Loading
-------------------