Add BootROM | Fix ResetWrangler for DDR | Add scripts
This commit is contained in:
Abraham Gonzalez
45
fpga/scripts/run_impl_bitstream.tcl
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45
fpga/scripts/run_impl_bitstream.tcl
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#### Command line arguments to this script
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# argv[0] = absolute path to post_synth checkpoint file
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# argv[1] = part
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# argv[2] = output directory
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set synth_checkpoint_file [lindex $argv 0]
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set part [lindex $argv 1]
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set output_dir [lindex $argv 2]
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# Set the project part to the part passed into this script
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set_part ${part}
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# Create output directory if it doesn't exist
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file mkdir ${output_dir}
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file mkdir ${output_dir}/reports
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file mkdir ${output_dir}/outputs
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# Load synthesis checkpoint
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open_checkpoint ${synth_checkpoint_file}
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# Run implementation and save reports as needed
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opt_design
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place_design
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phys_opt_design
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write_checkpoint -force ${output_dir}/outputs/post_place
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report_timing_summary -file ${output_dir}/reports/post_place_timing_summary.rpt
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report_drc -file ${output_dir}/reports/post_place_drc.rpt
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route_design
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write_checkpoint -force ${output_dir}/outputs/post_route
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report_timing_summary -file ${output_dir}/reports/post_route_timing_summary.rpt
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report_timing -sort_by group -max_paths 100 -path_type summary -file ${output_dir}/reports/post_route_timing.rpt
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report_clock_utilization -file ${output_dir}/reports/post_route_clock_utilization.rpt
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report_utilization -file ${output_dir}/reports/post_route_utilization.rpt
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report_drc -file ${output_dir}/reports/post_route_drc.rpt
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report_cdc -details -file ${output_dir}/reports/post_route_cdc.rpt
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report_clock_interaction -file ${output_dir}/reports/post_route_clock_interaction.rpt
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report_bus_skew -file ${output_dir}/reports/post_route_bus_skew.rpt
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report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file ${output_dir}/reports/post_route_timing_violations.rpt
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write_verilog -force ${output_dir}/outputs/post_route.v
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write_xdc -no_fixed_only -force ${output_dir}/outputs/post_route.xdc
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write_bitstream -force ${output_dir}/outputs/top.bit
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write_debug_probes -force ${output_dir}/outputs/debug_nets.ltx
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75
fpga/scripts/write_mmi.tcl
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75
fpga/scripts/write_mmi.tcl
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proc write_mmi {filepath inst} {
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current_instance
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current_instance $inst
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set chn [open $filepath w]
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puts $chn "<?xml version=\"1.0\" encoding=\"UTF-8\"?>"
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puts $chn "<MemInfo Version=\"1\" Minor=\"0\">"
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puts $chn "\t<Processor Endianness=\"Little\" InstPath=\"${inst}\">"
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set brams [dict create]
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foreach cell [get_cells -hierarchical -filter { PRIMITIVE_GROUP =~ BLOCKRAM }] {
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set name [get_property RTL_RAM_NAME $cell]
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dict update brams $name name {
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dict lappend name cells $cell
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dict set name size [get_property RTL_RAM_BITS $cell]
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}
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}
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proc compare {a b} {
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set a_addr [get_property bram_addr_begin $a]
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set b_addr [get_property bram_addr_begin $b]
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if {$a_addr > $b_addr} {
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return 1
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} elseif {$a_addr < $b_addr} {
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return -1
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}
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set a_slice [get_property bram_slice_begin $a]
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set b_slice [get_property bram_slice_begin $b]
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if {$a_slice > $b_slice} {
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return 1
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} elseif {$a_slice < $b_slice} {
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return -1
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}
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return 0
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}
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dict for {name desc} $brams {
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dict with desc {
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puts $chn "\t\t<AddressSpace Name=\"${name}\" Begin=\"0\" End=\"[expr $size >> 3]\">"
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puts $chn "\t\t\t<BusBlock>"
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foreach cell [lsort -command compare $cells] {
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set type [switch [get_property REF_NAME $cell] \
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RAMB36E2 {expr {"RAMB32"}} \
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RAMB36E1 {expr {"RAMB32"}}]
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set loc [lindex [split [get_property LOC $cell] "_"] 1]
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set lsb [get_property bram_slice_begin $cell]
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set msb [get_property bram_slice_end $cell]
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set addr_bgn [get_property bram_addr_begin $cell]
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set addr_end [get_property bram_addr_end $cell]
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puts $chn "\t\t\t\t<BitLane MemType=\"${type}\" Placement=\"${loc}\">"
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puts $chn "\t\t\t\t\t<DataWidth MSB=\"${msb}\" LSB=\"${lsb}\"/>"
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puts $chn "\t\t\t\t\t<AddressRange Begin=\"${addr_bgn}\" End=\"${addr_end}\"/>"
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puts $chn "\t\t\t\t\t<Parity ON=\"false\" NumBits=\"0\"/>"
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puts $chn "\t\t\t\t</BitLane>"
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}
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puts $chn "\t\t\t</BusBlock>"
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puts $chn "\t\t</AddressSpace>"
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}
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}
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puts $chn "\t</Processor>"
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puts $chn "\t<Config>"
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puts $chn "\t\t<Option Name=\"Part\" Val=\"[get_property PART [current_project]]\"/>"
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puts $chn "\t</Config>"
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puts $chn "</MemInfo>"
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close $chn
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current_instance
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}
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if {$argc != 3} {
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puts $argc
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puts {Error: Invalid number of arguments}
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puts {Usage: write_mmi.tcl checkpoint mmi_file instance}
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}
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lassign $argv checkpoint mmi_file instance
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open_checkpoint $checkpoint
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write_mmi $mmi_file $instance
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