From 4c0314a46a2c93d8faae4914a8d226b616eea98e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 12 Mar 2023 11:19:37 -0700 Subject: [PATCH 001/184] Bump verilator --- conda-reqs/chipyard.yaml | 2 +- ...ements-riscv-tools-linux-64.conda-lock.yml | 200 ++++++++++-------- sims/verilator/Makefile | 2 +- 3 files changed, 114 insertions(+), 90 deletions(-) diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml index 9396f3b9..511fd70d 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard.yaml @@ -89,7 +89,7 @@ dependencies: - graphviz - expect - dtc - - verilator==4.226 + - verilator==5.006 - screen - elfutils - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index 673bc0f9..de819a23 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -19,7 +19,7 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: c24ce91cc2acc7e81ada9fe14d2a5dc398fc977952ab8ab03b82a6d32de079b3 + linux-64: e51f9c0b2e38f85b5879f02e9ae73bc539026c4e9196d97447f2249e5a486d43 platforms: - linux-64 sources: @@ -1421,16 +1421,16 @@ package: - category: main dependencies: gmp: '>=6.2.1,<7.0a0' - libgcc-ng: '>=7.5.0' + libgcc-ng: '>=12' hash: - md5: ea9ebeddb066da8fad4a815e61b139be - sha256: d2d71ac6ed3b32f06b7db2691e0a1760016ce13fb0c50a9de6ed1ccc33e35ff3 + md5: 14d87bdff2cbd3b1179a29fb316ed743 + sha256: 03097f21c75b0936471809e533dbae44af9d9ae696ecf264d1a929fc9f9e4b83 manager: conda name: mpfr optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/mpfr-4.1.0-h9202a9a_1.tar.bz2 - version: 4.1.0 + url: https://conda.anaconda.org/conda-forge/linux-64/mpfr-4.2.0-hb012696_0.conda + version: 4.2.0 - category: main dependencies: libffi: '>=3.4.2,<3.5.0a0' @@ -3078,14 +3078,14 @@ package: dependencies: python: '>=3.7' hash: - md5: 5aec57dd42104f4916c397fe291f9697 - sha256: bf40dd7bde1902859517888f72802fbc97709af7675de78eec38a1cd73ab898a + md5: e18ed61c37145bb9b48d1d98801960f7 + sha256: a5c48b1fc7c89c5c937475e9434a63af7ce2e591f8e51afd56e3b2e232a9989d manager: conda name: setuptools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/setuptools-67.5.1-pyhd8ed1ab_0.conda - version: 67.5.1 + url: https://conda.anaconda.org/conda-forge/noarch/setuptools-67.6.0-pyhd8ed1ab_0.conda + version: 67.6.0 - category: main dependencies: python: '>=3.6' @@ -3320,14 +3320,14 @@ package: dependencies: python: '>=3.7' hash: - md5: 2d93b130d148d7fc77e583677792fc6a - sha256: 70c57b5ac94cd32e78f1a2fa2c38572bfac85b901a6a99aa254a9e8e126c132d + md5: 43e7d9e50261fb11deb76e17d8431aac + sha256: f81eee64fcdfb379e27d01773b34041fbf7f9e86f33b157c9925d19e0a442452 manager: conda name: typing_extensions optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/typing_extensions-4.4.0-pyha770c72_0.tar.bz2 - version: 4.4.0 + url: https://conda.anaconda.org/conda-forge/noarch/typing_extensions-4.5.0-pyha770c72_0.conda + version: 4.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -3365,18 +3365,19 @@ package: gxx_impl_linux-64: '' libgcc-ng: '>=12' libstdcxx-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' + libzlib: '>=1.2.13,<1.3.0a0' make: '' perl: '' + python: '' hash: - md5: 41af6df1758bae89161daf268566384e - sha256: e2f2302d69c0d6928d95a1c699b5ef0b14e0243e78495734962c78136d2e6b9f + md5: 1a0130b3de431ee4dd26734a234a1cde + sha256: 12971e7e175a7dfb70d4afcf76e38d1ed21a979d49e215d439e7392de221a14d manager: conda name: verilator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/verilator-4.226-he0ac6c6_1.tar.bz2 - version: '4.226' + url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.006-h07cc95c_1.conda + version: '5.006' - category: main dependencies: gettext: '>=0.21.1,<1.0a0' @@ -3523,6 +3524,19 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/zipp-3.15.0-pyhd8ed1ab_0.conda version: 3.15.0 +- category: main + dependencies: + python: '>=3.6' + typing_extensions: '>=4.0' + hash: + md5: 59c40397276a286241c65faec5e1be3c + sha256: be2dbd6710438fa48b83bf06841091227276ae545d145dfe5cb5149c6484e951 + manager: conda + name: aioitertools + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/aioitertools-0.11.0-pyhd8ed1ab_0.tar.bz2 + version: 0.11.0 - category: main dependencies: frozenlist: '>=1.1.0' @@ -4171,16 +4185,16 @@ package: version: 2.28.11.15 - category: main dependencies: - typing_extensions: 4.4.0 pyha770c72_0 + typing_extensions: 4.5.0 pyha770c72_0 hash: - md5: be969210b61b897775a0de63cd9e9026 - sha256: 6f129b1bc18d111dcf3abaec6fcf6cbee00f1b77bb42d0f0bc8d85f8faa65cf0 + md5: b3c594fde1a80a1fc3eb9cc4a5dfe392 + sha256: 6da5e15fa533620ae2e7aca9a7d16013eed3a73ac64c47d7c3bf3deec39b63b9 manager: conda name: typing-extensions optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.4.0-hd8ed1ab_0.tar.bz2 - version: 4.4.0 + url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.5.0-hd8ed1ab_0.conda + version: 4.5.0 - category: main dependencies: libgcc-ng: '>=9.3.0' @@ -4416,20 +4430,19 @@ package: dependencies: attrs: '>=17.4.0' importlib-metadata: '' - importlib_resources: '>=1.4.0' - pkgutil-resolve-name: '>=1.3.10' - pyrsistent: '!=0.17.0,!=0.17.1,!=0.17.2,>=0.14.0' - python: '>=3.7' - typing_extensions: '' + pyrsistent: '>=0.14.0' + python: '>=3.6' + setuptools: '' + six: '>=1.11.0' hash: - md5: 723268a468177cd44568eb8f794e0d80 - sha256: 4f68a23430d1afc5c9b41c46fbac0ade33c0bf57a293c646bfdd6dc65350eada + md5: 66125e28711d8ffc04a207a2b170316d + sha256: d74a3ddd3c3dd9bd7b00110a196e3af90490c5660674f18bfd53a8fdf91de418 manager: conda name: jsonschema optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/jsonschema-4.17.3-pyhd8ed1ab_0.conda - version: 4.17.3 + url: https://conda.anaconda.org/conda-forge/noarch/jsonschema-3.2.0-pyhd8ed1ab_3.tar.bz2 + version: 3.2.0 - category: main dependencies: elfutils: '>=0.187,<0.188.0a0' @@ -4635,14 +4648,14 @@ package: types-awscrt: '' typing_extensions: '' hash: - md5: 1284ea7cf431f599298c3e86922cb6ef - sha256: 949071f4ffaada1a7df890a0eca82507446f427d913272bae109c39f42b03361 + md5: 038f7d8f0f0b7cae4aee87bfbd09bd06 + sha256: 4c3babde56c86a3d0f83add59002275f8e8fd328acf432377c86ceb82b693131 manager: conda name: botocore-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.87-pyhd8ed1ab_0.conda - version: 1.29.87 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.88-pyhd8ed1ab_0.conda + version: 1.29.88 - category: main dependencies: clang-format: 15.0.7 default_had23c3d_1 @@ -4775,19 +4788,17 @@ package: version: 3.7.1 - category: main dependencies: - attrs: '>=19.2.0' - jsonschema: '>=4.0.0,<5.0.0' + jsonschema: '>=3.0.0,<5.0.0' python: '>=3.7' - rfc3339-validator: '' hash: - md5: 8b32c5ef540b6afe23ea8e75dd400fbb - sha256: 8e69b65ffdc0d71f5d924c34d8e45bb2ca169573db29ede1844a46a2c8e3a5d0 + md5: 277aff70bb1def188c9c016ba4564e23 + sha256: 0c2f971f86211f2b6db431de9d8ab4c9e38eed5422bd06f93cd8be3cbb882a2c manager: conda name: openapi-schema-validator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/openapi-schema-validator-0.4.3-pyhd8ed1ab_0.conda - version: 0.4.3 + url: https://conda.anaconda.org/conda-forge/noarch/openapi-schema-validator-0.2.3-pyhd8ed1ab_0.tar.bz2 + version: 0.2.3 - category: main dependencies: alsa-lib: '>=1.2.8,<1.2.9.0a0' @@ -5024,22 +5035,20 @@ package: version: 2.54.4 - category: main dependencies: - importlib_resources: '>=5.8.0,<6.0.0' - jsonschema: '>=4.0.0,<5.0.0' - jsonschema-spec: '>=0.1.1,<0.2.0' - lazy-object-proxy: '>=1.7.1,<2.0.0' - openapi-schema-validator: '>=0.4.2,<0.5' + jsonschema: '>=3.2.0,<5.0.0' + openapi-schema-validator: '>=0.2.0,<0.3.0' python: '>=3.7' pyyaml: '>=5.1' + setuptools: '' hash: - md5: 243b7dc9b3e129a2e7d5f2ca690f337c - sha256: 3053d96adb90a7dd6002c1151531485d9973a94050139a233701c3c25f94e0ea + md5: 5ff3ff67d18fd4938c4ae38c3baf21bb + sha256: 11f24d36001aaba0a7197ff7b9a07ab943d05f969b13e5a9c4ffec13eca19cd0 manager: conda name: openapi-spec-validator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/openapi-spec-validator-0.5.5-pyhd8ed1ab_0.conda - version: 0.5.5 + url: https://conda.anaconda.org/conda-forge/noarch/openapi-spec-validator-0.4.0-pyhd8ed1ab_1.tar.bz2 + version: 0.4.0 - category: main dependencies: cfgv: '>=2.0.0' @@ -5081,14 +5090,14 @@ package: pysocks: '>=1.5.6,<2.0,!=1.5.7' python: <4.0 hash: - md5: 01f33ad2e0aaf6b5ba4add50dad5ad29 - sha256: f2f09c44e47946ce631dbc9a8a79bb463ac0f4122aaafdbcc51f200a1e420ca6 + md5: 27db656619a55d727eaf5a6ece3d2fd6 + sha256: 213bdf6c3a5d721fa83b45d527d3ecd340f9547c0d6bbd0b8d9d746ec9a1fb4b manager: conda name: urllib3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/urllib3-1.26.14-pyhd8ed1ab_0.conda - version: 1.26.14 + url: https://conda.anaconda.org/conda-forge/noarch/urllib3-1.26.15-pyhd8ed1ab_0.conda + version: 1.26.15 - category: main dependencies: jmespath: '>=0.7.1,<2.0.0' @@ -5096,14 +5105,14 @@ package: python-dateutil: '>=2.1,<3.0.0' urllib3: '>=1.25.4,<1.27' hash: - md5: 2b1918369bcec3f3ff8dc380c60dff99 - sha256: 15b4107b40b9c39b3ca3631acc64f9734c71a7f1ede4e3b9c28275a2f62c4777 + md5: 7aa03b260e0e7803fafc414707cac996 + sha256: 9c3f2b48b8b69e436f80c4b5bd716ba4410ea1fe5f851406916e43f3feca05df manager: conda name: botocore optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.87-pyhd8ed1ab_0.conda - version: 1.29.87 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.88-pyhd8ed1ab_0.conda + version: 1.29.88 - category: main dependencies: cairo: '>=1.16.0,<2.0a0' @@ -5149,6 +5158,22 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/requests-2.28.2-pyhd8ed1ab_0.conda version: 2.28.2 +- category: main + dependencies: + aiohttp: '>=3.3.1' + aioitertools: '>=0.5.1' + botocore: '>=1.27.59,<1.27.60' + python: '>=3.6' + wrapt: '>=1.10.10' + hash: + md5: a3f48ea10883a5df371b895008b1ca4b + sha256: 76068553358b26c9c03be992cbe982a369d1e015a53700f092db92c784ce98a9 + manager: conda + name: aiobotocore + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/aiobotocore-2.4.2-pyhd8ed1ab_0.conda + version: 2.4.2 - category: main dependencies: botocore: '>=1.11.3' @@ -5347,7 +5372,7 @@ package: version: 5.1.1 - category: main dependencies: - botocore: 1.29.87 + botocore: 1.29.88 colorama: '>=0.2.5,<0.4.5' docutils: '>=0.10,<0.17' python: '>=3.9,<3.10.0a0' @@ -5356,29 +5381,29 @@ package: rsa: '>=3.1.2,<4.8' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: e34597b1774f550f23cca3fb3ad44079 - sha256: b92577f1601b257e7fc64bef8e733a8be7ac2ce1602d53e05c4497902371ad3c + md5: e9c5b0e909628d74e4ce807bb2a7693f + sha256: 2c641bc5be23dc659180c46126cb509034c67e4e5d3f68dc286d06199459f57e manager: conda name: awscli optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.87-py39hf3d152e_0.conda - version: 1.27.87 + url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.88-py39hf3d152e_0.conda + version: 1.27.88 - category: main dependencies: - botocore: '>=1.29.87,<1.30.0' + botocore: '>=1.29.88,<1.30.0' jmespath: '>=0.7.1,<2.0.0' python: '>=3.7' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: 81cc299ce1dec9d92f55163356553fbe - sha256: 4712065876e3303bda6b2995770f2a7c131f6184b4d372c055ba505f56c77b50 + md5: 6d9d3d9ed7d005bf4180948445cf15a7 + sha256: f073885ff0739d25e35d62aa202f44df59fa75beb95a247b0f041c4973964c4b manager: conda name: boto3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.87-pyhd8ed1ab_0.conda - version: 1.26.87 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.88-pyhd8ed1ab_0.conda + version: 1.26.88 - category: main dependencies: cachecontrol: 0.12.11 pyhd8ed1ab_1 @@ -5500,20 +5525,19 @@ package: version: 2.0.0 - category: main dependencies: - boto3: '>=1.19.5,<2' - jsonschema: '>=3.2,<5' - pydantic: ~=1.10.2 - python: '>=3.7' - typing_extensions: ~=4.4.0 + boto3: ~=1.5 + jsonschema: ~=3.2 + python: '>=3.6' + six: ~=1.15 hash: - md5: 1136b4bb3893069daeb272a3d6aecd7b - sha256: 9d9316f995fa2aedd97a8495b1a8b87265d3d8fc0771c8a0e51da7c3c1a0571c + md5: 6a8ad721f4edea85a40070c78f379dd4 + sha256: d9b2ff5fdf1e8de7cf80f2a14a7cb76c65c0bae18a2fe51700e6ed3c71fdb5b5 manager: conda name: aws-sam-translator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.60.1-pyhd8ed1ab_0.conda - version: 1.60.1 + url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.55.0-pyhd8ed1ab_0.conda + version: 1.55.0 - category: main dependencies: azure-core: '>=1.11.0,<2.0.0' @@ -5537,14 +5561,14 @@ package: python: '' typing_extensions: '' hash: - md5: 5a9a5263ff74eabd589aab692b8d56cf - sha256: 2f4a2d7918d6aa3256c9491ccd3786206c1329825c2b7a21c902b0cb77c82703 + md5: 0665225dcc452177ebf284917328c4c1 + sha256: b03ab85abbac40c456ae8447d8a03345f54a6c7690efc1e1cf687db0ace600b8 manager: conda name: boto3-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.87-pyhd8ed1ab_0.conda - version: 1.26.87 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.88-pyhd8ed1ab_0.conda + version: 1.26.88 - category: main dependencies: cachecontrol-with-filecache: '>=0.12.9' @@ -5685,14 +5709,14 @@ package: werkzeug: <2.2.0,>=0.5 xmltodict: '' hash: - md5: 24a19f3ea233ebd0cc0b8e6e0bc5df58 - sha256: 55e3f4fd163518afd72e926d88011cc47933779c97523b4d64b3680f99bd787b + md5: 7b8eaea28d5c08c8539c3b35a07fe3d1 + sha256: 47f8f38a9eff042ebd7754fa6c36739021c0e6cdca1848cc4b0138cfc4043ace manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.3-pyhd8ed1ab_0.conda - version: 4.1.3 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.4-pyhd8ed1ab_0.conda + version: 4.1.4 - dependencies: {} hash: sha256: ae88eca3024bb34bb3430f964beab71226e761f51b912de5133470b649d82344 diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index d48da28e..a6b97a1e 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -92,7 +92,7 @@ HELP_COMPILATION_VARIABLES += \ ######################################################################################### # verilator/cxx binary and flags ######################################################################################### -VERILATOR := verilator --cc --exe +VERILATOR := verilator --cc --exe --timing #---------------------------------------------------------------------------------------- # user configs From 95349755b553b66554ce55825ddad8964dd89f92 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 12 Mar 2023 12:51:31 -0700 Subject: [PATCH 002/184] Support TestDriver.v as top --- .../src/main/resources/csrc/emulator.cc | 394 ------------------ sims/common-sim-flags.mk | 14 + sims/vcs/Makefile | 4 +- vcs.mk => sims/vcs/vcs.mk | 13 +- sims/verilator/Makefile | 65 ++- vlsi/Makefile | 2 +- 6 files changed, 43 insertions(+), 449 deletions(-) delete mode 100644 generators/chipyard/src/main/resources/csrc/emulator.cc rename vcs.mk => sims/vcs/vcs.mk (82%) diff --git a/generators/chipyard/src/main/resources/csrc/emulator.cc b/generators/chipyard/src/main/resources/csrc/emulator.cc deleted file mode 100644 index 40b5a2fa..00000000 --- a/generators/chipyard/src/main/resources/csrc/emulator.cc +++ /dev/null @@ -1,394 +0,0 @@ -// See LICENSE.SiFive for license details. -// See LICENSE.Berkeley for license details. - -#if VM_TRACE -#include -#if CY_FST_TRACE -#include "verilated_fst_c.h" -#else -#include "verilated.h" -#include "verilated_vcd_c.h" -#endif // CY_FST_TRACE -#endif // VM_TRACE -#include -#include -#include "remote_bitbang.h" -#include -#include -#include -#include -#include -#include -#include - -// For option parsing, which is split across this file, Verilog, and -// FESVR's HTIF, a few external files must be pulled in. The list of -// files and what they provide is enumerated: -// -// $RISCV/include/fesvr/htif.h: -// defines: -// - HTIF_USAGE_OPTIONS -// - HTIF_LONG_OPTIONS_OPTIND -// - HTIF_LONG_OPTIONS -// $(ROCKETCHIP_DIR)/generated-src(-debug)?/$(CONFIG).plusArgs: -// defines: -// - PLUSARG_USAGE_OPTIONS -// variables: -// - static const char * verilog_plusargs - -extern tsi_t* tsi; -extern dtm_t* dtm; -extern remote_bitbang_t * jtag; - -static uint64_t trace_count = 0; -bool verbose = false; -bool done_reset = false; - -void handle_sigterm(int sig) -{ - dtm->stop(); -} - -double sc_time_stamp() -{ - return trace_count; -} - -static void usage(const char * program_name) -{ - printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n", - program_name); - fputs("\ -Run a BINARY on the Rocket Chip emulator.\n\ -\n\ -Mandatory arguments to long options are mandatory for short options too.\n\ -\n\ -EMULATOR OPTIONS\n\ - -c, --cycle-count Print the cycle count before exiting\n\ - +cycle-count\n\ - -h, --help Display this help and exit\n\ - -m, --max-cycles=CYCLES Kill the emulation after CYCLES\n\ - +max-cycles=CYCLES\n\ - -s, --seed=SEED Use random number seed SEED\n\ - -r, --rbb-port=PORT Use PORT for remote bit bang (with OpenOCD and GDB) \n\ - If not specified, a random port will be chosen\n\ - automatically.\n\ - -V, --verbose Enable all Chisel printfs (cycle-by-cycle info)\n\ - +verbose\n\ -", stdout); -#if VM_TRACE == 0 - fputs("\ -\n\ -EMULATOR DEBUG OPTIONS (only supported in debug build -- try `make debug`)\n", - stdout); -#endif - fputs("\ - -v, --vcd=FILE, Write vcd trace to FILE (or '-' for stdout)\n\ - -x, --dump-start=CYCLE Start VCD tracing at CYCLE\n\ - +dump-start\n\ -", stdout); - fputs("\n" PLUSARG_USAGE_OPTIONS, stdout); - fputs("\n" HTIF_USAGE_OPTIONS, stdout); - printf("\n" -"EXAMPLES\n" -" - run a bare metal test:\n" -" %s $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n" -" - run a bare metal test showing cycle-by-cycle information:\n" -" %s +verbose $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add 2>&1 | spike-dasm\n" -#if VM_TRACE -" - run a bare metal test to generate a VCD waveform:\n" -" %s -v rv64ui-p-add.vcd $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n" -#endif -" - run an ELF (you wrote, called 'hello') using the proxy kernel:\n" -" %s pk hello\n", - program_name, program_name, program_name -#if VM_TRACE - , program_name -#endif - ); -} - -int main(int argc, char** argv) -{ - unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid(); - uint64_t max_cycles = -1; - int ret = 0; - bool print_cycles = false; - // Port numbers are 16 bit unsigned integers. - uint16_t rbb_port = 0; -#if VM_TRACE - const char* vcdfile_name = NULL; - FILE * vcdfile = NULL; - uint64_t start = 0; -#endif - int verilog_plusargs_legal = 1; - - int verilated_argc = 1; - char** verilated_argv = new char*[argc]; - verilated_argv[0] = argv[0]; - - opterr = 1; - - while (1) { - static struct option long_options[] = { - {"cycle-count", no_argument, 0, 'c' }, - {"help", no_argument, 0, 'h' }, - {"max-cycles", required_argument, 0, 'm' }, - {"seed", required_argument, 0, 's' }, - {"rbb-port", required_argument, 0, 'r' }, - {"verbose", no_argument, 0, 'V' }, - {"permissive", no_argument, 0, 'p' }, - {"permissive-off", no_argument, 0, 'o' }, -#if VM_TRACE - {"vcd", required_argument, 0, 'v' }, - {"dump-start", required_argument, 0, 'x' }, -#endif - HTIF_LONG_OPTIONS - }; - int option_index = 0; -#if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:po", long_options, &option_index); -#else - int c = getopt_long(argc, argv, "-chm:s:r:Vpo", long_options, &option_index); -#endif - if (c == -1) break; - retry: - switch (c) { - // Process long and short EMULATOR options - case '?': usage(argv[0]); return 1; - case 'c': print_cycles = true; break; - case 'h': usage(argv[0]); return 0; - case 'm': max_cycles = atoll(optarg); break; - case 's': random_seed = atoi(optarg); break; - case 'r': rbb_port = atoi(optarg); break; - case 'V': verbose = true; break; - case 'p': opterr = 0; break; - case 'o': opterr = 1; break; -#if VM_TRACE - case 'v': { - vcdfile_name = optarg; - vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); - if (!vcdfile) { - std::cerr << "Unable to open " << optarg << " for VCD write\n"; - return 1; - } - break; - } - case 'x': start = atoll(optarg); break; -#endif - // Process legacy '+' EMULATOR arguments by replacing them with - // their getopt equivalents - case 1: { - std::string arg = optarg; - if (arg.substr(0, 1) != "+") { - optind--; - goto done_processing; - } - if (arg == "+verbose") - c = 'V'; - else if (arg.substr(0, 12) == "+max-cycles=") { - c = 'm'; - optarg = optarg+12; - } -#if VM_TRACE - else if (arg.substr(0, 12) == "+dump-start=") { - c = 'x'; - optarg = optarg+12; - } -#endif - else if (arg.substr(0, 12) == "+cycle-count") - c = 'c'; - else if (arg == "+permissive") - { - c = 'p'; - verilated_argv[verilated_argc++] = optarg; - } - else if (arg == "+permissive-off") - { - c = 'o'; - verilated_argv[verilated_argc++] = optarg; - } - // If we don't find a legacy '+' EMULATOR argument, it still could be - // a VERILOG_PLUSARG and not an error. - else if (verilog_plusargs_legal) { - const char ** plusarg = &verilog_plusargs[0]; - int legal_verilog_plusarg = 0; - while (*plusarg && (legal_verilog_plusarg == 0)){ - if (arg.substr(1, strlen(*plusarg)) == *plusarg) { - legal_verilog_plusarg = 1; - } - plusarg ++; - } - if (!legal_verilog_plusarg) { - verilog_plusargs_legal = 0; - } else { - c = 'P'; - } - goto retry; - } - // If we STILL don't find a legacy '+' argument, it still could be - // an HTIF (HOST) argument and not an error. If this is the case, then - // we're done processing EMULATOR and VERILOG arguments. - else { - static struct option htif_long_options [] = { HTIF_LONG_OPTIONS }; - struct option * htif_option = &htif_long_options[0]; - while (htif_option->name) { - if (arg.substr(1, strlen(htif_option->name)) == htif_option->name) { - optind--; - goto done_processing; - } - htif_option++; - } - if(opterr) { - std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" - << arg << "\"\n"; - c = '?'; - } else { - c = 'P'; - } - } - goto retry; - } - case 'P': // Verilog PlusArg, add to the argument list for verilator environment - verilated_argv[verilated_argc++] = optarg; - break; - // Realize that we've hit HTIF (HOST) arguments or error out - default: - if (c >= HTIF_LONG_OPTIONS_OPTIND) { - optind--; - goto done_processing; - } - c = '?'; - goto retry; - } - } - -done_processing: - if (optind == argc) { - std::cerr << "No binary specified for emulator\n"; - usage(argv[0]); - return 1; - } - - // Copy remaining HTIF arguments (if any) and the binary file name into the verilator argument stack - while (optind < argc) verilated_argv[verilated_argc++] = argv[optind++]; - - if (verbose) - fprintf(stderr, "using random seed %u\n", random_seed); - - srand(random_seed); - srand48(random_seed); - - Verilated::randReset(2); - Verilated::commandArgs(verilated_argc, verilated_argv); - TEST_HARNESS *tile = new TEST_HARNESS; - -#if VM_TRACE - Verilated::traceEverOn(true); // Verilator must compute traced signals -#if CY_FST_TRACE - std::unique_ptr tfp(new VerilatedFstC); -#else - std::unique_ptr vcdfd(new VerilatedVcdFILE(vcdfile)); - std::unique_ptr tfp(new VerilatedVcdC(vcdfd.get())); -#endif // CY_FST_TRACE - if (vcdfile_name) { - tile->trace(tfp.get(), 99); // Trace 99 levels of hierarchy - tfp->open(vcdfile_name); - } -#endif // VM_TRACE - - // RocketChip currently only supports RBB port 0, so this needs to stay here - jtag = new remote_bitbang_t(rbb_port); - - signal(SIGTERM, handle_sigterm); - - bool dump; - // start reset off low so a rising edge triggers async reset - tile->reset = 0; - tile->clock = 0; - tile->eval(); - // reset for several cycles to handle pipelined reset - for (int i = 0; i < 100; i++) { - tile->reset = 1; - tile->clock = 0; - tile->eval(); -#if VM_TRACE - dump = tfp && trace_count >= start; - if (dump) - tfp->dump(static_cast(trace_count * 2)); -#endif - tile->clock = 1; - tile->eval(); -#if VM_TRACE - if (dump) - tfp->dump(static_cast(trace_count * 2 + 1)); -#endif - trace_count ++; - } - tile->reset = 0; - done_reset = true; - - do { - tile->clock = 0; - tile->eval(); -#if VM_TRACE - dump = tfp && trace_count >= start; - if (dump) - tfp->dump(static_cast(trace_count * 2)); -#endif - - tile->clock = 1; - tile->eval(); -#if VM_TRACE - if (dump) - tfp->dump(static_cast(trace_count * 2 + 1)); -#endif - trace_count++; - } - // for verilator multithreading. need to do 1 loop before checking if - // tsi exists, since tsi is created by verilated thread on the first - // serial_tick. - while ((!dtm || !dtm->done()) && - (!jtag || !jtag->done()) && - (!tsi || !tsi->done()) && - !tile->io_success && trace_count < max_cycles); - -#if VM_TRACE - if (tfp) - tfp->close(); - if (vcdfile) - fclose(vcdfile); -#endif - - if (dtm && dtm->exit_code()) - { - fprintf(stderr, "*** FAILED *** via dtm (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count); - ret = dtm->exit_code(); - } - else if (tsi && tsi->exit_code()) - { - fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", tsi->exit_code(), random_seed, trace_count); - ret = tsi->exit_code(); - } - else if (jtag && jtag->exit_code()) - { - fprintf(stderr, "*** FAILED *** via jtag (code = %d, seed %d) after %ld cycles\n", jtag->exit_code(), random_seed, trace_count); - ret = jtag->exit_code(); - } - else if (trace_count == max_cycles) - { - fprintf(stderr, "*** FAILED *** via trace_count (timeout, seed %d) after %ld cycles\n", random_seed, trace_count); - ret = 2; - } - else if (verbose || print_cycles) - { - fprintf(stderr, "*** PASSED *** Completed after %ld cycles\n", trace_count); - } - - if (dtm) delete dtm; - if (tsi) delete tsi; - if (jtag) delete jtag; - if (tile) delete tile; - if (verilated_argv) delete[] verilated_argv; - return ret; -} diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 0736b43c..c2ae022c 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -33,3 +33,17 @@ SIM_LDFLAGS = \ -lfesvr \ -ldramsim \ $(EXTRA_SIM_LDFLAGS) + +CLOCK_PERIOD ?= 1.0 +RESET_DELAY ?= 777.7 + +SIM_PREPROC_DEFINES = \ + +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ + +define+RESET_DELAY=$(RESET_DELAY) \ + +define+PRINTF_COND=$(TB).printf_cond \ + +define+STOP_COND=!$(TB).reset \ + +define+MODEL=$(MODEL) \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index b6f11a80..fc0a9fdb 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,7 +25,7 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -include $(base_dir)/vcs.mk +include $(sim_dir)/vcs.mk .PHONY: default debug default: $(sim) @@ -56,7 +56,7 @@ include $(base_dir)/common.mk ######################################################################################### VCS = vcs -full64 -VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES) +VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(SIM_PREPROC_DEFINES) $(VCS_PREPROC_DEFINES) ######################################################################################### # vcs build paths diff --git a/vcs.mk b/sims/vcs/vcs.mk similarity index 82% rename from vcs.mk rename to sims/vcs/vcs.mk index edd19f8c..31784ad9 100644 --- a/vcs.mk +++ b/sims/vcs/vcs.mk @@ -53,17 +53,8 @@ VCS_NONCC_OPTS = \ -debug_pp \ +incdir+$(GEN_COLLATERAL_DIR) -PREPROC_DEFINES = \ - +define+VCS \ - +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ - +define+RESET_DELAY=$(RESET_DELAY) \ - +define+PRINTF_COND=$(TB).printf_cond \ - +define+STOP_COND=!$(TB).reset \ - +define+MODEL=$(MODEL) \ - +define+RANDOMIZE_MEM_INIT \ - +define+RANDOMIZE_REG_INIT \ - +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN +VCS_PREPROC_DEFINES = \ + +define+VCS ifndef USE_VPD PREPROC_DEFINES += +define+FSDB diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index a6b97a1e..9e22821d 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,8 +28,6 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -WAVEFORM_FLAG=-v$(sim_out_name).vcd - include $(base_dir)/sims/common-sim-flags.mk # If verilator seed unspecified, verilator uses srand as random seed @@ -47,23 +45,7 @@ debug: $(sim_debug) # simulaton requirements ######################################################################################### SIM_FILE_REQS += \ - $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ - -# the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build) -SIM_FILE_REQS += \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc + $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files and add -FI for *.h files in *.f $(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR) @@ -87,12 +69,15 @@ HELP_COMPILATION_VARIABLES += \ " 'all' if full verilator runtime profiling" \ " 'threads' if runtime thread profiling only" \ " VERILATOR_THREADS = how many threads the simulator will use (default 1)" \ -" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build" +" USE_FST = set to '1' to build Verilator simulator to emit FST instead of VCD." + +HELP_SIMULATION_VARIABLES += \ +" USE_FST = set to '1' to run Verilator simulator emitting FST instead of VCD." ######################################################################################### # verilator/cxx binary and flags ######################################################################################### -VERILATOR := verilator --cc --exe --timing +VERILATOR := verilator --main --timing --cc --exe #---------------------------------------------------------------------------------------- # user configs @@ -107,10 +92,12 @@ RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\ VERILATOR_THREADS ?= 1 RUNTIME_THREADS := --threads $(VERILATOR_THREADS) --threads-dpi all -VERILATOR_FST_MODE ?= 0 -TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\ +USE_FST ?= 0 +TRACING_OPTS := $(if $(filter $(USE_FST),0),\ --trace,--trace-fst --trace-threads 1) -TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) +# TODO: consider renaming +vcdfile in TestDriver.v to +waveformfile (or similar) +WAVEFORM_FLAG := +vcdfile=$(sim_out_name).$(if $(filter $(USE_FST),0),\ + vcd,fst) #---------------------------------------------------------------------------------------- # verilation configuration/optimization @@ -153,9 +140,8 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 # see: https://github.com/ucb-bar/riscv-mini/issues/31 MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }') -PREPROC_DEFINES := \ - +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) +VERILATOR_PREPROC_DEFINES = \ + +define+VERILATOR VERILATOR_NONCC_OPTS = \ $(RUNTIME_PROFILING_VFLAGS) \ @@ -165,8 +151,9 @@ VERILATOR_NONCC_OPTS = \ -Wno-fatal \ $(TIMESCALE_OPTS) \ $(MAX_WIDTH_OPTS) \ - $(PREPROC_DEFINES) \ - --top-module $(VLOG_MODEL) \ + $(SIM_PREPROC_DEFINES) \ + $(VERILATOR_PREPROC_DEFINES) \ + --top-module $(TB) \ --vpi \ -f $(sim_common_files) @@ -176,12 +163,8 @@ VERILATOR_NONCC_OPTS = \ VERILATOR_CXXFLAGS = \ $(SIM_CXXFLAGS) \ $(RUNTIME_PROFILING_CFLAGS) \ - $(TRACING_CFLAGS) \ - -D__STDC_FORMAT_MACROS \ - -DTEST_HARNESS=V$(VLOG_MODEL) \ -DVERILATOR \ - -include $(build_dir)/$(long_name).plusArgs \ - -include $(GEN_COLLATERAL_DIR)/verilator.h + -include $(build_dir)/$(long_name).plusArgs VERILATOR_LDFLAGS = $(SIM_LDFLAGS) @@ -200,11 +183,11 @@ VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug -model_header = $(model_dir)/V$(VLOG_MODEL).h -model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h +model_header = $(model_dir)/V$(TB).h +model_header_debug = $(model_dir_debug)/V$(TB).h -model_mk = $(model_dir)/V$(VLOG_MODEL).mk -model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk +model_mk = $(model_dir)/V$(TB).mk +model_mk_debug = $(model_dir_debug)/V$(TB).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules @@ -218,17 +201,17 @@ $(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS) $(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir_debug) mkdir -p $(model_dir_debug) - $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" + $(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ ######################################################################################### # invoke make to make verilator sim rules ######################################################################################### $(sim): $(model_mk) $(dramsim_lib) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk $(sim_debug): $(model_mk_debug) $(dramsim_lib) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk ######################################################################################### # create a verilator vpd rule diff --git a/vlsi/Makefile b/vlsi/Makefile index 8259e7a6..a19e63fe 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -134,7 +134,7 @@ $(SYN_CONF): $(VLSI_RTL) ######################################################################################### # simulation and power input configuration ######################################################################################### -include $(base_dir)/vcs.mk +include $(base_dir)/sims/vcs/vcs.mk SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v From d4dcbe3297044b9d9d19d14ba214d2b2dfbb4150 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 14 Mar 2023 15:45:39 -0700 Subject: [PATCH 003/184] Static cast enums --- generators/ibex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/ibex b/generators/ibex index 5a512227..771a4f4e 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 5a512227d8f6d2929cc354c02d40200002e661e5 +Subproject commit 771a4f4ee94bf7ad144b328775ac1ab011443a8a From 93f1c5cf333a96048f7a21de8355e272ddc05c8f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 25 Mar 2023 21:34:10 -0700 Subject: [PATCH 004/184] Bump sifive-blocks --- generators/sifive-blocks | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 4273925f..8311bc8a 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 4273925fdd5d8872d6b6a8dec6cee3330b9a68c7 +Subproject commit 8311bc8abceaa4e785b7c42d47b2116b3a92e44d From f474646c17532c200d56bfb42b8f42eaf22a22f0 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 25 Mar 2023 21:34:32 -0700 Subject: [PATCH 005/184] Add chosen node to DTS to enable dynamic earlycon select --- .../chipyard/src/main/scala/Subsystem.scala | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 34175d39..3b4d312b 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -12,6 +12,7 @@ import freechips.rocketchip.prci._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey} +import sifive.blocks.devices.uart.{HasPeripheryUART, PeripheryUARTKey} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ @@ -45,9 +46,35 @@ trait CanHaveHTIF { this: BaseSubsystem => } } +// This trait adds the "chosen" node to DTS, which +// can be used to pass information to OS about the earlycon +case object ChosenInDTS extends Field[Boolean](true) +trait CanHaveChosenInDTS { this: BaseSubsystem => + if (p(ChosenInDTS)) { + println("got here") + this match { + case t: HasPeripheryUART if (!p(PeripheryUARTKey).isEmpty) => { + println("Add chosen resource") + val chosen = new Device { + def describe(resources: ResourceBindings): Description = { + val stdout = resources("stdout").map(_.value) + Description("chosen", resources("uart").headOption.map { case Binding(_, value) => + "stdout-path" -> Seq(value) + }.toMap) + } + } + ResourceBinding { + t.uarts.foreach(u => Resource(chosen, "uart").bind(ResourceAlias(u.device.label))) + } + } + } + } +} + class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem with HasTiles with CanHaveHTIF + with CanHaveChosenInDTS { def coreMonitorBundles = tiles.map { case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle From c1d609a03cf3cc7ba934df7bf716762bb622a5b0 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 25 Mar 2023 21:35:20 -0700 Subject: [PATCH 006/184] Add hello world to baremetal tests --- tests/Makefile | 3 ++- tests/hello.c | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 tests/hello.c diff --git a/tests/Makefile b/tests/Makefile index 54959bf0..8756350d 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -6,7 +6,8 @@ LDFLAGS= -static include libgloss.mk PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \ - streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd + streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd \ + hello spiflash.img: spiflash.py python3 $< diff --git a/tests/hello.c b/tests/hello.c new file mode 100644 index 00000000..28d667e0 --- /dev/null +++ b/tests/hello.c @@ -0,0 +1,6 @@ +#include + +int main(void) { + printf("Hello world\n"); + return 0; +} From 298aadafc5383a151a2fb61d55be191699a143f3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 25 Mar 2023 21:41:40 -0700 Subject: [PATCH 007/184] Add support for TightlyCoupledMemory for SpikeTile --- .../src/main/resources/csrc/spiketile.cc | 160 ++++++++++++++- .../src/main/resources/vsrc/spiketile.v | 59 +++++- .../chipyard/src/main/scala/SpikeTile.scala | 182 +++++++++++++----- .../src/main/scala/config/SpikeConfigs.scala | 17 +- 4 files changed, 351 insertions(+), 67 deletions(-) diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index 4d2bb8a5..9942364f 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -6,6 +6,9 @@ #include #include #include +#include "testchip_tsi.h" + +extern testchip_tsi_t* tsi; enum transfer_t { NToB, @@ -73,6 +76,12 @@ public: void dcache_b(uint64_t address, uint64_t source, int param); bool dcache_c(uint64_t *address, uint64_t* source, int* param, unsigned char* voluntary, unsigned char* has_data, uint64_t* data[8]); void dcache_d(uint64_t sourceid, uint64_t data[8], unsigned char has_data, unsigned char grantack); + + void tcm_a(uint64_t address, uint64_t data, uint32_t mask, uint32_t opcode, uint32_t size); + bool tcm_d(uint64_t *data); + + void loadmem(const char* fname); + void drain_stq(); bool stq_empty() { return st_q.size() == 0; }; @@ -86,9 +95,13 @@ public: char* readonly_uncacheable, char* executable, size_t icache_sourceids, - size_t dcache_sourceids); + size_t dcache_sourceids, + size_t tcm_base, + size_t tcm_size); uint64_t cycle; bool use_stq; + htif_t *htif; + bool fast_clint; private: bool handle_cache_access(reg_t addr, size_t len, uint8_t* load_bytes, @@ -133,6 +146,11 @@ private: uint64_t mmio_stdata; size_t mmio_len; uint64_t mmio_lddata; + + uint64_t tcm_base; + uint64_t tcm_size; + uint8_t* tcm; + std::vector tcm_q; }; class tile_t { @@ -163,6 +181,7 @@ extern "C" void spike_tile(int hartid, char* isa, int dcache_sets, int dcache_ways, char* cacheable, char* uncacheable, char* readonly_uncacheable, char* executable, int icache_sourceids, int dcache_sourceids, + long long int tcm_base, long long int tcm_size, long long int reset_vector, long long int ipc, long long int cycle, @@ -237,7 +256,18 @@ extern "C" void spike_tile(int hartid, char* isa, int* mmio_a_size, unsigned char mmio_d_valid, - long long int mmio_d_data + long long int mmio_d_data, + + unsigned char tcm_a_valid, + long long int tcm_a_address, + long long int tcm_a_data, + int tcm_a_mask, + int tcm_a_opcode, + int tcm_a_size, + + unsigned char* tcm_d_valid, + unsigned char tcm_d_ready, + long long int* tcm_d_data ) { if (!host) { @@ -251,7 +281,8 @@ extern "C" void spike_tile(int hartid, char* isa, chipyard_simif_t* simif = new chipyard_simif_t(icache_ways, icache_sets, dcache_ways, dcache_sets, cacheable, uncacheable, readonly_uncacheable, executable, - icache_sourceids, dcache_sourceids); + icache_sourceids, dcache_sourceids, + tcm_base, tcm_size); std::string* isastr = new std::string(isa); cfg_t* cfg = new cfg_t(std::make_pair(0, 0), nullptr, @@ -264,7 +295,7 @@ extern "C" void spike_tile(int hartid, char* isa, std::vector(), std::vector(), false, - 0); + 0); processor_t* p = new processor_t(isa_parser, cfg, simif, @@ -278,6 +309,7 @@ extern "C" void spike_tile(int hartid, char* isa, s_vpi_vlog_info vinfo; if (!vpi_get_vlog_info(&vinfo)) abort(); + std::string loadmem_file = ""; for (int i = 1; i < vinfo.argc; i++) { std::string arg(vinfo.argv[i]); if (arg == "+spike-debug") { @@ -286,7 +318,15 @@ extern "C" void spike_tile(int hartid, char* isa, if (arg == "+spike-stq") { simif->use_stq = true; } + if (arg.find("+loadmem=") == 0) { + loadmem_file = arg.substr(strlen("+loadmem=")); + } + if (arg == "+spike-fast-clint") { + simif->fast_clint = true; + } } + if (loadmem_file != "" && tcm_size > 0) + simif->loadmem(loadmem_file.c_str()); p->reset(); p->get_state()->pc = reset_vector; @@ -296,6 +336,9 @@ extern "C" void spike_tile(int hartid, char* isa, tile_t* tile = tiles[hartid]; chipyard_simif_t* simif = tile->simif; processor_t* proc = tile->proc; + if (!simif->htif && tsi) { + simif->htif = (htif_t*) tsi; + } simif->cycle = cycle; if (debug) { @@ -357,6 +400,13 @@ extern "C" void spike_tile(int hartid, char* isa, if (mmio_d_valid) { simif->mmio_d(mmio_d_data); } + + if (tcm_a_valid) { + simif->tcm_a(tcm_a_address, tcm_a_data, tcm_a_mask, tcm_a_opcode, tcm_a_size); + } + if (tcm_d_ready) { + *tcm_d_valid = simif->tcm_d((uint64_t*)tcm_d_data); + } } @@ -369,14 +419,20 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, char* readonly_uncacheable, char* executable, size_t ic_sourceids, - size_t dc_sourceids + size_t dc_sourceids, + size_t tcm_base, + size_t tcm_size ) : cycle(0), use_stq(false), + htif(nullptr), + fast_clint(false), icache_ways(icache_ways), icache_sets(icache_sets), dcache_ways(dcache_ways), dcache_sets(dcache_sets), + tcm_base(tcm_base), + tcm_size(tcm_size), mmio_valid(false), mmio_inflight(false) { @@ -432,6 +488,8 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, uint64_t size_int = std::stoul(size); executables.push_back(mem_region_t { base_int, size_int }); } + + tcm = (uint8_t*)malloc(tcm_size); } bool chipyard_simif_t::reservable(reg_t addr) { @@ -440,12 +498,20 @@ bool chipyard_simif_t::reservable(reg_t addr) { return true; } } + if (addr >= tcm_base && addr < tcm_base + tcm_size) { + return true; + } return false; } bool chipyard_simif_t::mmio_fetch(reg_t addr, size_t len, uint8_t* bytes) { bool executable = false; + if (addr >= tcm_base && addr < tcm_base + tcm_size) { + memcpy(bytes, tcm + addr - tcm_base, len); + return true; + } + for (auto& r: executables) { if (addr >= r.base && addr + len <= r.base + r.size) { executable = true; @@ -466,6 +532,10 @@ bool chipyard_simif_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) { bool found = false; bool cacheable = false; bool readonly = false; + if (addr >= tcm_base && addr < tcm_base + tcm_size) { + memcpy(bytes, tcm + addr - tcm_base, len); + return true; + } for (auto& r: cacheables) { if (addr >= r.base && addr + len <= r.base + r.size) { cacheable = true; @@ -829,9 +899,14 @@ bool chipyard_simif_t::dcache_c(uint64_t* address, uint64_t* source, int* param, } bool chipyard_simif_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) { + if (addr >= tcm_base && addr < tcm_base + tcm_size) { + memcpy(tcm + addr - tcm_base, bytes, len); + return true; + } + bool found = false; bool cacheable = false; - for (auto& r: cacheables) { + for (auto& r: cacheables) { if (addr >= r.base && addr + len <= r.base + r.size) { cacheable = true; found = true; @@ -899,11 +974,64 @@ void chipyard_simif_t::dcache_d(uint64_t sourceid, uint64_t data[8], unsigned ch } } +void chipyard_simif_t::tcm_a(uint64_t address, uint64_t data, uint32_t mask, uint32_t opcode, uint32_t size) { + bool load = opcode == 4; + uint64_t rdata = 0; + memcpy(&rdata, tcm + address - tcm_base, 8); + tcm_q.push_back(rdata); + + if (!load) { + for (size_t i = 0; i < 8; i++) { + if ((mask >> i) & 1) { + memcpy(tcm + address - tcm_base + i, ((uint8_t*)&data) + i, 1); + } + } + } +} + +bool chipyard_simif_t::tcm_d(uint64_t* data) { + if (tcm_q.size() == 0) + return false; + *data = tcm_q[0]; + tcm_q.erase(tcm_q.begin()); + return true; +} + +#define parse_nibble(c) ((c) >= 'a' ? (c)-'a'+10 : (c)-'0') +void chipyard_simif_t::loadmem(const char* fname) { + std::ifstream in(fname); + std::string line; + if (!in.is_open()) { + printf("SpikeTile couldn't open loadmem file %s\n", fname); + abort(); + } + size_t fsize = 0; + size_t start = 0; + while (std::getline(in, line)) { + for (ssize_t i = line.length()-2, j = 0; i >= 0; i -= 2, j++) { + char byte = (parse_nibble(line[i]) << 4) | parse_nibble(line[i+1]); + ssize_t addr = (start + j) % tcm_size; + tcm[addr] = (uint8_t)byte; + } + start += line.length()/2; + fsize += line.length()/2; + + if (fsize > tcm_size) { + fprintf(stderr, "Loadmem file is too large\n"); + abort(); + } + } +} + bool insn_should_fence(uint64_t bits) { uint8_t opcode = bits & 0x7f; return opcode == 0b0101111 || opcode == 0b0001111; } +bool insn_is_wfi(uint64_t bits) { + return bits == 0x10500073; +} + void spike_thread_main(void* arg) { tile_t* tile = (tile_t*) arg; @@ -913,12 +1041,30 @@ void spike_thread_main(void* arg) } while (tile->max_insns != 0) { // TODO: Fences don't work - // uint64_t last_bits = tile->proc->get_last_bits(); + //uint64_t last_bits = tile->proc->get_last_bits(); // if (insn_should_fence(last_bits) && !tile->simif->stq_empty()) { // host->switch_to(); // } + uint64_t old_minstret = tile->proc->get_state()->minstret->read(); tile->proc->step(1); tile->max_insns--; + if (tile->proc->is_waiting_for_interrupt()) { + if (tile->simif->fast_clint) { + tile->proc->get_state()->mip->backdoor_write_with_mask(MIP_MTIP, MIP_MTIP); + } + tile->max_insns = 0; + } + if (tile->max_insns % 100 == 0) { + uint64_t tohost_addr = tile->simif->htif ? tile->simif->htif->get_tohost_addr() : 0; + uint64_t fromhost_addr = tile->simif->htif ? tile->simif->htif->get_fromhost_addr() : 0; + auto& mem_read = tile->proc->get_state()->log_mem_read; + reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]); + if ((old_minstret == tile->proc->get_state()->minstret->read()) || + (tohost_addr && mem_read_addr == tohost_addr) || + (fromhost_addr && mem_read_addr == fromhost_addr)) { + tile->max_insns == 0; + } + } tile->proc->get_state()->mcycle->write(tile->simif->cycle); } } diff --git a/generators/chipyard/src/main/resources/vsrc/spiketile.v b/generators/chipyard/src/main/resources/vsrc/spiketile.v index 87254e35..c78d7a0f 100644 --- a/generators/chipyard/src/main/resources/vsrc/spiketile.v +++ b/generators/chipyard/src/main/resources/vsrc/spiketile.v @@ -13,6 +13,8 @@ import "DPI-C" function void spike_tile(input int hartid, input string executable, input int icache_sourceids, input int dcache_sourceids, + input longint tcm_base, + input longint tcm_size, input longint reset_vector, input longint ipc, input longint cycle, @@ -89,7 +91,18 @@ import "DPI-C" function void spike_tile(input int hartid, output int mmio_a_size, input bit mmio_d_valid, - input longint mmio_d_data + input longint mmio_d_data, + + input bit tcm_a_valid, + input longint tcm_a_address, + input longint tcm_a_data, + input int tcm_a_mask, + input int tcm_a_opcode, + input int tcm_a_size, + + output bit tcm_d_valid, + input bit tcm_d_ready, + output longint tcm_d_data ); @@ -106,7 +119,9 @@ module SpikeBlackBox #( parameter READONLY_UNCACHEABLE, parameter EXECUTABLE, parameter ICACHE_SOURCEIDS, - parameter DCACHE_SOURCEIDS )( + parameter DCACHE_SOURCEIDS, + parameter TCM_BASE, + parameter TCM_SIZE)( input clock, input reset, input [63:0] reset_vector, @@ -185,7 +200,18 @@ module SpikeBlackBox #( output [31:0] mmio_a_size, input mmio_d_valid, - input [63:0] mmio_d_data + input [63:0] mmio_d_data, + + input tcm_a_valid, + input [63:0] tcm_a_address, + input [63:0] tcm_a_data, + input [31:0] tcm_a_mask, + input [31:0] tcm_a_opcode, + input [31:0] tcm_a_size, + + output tcm_d_valid, + input tcm_d_ready, + output [63:0] tcm_d_data ); longint __insns_retired; @@ -257,7 +283,13 @@ module SpikeBlackBox #( reg [63:0] __dcache_c_data_6_reg; reg [63:0] __dcache_c_data_7_reg; - + wire __tcm_d_ready; + bit __tcm_d_valid; + longint __tcm_d_data; + + reg __tcm_d_valid_reg; + reg [63:0] __tcm_d_data_reg; + always @(posedge clock) begin @@ -322,12 +354,18 @@ module SpikeBlackBox #( __dcache_c_data_6_reg <= 64'h0; __dcache_c_data_7 = 64'h0; __dcache_c_data_7_reg <= 64'h0; + + __tcm_d_valid = 1'b0; + __tcm_d_valid_reg <= 1'b0; + __tcm_d_data = 64'h0; + __tcm_d_data_reg <= 64'h0; spike_tile_reset(HARTID); end else begin spike_tile(HARTID, ISA, PMPREGIONS, ICACHE_SETS, ICACHE_WAYS, DCACHE_SETS, DCACHE_WAYS, CACHEABLE, UNCACHEABLE, READONLY_UNCACHEABLE, EXECUTABLE, ICACHE_SOURCEIDS, DCACHE_SOURCEIDS, + TCM_BASE, TCM_SIZE, reset_vector, ipc, cycle, __insns_retired, debug, mtip, msip, meip, seip, @@ -350,7 +388,10 @@ module SpikeBlackBox #( dcache_d_data_4, dcache_d_data_5, dcache_d_data_6, dcache_d_data_7, __mmio_a_ready, __mmio_a_valid, __mmio_a_address, __mmio_a_data, __mmio_a_store, __mmio_a_size, - mmio_d_valid, mmio_d_data + mmio_d_valid, mmio_d_data, + + tcm_a_valid, tcm_a_address, tcm_a_data, tcm_a_mask, tcm_a_opcode, tcm_a_size, + __tcm_d_valid, __tcm_d_ready, __tcm_d_data ); __insns_retired_reg <= __insns_retired; @@ -385,6 +426,10 @@ module SpikeBlackBox #( __mmio_a_data_reg <= __mmio_a_data; __mmio_a_store_reg <= __mmio_a_store; __mmio_a_size_reg <= __mmio_a_size; + + __tcm_d_valid_reg <= __tcm_d_valid; + __tcm_d_data_reg <= __tcm_d_data; + end end // always @ (posedge clock) assign insns_retired = __insns_retired_reg; @@ -424,6 +469,8 @@ module SpikeBlackBox #( assign mmio_a_size = __mmio_a_size_reg; assign __mmio_a_ready = mmio_a_ready; - + assign tcm_d_valid = __tcm_d_valid_reg; + assign tcm_d_data = __tcm_d_data_reg; + assign __tcm_d_ready = tcm_d_ready; endmodule; diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index c7e5b69d..98c750ce 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -15,8 +15,7 @@ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci.ClockSinkParameters -case class SpikeCoreParams( -) extends CoreParams { +case class SpikeCoreParams() extends CoreParams { val useVM = true val useHypervisor = false val useSupervisor = true @@ -79,7 +78,8 @@ case class SpikeTileParams( hartId: Int = 0, val core: SpikeCoreParams = SpikeCoreParams(), icacheParams: ICacheParams = ICacheParams(nWays = 32), - dcacheParams: DCacheParams = DCacheParams(nWays = 32) + dcacheParams: DCacheParams = DCacheParams(nWays = 32), + tcmParams: Option[MasterPortParams] = None // tightly coupled memory ) extends InstantiableTileParams[SpikeTile] { val name = Some("spike_tile") @@ -145,6 +145,27 @@ class SpikeTile( sourceId = IdRange(0, 1), requestFifo = true)))))) + tlSlaveXbar.node :*= slaveNode + val tcmNode = spikeTileParams.tcmParams.map { tcmP => + val device = new MemoryDevice + val base = AddressSet.misaligned(tcmP.base, tcmP.size) + val tcmNode = TLManagerNode(Seq(TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = base, + resources = device.reg, + regionType = RegionType.IDEMPOTENT, // not cacheable + executable = true, + supportsGet = TransferSizes(1, 8), + supportsPutFull = TransferSizes(1, 8), + supportsPutPartial = TransferSizes(1, 8), + fifoId = Some(0) + )), + beatBytes = 8 + ))) + connectTLSlave(tcmNode := TLBuffer(), 8) + tcmNode + } + tlOtherMastersNode := TLBuffer() := tlMasterXbar.node masterNode :=* tlOtherMastersNode tlMasterXbar.node := TLWidthWidget(64) := TLBuffer():= icacheNode @@ -166,7 +187,9 @@ class SpikeBlackBox( cacheable_regions: String, uncacheable_regions: String, readonly_uncacheable_regions: String, - executable_regions: String) extends BlackBox(Map( + executable_regions: String, + tcm_base: BigInt, + tcm_size: BigInt) extends BlackBox(Map( "HARTID" -> IntParam(hartId), "ISA" -> StringParam(isa), "PMPREGIONS" -> IntParam(pmpregions), @@ -179,7 +202,9 @@ class SpikeBlackBox( "UNCACHEABLE" -> StringParam(uncacheable_regions), "READONLY_UNCACHEABLE" -> StringParam(readonly_uncacheable_regions), "CACHEABLE" -> StringParam(cacheable_regions), - "EXECUTABLE" -> StringParam(executable_regions) + "EXECUTABLE" -> StringParam(executable_regions), + "TCM_BASE" -> IntParam(tcm_base), + "TCM_SIZE" -> IntParam(tcm_size) )) with HasBlackBoxResource { val io = IO(new Bundle { @@ -258,6 +283,22 @@ class SpikeBlackBox( val data = Input(UInt(64.W)) } } + + val tcm = new Bundle { + val a = new Bundle { + val valid = Input(Bool()) + val address = Input(UInt(64.W)) + val data = Input(UInt(64.W)) + val mask = Input(UInt(32.W)) + val opcode = Input(UInt(32.W)) + val size = Input(UInt(32.W)) + } + val d = new Bundle { + val valid = Output(Bool()) + val ready = Input(Bool()) + val data = Output(UInt(64.W)) + } + } }) addResource("/vsrc/spiketile.v") addResource("/csrc/spiketile.cc") @@ -289,7 +330,10 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { tileParams.icache.get.nSets, tileParams.icache.get.nWays, tileParams.dcache.get.nSets, tileParams.dcache.get.nWays, tileParams.dcache.get.nMSHRs, - cacheable_regions, uncacheable_regions, readonly_uncacheable_regions, executable_regions)) + cacheable_regions, uncacheable_regions, readonly_uncacheable_regions, executable_regions, + outer.spikeTileParams.tcmParams.map(_.base).getOrElse(0), + outer.spikeTileParams.tcmParams.map(_.size).getOrElse(0) + )) spike.io.clock := clock.asBool val cycle = RegInit(0.U(64.W)) cycle := cycle + 1.U @@ -304,64 +348,63 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { spike.io.msip := int_bundle.msip spike.io.meip := int_bundle.meip spike.io.seip := int_bundle.seip.get - spike.io.ipc := PlusArg("spike-ipc", 10000, width=64) + spike.io.ipc := PlusArg("spike-ipc", width=32, default=10000) val blockBits = log2Ceil(p(CacheBlockBytes)) - - val icache_a_q = Module(new Queue(new TLBundleA(icacheEdge.bundle), 1, flow=true, pipe=true)) - spike.io.icache.a.ready := icache_a_q.io.enq.ready && icache_a_q.io.count === 0.U - icache_tl.a <> icache_a_q.io.deq - icache_a_q.io.enq.valid := spike.io.icache.a.valid - icache_a_q.io.enq.bits := icacheEdge.Get( + spike.io.icache.a.ready := icache_tl.a.ready + icache_tl.a.valid := spike.io.icache.a.valid + icache_tl.a.bits := icacheEdge.Get( fromSource = spike.io.icache.a.sourceid, toAddress = (spike.io.icache.a.address >> blockBits) << blockBits, lgSize = blockBits.U)._2 - icache_tl.d.ready := true.B spike.io.icache.d.valid := icache_tl.d.valid spike.io.icache.d.sourceid := icache_tl.d.bits.source spike.io.icache.d.data := icache_tl.d.bits.data.asTypeOf(Vec(8, UInt(64.W))) - val dcache_a_q = Module(new Queue(new TLBundleA(dcacheEdge.bundle), 1, flow=true, pipe=true)) - spike.io.dcache.a.ready := dcache_a_q.io.enq.ready && dcache_a_q.io.count === 0.U - dcache_tl.a <> dcache_a_q.io.deq - dcache_a_q.io.enq.valid := spike.io.dcache.a.valid - dcache_a_q.io.enq.bits := dcacheEdge.AcquireBlock( - fromSource = spike.io.dcache.a.sourceid, - toAddress = (spike.io.dcache.a.address >> blockBits) << blockBits, - lgSize = blockBits.U, - growPermissions = Mux(spike.io.dcache.a.state_old, 2.U, Mux(spike.io.dcache.a.state_new, 1.U, 0.U)))._2 - + spike.io.dcache.a.ready := dcache_tl.a.ready + dcache_tl.a.valid := spike.io.dcache.a.valid + if (dcacheEdge.manager.anySupportAcquireB) { + dcache_tl.a.bits := dcacheEdge.AcquireBlock( + fromSource = spike.io.dcache.a.sourceid, + toAddress = (spike.io.dcache.a.address >> blockBits) << blockBits, + lgSize = blockBits.U, + growPermissions = Mux(spike.io.dcache.a.state_old, 2.U, Mux(spike.io.dcache.a.state_new, 1.U, 0.U)))._2 + } else { + dcache_tl.a.bits := DontCare + } dcache_tl.b.ready := true.B spike.io.dcache.b.valid := dcache_tl.b.valid spike.io.dcache.b.address := dcache_tl.b.bits.address spike.io.dcache.b.source := dcache_tl.b.bits.source spike.io.dcache.b.param := dcache_tl.b.bits.param - val dcache_c_q = Module(new Queue(new TLBundleC(dcacheEdge.bundle), 1, flow=true, pipe=true)) - spike.io.dcache.c.ready := dcache_c_q.io.enq.ready && dcache_c_q.io.count === 0.U - dcache_tl.c <> dcache_c_q.io.deq - dcache_c_q.io.enq.valid := spike.io.dcache.c.valid - dcache_c_q.io.enq.bits := Mux(spike.io.dcache.c.voluntary, - dcacheEdge.Release( - fromSource = spike.io.dcache.c.sourceid, - toAddress = spike.io.dcache.c.address, - lgSize = blockBits.U, - shrinkPermissions = spike.io.dcache.c.param, - data = spike.io.dcache.c.data.asUInt)._2, - Mux(spike.io.dcache.c.has_data, - dcacheEdge.ProbeAck( + spike.io.dcache.c.ready := dcache_tl.c.ready + dcache_tl.c.valid := spike.io.dcache.c.valid + if (dcacheEdge.manager.anySupportAcquireB) { + dcache_tl.c.bits := Mux(spike.io.dcache.c.voluntary, + dcacheEdge.Release( fromSource = spike.io.dcache.c.sourceid, toAddress = spike.io.dcache.c.address, lgSize = blockBits.U, - reportPermissions = spike.io.dcache.c.param, - data = spike.io.dcache.c.data.asUInt), - dcacheEdge.ProbeAck( - fromSource = spike.io.dcache.c.sourceid, - toAddress = spike.io.dcache.c.address, - lgSize = blockBits.U, - reportPermissions = spike.io.dcache.c.param) - )) + shrinkPermissions = spike.io.dcache.c.param, + data = spike.io.dcache.c.data.asUInt)._2, + Mux(spike.io.dcache.c.has_data, + dcacheEdge.ProbeAck( + fromSource = spike.io.dcache.c.sourceid, + toAddress = spike.io.dcache.c.address, + lgSize = blockBits.U, + reportPermissions = spike.io.dcache.c.param, + data = spike.io.dcache.c.data.asUInt), + dcacheEdge.ProbeAck( + fromSource = spike.io.dcache.c.sourceid, + toAddress = spike.io.dcache.c.address, + lgSize = blockBits.U, + reportPermissions = spike.io.dcache.c.param) + )) + } else { + dcache_tl.c.bits := DontCare + } val has_data = dcacheEdge.hasData(dcache_tl.d.bits) val should_finish = dcacheEdge.isRequest(dcache_tl.d.bits) @@ -376,12 +419,10 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { dcache_tl.e.valid := dcache_tl.d.valid && should_finish dcache_tl.e.bits := dcacheEdge.GrantAck(dcache_tl.d.bits) - val mmio_a_q = Module(new Queue(new TLBundleA(mmioEdge.bundle), 1, flow=true, pipe=true)) - spike.io.mmio.a.ready := mmio_a_q.io.enq.ready && mmio_a_q.io.count === 0.U - mmio_tl.a <> mmio_a_q.io.deq - mmio_a_q.io.enq.valid := spike.io.mmio.a.valid + spike.io.mmio.a.ready := mmio_tl.a.ready + mmio_tl.a.valid := spike.io.mmio.a.valid val log_size = MuxCase(0.U, (0 until 3).map { i => (spike.io.mmio.a.size === (1 << i).U) -> i.U }) - mmio_a_q.io.enq.bits := Mux(spike.io.mmio.a.store, + mmio_tl.a.bits := Mux(spike.io.mmio.a.store, mmioEdge.Put(0.U, spike.io.mmio.a.address, log_size, spike.io.mmio.a.data)._2, mmioEdge.Get(0.U, spike.io.mmio.a.address, log_size)._2) @@ -389,9 +430,33 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { spike.io.mmio.d.valid := mmio_tl.d.valid spike.io.mmio.d.data := mmio_tl.d.bits.data + spike.io.tcm := DontCare + spike.io.tcm.a.valid := false.B + spike.io.tcm.d.ready := true.B + outer.tcmNode.map { tcmNode => + val (tcm_tl, tcmEdge) = tcmNode.in(0) + val debug_tcm_tl = WireInit(tcm_tl) + dontTouch(debug_tcm_tl) + tcm_tl.a.ready := true.B + spike.io.tcm.a.valid := tcm_tl.a.valid + spike.io.tcm.a.address := tcm_tl.a.bits.address + spike.io.tcm.a.data := tcm_tl.a.bits.data + spike.io.tcm.a.mask := tcm_tl.a.bits.mask + spike.io.tcm.a.opcode := tcm_tl.a.bits.opcode + spike.io.tcm.a.size := tcm_tl.a.bits.size + + spike.io.tcm.d.ready := tcm_tl.d.ready + tcm_tl.d.bits := tcmEdge.AccessAck(RegNext(tcm_tl.a.bits)) + when (RegNext(tcm_tl.a.bits.opcode === TLMessages.Get)) { + tcm_tl.d.bits.opcode := TLMessages.AccessAckData + } + tcm_tl.d.valid := spike.io.tcm.d.valid + tcm_tl.d.bits.data := spike.io.tcm.d.data + } } -class WithNSpikeCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => { +class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams(), + overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { // Calculate the next available hart ID (since hart ID cannot be duplicated) val prev = up(TilesLocated(InSubsystem), site) @@ -399,8 +464,21 @@ class WithNSpikeCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends // Create TileAttachParams for every core to be instantiated (0 until n).map { i => SpikeTileAttachParams( - tileParams = SpikeTileParams(hartId = i + idOffset) + tileParams = tileParams.copy(hartId = i + idOffset) ) } ++ prev } }) + +class WithSpikeTCM extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => { + val prev = up(TilesLocated(InSubsystem)) + require(prev.size == 1) + val spike = prev(0).asInstanceOf[SpikeTileAttachParams] + Seq(spike.copy(tileParams = spike.tileParams.copy( + tcmParams = Some(up(ExtMem).get.master) + ))) + } + case ExtMem => None + case BankedL2Key => up(BankedL2Key).copy(nBanks = 0) +}) diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index b45245c0..0d9972a9 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -1,6 +1,7 @@ package chipyard import freechips.rocketchip.config.{Config} +import freechips.rocketchip.rocket.{DCacheParams} // Configs which instantiate a Spike-simulated // tile that interacts with the Chipyard SoC @@ -14,6 +15,18 @@ class SpikeConfig extends Config( class SpikeFastUARTConfig extends Config( new chipyard.WithNSpikeCores(1) ++ new chipyard.config.WithUARTFIFOEntries(128, 128) ++ - new chipyard.config.WithMemoryBusFrequency(1) ++ - new chipyard.config.WithPeripheryBusFrequency(1) ++ + new chipyard.config.WithMemoryBusFrequency(2) ++ + new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.AbstractConfig) + +// Makes the UART fast, also builds no L2 and a ludicrous L1D +class SpikeUltraFastConfig extends Config( + new chipyard.WithSpikeTCM ++ + new chipyard.WithNSpikeCores(1) ++ + new testchipip.WithSerialPBusMem ++ + new chipyard.config.WithUARTFIFOEntries(128, 128) ++ + new chipyard.config.WithMemoryBusFrequency(2) ++ + new chipyard.config.WithPeripheryBusFrequency(2) ++ + new chipyard.config.WithBroadcastManager ++ + new chipyard.config.AbstractConfig) + From 0c5b29707131455d433a7dd95d9ff2d7f76141a1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 25 Mar 2023 21:45:56 -0700 Subject: [PATCH 008/184] Bump riscv-isa-sim --- toolchains/riscv-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 34bebfe3..a6eb6c2a 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 34bebfe31183289b5428b9a363a4596750030d3f +Subproject commit a6eb6c2a99ec7a23640d2aee5f3c05dc35c223d9 From 24b416c40bc954a86fe8630e28aeb23d37474ab5 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 25 Mar 2023 22:20:54 -0700 Subject: [PATCH 009/184] Set DTS to say we are chipyard --- generators/chipyard/src/main/scala/config/AbstractConfig.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index b084845e..c13139bf 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -60,4 +60,5 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 + new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system From b077361749e2bcc48b171e33d18aca925f7e238c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 26 Mar 2023 09:20:15 -0700 Subject: [PATCH 010/184] Bump sifive-blocks --- generators/sifive-blocks | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 8311bc8a..8e022e15 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 8311bc8abceaa4e785b7c42d47b2116b3a92e44d +Subproject commit 8e022e155cc5ccfafbda4ba2fd75acd399bcba01 From 0dd0bb0a5fb737e3f8effcbd9f034819184fc6b0 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 26 Mar 2023 10:37:37 -0700 Subject: [PATCH 011/184] Remove printfs from CanHaveChosenInDTS --- generators/chipyard/src/main/scala/Subsystem.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 3b4d312b..a2f81c0a 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -51,10 +51,8 @@ trait CanHaveHTIF { this: BaseSubsystem => case object ChosenInDTS extends Field[Boolean](true) trait CanHaveChosenInDTS { this: BaseSubsystem => if (p(ChosenInDTS)) { - println("got here") this match { case t: HasPeripheryUART if (!p(PeripheryUARTKey).isEmpty) => { - println("Add chosen resource") val chosen = new Device { def describe(resources: ResourceBindings): Description = { val stdout = resources("stdout").map(_.value) From 4020d2eff03eb3a7e8dfa2d01bd744a40856ce8b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 26 Mar 2023 15:07:25 -0700 Subject: [PATCH 012/184] Add flag to enable spike commit-log --- generators/chipyard/src/main/resources/csrc/spiketile.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index 9942364f..567d87b6 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -304,8 +304,6 @@ extern "C" void spike_tile(int hartid, char* isa, log_file->get(), sout); - p->enable_log_commits(); - s_vpi_vlog_info vinfo; if (!vpi_get_vlog_info(&vinfo)) abort(); @@ -324,6 +322,9 @@ extern "C" void spike_tile(int hartid, char* isa, if (arg == "+spike-fast-clint") { simif->fast_clint = true; } + if (arg == "+spike-verbose") { + p->enable_log_commits(); + } } if (loadmem_file != "" && tcm_size > 0) simif->loadmem(loadmem_file.c_str()); From d0ab1ee2be900c232cc78989d256cf1b454ef8f2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 26 Mar 2023 15:07:36 -0700 Subject: [PATCH 013/184] Update spiketile time csr --- generators/chipyard/src/main/resources/csrc/spiketile.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index 567d87b6..a496a98e 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -1067,6 +1067,7 @@ void spike_thread_main(void* arg) } } tile->proc->get_state()->mcycle->write(tile->simif->cycle); + tile->proc->get_state()->time->sync(tile->simif->cycle); } } } From 154cb08a34b2ce45b1eef2462f7b96dea86b4da7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 27 Mar 2023 14:03:20 -0700 Subject: [PATCH 014/184] Add SpikeUltraFastDevices config --- .../src/main/scala/config/SpikeConfigs.scala | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index 0d9972a9..cc6d0c90 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -30,3 +30,18 @@ class SpikeUltraFastConfig extends Config( new chipyard.config.WithBroadcastManager ++ new chipyard.config.AbstractConfig) +// Add the default firechip devices +class SpikeUltraFastDevicesConfig extends Config( + new chipyard.harness.WithSimBlockDevice ++ + new chipyard.harness.WithLoopbackNIC ++ + new icenet.WithIceNIC ++ + new testchipip.WithBlockDevice ++ + + new chipyard.WithSpikeTCM ++ + new chipyard.WithNSpikeCores(1) ++ + new testchipip.WithSerialPBusMem ++ + new chipyard.config.WithUARTFIFOEntries(128, 128) ++ + new chipyard.config.WithMemoryBusFrequency(2) ++ + new chipyard.config.WithPeripheryBusFrequency(2) ++ + new chipyard.config.WithBroadcastManager ++ + new chipyard.config.AbstractConfig) From b54eb9f6120223090c064d893149792a3ee75592 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 27 Mar 2023 14:35:21 -0700 Subject: [PATCH 015/184] Bump boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index deae9f70..051dbadb 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit deae9f70469336a3787fa7fcc10135ffb93d21d9 +Subproject commit 051dbadb6d0e9018c5b1f843ac73cff4242a02f8 From a750a864ff7bfccd586ea74180b42def7ef77d8a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 27 Mar 2023 14:38:07 -0700 Subject: [PATCH 016/184] Bump spike --- .../src/main/resources/csrc/spiketile.cc | 82 ++++++++++++------- toolchains/riscv-tools/riscv-isa-sim | 2 +- 2 files changed, 52 insertions(+), 32 deletions(-) diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index a496a98e..f59e825a 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -85,6 +85,9 @@ public: void drain_stq(); bool stq_empty() { return st_q.size() == 0; }; + const cfg_t &get_cfg() const { return cfg; } + const std::map& get_harts() const { return harts; } + ~chipyard_simif_t() { }; chipyard_simif_t(size_t icache_ways, size_t icache_sets, @@ -97,11 +100,15 @@ public: size_t icache_sourceids, size_t dcache_sourceids, size_t tcm_base, - size_t tcm_size); + size_t tcm_size, + const char* isastr, + size_t pmpregions); uint64_t cycle; bool use_stq; htif_t *htif; bool fast_clint; + cfg_t cfg; + std::map harts; private: bool handle_cache_access(reg_t addr, size_t len, uint8_t* load_bytes, @@ -278,31 +285,21 @@ extern "C" void spike_tile(int hartid, char* isa, if (tiles.find(hartid) == tiles.end()) { printf("Constructing spike processor_t\n"); isa_parser_t *isa_parser = new isa_parser_t(isa, "MSU"); + std::string* isastr = new std::string(isa); chipyard_simif_t* simif = new chipyard_simif_t(icache_ways, icache_sets, dcache_ways, dcache_sets, cacheable, uncacheable, readonly_uncacheable, executable, icache_sourceids, dcache_sourceids, - tcm_base, tcm_size); - std::string* isastr = new std::string(isa); - cfg_t* cfg = new cfg_t(std::make_pair(0, 0), - nullptr, - isastr->c_str(), - "MSU", - "vlen:128,elen:64", - false, - endianness_little, - pmpregions, - std::vector(), - std::vector(), - false, - 0); + tcm_base, tcm_size, + isastr->c_str(), pmpregions); processor_t* p = new processor_t(isa_parser, - cfg, + &simif->get_cfg(), simif, hartid, false, log_file->get(), sout); + simif->harts[hartid] = p; s_vpi_vlog_info vinfo; if (!vpi_get_vlog_info(&vinfo)) @@ -422,12 +419,26 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, size_t ic_sourceids, size_t dc_sourceids, size_t tcm_base, - size_t tcm_size + size_t tcm_size, + const char* isastr, + size_t pmpregions ) : cycle(0), use_stq(false), htif(nullptr), fast_clint(false), + cfg(std::make_pair(0, 0), + nullptr, + isastr, + "MSU", + "vlen:128,elen:64", + false, + endianness_little, + pmpregions, + std::vector(), + std::vector(), + false, + 0), icache_ways(icache_ways), icache_sets(icache_sets), dcache_ways(dcache_ways), @@ -1036,38 +1047,47 @@ bool insn_is_wfi(uint64_t bits) { void spike_thread_main(void* arg) { tile_t* tile = (tile_t*) arg; + processor_t* proc = tile->proc; + chipyard_simif_t* simif = tile->simif; + state_t* state = proc->get_state(); while (true) { while (tile->max_insns == 0) { host->switch_to(); } while (tile->max_insns != 0) { // TODO: Fences don't work - //uint64_t last_bits = tile->proc->get_last_bits(); - // if (insn_should_fence(last_bits) && !tile->simif->stq_empty()) { + //uint64_t last_bits = proc->get_last_bits(); + // if (insn_should_fence(last_bits) && !simif->stq_empty()) { // host->switch_to(); // } - uint64_t old_minstret = tile->proc->get_state()->minstret->read(); - tile->proc->step(1); + proc->step(1); tile->max_insns--; - if (tile->proc->is_waiting_for_interrupt()) { - if (tile->simif->fast_clint) { - tile->proc->get_state()->mip->backdoor_write_with_mask(MIP_MTIP, MIP_MTIP); + if (proc->is_waiting_for_interrupt()) { + if (simif->fast_clint) { + // uint64_t mip = state->mip->read(); + // uint64_t mie = state->mie->read(); + //printf("Setting MTIP %x %x %x %x %lx\n", simif->cycle, old_minstret, mip, mie, + // state->pc); + state->mip->backdoor_write_with_mask(MIP_MTIP, MIP_MTIP); + tile->max_insns = tile->max_insns <= 1 ? 0 : 1; + } else { + //printf("SpikeTile in WFI\n"); + tile->max_insns = 0; } - tile->max_insns = 0; } if (tile->max_insns % 100 == 0) { - uint64_t tohost_addr = tile->simif->htif ? tile->simif->htif->get_tohost_addr() : 0; - uint64_t fromhost_addr = tile->simif->htif ? tile->simif->htif->get_fromhost_addr() : 0; - auto& mem_read = tile->proc->get_state()->log_mem_read; + uint64_t old_minstret = state->minstret->read(); + uint64_t tohost_addr = simif->htif ? simif->htif->get_tohost_addr() : 0; + uint64_t fromhost_addr = simif->htif ? simif->htif->get_fromhost_addr() : 0; + auto& mem_read = state->log_mem_read; reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]); - if ((old_minstret == tile->proc->get_state()->minstret->read()) || + if ((old_minstret == state->minstret->read()) || (tohost_addr && mem_read_addr == tohost_addr) || (fromhost_addr && mem_read_addr == fromhost_addr)) { tile->max_insns == 0; } } - tile->proc->get_state()->mcycle->write(tile->simif->cycle); - tile->proc->get_state()->time->sync(tile->simif->cycle); + state->mcycle->write(simif->cycle); } } } diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index a6eb6c2a..fcfb795b 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit a6eb6c2a99ec7a23640d2aee5f3c05dc35c223d9 +Subproject commit fcfb795bea24c0489a0dbe9d446d05df35dc700d From 1c1f5c9bad30e1587c9b20d04939981a9b8ba464 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 27 Mar 2023 14:38:20 -0700 Subject: [PATCH 017/184] Bump rocket-chip-blocks --- generators/sifive-blocks | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 8e022e15..be4262b9 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 8e022e155cc5ccfafbda4ba2fd75acd399bcba01 +Subproject commit be4262b99650fc1a9f28ed3080bbb459bf9946eb From c7a2a5383c72f51c2dfaa4406593b332e2e893ad Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 27 Mar 2023 14:38:54 -0700 Subject: [PATCH 018/184] Bump firemarshal --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index 12784a42..48302281 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 12784a42cb1b2188536ef5bfc123f800374d3177 +Subproject commit 48302281ee88ecca0bce47641882cbd74f434f36 From df2e5ad9dc550d0ec23f8c23b334525bbb144cd7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 20 Mar 2023 23:26:53 -0700 Subject: [PATCH 019/184] Bump to latest rocket-chip/chisel3.5.6 --- .gitmodules | 6 ++--- build.sbt | 26 +++++-------------- fpga/fpga-shells | 2 +- fpga/src/main/scala/arty/Configs.scala | 2 +- fpga/src/main/scala/arty/HarnessBinders.scala | 4 +-- fpga/src/main/scala/arty/IOBinders.scala | 4 +-- fpga/src/main/scala/arty/TestHarness.scala | 2 +- fpga/src/main/scala/arty100t/Configs.scala | 2 +- fpga/src/main/scala/arty100t/Harness.scala | 2 +- .../main/scala/arty100t/HarnessBinders.scala | 1 - fpga/src/main/scala/vc707/Configs.scala | 2 +- fpga/src/main/scala/vc707/TestHarness.scala | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 2 +- .../main/scala/vcu118/CustomOverlays.scala | 2 +- fpga/src/main/scala/vcu118/TestHarness.scala | 2 +- .../main/scala/vcu118/bringup/Configs.scala | 2 +- .../scala/vcu118/bringup/CustomOverlays.scala | 2 +- .../scala/vcu118/bringup/DigitalTop.scala | 2 +- .../scala/vcu118/bringup/TestHarness.scala | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/ChipTop.scala | 2 +- .../chipyard/src/main/scala/Cospike.scala | 2 +- .../chipyard/src/main/scala/DigitalTop.scala | 2 +- .../src/main/scala/HarnessBinders.scala | 2 +- .../chipyard/src/main/scala/IOBinders.scala | 4 +-- .../chipyard/src/main/scala/SpikeTile.scala | 2 +- .../chipyard/src/main/scala/Subsystem.scala | 5 ++-- .../chipyard/src/main/scala/System.scala | 2 +- .../chipyard/src/main/scala/TestHarness.scala | 2 +- .../chipyard/src/main/scala/TestSuites.scala | 2 +- .../scala/clocking/ClockGroupCombiner.scala | 2 +- .../clocking/ClockGroupNamePrefixer.scala | 2 +- .../clocking/DividerOnlyClockGenerator.scala | 2 +- .../main/scala/clocking/HasChipyardPRCI.scala | 2 +- .../main/scala/clocking/TileClockGater.scala | 2 +- .../main/scala/clocking/TileResetSetter.scala | 2 +- .../main/scala/config/AbstractConfig.scala | 2 +- .../src/main/scala/config/BoomConfigs.scala | 2 +- .../src/main/scala/config/CVA6Configs.scala | 2 +- .../src/main/scala/config/HeteroConfigs.scala | 2 +- .../src/main/scala/config/IbexConfigs.scala | 2 +- .../scala/config/MMIOAcceleratorConfigs.scala | 2 +- .../src/main/scala/config/NoCConfigs.scala | 2 +- .../src/main/scala/config/NoCoreConfigs.scala | 2 +- .../config/PeripheralDeviceConfigs.scala | 2 +- .../scala/config/RoCCAcceleratorConfigs.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 2 +- .../main/scala/config/RocketSha3Configs.scala | 2 +- .../src/main/scala/config/SodorConfigs.scala | 2 +- .../src/main/scala/config/SpikeConfigs.scala | 2 +- .../main/scala/config/TracegenConfigs.scala | 2 +- .../main/scala/config/TutorialConfigs.scala | 2 +- .../config/fragments/ClockingFragments.scala | 2 +- .../fragments/PeripheralFragments.scala | 2 +- .../config/fragments/RoCCFragments.scala | 2 +- .../config/fragments/SubsystemFragments.scala | 2 +- .../config/fragments/TileFragments.scala | 2 +- .../config/fragments/TracegenFragments.scala | 2 +- .../chipyard/src/main/scala/example/GCD.scala | 2 +- .../src/main/scala/example/InitZero.scala | 2 +- .../src/main/scala/example/NodeTypes.scala | 2 +- .../scala/example/RegisterNodeExample.scala | 2 +- .../src/main/scala/example/TutorialTile.scala | 2 +- .../scala/example/dsptools/DspBlocks.scala | 2 +- .../scala/example/dsptools/GenericFIR.scala | 2 +- .../dsptools/StreamingPassthrough.scala | 2 +- .../scala/stage/phases/AddDefaultTests.scala | 2 +- .../src/main/scala/unittest/TestHarness.scala | 2 +- .../main/scala/unittest/UnitTestSuite.scala | 2 +- generators/constellation | 2 +- generators/cva6 | 2 +- generators/fft-generator | 2 +- .../src/main/scala/BridgeBinders.scala | 4 +-- .../firechip/src/main/scala/FireSim.scala | 2 +- .../src/main/scala/TargetConfigs.scala | 2 +- generators/gemmini | 2 +- generators/hwacha | 2 +- generators/ibex | 2 +- generators/icenet | 2 +- generators/mempress | 2 +- generators/nvdla | 2 +- generators/riscv-sodor | 2 +- generators/rocket-chip | 2 +- generators/sha3 | 2 +- generators/sifive-blocks | 2 +- generators/sifive-cache | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/Configs.scala | 2 +- .../tracegen/src/main/scala/System.scala | 5 ++-- sims/firesim | 2 +- tools/api-config-chipsalliance | 1 - tools/cde | 1 + tools/rocket-dsp-utils | 2 +- 93 files changed, 106 insertions(+), 119 deletions(-) delete mode 160000 tools/api-config-chipsalliance create mode 160000 tools/cde diff --git a/.gitmodules b/.gitmodules index b4beb696..f5055865 100644 --- a/.gitmodules +++ b/.gitmodules @@ -73,9 +73,6 @@ [submodule "fpga/fpga-shells"] path = fpga/fpga-shells url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git -[submodule "tools/api-config-chipsalliance"] - path = tools/api-config-chipsalliance - url = https://github.com/chipsalliance/api-config-chipsalliance.git [submodule "tools/rocket-dsp-utils"] path = tools/rocket-dsp-utils url = https://github.com/ucb-bar/rocket-dsp-utils @@ -121,3 +118,6 @@ [submodule "generators/mempress"] path = generators/mempress url = https://github.com/ucb-bar/mempress.git +[submodule "tools/cde"] + path = tools/cde + url = https://github.com/chipsalliance/cde.git diff --git a/build.sbt b/build.sbt index 0f065836..24862c45 100644 --- a/build.sbt +++ b/build.sbt @@ -62,7 +62,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.5.5" +val chiselVersion = "3.5.6" lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion, @@ -102,18 +102,8 @@ lazy val rocketMacros = (project in rocketChipDir / "macros") ) ) -lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt") - .settings(commonSettings) - .settings( - libraryDependencies ++= Seq( - "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "org.json4s" %% "json4s-jackson" % "3.6.6", - "org.scalatest" %% "scalatest" % "3.2.0" % "test" - ) - ) - lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .dependsOn(hardfloat, rocketMacros, rocketConfig) + .dependsOn(hardfloat, rocketMacros, cde) .settings(commonSettings) .settings(chiselSettings) .settings( @@ -246,16 +236,12 @@ lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) "org.scalacheck" %% "scalacheck" % "1.14.3" % "test", )) -lazy val `api-config-chipsalliance` = freshProject("api-config-chipsalliance", file("./tools/api-config-chipsalliance")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scalatest" %% "scalatest" % "3.0.+" % "test", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test", - )) +lazy val cde = (project in file("tools/cde")) + .settings(commonSettings) + .settings(Compile / scalaSource := baseDirectory.value / "cde/src/chipsalliance/rocketchip") lazy val `rocket-dsp-utils` = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils")) - .dependsOn(rocketchip, `api-config-chipsalliance`, dsptools) + .dependsOn(rocketchip, cde, dsptools) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) diff --git a/fpga/fpga-shells b/fpga/fpga-shells index b6cd1bb7..9f4c6ac5 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit b6cd1bb7fe35bb7a44b6fe5a0d88d1293d7a3bc9 +Subproject commit 9f4c6ac5719b03ded61022dc3767e750872d0535 diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index a88848d0..421ba355 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -1,7 +1,7 @@ // See LICENSE for license details. package chipyard.fpga.arty -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 4e90e858..e1743c0b 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -2,7 +2,7 @@ package chipyard.fpga.arty import chisel3._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug} import freechips.rocketchip.jtag.{JTAGIO} import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp} @@ -15,7 +15,7 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} import chipyard.iobinders.JTAGChipIO class WithArtyResetHarnessBinder extends ComposeHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => { + (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Bool]) => { require(ports.size == 2) withClockAndReset(th.clock_32MHz, th.ck_rst) { diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala index db656752..da6c7318 100644 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -3,12 +3,12 @@ package chipyard.fpga.arty import chisel3._ import chisel3.experimental.{IO} -import freechips.rocketchip.devices.debug.{HasPeripheryDebugModuleImp} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug} import chipyard.iobinders.{ComposeIOBinder} class WithDebugResetPassthrough extends ComposeIOBinder({ - (system: HasPeripheryDebugModuleImp) => { + (system: HasPeripheryDebug) => { // Debug module reset val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset") io_ndreset := system.debug.get.ndreset diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index a3d7fc33..5e280469 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -3,7 +3,7 @@ package chipyard.fpga.arty import chisel3._ import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Parameters} +import org.chipsalliance.cde.config.{Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index 0930dbdb..673b8b58 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -1,7 +1,7 @@ // See LICENSE for license details. package chipyard.fpga.arty100t -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index 5cc1e348..88ea88af 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -3,7 +3,7 @@ package chipyard.fpga.arty100t import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters} +import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset} import sifive.fpgashells.shell.xilinx._ diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 3d86f354..d9a2df45 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -2,7 +2,6 @@ package chipyard.fpga.arty100t import chisel3._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem.{PeripheryBusKey} import freechips.rocketchip.tilelink.{TLBundle} diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index 07a96cfd..fa08a184 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -2,7 +2,7 @@ package chipyard.fpga.vc707 import sys.process._ -import freechips.rocketchip.config.{Config, Parameters} +import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 924c768e..94c0ba8e 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.experimental.{IO} import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource} -import freechips.rocketchip.config.{Parameters} +import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode} import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay} diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 85b6ee24..c4f4684e 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -2,7 +2,7 @@ package chipyard.fpga.vcu118 import sys.process._ -import freechips.rocketchip.config.{Config, Parameters} +import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala index 250e2040..02669b79 100644 --- a/fpga/src/main/scala/vcu118/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -3,7 +3,7 @@ package chipyard.fpga.vcu118 import chisel3._ import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters, Field} +import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} import sifive.fpgashells.shell._ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 9a3cc0d5..e46745a8 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.experimental.{IO} import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource} -import freechips.rocketchip.config.{Parameters} +import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode} import sifive.fpgashells.shell.xilinx._ diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 62c2af31..bff715dc 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -2,7 +2,7 @@ package chipyard.fpga.vcu118.bringup import math.min -import freechips.rocketchip.config.{Config, Parameters} +import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} import freechips.rocketchip.tilelink._ import freechips.rocketchip.diplomacy._ diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 43d559f0..4b9604f9 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters, Field} +import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} import sifive.fpgashells.shell._ diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index 5b554f5b..c5401d32 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -4,7 +4,7 @@ import chisel3._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 2406cb7b..c311d84f 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -3,7 +3,7 @@ package chipyard.fpga.vcu118.bringup import chisel3._ import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ diff --git a/generators/boom b/generators/boom index deae9f70..0101e204 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit deae9f70469336a3787fa7fcc10135ffb93d21d9 +Subproject commit 0101e2041d4a7c11d6b4aff685200aa387fcbc51 diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 184f30f2..150221b6 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -6,7 +6,7 @@ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} -import freechips.rocketchip.config.{Parameters, Field} +import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope} import freechips.rocketchip.util.{ResetCatchAndSync} import chipyard.iobinders._ diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala index 7b663b24..fffb97d6 100644 --- a/generators/chipyard/src/main/scala/Cospike.scala +++ b/generators/chipyard/src/main/scala/Cospike.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.experimental.{IntParam, StringParam, IO} import chisel3.util._ -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.devices.tilelink._ diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 2777ba36..d20bade9 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -4,7 +4,7 @@ import chisel3._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.tilelink._ // ------------------------------------ diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 21dfe588..1992bc1e 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction} -import freechips.rocketchip.config.{Field, Config, Parameters} +import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} import freechips.rocketchip.devices.debug._ diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 71eef713..3eaac605 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -3,7 +3,7 @@ package chipyard.iobinders import chisel3._ import chisel3.experimental.{Analog, IO, DataMirror} -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} @@ -219,7 +219,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({ def clockBundle = clockSinkNode.get.in.head._1 - InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebugModuleImp => { + InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebug => { system.debug.map({ debug => // We never use the PSDIO, so tie it off on-chip system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index c7e5b69d..b7611448 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{IntParam, StringParam, IO} -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 34175d39..949a4aa4 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -9,9 +9,9 @@ import chisel3._ import chisel3.internal.sourceinfo.{SourceInfo} import freechips.rocketchip.prci._ -import freechips.rocketchip.config.{Field, Parameters} +import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, ExportDebug, DebugModuleKey} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ @@ -47,6 +47,7 @@ trait CanHaveHTIF { this: BaseSubsystem => class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem with HasTiles + with HasPeripheryDebug with CanHaveHTIF { def coreMonitorBundles = tiles.map { diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 827b97c0..a6c4b6b3 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -7,7 +7,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Parameters, Field} +import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 240ae5cc..23bda680 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -4,7 +4,7 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Field, Parameters} +import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util.{ResetCatchAndSync} import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters} diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index a47ae425..0e4e3310 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -4,7 +4,7 @@ import scala.collection.mutable.{LinkedHashSet} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen, TileParams} -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} /** diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala index 07ae536b..c8bad8c4 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{Analog, IO} -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala index 965beed3..39cb379b 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala @@ -2,7 +2,7 @@ package chipyard.clocking import chisel3._ -import freechips.rocketchip.config.{Parameters, Config, Field} +import org.chipsalliance.cde.config.{Parameters, Config, Field} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala index d72b2a70..121cca24 100644 --- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala +++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala @@ -2,7 +2,7 @@ package chipyard.clocking import chisel3._ -import freechips.rocketchip.config.{Parameters} +import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util.ElaborationArtefacts diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 0cfc702a..d2c4f2e5 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -4,7 +4,7 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer} -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala index 5ca8d271..9b7696fb 100644 --- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala +++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{Analog, IO} -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala index b67371d5..d8243e37 100644 --- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala +++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{Analog, IO} -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index b084845e..d7e5a8f2 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -1,6 +1,6 @@ package chipyard.config -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // -------------- // Chipyard abstract ("base") configuration diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 0de224c9..4c101403 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // --------------------- // BOOM Configs diff --git a/generators/chipyard/src/main/scala/config/CVA6Configs.scala b/generators/chipyard/src/main/scala/config/CVA6Configs.scala index 132a3009..c0d6adb1 100644 --- a/generators/chipyard/src/main/scala/config/CVA6Configs.scala +++ b/generators/chipyard/src/main/scala/config/CVA6Configs.scala @@ -2,7 +2,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // --------------------- // CVA6 Configs diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index 8e8c7fe9..206b086b 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // --------------------- // Heterogenous Configs diff --git a/generators/chipyard/src/main/scala/config/IbexConfigs.scala b/generators/chipyard/src/main/scala/config/IbexConfigs.scala index 63b7aa5d..6d1b6e4e 100644 --- a/generators/chipyard/src/main/scala/config/IbexConfigs.scala +++ b/generators/chipyard/src/main/scala/config/IbexConfigs.scala @@ -2,7 +2,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // --------------------- // Ibex Configs diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala index fcb4804d..8c5aa2e9 100644 --- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // ------------------------------ diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index bd36fe04..0036e988 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.subsystem.{SBUS, MBUS} diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala index 9d0c4132..10be8aca 100644 --- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // A empty config with no cores. Useful for testing class NoCoresConfig extends Config( diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index d01bcd8d..3bb2390d 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // --------------------------------------------------------- diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 7487a50e..4077fcbd 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // ------------------------------ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index b6677cb1..f8b20600 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // -------------- diff --git a/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala b/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala index 3eb568ba..43ad1de3 100644 --- a/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala +++ b/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // -------------- diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 3679ed07..24eb1f4d 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -2,7 +2,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} class Sodor1StageConfig extends Config( // Create a Sodor 1-stage core diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index b45245c0..eb5a9e9d 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // Configs which instantiate a Spike-simulated // tile that interacts with the Chipyard SoC diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 4ab51994..605db4d3 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.rocket.{DCacheParams} class AbstractTraceGenConfig extends Config( diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index c9956b7a..e10b3368 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import constellation.channel._ import constellation.routing._ import constellation.topology._ diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 0c79f6dc..7000c81c 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -4,7 +4,7 @@ import scala.util.matching.Regex import chisel3._ import chisel3.util.{log2Up} -import freechips.rocketchip.config.{Field, Parameters, Config} +import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.subsystem._ import freechips.rocketchip.prci._ import freechips.rocketchip.diplomacy._ diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index ec9ff47c..7ac7f569 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -4,7 +4,7 @@ import scala.util.matching.Regex import chisel3._ import chisel3.util.{log2Up} -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey} import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} import freechips.rocketchip.stage.phases.TargetDirKey diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala index 774b23c2..4680eeeb 100644 --- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala @@ -2,7 +2,7 @@ package chipyard.config import chisel3._ -import freechips.rocketchip.config.{Field, Parameters, Config} +import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.tile._ import freechips.rocketchip.diplomacy._ diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index c41e2716..40f18d5d 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -1,6 +1,6 @@ package chipyard.config -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper} import freechips.rocketchip.diplomacy.{DTSTimebase} diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index f19759cb..56042c3d 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -2,7 +2,7 @@ package chipyard.config import chisel3._ -import freechips.rocketchip.config.{Field, Parameters, Config} +import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.tile._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} diff --git a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala index 2e849c58..c8b4f828 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala @@ -1,6 +1,6 @@ package chipyard.config -import freechips.rocketchip.config.{Config, Field, Parameters} +import org.chipsalliance.cde.config.{Config, Field, Parameters} import tracegen.{TraceGenSystem} import chipyard.{BuildSystem} import chipyard.clocking.{HasChipyardPRCI} diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index fe55f288..bf05ba9c 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -5,7 +5,7 @@ import chisel3.util._ import chisel3.experimental.{IntParam, BaseModule} import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper.{HasRegMap, RegField} import freechips.rocketchip.tilelink._ diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala index 5051c37d..bb6ecd72 100644 --- a/generators/chipyard/src/main/scala/example/InitZero.scala +++ b/generators/chipyard/src/main/scala/example/InitZero.scala @@ -3,7 +3,7 @@ package chipyard.example import chisel3._ import chisel3.util._ import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes} -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange} import freechips.rocketchip.tilelink._ diff --git a/generators/chipyard/src/main/scala/example/NodeTypes.scala b/generators/chipyard/src/main/scala/example/NodeTypes.scala index cafc470f..1cdddd32 100644 --- a/generators/chipyard/src/main/scala/example/NodeTypes.scala +++ b/generators/chipyard/src/main/scala/example/NodeTypes.scala @@ -1,6 +1,6 @@ package chipyard.example -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ diff --git a/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala b/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala index cda91ffe..e7a8b0b8 100644 --- a/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala +++ b/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala @@ -2,7 +2,7 @@ import chisel3._ import chisel3.util._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink.TLRegisterNode diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 3d8e1ae1..1a9114b9 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -3,7 +3,7 @@ package chipyard.example import chisel3._ import chisel3.util._ -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ diff --git a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala index b51e2223..9ad23a4c 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala @@ -5,7 +5,7 @@ import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index f45b318c..15dfb992 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -8,7 +8,7 @@ import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index c6ffaf42..2846277c 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -8,7 +8,7 @@ import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 03aa0b56..2258228e 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -6,7 +6,7 @@ package chipyard.stage.phases import scala.util.Try import scala.collection.mutable -import chipsalliance.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import chisel3.stage.phases.Elaborate import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} diff --git a/generators/chipyard/src/main/scala/unittest/TestHarness.scala b/generators/chipyard/src/main/scala/unittest/TestHarness.scala index 8bb4bbd9..a5ca5551 100644 --- a/generators/chipyard/src/main/scala/unittest/TestHarness.scala +++ b/generators/chipyard/src/main/scala/unittest/TestHarness.scala @@ -1,7 +1,7 @@ package chipyard.unittest import chisel3._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters class TestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) diff --git a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala index 40e991a2..d3281dc1 100644 --- a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala +++ b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala @@ -1,6 +1,6 @@ package chipyard.unittest -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts} class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite { diff --git a/generators/constellation b/generators/constellation index 4606ee19..e9f1c828 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit 4606ee19b74d32d165b1708ef6f4ee98baa1c50d +Subproject commit e9f1c828ca5adb4fa46a242cd1798391fc9e6f62 diff --git a/generators/cva6 b/generators/cva6 index 737fd83b..0011494b 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 737fd83b820aea6d615f372a97766b1d390a18d5 +Subproject commit 0011494bb70d2327ab4d6b0258f5073f137927ee diff --git a/generators/fft-generator b/generators/fft-generator index a31bd038..be8ab768 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit a31bd038ddf3c941634cb830608edb0bdd6442db +Subproject commit be8ab768bd15824c69531df632478e4429078b94 diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 4d64a8ad..4d768da9 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -6,9 +6,9 @@ import chisel3._ import chisel3.experimental.annotate import chisel3.util.experimental.BoringUtils -import freechips.rocketchip.config.{Field, Config, Parameters} +import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug} import freechips.rocketchip.amba.axi4.{AXI4Bundle} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{RocketTile} diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index bd35341b..a62059e3 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -9,7 +9,7 @@ import chisel3.experimental.{IO} import freechips.rocketchip.prci._ import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} -import freechips.rocketchip.config.{Field, Config, Parameters} +import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName} import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap} diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 2ea848df..7af98c57 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -4,7 +4,7 @@ import java.io.File import chisel3._ import chisel3.util.{log2Up} -import freechips.rocketchip.config.{Parameters, Config} +import org.chipsalliance.cde.config.{Parameters, Config} import freechips.rocketchip.groundtest.TraceGenParams import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ diff --git a/generators/gemmini b/generators/gemmini index 686cb15d..11e15ab1 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 686cb15dad756887db62460968bc616392bc4341 +Subproject commit 11e15ab1c5d6dbc3afc4787350b93603062a2e43 diff --git a/generators/hwacha b/generators/hwacha index e1be8e2a..d01ca1e7 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit e1be8e2a41c6bc2239aed4e23355cf34a224f380 +Subproject commit d01ca1e7f8a3ba3f419509273dfef00e41095f6a diff --git a/generators/ibex b/generators/ibex index 626127f2..916fb7a6 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 626127f229dd6dc926b7670eb4dd138f32a7940a +Subproject commit 916fb7a6ff4a65f989279bcc082676a565beee0c diff --git a/generators/icenet b/generators/icenet index 90d52a6a..ce1ec55c 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 90d52a6a8435c862e6435d04436f587c3b36c8c0 +Subproject commit ce1ec55c1fd9c4339e7c0eec3a82d86041fa5d20 diff --git a/generators/mempress b/generators/mempress index b9eaedc0..295ae085 160000 --- a/generators/mempress +++ b/generators/mempress @@ -1 +1 @@ -Subproject commit b9eaedc061adbbe488f4c094f0ddd2177852e11a +Subproject commit 295ae0854a429182e4a38b120c8771a4e898834e diff --git a/generators/nvdla b/generators/nvdla index 2b17011b..7130a5c0 160000 --- a/generators/nvdla +++ b/generators/nvdla @@ -1 +1 @@ -Subproject commit 2b17011b266025704b958efeeca2363c0cdd446d +Subproject commit 7130a5c0f7016cd177ec9cf908a18edd668660d1 diff --git a/generators/riscv-sodor b/generators/riscv-sodor index d6ccc5de..c051956d 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit d6ccc5de5cf6f07be500a0d1351656bb0c50e4a3 +Subproject commit c051956d3be3269c4ed9fcbb6afe920a6f54fd32 diff --git a/generators/rocket-chip b/generators/rocket-chip index f5ebf26b..4fbd2f23 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit f5ebf26b369922b2924d71e185c473c0385bf54e +Subproject commit 4fbd2f238db36b2862319e94c2f96d63bd52c98b diff --git a/generators/sha3 b/generators/sha3 index 8c5d2443..1fa5ef8a 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 8c5d244303694311c4e63e51915a492491a3f5c7 +Subproject commit 1fa5ef8ae5b67126d709193896e75dba50c5fd28 diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 4273925f..19d42938 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 4273925fdd5d8872d6b6a8dec6cee3330b9a68c7 +Subproject commit 19d42938f27ff480d778e379d0724d8373081377 diff --git a/generators/sifive-cache b/generators/sifive-cache index 850e1215..65f8bc26 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 850e12154c1de6baee9e40094d115e9b85d799b1 +Subproject commit 65f8bc26b2eca4e0167070d6954e7aea2efb26e7 diff --git a/generators/testchipip b/generators/testchipip index dead693f..ee47d2ea 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit dead693f8f317bfeeb4eb777c4d58c4427fbba31 +Subproject commit ee47d2ea205c7525b21333d3caf835fcd963fa42 diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala index ac2477a1..5d4f0211 100644 --- a/generators/tracegen/src/main/scala/Configs.scala +++ b/generators/tracegen/src/main/scala/Configs.scala @@ -2,7 +2,7 @@ package tracegen import chisel3._ import chisel3.util.log2Ceil -import freechips.rocketchip.config.{Config, Parameters} +import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.groundtest.{TraceGenParams, TraceGenTileAttachParams} import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.BaseConfig diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index fceb0072..53d88c6d 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -1,9 +1,9 @@ package tracegen import chisel3._ -import freechips.rocketchip.config.{Field, Parameters} +import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} -import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} +import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource} import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile} import freechips.rocketchip.subsystem._ import boom.lsu.BoomTraceGenTile @@ -17,6 +17,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem case t: GroundTestTile => t.statusNode.makeSink() case t: BoomTraceGenTile => t.statusNode.makeSink() } + val debugNode = NullIntSyncSource() override lazy val module = new TraceGenSystemModuleImp(this) } diff --git a/sims/firesim b/sims/firesim index 68e51138..8c85960b 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 68e5113887d36e87bb6202e7fd1e7e51e786a91b +Subproject commit 8c85960b939a0090de30a31936981972874d979d diff --git a/tools/api-config-chipsalliance b/tools/api-config-chipsalliance deleted file mode 160000 index fd8df110..00000000 --- a/tools/api-config-chipsalliance +++ /dev/null @@ -1 +0,0 @@ -Subproject commit fd8df1105a92065425cd353b6855777e35bd79b4 diff --git a/tools/cde b/tools/cde new file mode 160000 index 00000000..384c06b8 --- /dev/null +++ b/tools/cde @@ -0,0 +1 @@ +Subproject commit 384c06b8d45c8184ca2f3fba2f8e78f79d2c1b51 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index 46d6ed77..dcd9eb21 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit 46d6ed77981ef18789636426cc23f0bd7edc64d9 +Subproject commit dcd9eb212aefd8040cdf9c50adffbbf975422a1d From 21ff05d684264098d4593eb53f2c8e3e883e4d75 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 29 Mar 2023 11:24:26 -0700 Subject: [PATCH 020/184] Bump FireMarshal --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index 48302281..9ae3e90f 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 48302281ee88ecca0bce47641882cbd74f434f36 +Subproject commit 9ae3e90f11a429483c20b043eb59340404f3552e From 0486a62eebb3c136d3b9b68e0e6e24d90373bd43 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 29 Mar 2023 12:50:07 -0700 Subject: [PATCH 021/184] Update DebugIO IOBinder --- generators/chipyard/src/main/scala/IOBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 3eaac605..af829869 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -219,7 +219,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({ def clockBundle = clockSinkNode.get.in.head._1 - InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebug => { + InModuleBody { system.asInstanceOf[BaseSubsystem] match { case system: HasPeripheryDebug => { system.debug.map({ debug => // We never use the PSDIO, so tie it off on-chip system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } From 22d581af6f4502606d73fbff3a6e7d668e27f338 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 29 Mar 2023 12:51:30 -0700 Subject: [PATCH 022/184] Bump gemmini/cache --- generators/gemmini | 2 +- generators/sifive-cache | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/gemmini b/generators/gemmini index 11e15ab1..77e407ae 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 11e15ab1c5d6dbc3afc4787350b93603062a2e43 +Subproject commit 77e407ae59f9d9e5f93f7fd4c514e55bc7b73280 diff --git a/generators/sifive-cache b/generators/sifive-cache index 65f8bc26..bfe2d926 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 65f8bc26b2eca4e0167070d6954e7aea2efb26e7 +Subproject commit bfe2d9260b6d87de324ce94037c431b9a08fbbbc From ba5360cd08257c70e28d5d48297392feee72c600 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 29 Mar 2023 13:15:22 -0700 Subject: [PATCH 023/184] Bump spike --- toolchains/riscv-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index fcfb795b..929ff56a 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit fcfb795bea24c0489a0dbe9d446d05df35dc700d +Subproject commit 929ff56a09462978628c59c22fe6cb6895aa136f From 684bc0b02567f12a8a257acfa458c73cb3456b08 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 29 Mar 2023 20:35:17 -0700 Subject: [PATCH 024/184] Bump sifive-blocks --- generators/sifive-blocks | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-blocks b/generators/sifive-blocks index be4262b9..3938f301 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit be4262b99650fc1a9f28ed3080bbb459bf9946eb +Subproject commit 3938f301ce453c86e908211788017fd3a7e2765e From fe14cf54b5f4d341ddca3def3a36f7c0a423427a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 30 Mar 2023 17:33:57 -0700 Subject: [PATCH 025/184] Bump LLC --- generators/sifive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-cache b/generators/sifive-cache index bfe2d926..02e002b3 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit bfe2d9260b6d87de324ce94037c431b9a08fbbbc +Subproject commit 02e002b324c0e6316234045fa739fdb9d716170d From 8cb97bff858541eb8434eeff8f17b2f99b9248f3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 30 Mar 2023 23:41:27 -0700 Subject: [PATCH 026/184] Re-add check commit | Add CI | Bump Gemmini | Bump FireMarshal --- .github/scripts/check-commit.sh | 2 +- .github/workflows/chipyard-run-tests.yml | 50 ++++++++++++++++++++++++ generators/gemmini | 2 +- software/firemarshal | 2 +- 4 files changed, 53 insertions(+), 3 deletions(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index b0f16636..fe1de2bf 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,7 +45,7 @@ search () { done } -submodules=("cva6" "boom" "ibex" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress") +submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress") dir="generators" branches=("master" "main" "dev") search diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index c3e77e8b..86ce5675 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -390,6 +390,33 @@ jobs: ########################################################################## + chipyard-spike-gemmini-run-tests: + name: chipyard-spike-gemmini-run-tests + needs: prepare-chipyard-accels # technically doesn't depend on RTL + runs-on: self-hosted + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Build Gemmini FireMarshal + run: | + conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-${{ inputs.toolchain }} + cd software/firemarshal && ./init-submodules.sh + cd generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json + - name: Running Gemmini FireMarshal smoke test + run: | + conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-${{ inputs.toolchain }} + cd generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d launch -s gemmini-smoke.json + chipyard-rocket-run-tests: name: chipyard-rocket-run-tests needs: prepare-chipyard-cores @@ -666,6 +693,29 @@ jobs: group-key: "group-accels" project-key: "chipyard-gemmini" + chipyard-gemmini-spike-run-tests: + name: chipyard-gemmini-spike-run-tests + needs: prepare-chipyard-accels + runs-on: self-hosted + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-accels" + project-key: "chipyard-gemmini-spike" + chipyard-manymmioaccels-run-tests: name: chipyard-manymmioaccels-run-tests needs: prepare-chipyard-accels diff --git a/generators/gemmini b/generators/gemmini index 686cb15d..4dd19f3e 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 686cb15dad756887db62460968bc616392bc4341 +Subproject commit 4dd19f3e93d2decc24048eb1776e53fb20855841 diff --git a/software/firemarshal b/software/firemarshal index 9ae3e90f..fb93e311 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 9ae3e90f11a429483c20b043eb59340404f3552e +Subproject commit fb93e3116fed07191e669291b941e9eabb565ee3 From 162ceca9ab1ea94bbc345335d77e8bba0ae9e64f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 30 Mar 2023 23:55:08 -0700 Subject: [PATCH 027/184] Update spike-as-a-tile docs --- docs/Software/Spike.rst | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/docs/Software/Spike.rst b/docs/Software/Spike.rst index bdaa4750..9e978210 100644 --- a/docs/Software/Spike.rst +++ b/docs/Software/Spike.rst @@ -32,4 +32,21 @@ In this configuration, Spike is cache-coherent, and communicates with the uncore make CONFIG=SpikeConfig run-binary BINARY=hello.riscv +Spike-as-a-Tile also supports Tightly-Coupled-Memory (TCM) for the SpikeTile, in which the main system memory is entirely modeled +within the Spike tile, allowing for very fast simulatoin performance. +.. code-block:: shell + + make CONFIG=SpikeUltraFastConfig run-binary BINARY=hello.riscv + +Spike-as-a-Tile can be configure with custom IPC, commit logging, and other behaviors. Spike-specific flags can be added as plusargs to ``EXTRA_SIM_FLAGS`` + +.. code-block:: shell + + make CONFIG=SpikeUltraFastConfig run-binary-hex BINARY=hello.riscv EXTRA_SPIKE_FLAGS="+spike-ipc=10000 +spike-fast-clint +spike-debug" + + +* ``+spike-ipc=``: Sets the maximum number of instructions Spike can retire in a single "tick", or cycle of the uncore simulation. +* ``+spike-fast-clint``: Enables fast-forwrding through WFI stalls by generating fake timer interrupts +* ``+spike-debug``: Enables debug spike logging +* ``+spike-verbose``: Enabbls spike commit-log generation From c83838c6b7bb8c8bcf7d3026a2e0f250ff1c307b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 31 Mar 2023 08:29:59 -0700 Subject: [PATCH 028/184] Bump CI --- .github/workflows/chipyard-run-tests.yml | 29 +++--------------------- 1 file changed, 3 insertions(+), 26 deletions(-) diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 86ce5675..4bb28597 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -392,7 +392,7 @@ jobs: chipyard-spike-gemmini-run-tests: name: chipyard-spike-gemmini-run-tests - needs: prepare-chipyard-accels # technically doesn't depend on RTL + needs: prepare-chipyard-accels # technically doesn't depend on RTL but should be after the build.sh for Gemmini runs-on: self-hosted steps: - name: Delete old checkout @@ -409,12 +409,12 @@ jobs: uses: ./.github/actions/create-conda-env - name: Build Gemmini FireMarshal run: | - conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-${{ inputs.toolchain }} + conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools cd software/firemarshal && ./init-submodules.sh cd generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json - name: Running Gemmini FireMarshal smoke test run: | - conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-${{ inputs.toolchain }} + conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools cd generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d launch -s gemmini-smoke.json chipyard-rocket-run-tests: @@ -693,29 +693,6 @@ jobs: group-key: "group-accels" project-key: "chipyard-gemmini" - chipyard-gemmini-spike-run-tests: - name: chipyard-gemmini-spike-run-tests - needs: prepare-chipyard-accels - runs-on: self-hosted - steps: - - name: Delete old checkout - run: | - ls -alh . - rm -rf ${{ github.workspace }}/* || true - rm -rf ${{ github.workspace }}/.* || true - ls -alh . - - name: Checkout - uses: actions/checkout@v3 - - name: Git workaround - uses: ./.github/actions/git-workaround - - name: Create conda env - uses: ./.github/actions/create-conda-env - - name: Run tests - uses: ./.github/actions/run-tests - with: - group-key: "group-accels" - project-key: "chipyard-gemmini-spike" - chipyard-manymmioaccels-run-tests: name: chipyard-manymmioaccels-run-tests needs: prepare-chipyard-accels From 381a804bf2b133d5e5a4a02147b62656515e7996 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 31 Mar 2023 10:14:10 -0700 Subject: [PATCH 029/184] Cleanup docs | Bump CI --- .github/workflows/chipyard-run-tests.yml | 2 +- docs/Software/Spike.rst | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 4bb28597..30c5c524 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -410,7 +410,7 @@ jobs: - name: Build Gemmini FireMarshal run: | conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools - cd software/firemarshal && ./init-submodules.sh + git submodule update --init software/firemarshal && cd software/firemarshal && ./init-submodules.sh cd generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json - name: Running Gemmini FireMarshal smoke test run: | diff --git a/docs/Software/Spike.rst b/docs/Software/Spike.rst index 9e978210..79e41d6e 100644 --- a/docs/Software/Spike.rst +++ b/docs/Software/Spike.rst @@ -39,14 +39,14 @@ within the Spike tile, allowing for very fast simulatoin performance. make CONFIG=SpikeUltraFastConfig run-binary BINARY=hello.riscv -Spike-as-a-Tile can be configure with custom IPC, commit logging, and other behaviors. Spike-specific flags can be added as plusargs to ``EXTRA_SIM_FLAGS`` +Spike-as-a-Tile can be configured with custom IPC, commit logging, and other behaviors. Spike-specific flags can be added as plusargs to ``EXTRA_SIM_FLAGS`` .. code-block:: shell - make CONFIG=SpikeUltraFastConfig run-binary-hex BINARY=hello.riscv EXTRA_SPIKE_FLAGS="+spike-ipc=10000 +spike-fast-clint +spike-debug" + make CONFIG=SpikeUltraFastConfig run-binary-hex BINARY=hello.riscv EXTRA_SPIKE_FLAGS="+spike-ipc=10000 +spike-fast-clint +spike-debug" * ``+spike-ipc=``: Sets the maximum number of instructions Spike can retire in a single "tick", or cycle of the uncore simulation. -* ``+spike-fast-clint``: Enables fast-forwrding through WFI stalls by generating fake timer interrupts -* ``+spike-debug``: Enables debug spike logging -* ``+spike-verbose``: Enabbls spike commit-log generation +* ``+spike-fast-clint``: Enables fast-forwarding through WFI stalls by generating fake timer interrupts +* ``+spike-debug``: Enables debug Spike logging +* ``+spike-verbose``: Enables Spike commit-log generation From 7ec79f4ed80c2a291b82669b5fe0a713015915b1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 31 Mar 2023 18:05:04 -0700 Subject: [PATCH 030/184] Bump gemmini --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 77e407ae..c99bb4db 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 77e407ae59f9d9e5f93f7fd4c514e55bc7b73280 +Subproject commit c99bb4db63630865acf1ef243c9c20af14004f12 From 60bd1209cfbc1327b79f98b889a1b8064150aa74 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 31 Mar 2023 18:05:27 -0700 Subject: [PATCH 031/184] Bump rocket-chip --- generators/rocket-chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index 4fbd2f23..c49644ec 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 4fbd2f238db36b2862319e94c2f96d63bd52c98b +Subproject commit c49644ecdd2ebbeed8604011670bcc996322f65e From 7bfeef6459d084e5f666aef3583a0e99084e0d49 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 31 Mar 2023 18:07:36 -0700 Subject: [PATCH 032/184] Bump rocketchip | fix tracegen intnode --- generators/rocket-chip | 2 +- generators/tracegen/src/main/scala/System.scala | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index c49644ec..02dba8e3 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit c49644ecdd2ebbeed8604011670bcc996322f65e +Subproject commit 02dba8e3401e435f16cedbc07c0f27ab9604bc4f diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index 53d88c6d..2a0ba3d5 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -3,7 +3,7 @@ package tracegen import chisel3._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} -import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource} +import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource, IntSyncXbar} import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile} import freechips.rocketchip.subsystem._ import boom.lsu.BoomTraceGenTile @@ -17,7 +17,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem case t: GroundTestTile => t.statusNode.makeSink() case t: BoomTraceGenTile => t.statusNode.makeSink() } - val debugNode = NullIntSyncSource() + lazy val debugNode = IntSyncXbar() := NullIntSyncSource() override lazy val module = new TraceGenSystemModuleImp(this) } From 44c22aa69a2ab16d6a84a70fe319c1ea49b3a5ca Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 31 Mar 2023 22:42:24 -0700 Subject: [PATCH 033/184] Bump CI --- .github/workflows/chipyard-run-tests.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 30c5c524..0c7fc4d9 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -411,11 +411,11 @@ jobs: run: | conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools git submodule update --init software/firemarshal && cd software/firemarshal && ./init-submodules.sh - cd generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json + cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json - name: Running Gemmini FireMarshal smoke test run: | conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools - cd generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d launch -s gemmini-smoke.json + cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d launch -s gemmini-smoke.json chipyard-rocket-run-tests: name: chipyard-rocket-run-tests From 6abf970ccb03c32645a216a8d7bbc8fd72f0472b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 1 Apr 2023 10:23:22 -0700 Subject: [PATCH 034/184] Fix ArtyJTAG matching --- fpga/src/main/scala/arty/HarnessBinders.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index e1743c0b..720fafca 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -63,6 +63,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ io_jtag.TMS.i.po.map(_ := DontCare) io_jtag.TDO.i.po.map(_ := DontCare) } + case b: Bool => } } }) From 3e4c141b4e31a51d251a11c2bc3c113a016461a2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 1 Apr 2023 13:53:11 -0700 Subject: [PATCH 035/184] Update api-config-chipsalliance to cde in repo-clean.sh --- scripts/repo-clean.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/repo-clean.sh b/scripts/repo-clean.sh index 9c6d0389..0ecdbb27 100755 --- a/scripts/repo-clean.sh +++ b/scripts/repo-clean.sh @@ -21,7 +21,7 @@ rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log popd ) ( - pushd $RDIR/tools/api-config-chipsalliance + pushd $RDIR/tools/cde git config --local status.showUntrackedFiles no popd ) From e93bc3bed7f6521eea49e3906001e25f53eca168 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 1 Apr 2023 13:53:56 -0700 Subject: [PATCH 036/184] Fix Arty FPGA reset harness binder --- fpga/src/main/scala/arty/Configs.scala | 2 +- fpga/src/main/scala/arty/HarnessBinders.scala | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 421ba355..10af0223 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -17,9 +17,9 @@ import chipyard.{BuildSystem} // DOC include start: AbstractArty and Rocket class WithArtyTweaks extends Config( + new WithArtyResetHarnessBinder ++ new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ - new WithArtyResetHarnessBinder ++ new WithDebugResetPassthrough ++ new chipyard.config.WithDTSTimebase(32768) ++ diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 720fafca..84d47967 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -15,15 +15,15 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} import chipyard.iobinders.JTAGChipIO class WithArtyResetHarnessBinder extends ComposeHarnessBinder({ - (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Bool]) => { - require(ports.size == 2) - + (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => { + val resetPorts = ports.collect { case b: Bool => b } + require(resetPorts.size == 2) withClockAndReset(th.clock_32MHz, th.ck_rst) { // Debug module reset - th.dut_ndreset := ports(0) + th.dut_ndreset := resetPorts(0) // JTAG reset - ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz) + resetPorts(1) := PowerOnResetFPGAOnly(th.clock_32MHz) } } }) From a4665688098e9252a67c278c7c5e10bbfd2f75b6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 1 Apr 2023 13:55:21 -0700 Subject: [PATCH 037/184] Bump rocket-chip --- generators/rocket-chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index 02dba8e3..25e2c635 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 02dba8e3401e435f16cedbc07c0f27ab9604bc4f +Subproject commit 25e2c63567689ebe1fc5e60fdfe3375a8dba071c From 443d16e25815bb3ec379a4c62b36f521f32e54e3 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sun, 2 Apr 2023 19:00:41 -0700 Subject: [PATCH 038/184] Update chipyard-run-tests.yml --- .github/workflows/chipyard-run-tests.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 0c7fc4d9..6d4c02be 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -410,6 +410,7 @@ jobs: - name: Build Gemmini FireMarshal run: | conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools + cd ${{ github.workspace }} && ./scripts/init-submodules-no-riscv-tools.sh --force git submodule update --init software/firemarshal && cd software/firemarshal && ./init-submodules.sh cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json - name: Running Gemmini FireMarshal smoke test From 756403a4a1593037f147bffab6e19ac95822909d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 3 Apr 2023 13:52:34 -0700 Subject: [PATCH 039/184] Bump CI --- .github/workflows/chipyard-run-tests.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 6d4c02be..ac3aea0d 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -411,6 +411,7 @@ jobs: run: | conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools cd ${{ github.workspace }} && ./scripts/init-submodules-no-riscv-tools.sh --force + cd ${{ github.workspace }} && source ./scripts/fix-open-files.sh git submodule update --init software/firemarshal && cd software/firemarshal && ./init-submodules.sh cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json - name: Running Gemmini FireMarshal smoke test From c5e7c35da978f9bcdb69b80da309ba6e49b8cf7f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 3 Apr 2023 16:13:21 -0700 Subject: [PATCH 040/184] Bump CI --- .github/workflows/chipyard-run-tests.yml | 2 +- toolchains/riscv-tools/riscv-isa-sim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index ac3aea0d..f7917e92 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -393,7 +393,7 @@ jobs: chipyard-spike-gemmini-run-tests: name: chipyard-spike-gemmini-run-tests needs: prepare-chipyard-accels # technically doesn't depend on RTL but should be after the build.sh for Gemmini - runs-on: self-hosted + runs-on: ferry steps: - name: Delete old checkout run: | diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 929ff56a..fcfb795b 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 929ff56a09462978628c59c22fe6cb6895aa136f +Subproject commit fcfb795bea24c0489a0dbe9d446d05df35dc700d From dc17780d636a8419c70b3d444b44f8dd4ec0ff8b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 14 Mar 2023 20:23:29 -0700 Subject: [PATCH 041/184] Improve IOBinders implementation | add debug prints --- .../chipyard/src/main/scala/IOBinders.scala | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 71eef713..a2b6ab93 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -67,10 +67,29 @@ abstract trait HasIOBinders { this: LazyModule => }) // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) - lazy val iocells = (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer + val iocells = InModuleBody { (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer } // A mapping between stringified DigitalSystem traits and their corresponding ChipTop ports - lazy val portMap = iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap + val portMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap } + + // A mapping between stringified DigitalSystem traits and their corresponding ChipTop iocells + val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap } + + InModuleBody { + println("IOCells generated by IOBinders:") + for ((k, v) <- iocellMap) { + if (!v.isEmpty) { + val cells = v.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size) + + println(s" IOBinder for $k generated:") + for ((t, c) <- cells) { println(s" $c X $t") } + } + } + println() + val totals = iocells.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size) + println(s" Total generated ${iocells.size} IOCells:") + for ((t, c) <- totals) { println(s" $c X $t") } + } } // Note: The parameters instance is accessible only through LazyModule From 477456bc0b2dd4342a51808448cfc5837aebc4da Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 14 Mar 2023 20:25:28 -0700 Subject: [PATCH 042/184] Add custom chiptop+iocell example --- .../src/main/scala/config/RocketConfigs.scala | 6 ++ .../main/scala/example/CustomChipTop.scala | 64 +++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 generators/chipyard/src/main/scala/example/CustomChipTop.scala diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index b6677cb1..dcd15b46 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -126,3 +126,9 @@ class MulticlockAXIOverSerialConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(2) ++ new chipyard.config.AbstractConfig) // DOC include end: MulticlockAXIOverSerialConfig + +class CustomIOChipTopRocketConfig extends Config( + new chipyard.example.WithCustomChipTop ++ + new chipyard.example.WithCustomIOCells ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala new file mode 100644 index 00000000..19be7d5b --- /dev/null +++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala @@ -0,0 +1,64 @@ +package chipyard.example + +import chisel3._ +import chipyard.iobinders._ + +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy.{InModuleBody} +import barstools.iocell.chisel._ +import chipyard._ + +// A "custom" IOCell with additional I/O +// The IO don't do anything here in this example +class CustomDigitalInIOCellBundle extends DigitalInIOCellBundle { + val custom_out = Output(Bool()) + val custom_in = Input(Bool()) +} + +// Using a custom digital in iocell instead of the default one +class CustomDigitalInIOCell extends RawModule with DigitalInIOCell { + val io = IO(new CustomDigitalInIOCellBundle) + io.i := io.pad + io.custom_out := io.pad +} + +case class CustomIOCellParams() extends IOCellTypeParams { + def analog() = Module(new GenericAnalogIOCell) + def gpio() = Module(new GenericDigitalGPIOCell) + def input() = Module(new CustomDigitalInIOCell) + def output() = Module(new GenericDigitalOutIOCell) +} + +class CustomChipTop(implicit p: Parameters) extends ChipTop { + // making the module name ChipTop instead of CustomChipTop means + // we don't have to set the TOP make variable to CustomChipTop + override lazy val desiredName = "ChipTop" + + // InModuleBody blocks are executed within the LazyModuleImp of this block + InModuleBody { + iocellMap.foreach { case (interface, cells) => { + cells.foreach { _ match { + case c: CustomDigitalInIOCell => { + c.io.custom_in := false.B + } + case c: GenericDigitalOutIOCell => { + // do nothing + } + case c => { + require(false, "Unsupported iocell type ${c.getClass}") + } + }} + }} + + // demonstrate accessing the iocellMap directly + val serialTLIOCells = iocellMap("interface testchipip.CanHavePeripheryTLSerial") + } +} + +class WithCustomIOCells extends Config((site, here, up) => { + case IOCellKey => CustomIOCellParams() +}) + +class WithCustomChipTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => new CustomChipTop()(p) +}) From 283111113468b039edbb0493f9f76a2261cfa2a0 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 20 Mar 2023 11:20:31 -0700 Subject: [PATCH 043/184] Mention custom ChipTop in documentation' --- docs/Advanced-Concepts/Top-Testharness.rst | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index 23f3f56a..e412eeff 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -18,6 +18,13 @@ The ``IOBinders`` are responsible for instantiating the IO cells for ``ChipTop`` The ``HarnessBinders`` are responsible for instantiating test harness collateral that connects to the ``ChipTop`` ports. Most types of devices and testing collateral can be instantiated using custom ``IOBinders`` and ``HarnessBinders``. +Custom ChipTops +^^^^^^^^^^^^^^^^^^^^^^^^^ + +The default standard ``ChipTop`` provides a mimimal, barebones template for ``IOBinders`` to generate IOCells around ``DigitalTop`` traits. +For tapeouts, integrating Analog IP, or other non-standard use cases, Chipyard supports specifying a custom ``ChipTop`` using the ``BuildTop`` key. +An example of a custom ChipTop which uses non-standard IOCells is provided in `generators/chipyard/src/main/scala/example/CustomChipTop.scala `__ + System/DigitalTop ------------------------- From bf3642d8d06507e0639398d21ba46f0af339f4bc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 1 Apr 2023 13:34:07 -0700 Subject: [PATCH 044/184] DontTouch ChipTop ports --- generators/chipyard/src/main/scala/IOBinders.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index a2b6ab93..0e5d60ac 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -76,6 +76,8 @@ abstract trait HasIOBinders { this: LazyModule => val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap } InModuleBody { + portMap.values.foreach(_.foreach(dontTouch(_))) + println("IOCells generated by IOBinders:") for ((k, v) <- iocellMap) { if (!v.isEmpty) { From 853b4349a4b39c9f3b4354330700d87e985c59e8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 3 Apr 2023 18:41:17 -0700 Subject: [PATCH 045/184] Switch to spike master branch --- toolchains/riscv-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index fcfb795b..d70ea67d 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit fcfb795bea24c0489a0dbe9d446d05df35dc700d +Subproject commit d70ea67df7e85a8d92a8baa254afde67c33c43a9 From 149c89d7130683cb326f9c647aae993015273520 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 3 Apr 2023 17:55:44 -0700 Subject: [PATCH 046/184] Add option to disable ChipTop port dontTouch --- generators/chipyard/src/main/scala/IOBinders.scala | 12 ++++++++++-- .../main/scala/config/MMIOAcceleratorConfigs.scala | 2 ++ .../src/main/scala/config/RocketConfigs.scala | 1 + .../src/main/scala/config/TutorialConfigs.scala | 1 + 4 files changed, 14 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 0e5d60ac..9ef32091 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -51,6 +51,12 @@ case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]]( Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil) ) +case object DontTouchIOBindersPorts extends Field[Boolean](true) + +class WithDontTouchIOBinders(b: Boolean = true) extends Config((site, here, up) => { + case DontTouchIOBindersPorts => b +}) + abstract trait HasIOBinders { this: LazyModule => val lazySystem: LazyModule private val iobinders = p(IOBinders) @@ -76,8 +82,10 @@ abstract trait HasIOBinders { this: LazyModule => val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap } InModuleBody { - portMap.values.foreach(_.foreach(dontTouch(_))) - + if (p(DontTouchIOBindersPorts)) { + portMap.values.foreach(_.foreach(dontTouch(_))) + } + println("IOCells generated by IOBinders:") for ((k, v) <- iocellMap) { if (!v.isEmpty) { diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala index fcb4804d..aa04cfe1 100644 --- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // DOC include start: FFTRocketConfig class FFTRocketConfig extends Config( + new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO: hack around dontTouch not working in SFC new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers. new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -58,6 +59,7 @@ class LargeNVDLARocketConfig extends Config( new chipyard.config.AbstractConfig) class ManyMMIOAcceleratorRocketConfig extends Config( + new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO: hack around dontTouch not working in SFC new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers. new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index dcd15b46..f70ef274 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -12,6 +12,7 @@ class RocketConfig extends Config( new chipyard.config.AbstractConfig) class TinyRocketConfig extends Config( + new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO FIX: Don't dontTouch the ports new chipyard.config.WithTLSerialLocation( freechips.rocketchip.subsystem.FBUS, freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index c9956b7a..c871ba6f 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -77,6 +77,7 @@ class TutorialSha3BlackBoxConfig extends Config( // Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators class TutorialNoCConfig extends Config( + new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // Try changing the dimensions of the Mesh topology new constellation.soc.WithGlobalNoC(constellation.soc.GlobalNoCParams( NoCParams( From 89a2458291793c9b71c967181c8f1a9b4a20baaa Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 4 Apr 2023 14:18:33 -0700 Subject: [PATCH 047/184] Ensure conda cleanup regex properly filters out non-numeric chars --- .github/actions/cleanup-conda/action.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/actions/cleanup-conda/action.yml b/.github/actions/cleanup-conda/action.yml index 3b0fdf88..7958b0a4 100644 --- a/.github/actions/cleanup-conda/action.yml +++ b/.github/actions/cleanup-conda/action.yml @@ -15,7 +15,7 @@ runs: conda env remove -n $env done fi - IS_NUMBER_REGEX='[0-9]+$' + IS_NUMBER_REGEX='^[0-9]+$' conda env list | awk '{print $1}' | tail -n +4 | while read envname; do ENV_DATE=$(echo $envname | sed "s/cy-[[:digit:]]\+-\(.*\)-\(riscv\|esp\)-tools/\1/") if ! [[ $ENV_DATE =~ $IS_NUMBER_REGEX ]]; then From a5ee995ed46d86d0af6a30cb9fdffd47c4c50814 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 4 Apr 2023 12:22:44 -0700 Subject: [PATCH 048/184] New Scala-based Config Finder --- build.sbt | 7 ++++++- common.mk | 10 +++------- docs/Customization/Keys-Traits-Configs.rst | 3 +-- .../src/main/scala/ConfigFinder.scala | 19 +++++++++++++++++++ 4 files changed, 29 insertions(+), 10 deletions(-) create mode 100644 generators/chipyard/src/main/scala/ConfigFinder.scala diff --git a/build.sbt b/build.sbt index 0f065836..4e9656bc 100644 --- a/build.sbt +++ b/build.sbt @@ -149,7 +149,12 @@ lazy val chipyard = (project in file("generators/chipyard")) gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, constellation, mempress) .settings(libraryDependencies ++= rocketLibDeps.value) - .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.reflections" % "reflections" % "0.10.2" + ) + ) + .settings(commonSettings) lazy val mempress = (project in file("generators/mempress")) .dependsOn(rocketchip, midasTargetUtils) diff --git a/common.mk b/common.mk index 6cebf335..a4668075 100644 --- a/common.mk +++ b/common.mk @@ -50,7 +50,7 @@ HELP_COMMANDS += \ " run-tests = run all assembly and benchmark tests" \ " launch-sbt = start sbt terminal" \ " {shutdown,start}-sbt-server = shutdown or start sbt server if using ENABLE_SBT_THIN_CLIENT" \ -" find-config-fragments = list all config. fragments and their locations (recursive up to CONFIG_FRAG_LEVELS=$(CONFIG_FRAG_LEVELS))" +" find-config-fragments = list all config. fragments" ######################################################################################### # include additional subproject make fragments @@ -406,13 +406,9 @@ define \n endef -CONFIG_FRAG_LEVELS ?= 3 .PHONY: find-config-fragments -find-config-fragments: private IN_F := $(shell mktemp -d -t cy-XXXXXXXX)/scala_files.f -find-config-fragments: $(SCALA_SOURCES) - @$(foreach file,$(SCALA_SOURCES),echo $(file) >> $(IN_F)${\n}) - $(base_dir)/scripts/config-finder.py -l $(CONFIG_FRAG_LEVELS) $(IN_F) - @rm -rf $(dir $(IN_F)) +find-config-fragments: + $(call run_scala_main,chipyard,chipyard.ConfigFinder,) .PHONY: help help: diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index 364f31cb..7b6d565b 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -79,5 +79,4 @@ We can use this config fragment when composing our configs. Chipyard Config Fragments ------------------------- -For discoverability, users can run ``make find-config-fragments`` to see a list of config. fragments -(config. fragments that match "class NAME extends CONFIG\n" on a single line and a subset of their children) and their file path in a fully initialized Chipyard repository. +For discoverability, users can run ``make find-config-fragments`` to see a list of config. fragments. diff --git a/generators/chipyard/src/main/scala/ConfigFinder.scala b/generators/chipyard/src/main/scala/ConfigFinder.scala new file mode 100644 index 00000000..1c83c3d1 --- /dev/null +++ b/generators/chipyard/src/main/scala/ConfigFinder.scala @@ -0,0 +1,19 @@ +package chipyard + +import org.reflections.Reflections +import org.reflections.scanners.Scanners.SubTypes +import scala.jdk.CollectionConverters._ +import scala.collection.{SortedSet} + +import freechips.rocketchip.config.{Config} + +object ConfigFinder { + def main(args: Array[String]) = { + val reflections = new Reflections() + val classes = reflections.get(SubTypes.of(classOf[Config]).asClass()).asScala + val sortedClasses = SortedSet[String]() ++ classes.map(_.getName) + for (cls <- sortedClasses) { + println(cls) + } + } +} From ee9ee109109baad6971c9cafe99507768e9b9cb8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 4 Apr 2023 12:26:02 -0700 Subject: [PATCH 049/184] Remove old config-finder.py --- scripts/config-finder.py | 76 ---------------------------------------- 1 file changed, 76 deletions(-) delete mode 100755 scripts/config-finder.py diff --git a/scripts/config-finder.py b/scripts/config-finder.py deleted file mode 100755 index a7377939..00000000 --- a/scripts/config-finder.py +++ /dev/null @@ -1,76 +0,0 @@ -#!/usr/bin/env python3 - -import argparse -import subprocess -from collections import defaultdict -import re -from copy import deepcopy -import os - -cy_path = os.path.dirname(os.path.dirname(os.path.realpath(__file__))) - -# from https://gist.github.com/angstwad/bf22d1822c38a92ec0a9 -def deep_merge(a: dict, b: dict) -> dict: - """Merge two dicts and return a singular dict""" - result = deepcopy(a) - for bk, bv in b.items(): - av = result.get(bk) - if isinstance(av, dict) and isinstance(bv, dict): - result[bk] = deep_merge(av, bv) - else: - result[bk] = deepcopy(bv) - return result - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description='Pretty print all configs given a filelist of scala files') - parser.add_argument('FILE', type=str, help='Filelist of scala files to search within') - parser.add_argument('-l', '--levels', default=0, type=int, help='Number of levels to recursively look for configs') - args = parser.parse_args() - - files = [] - with open(args.FILE, 'r') as f: - files = f.read().splitlines() - - cmd = ['grep', '-o', r"class \+.* \+extends \+Config"] + files - r = subprocess.run(cmd, check=True, capture_output=True) - - base_file_path_dict = defaultdict(list) - for l in r.stdout.decode("UTF-8").splitlines(): - match = re.match(r"^(.*):class +([a-zA-Z_$][a-zA-Z\d_$]*).* +extends", l) - if match: - base_file_path_dict[match.group(1)].append(match.group(2)) - - levels = [] - for level in range(args.levels): - if level == 0: - # use the base - dict_to_use = base_file_path_dict - else: - # use the level-1 dict - assert len(levels) > 0 - dict_to_use = levels[-1] - - file_path_dict = defaultdict(list) - - for configs in dict_to_use.values(): - for config in configs: - cmd = ['grep', '-o', r"class \+.* \+extends \+" + f"{config}"] + files - r = subprocess.run(cmd, capture_output=True) - - for l in r.stdout.decode("UTF-8").splitlines(): - match = re.match(r"^(.*):class +([a-zA-Z_$][a-zA-Z\d_$]*).* +extends", l) - if match: - file_path_dict[match.group(1)].append(match.group(2)) - - levels.append(file_path_dict) - - final_dict = base_file_path_dict - for dct in levels: - final_dict = deep_merge(final_dict, dct) - - print(f"Finding all one-line config. fragments (up to {args.levels} levels)\n") - for k, v in final_dict.items(): - print(f"{k.replace(cy_path, 'chipyard')}:") - for e in v: - print(f" {e}") - print("") From 54a6288f1afadf4336eda1487d6d60e6d0f79ec4 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 6 Apr 2023 17:36:13 -0700 Subject: [PATCH 050/184] Add mt-helloworld example --- tests/Makefile | 2 +- tests/encoding.h | 1 + tests/hello.c | 6 +++++- tests/marchid.h | 17 +++++++++++++++++ tests/mt-hello.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 72 insertions(+), 2 deletions(-) create mode 120000 tests/encoding.h create mode 100644 tests/marchid.h create mode 100644 tests/mt-hello.c diff --git a/tests/Makefile b/tests/Makefile index 8756350d..5bea4da4 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -7,7 +7,7 @@ include libgloss.mk PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \ streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd \ - hello + hello mt-hello spiflash.img: spiflash.py python3 $< diff --git a/tests/encoding.h b/tests/encoding.h new file mode 120000 index 00000000..f398b163 --- /dev/null +++ b/tests/encoding.h @@ -0,0 +1 @@ +../toolchains/riscv-tools/riscv-tests/env/encoding.h \ No newline at end of file diff --git a/tests/hello.c b/tests/hello.c index 28d667e0..dbfbfe56 100644 --- a/tests/hello.c +++ b/tests/hello.c @@ -1,6 +1,10 @@ #include +#include "encoding.h" +#include "marchid.h" int main(void) { - printf("Hello world\n"); + uint64_t marchid = read_csr(marchid); + const char* march = get_march(marchid); + printf("Hello world from core 0, a %s\n", march); return 0; } diff --git a/tests/marchid.h b/tests/marchid.h new file mode 100644 index 00000000..5dfb2a3c --- /dev/null +++ b/tests/marchid.h @@ -0,0 +1,17 @@ +#ifndef MARCHID_H +#define MARCHID_H + +const char* get_march(size_t marchid) { + switch (marchid) { + case 1: + return "rocket"; + case 2: + return "sonicboom"; + case 5: + return "spike"; + default: + return "unknown"; + } +} + +#endif diff --git a/tests/mt-hello.c b/tests/mt-hello.c new file mode 100644 index 00000000..5ab47a56 --- /dev/null +++ b/tests/mt-hello.c @@ -0,0 +1,48 @@ +#include "encoding.h" +#include +#include "marchid.h" + +// EDIT THIS +static size_t n_cores = 4; + +static void __attribute__((noinline)) barrier() +{ + static volatile int sense; + static volatile int count; + static __thread int threadsense; + + __sync_synchronize(); + + threadsense = !threadsense; + if (__sync_fetch_and_add(&count, 1) == n_cores-1) + { + count = 0; + sense = threadsense; + } + else while(sense != threadsense) + ; + + __sync_synchronize(); +} + +void __main(void) { + size_t mhartid = read_csr(mhartid); + + if (mhartid >= n_cores) while (1); + + const char* march = get_march(read_csr(marchid)); + for (size_t i = 0; i < n_cores; i++) { + if (mhartid == i) { + printf("Hello world from core %lu, a %s\n", mhartid, march); + } + barrier(); + } + + // Spin if not core 0 + if (mhartid > 0) while (1); +} + +int main(void) { + __main(); + return 0; +} From 0f6f38e66b211474dc2122f2021579a03a4cb6ae Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 8 Apr 2023 14:22:51 -0700 Subject: [PATCH 051/184] Resolve merge conflicts in chisel3.5.6 bump --- generators/chipyard/src/main/scala/ConfigFinder.scala | 2 +- generators/chipyard/src/main/scala/example/CustomChipTop.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFinder.scala b/generators/chipyard/src/main/scala/ConfigFinder.scala index 1c83c3d1..dfee340d 100644 --- a/generators/chipyard/src/main/scala/ConfigFinder.scala +++ b/generators/chipyard/src/main/scala/ConfigFinder.scala @@ -5,7 +5,7 @@ import org.reflections.scanners.Scanners.SubTypes import scala.jdk.CollectionConverters._ import scala.collection.{SortedSet} -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} object ConfigFinder { def main(args: Array[String]) = { diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala index 19be7d5b..19ec945b 100644 --- a/generators/chipyard/src/main/scala/example/CustomChipTop.scala +++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala @@ -3,7 +3,7 @@ package chipyard.example import chisel3._ import chipyard.iobinders._ -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy.{InModuleBody} import barstools.iocell.chisel._ import chipyard._ From 8a1ebb090cad661cbf9b17d902f061dae8f4f7e7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 5 Apr 2023 11:42:41 -0700 Subject: [PATCH 052/184] Move Clock binders to separate file --- .../src/main/scala/HarnessBinders.scala | 4 +- .../chipyard/src/main/scala/IOBinders.scala | 41 --------------- .../main/scala/clocking/ClockBinders.scala | 52 +++++++++++++++++++ .../main/scala/config/AbstractConfig.scala | 6 ++- .../main/scala/config/TracegenConfigs.scala | 2 +- 5 files changed, 60 insertions(+), 45 deletions(-) create mode 100644 generators/chipyard/src/main/scala/clocking/ClockBinders.scala diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 1992bc1e..51d39ce4 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -22,8 +22,8 @@ import barstools.iocell.chisel._ import testchipip._ import chipyard._ -import chipyard.clocking.{HasChipyardPRCI} -import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, ClockWithFreq} +import chipyard.clocking.{HasChipyardPRCI, ClockWithFreq} +import chipyard.iobinders.{GetSystemParameters, JTAGChipIO} import tracegen.{TraceGenSystemModuleImp} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index f883931e..1e234144 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -425,45 +425,4 @@ class WithDontTouchPorts extends OverrideIOBinder({ (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil) }) -class ClockWithFreq(val freqMHz: Double) extends Bundle { - val clock = Clock() -} -class WithDividerOnlyClockGenerator extends OverrideLazyIOBinder({ - (system: HasChipyardPRCI) => { - // Connect the implicit clock - implicit val p = GetSystemParameters(system) - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - InModuleBody { - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - } - - // Connect all other requested clocks - val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) - val dividerOnlyClockGen = LazyModule(new DividerOnlyClockGenerator("buildTopClockGenerator")) - - (system.allClockGroupsNode - := dividerOnlyClockGen.node - := referenceClockSource) - - InModuleBody { - val clock_wire = Wire(Input(new ClockWithFreq(dividerOnlyClockGen.module.referenceFreq))) - val reset_wire = Wire(Input(AsyncReset())) - val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) - val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) - - referenceClockSource.out.unzip._1.map { o => - o.clock := clock_wire.clock - o.reset := reset_wire - } - - (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) - } - } -}) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala new file mode 100644 index 00000000..5aa7cbc8 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -0,0 +1,52 @@ +package chipyard.clocking + +import chisel3._ +import chisel3.util._ +import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey} +import freechips.rocketchip.prci._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.subsystem._ +import barstools.iocell.chisel._ + +class ClockWithFreq(val freqMHz: Double) extends Bundle { + val clock = Clock() +} + +class WithDividerOnlyClockGenerator extends OverrideLazyIOBinder({ + (system: HasChipyardPRCI) => { + // Connect the implicit clock + implicit val p = GetSystemParameters(system) + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) + system.connectImplicitClockSinkNode(implicitClockSinkNode) + InModuleBody { + val implicit_clock = implicitClockSinkNode.in.head._1.clock + val implicit_reset = implicitClockSinkNode.in.head._1.reset + system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { + l.clock := implicit_clock + l.reset := implicit_reset + }} + } + + // Connect all other requested clocks + val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) + val dividerOnlyClockGen = LazyModule(new DividerOnlyClockGenerator("buildTopClockGenerator")) + + (system.allClockGroupsNode + := dividerOnlyClockGen.node + := referenceClockSource) + + InModuleBody { + val clock_wire = Wire(Input(new ClockWithFreq(dividerOnlyClockGen.module.referenceFreq))) + val reset_wire = Wire(Input(AsyncReset())) + val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) + val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) + + referenceClockSource.out.unzip._1.map { o => + o.clock := clock_wire.clock + o.reset := reset_wire + } + + (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) + } + } +}) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index c9a6e838..e270c978 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -40,7 +40,11 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithExtInterruptIOCells ++ new chipyard.iobinders.WithCustomBootPin ++ - new chipyard.iobinders.WithDividerOnlyClockGenerator ++ + + // Default behavior is to use a divider-only clock-generator + // This works in VCS, Verilator, and FireSim/ + // This should get replaced with a PLL-like config instead + new chipyard.clocking.WithDividerOnlyClockGenerator ++ new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 605db4d3..b92b2f46 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -9,7 +9,7 @@ class AbstractTraceGenConfig extends Config( new chipyard.harness.WithClockAndResetFromHarness ++ new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ - new chipyard.iobinders.WithDividerOnlyClockGenerator ++ + new chipyard.clocking.WithDividerOnlyClockGenerator ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ From 70ea3b78ab72abb01b17f5907ff6f90f6463191d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 5 Apr 2023 15:31:21 -0700 Subject: [PATCH 053/184] Add ChipLikeRocketConfig ... improve harness clocking APIs --- .../src/main/scala/HarnessBinders.scala | 2 +- .../src/main/scala/HarnessClocks.scala | 85 +++++++++++++++++++ .../chipyard/src/main/scala/TestHarness.scala | 53 +----------- .../main/scala/clocking/ClockBinders.scala | 61 +++++++++++++ .../src/main/scala/clocking/FakePLL.scala | 36 ++++++++ .../main/scala/clocking/TLClockDivider.scala | 52 ++++++++++++ .../main/scala/clocking/TLClockSelector.scala | 70 +++++++++++++++ .../main/scala/clocking/TileClockGater.scala | 2 +- .../main/scala/clocking/TileResetSetter.scala | 6 +- 9 files changed, 313 insertions(+), 54 deletions(-) create mode 100644 generators/chipyard/src/main/scala/HarnessClocks.scala create mode 100644 generators/chipyard/src/main/scala/clocking/FakePLL.scala create mode 100644 generators/chipyard/src/main/scala/clocking/TLClockDivider.scala create mode 100644 generators/chipyard/src/main/scala/clocking/TLClockSelector.scala diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 51d39ce4..c39242f9 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -154,7 +154,7 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({ ports.map({ port => // DOC include start: HarnessClockInstantiatorEx withClockAndReset(th.buildtopClock, th.buildtopReset) { - val memOverSerialTLClockBundle = p(HarnessClockInstantiatorKey).requestClockBundle("mem_over_serial_tl_clock", memFreq) + val memOverSerialTLClockBundle = th.harnessClockInstantiator.requestClockBundle("mem_over_serial_tl_clock", memFreq) val serial_bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM( system.serdesser.get, diff --git a/generators/chipyard/src/main/scala/HarnessClocks.scala b/generators/chipyard/src/main/scala/HarnessClocks.scala new file mode 100644 index 00000000..f973c292 --- /dev/null +++ b/generators/chipyard/src/main/scala/HarnessClocks.scala @@ -0,0 +1,85 @@ +package chipyard + +import chisel3._ + +import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.util.{ResetCatchAndSync} +import freechips.rocketchip.prci._ + +import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} +import chipyard.iobinders.HasIOBinders +import chipyard.clocking.{SimplePllConfiguration, ClockDividerN} +import chipyard.HarnessClockInstantiatorKey + +trait HarnessClockInstantiator { + val _clockMap: LinkedHashMap[String, (Double, ClockBundle)] = LinkedHashMap.empty + + // request a clock bundle at a particular frequency + def requestClockBundle(name: String, freqRequested: Double): ClockBundle = { + val clockBundle = Wire(new ClockBundle(ClockBundleParameters())) + _clockMap(name) = (freqRequested, clockBundle) + clockBundle + } + + def instantiateHarnessClocks(refClock: ClockBundle): Unit +} + +class DividerOnlyHarnessClockInstantiator extends HarnessClockInstantiator { + // connect all clock wires specified to a divider only PLL + def instantiateHarnessClocks(refClock: ClockBundle): Unit = { + val sinks = _clockMap.map({ case (name, (freq, bundle)) => + ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name)) + }).toSeq + + val pllConfig = new SimplePllConfiguration("harnessDividerOnlyClockGenerator", sinks) + pllConfig.emitSummaries() + + val dividedClocks = LinkedHashMap[Int, Clock]() + def instantiateDivider(div: Int): Clock = { + val divider = Module(new ClockDividerN(div)) + divider.suggestName(s"ClockDivideBy${div}") + divider.io.clk_in := refClock.clock + dividedClocks(div) = divider.io.clk_out + divider.io.clk_out + } + + // connect wires to clock source + for (sinkParams <- sinks) { + // bypass the reference freq. (don't create a divider + reset sync) + val (divClock, divReset) = if (sinkParams.take.get.freqMHz != pllConfig.referenceFreqMHz) { + val div = pllConfig.sinkDividerMap(sinkParams) + val divClock = dividedClocks.getOrElse(div, instantiateDivider(div)) + (divClock, ResetCatchAndSync(divClock, refClock.reset.asBool)) + } else { + (refClock.clock, refClock.reset) + } + + _clockMap(sinkParams.name.get)._2.clock := divClock + _clockMap(sinkParams.name.get)._2.reset := divReset + } + } +} + +class AbsoluteFreqHarnessClockInstantiator extends HarnessClockInstantiator { + def instantiateHarnessClocks(refClock: ClockBundle): Unit = { + val sinks = _clockMap.map({ case (name, (freq, bundle)) => + ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name)) + }).toSeq + + // connect wires to clock source + for (sinkParams <- sinks) { + val source = Module(new ClockSourceAtFreq(sinkParams.take.get.freqMHz)) + source.io.power := true.B + source.io.gate := false.B + + _clockMap(sinkParams.name.get)._2.clock := source.io.clk + _clockMap(sinkParams.name.get)._2.reset := refClock.reset + } + } +} + +class WithAbsoluteFreqHarnessClockInstantiator extends Config((site, here, up) => { + case HarnessClockInstantiatorKey => () => new AbsoluteFreqHarnessClockInstantiator +}) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 23bda680..a8b18d4f 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -18,9 +18,11 @@ import chipyard.clocking.{SimplePllConfiguration, ClockDividerN} case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) => new ChipTop()(p)) case object DefaultClockFrequencyKey extends Field[Double](100.0) // MHz +case object HarnessClockInstantiatorKey extends Field[() => HarnessClockInstantiator](() => new DividerOnlyHarnessClockInstantiator) trait HasHarnessSignalReferences { implicit val p: Parameters + val harnessClockInstantiator = p(HarnessClockInstantiatorKey)() // clock/reset of the chiptop reference clock (can be different than the implicit harness clock/reset) var refClockFreq: Double = p(DefaultClockFrequencyKey) def setRefClockFreq(freqMHz: Double) = { refClockFreq = freqMHz } @@ -30,53 +32,6 @@ trait HasHarnessSignalReferences { def success: Bool } -class HarnessClockInstantiator { - private val _clockMap: LinkedHashMap[String, (Double, ClockBundle)] = LinkedHashMap.empty - - // request a clock bundle at a particular frequency - def requestClockBundle(name: String, freqRequested: Double): ClockBundle = { - val clockBundle = Wire(new ClockBundle(ClockBundleParameters())) - _clockMap(name) = (freqRequested, clockBundle) - clockBundle - } - - // connect all clock wires specified to a divider only PLL - def instantiateHarnessDividerPLL(refClock: ClockBundle): Unit = { - val sinks = _clockMap.map({ case (name, (freq, bundle)) => - ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name)) - }).toSeq - - val pllConfig = new SimplePllConfiguration("harnessDividerOnlyClockGenerator", sinks) - pllConfig.emitSummaries() - - val dividedClocks = LinkedHashMap[Int, Clock]() - def instantiateDivider(div: Int): Clock = { - val divider = Module(new ClockDividerN(div)) - divider.suggestName(s"ClockDivideBy${div}") - divider.io.clk_in := refClock.clock - dividedClocks(div) = divider.io.clk_out - divider.io.clk_out - } - - // connect wires to clock source - for (sinkParams <- sinks) { - // bypass the reference freq. (don't create a divider + reset sync) - val (divClock, divReset) = if (sinkParams.take.get.freqMHz != pllConfig.referenceFreqMHz) { - val div = pllConfig.sinkDividerMap(sinkParams) - val divClock = dividedClocks.getOrElse(div, instantiateDivider(div)) - (divClock, ResetCatchAndSync(divClock, refClock.reset.asBool)) - } else { - (refClock.clock, refClock.reset) - } - - _clockMap(sinkParams.name.get)._2.clock := divClock - _clockMap(sinkParams.name.get)._2.reset := divReset - } - } -} - -case object HarnessClockInstantiatorKey extends Field[HarnessClockInstantiator](new HarnessClockInstantiator) - class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSignalReferences { val io = IO(new Bundle { val success = Output(Bool()) @@ -96,7 +51,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign ApplyHarnessBinders(this, d.lazySystem, d.portMap) } - val refClkBundle = p(HarnessClockInstantiatorKey).requestClockBundle("buildtop_reference_clock", getRefClockFreq * (1000 * 1000)) + val refClkBundle = harnessClockInstantiator.requestClockBundle("buildtop_reference_clock", getRefClockFreq * (1000 * 1000)) buildtopClock := refClkBundle.clock buildtopReset := WireInit(refClkBundle.reset) @@ -104,5 +59,5 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) implicitHarnessClockBundle.clock := clock implicitHarnessClockBundle.reset := reset - p(HarnessClockInstantiatorKey).instantiateHarnessDividerPLL(implicitHarnessClockBundle) + harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle) } diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 5aa7cbc8..01eb261c 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -6,6 +6,7 @@ import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey} import freechips.rocketchip.prci._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tilelink._ import barstools.iocell.chisel._ class ClockWithFreq(val freqMHz: Double) extends Bundle { @@ -50,3 +51,63 @@ class WithDividerOnlyClockGenerator extends OverrideLazyIOBinder({ } } }) + +// Note: This will not simulate properly with verilator or firesim +class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ + (system: HasChipyardPRCI) => { + // Connect the implicit clock + implicit val p = GetSystemParameters(system) + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) + system.connectImplicitClockSinkNode(implicitClockSinkNode) + InModuleBody { + val implicit_clock = implicitClockSinkNode.in.head._1.clock + val implicit_reset = implicitClockSinkNode.in.head._1.reset + system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { + l.clock := implicit_clock + l.reset := implicit_reset + }} + } + val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere) + val baseAddress = system.prciParams.baseAddress + val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) } + val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } + val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } + + tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() } + tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() } + tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() } + + system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode + + // Connect all other requested clocks + val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) + val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters())) + + // The order of the connections to clockSelector.clockNode configures what + clockSelector.clockNode := slowClockSource + clockSelector.clockNode := pllClockSource + + val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]() + pllCtrlSink := pllCtrl.ctrlNode + + InModuleBody { + val clock_wire = Wire(Input(new ClockWithFreq(80))) + val reset_wire = Wire(Input(AsyncReset())) + val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) + val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) + + slowClockSource.out.unzip._1.map { o => + o.clock := clock_wire.clock + o.reset := reset_wire + } + + // For a real chip you should replace this ClockSourceAtFreqFromPlusArg + // with a blackbox of whatever PLL is being integrated + val fakeClockSource = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz")) + fakeClockSource.io.power := pllCtrlSink.in(0)._1.power + fakeClockSource.io.gate := pllCtrlSink.in(0)._1.gate + + (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) + } + } +}) diff --git a/generators/chipyard/src/main/scala/clocking/FakePLL.scala b/generators/chipyard/src/main/scala/clocking/FakePLL.scala new file mode 100644 index 00000000..a903ced6 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/FakePLL.scala @@ -0,0 +1,36 @@ +package chipyard.clocking + +import chisel3._ +import chisel3.util._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.util._ + +class FakePLLCtrlBundle extends Bundle { + val gate = Bool() + val power = Bool() +} + +class FakePLLCtrl(address: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule +{ + val device = new SimpleDevice(s"pll", Nil) + val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) + val ctrlNode = BundleBridgeSource(() => Output(new FakePLLCtrlBundle)) + lazy val module = new LazyModuleImp(this) { + // This PLL only has 2 address, the gate and power + // Both should be set to turn on the PLL + // TODO: Should these be reset by the top level reset pin? + val gate_reg = Module(new AsyncResetRegVec(w=1, init=0)) + val power_reg = Module(new AsyncResetRegVec(w=1, init=0)) + + ctrlNode.out(0)._1.gate := gate_reg.io.q + ctrlNode.out(0)._1.power := power_reg.io.q + tlNode.regmap( + 0 -> Seq(RegField.rwReg(1, gate_reg.io)), + 4 -> Seq(RegField.rwReg(1, power_reg.io)) + ) + } +} diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala new file mode 100644 index 00000000..b9d62344 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala @@ -0,0 +1,52 @@ +package chipyard.clocking + +import chisel3._ + +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.util._ +import freechips.rocketchip.prci._ +import freechips.rocketchip.util.ElaborationArtefacts + +import testchipip._ + +class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit p: Parameters) extends LazyModule { + val device = new SimpleDevice(s"clk-div-ctrl", Nil) + val clockNode = ClockGroupIdentityNode() + val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) + + lazy val module = new LazyModuleImp(this) { + require (clockNode.out.size == 1) + val sources = clockNode.in.head._1.member.data.toSeq + val sinks = clockNode.out.head._1.member.elements.toSeq + require (sources.size == sinks.size) + val nSinks = sinks.size + + val regs = (0 until nSinks) .map { i => + val sinkName = sinks(i)._1 + val asyncReset = sources(i).reset + val reg = withReset (asyncReset) { + Module(new AsyncResetRegVec(w=divBits, init=0)) + } + println(s"${(address+i*4).toString(16)}: Clock domain $sinkName divider") + sinks(i)._2.clock := withClockAndReset(sources(i).clock, asyncReset) { + val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl))) + divider.io.divisor := reg.io.q + divider.io.resetAsync := ResetStretcher(sources(i).clock, asyncReset, 20).asAsyncReset + divider.io.clockOut + } + + // Note this is not synchronized to the output clock, which takes time to appear + // so this is still asyncreset + sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset + reg + } + + tlNode.regmap((0 until nSinks).map { i => + i * 4 -> Seq(RegField.rwReg(divBits, regs(i).io)) + }: _*) + } +} diff --git a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala new file mode 100644 index 00000000..22110e62 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala @@ -0,0 +1,70 @@ +package chipyard.clocking + +import chisel3._ +import chisel3.util._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.util._ +import freechips.rocketchip.prci._ +import freechips.rocketchip.util.ElaborationArtefacts + +import testchipip._ + +object ResetStretcher { + def apply(clock: Clock, reset: Reset, cycles: Int): Reset = { + withClockAndReset(clock, reset) { + val n = log2Ceil(cycles) + val count = Module(new AsyncResetRegVec(w=n, init=0)) + val resetout = Module(new AsyncResetRegVec(w=1, init=1)) + count.io.en := resetout.io.q + count.io.d := count.io.q + 1.U + resetout.io.en := resetout.io.q + resetout.io.d := count.io.q < (cycles-1).U + + resetout.io.q.asBool + } + } +} + + +case class ClockSelNode()(implicit valName: ValName) + extends MixedNexusNode(ClockImp, ClockGroupImp)( + dFn = { d => ClockGroupSourceParameters() }, + uFn = { u => ClockSinkParameters() } +) + +class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule { + val device = new SimpleDevice("clk-sel-ctrl", Nil) + val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) + + val clockNode = ClockSelNode() + + lazy val module = new LazyModuleImp(this) { + val asyncReset = clockNode.in.map(_._1).map(_.reset).toSeq(0) + val clocks = clockNode.in.map(_._1).map(_.clock) + val (outClocks, _) = clockNode.out.head + val (sinkNames, sinks) = outClocks.member.elements.toSeq.unzip + + val regs = (0 until sinks.size).map { i => + val sinkName = sinkNames(i) + val sel = Wire(UInt(log2Ceil(clocks.size).W)) + val reg = withReset(asyncReset) { Module(new AsyncResetRegVec(w=log2Ceil(clocks.size), init=0)) } + sel := reg.io.q + println(s"${(address+i*4).toString(16)}: Clock domain $sinkName clock mux") + + val mux = testchipip.ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux") + mux.io.sel := sel + mux.io.resetAsync := asyncReset.asAsyncReset + sinks(i).clock := mux.io.clockOut + sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset + + reg + } + tlNode.regmap((0 until sinks.size).map { i => + i * 4 -> Seq(RegField.rwReg(log2Ceil(clocks.size), regs(i).io)) + }: _*) + } +} diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala index 9b7696fb..a77b02d5 100644 --- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala +++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala @@ -32,7 +32,7 @@ class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit val sinkName = sinks(i)._1 val reg = withReset(sources(i).reset) { Module(new AsyncResetRegVec(w=1, init=1)) } if (sinkName.contains("tile") && enable) { - println(s"ClockGate for ${sinkName} regmapped at ${(address+i*4).toString(16)}") + println(s"${(address+i*4).toString(16)}: Tile $sinkName clock gate") sinks(i)._2.clock := ClockGate(sources(i).clock, reg.io.q.asBool) sinks(i)._2.reset := sources(i).reset } else { diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala index d8243e37..9ea4bfd5 100644 --- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala +++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala @@ -39,16 +39,16 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i }): _*) val tileMap = tileNames.zipWithIndex.map({ case (n, i) => - n -> (tile_async_resets(i), r_tile_resets(i).io.q) + n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i * 4) }) (clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) => (o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) => oD.clock := iD.clock oD.reset := iD.reset - for ((n, (rIn, rOut)) <- tileMap) { + for ((n, (rIn, rOut, addr)) <- tileMap) { if (name.contains(n)) { - println(name, n) + println(s"${addr.toString(16)}: Tile $name reset control") // Async because the reset coming out of the AsyncResetRegVec is // clocked to the bus this is attached to, not the clock in this // clock bundle. We expect a ClockGroupResetSynchronizer downstream From f1b17b533bf1a9e30c2b18e4d290e18a625fdf8a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 5 Apr 2023 18:37:35 -0700 Subject: [PATCH 054/184] Add examples of ChipLikeRocketConfig/FlatChipTop/FlatTestHarness --- .../main/scala/clocking/ClockBinders.scala | 11 +- .../src/main/scala/config/ChipConfigs.scala | 44 ++++++ .../src/main/scala/example/FlatChipTop.scala | 143 ++++++++++++++++++ .../main/scala/example/FlatTestHarness.scala | 83 ++++++++++ 4 files changed, 278 insertions(+), 3 deletions(-) create mode 100644 generators/chipyard/src/main/scala/config/ChipConfigs.scala create mode 100644 generators/chipyard/src/main/scala/example/FlatChipTop.scala create mode 100644 generators/chipyard/src/main/scala/example/FlatTestHarness.scala diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 01eb261c..6d0ace69 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -103,9 +103,14 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ // For a real chip you should replace this ClockSourceAtFreqFromPlusArg // with a blackbox of whatever PLL is being integrated - val fakeClockSource = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz")) - fakeClockSource.io.power := pllCtrlSink.in(0)._1.power - fakeClockSource.io.gate := pllCtrlSink.in(0)._1.gate + val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz")) + fake_pll.io.power := pllCtrlSink.in(0)._1.power + fake_pll.io.gate := pllCtrlSink.in(0)._1.gate + + pllClockSource.out.unzip._1.map { o => + o.clock := fake_pll.io.clk + o.reset := reset_wire + } (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) } diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala new file mode 100644 index 00000000..1ed215f6 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -0,0 +1,44 @@ +package chipyard + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.diplomacy._ + +// A simple config demonstrating how to set up a basic chip in Chipyard +class ChipLikeRocketConfig extends Config( + //================================== + // Set up TestHarness + //================================== + new chipyard.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness + // NOTE: This only simulates properly in VCS + + //================================== + // Set up tiles + //================================== + new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add rational crossings between RocketTile and uncore + new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) + + //================================== + // Set up I/O + //================================== + new testchipip.WithSerialTLWidth(4) ++ + new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness + new chipyard.config.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory + + //================================== + // Set up clock./reset + //================================== + new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++ // Use a PLL-based clock selector/divider generator structure + + // Create two clock groups, uncore and fbus, in addition to the tile clock groups + new chipyard.clocking.WithClockGroupsCombinedByName("uncore", "implicit", "sbus", "mbus", "cbus", "system_bus") ++ + new chipyard.clocking.WithClockGroupsCombinedByName("fbus", "fbus", "pbus") ++ + + // Set up the crossings + new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS + new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS + new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS + new testchipip.WithSerialTLAsyncResetQueue ++ // Add Async reset queue to block ready while in reset + + new chipyard.config.AbstractConfig) + diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala new file mode 100644 index 00000000..97ac5032 --- /dev/null +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -0,0 +1,143 @@ +package chipyard.example + + +import chisel3._ +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.prci._ +import freechips.rocketchip.util._ +import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug} +import freechips.rocketchip.tilelink.{TLBuffer} +import chipyard.{BuildSystem, DigitalTop} +import chipyard.clocking._ +import chipyard.iobinders.{IOCellKey, JTAGChipIO} +import barstools.iocell.chisel._ + + +// This "FlatChipTop" uses no IOBinders, so all the IO have +// to be explicitly constructed. +// This only supports the base "DigitalTop" +class FlatChipTop(implicit p: Parameters) extends LazyModule { + override lazy val desiredName = "ChipTop" + val system = LazyModule(p(BuildSystem)(p)).suggestName("system").asInstanceOf[DigitalTop] + + //======================== + // Diplomatic clock stuff + //======================== + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) + system.connectImplicitClockSinkNode(implicitClockSinkNode) + + val tlbus = system.locateTLBusWrapper(system.prciParams.slaveWhere) + val baseAddress = system.prciParams.baseAddress + val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) } + val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } + val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } + + tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() } + tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() } + tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() } + + system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode + + // Connect all other requested clocks + val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) + val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters())) + + // The order of the connections to clockSelector.clockNode configures what + clockSelector.clockNode := slowClockSource + clockSelector.clockNode := pllClockSource + + val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]() + pllCtrlSink := pllCtrl.ctrlNode + + val debugClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters())) + debugClockSinkNode := system.locateTLBusWrapper(p(ExportDebug).slaveWhere).fixedClockNode + def debugClockBundle = debugClockSinkNode.in.head._1 + + override lazy val module = new FlatChipTopImpl + class FlatChipTopImpl extends LazyRawModuleImp(this) { + //========================= + // Clock/reset + //========================= + val implicit_clock = implicitClockSinkNode.in.head._1.clock + val implicit_reset = implicitClockSinkNode.in.head._1.reset + system.module match { case l: LazyModuleImp => { + l.clock := implicit_clock + l.reset := implicit_reset + }} + + val clock_wire = Wire(Input(new ClockWithFreq(80))) + val reset_wire = Wire(Input(AsyncReset())) + val (clock_pad, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) + val (reset_pad, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) + + slowClockSource.out.unzip._1.map { o => + o.clock := clock_wire.clock + o.reset := reset_wire + } + + // For a real chip you should replace this ClockSourceAtFreqFromPlusArg + // with a blackbox of whatever PLL is being integrated + val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz")) + fake_pll.io.power := pllCtrlSink.in(0)._1.power + fake_pll.io.gate := pllCtrlSink.in(0)._1.gate + + pllClockSource.out.unzip._1.map { o => + o.clock := fake_pll.io.clk + o.reset := reset_wire + } + + //========================= + // Custom Boot + //========================= + val (custom_boot_pad, customBootIOCell) = IOCell.generateIOFromSignal(system.custom_boot_pin.get.getWrappedValue, "custom_boot", p(IOCellKey)) + + //========================= + // Serialized TileLink + //========================= + val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey)) + + //========================= + // JTAG/Debug + //========================= + val debug = system.module.debug.get + // We never use the PSDIO, so tie it off on-chip + system.module.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } + system.module.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := false.B } } + + // Tie off extTrigger + debug.extTrigger.foreach { t => + t.in.req := false.B + t.out.ack := t.out.req + } + // Tie off disableDebug + debug.disableDebug.foreach { d => d := false.B } + // Drive JTAG on-chip IOs + debug.systemjtag.map { j => + j.reset := ResetCatchAndSync(j.jtag.TCK, debugClockBundle.reset.asBool) + j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) + j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) + j.version := p(JtagDTMKey).idcodeVersion.U(4.W) + } + + Debug.connectDebugClockAndReset(Some(debug), debugClockBundle.clock) + + // Add IOCells for the DMI/JTAG/APB ports + require(!debug.clockeddmi.isDefined) + require(!debug.apb.isDefined) + val (jtag_pad, jtagIOCells) = debug.systemjtag.map { j => + val jtag_wire = Wire(new JTAGChipIO) + j.jtag.TCK := jtag_wire.TCK + j.jtag.TMS := jtag_wire.TMS + j.jtag.TDI := jtag_wire.TDI + jtag_wire.TDO := j.jtag.TDO.data + IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true) + }.get + + //========================== + // UART + //========================== + require(system.uarts.size == 1) + val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey)) + } +} diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala new file mode 100644 index 00000000..a45a4a3b --- /dev/null +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -0,0 +1,83 @@ +package chipyard.example + +import chisel3._ + +import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} + +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.prci.{ClockSourceAtFreqFromPlusArg, ClockBundle, ClockBundleParameters} +import freechips.rocketchip.util.{PlusArg} +import freechips.rocketchip.subsystem.{CacheBlockBytes} +import freechips.rocketchip.devices.debug.{SimJTAG} +import freechips.rocketchip.jtag.{JTAGIO} +import testchipip.{SerialTLKey, SerialAdapter, UARTAdapter, SimDRAM} +import chipyard.{BuildTop} + +// A "flat" TestHarness that doesn't use IOBinders +// use with caution. +// This example is hard-coded to work only for FlatChipTop, and the ChipLikeRocketConfig +class FlatTestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + // This only works with FlatChipTop + val lazyDut = LazyModule(new FlatChipTop).suggestName("chiptop") + val dut = Module(lazyDut.module) + + // Clock + val clock_source = Module(new ClockSourceAtFreqFromPlusArg("slow_clk_freq_mhz")) + clock_source.io.power := true.B + clock_source.io.gate := false.B + dut.clock_pad.clock := clock_source.io.clk + + // Reset + dut.reset_pad := reset.asAsyncReset + + // Custom boot + dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1) + + // Serialized TL + val sVal = p(SerialTLKey).get + require(sVal.axiMemOverSerialTLParams.isDefined) + require(sVal.isMemoryDevice) + val axiDomainParams = sVal.axiMemOverSerialTLParams.get + val memFreq = axiDomainParams.getMemFrequency(lazyDut.system) + + withClockAndReset(clock, reset) { + val memOverSerialTLClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + memOverSerialTLClockBundle.clock := clock + memOverSerialTLClockBundle.reset := reset + val serial_bits = SerialAdapter.asyncQueue(dut.serial_tl_pad, clock, reset) + val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM( + lazyDut.system.serdesser.get, + serial_bits, + memOverSerialTLClockBundle, + reset) + io.success := SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, clock, reset) + + // connect SimDRAM from the AXI port coming from the harness multi clock axi ram + (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) => + val memSize = sVal.memParams.size + val lineSize = p(CacheBlockBytes) + val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), edge.bundle)).suggestName("simdram") + mem.io.axi <> axi_port.bits + mem.io.clock := axi_port.clock + mem.io.reset := axi_port.reset + } + } + + // JTAG + val jtag_wire = Wire(new JTAGIO) + jtag_wire.TDO.data := dut.jtag_pad.TDO + jtag_wire.TDO.driven := true.B + dut.jtag_pad.TCK := jtag_wire.TCK + dut.jtag_pad.TMS := jtag_wire.TMS + dut.jtag_pad.TDI := jtag_wire.TDI + val dtm_success = WireInit(false.B) + val jtag = Module(new SimJTAG(tickDelay=3)).connect(jtag_wire, clock, reset.asBool, ~(reset.asBool), dtm_success) + + // UART + UARTAdapter.connect(Seq(dut.uart_pad)) +} From 70643335d2cb662104e2ecb3cbaf3b5d62446719 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 5 Apr 2023 19:29:03 -0700 Subject: [PATCH 055/184] Fix RationalRockettiles not getting picked up in MulticlockRocketConfig --- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 01d901aa..8ed4acdc 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -86,6 +86,7 @@ class MbusScratchpadRocketConfig extends Config( // DOC include end: mbusscratchpadrocket class MulticlockRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Frequency specifications new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 @@ -96,7 +97,6 @@ class MulticlockRocketConfig extends Config( // Crossing specifications new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS - new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new chipyard.config.AbstractConfig) From 32f0f8390060e000db2aa8002d5c2e70f76865ec Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 6 Apr 2023 12:53:15 -0700 Subject: [PATCH 056/184] [ci skip] Update comments for FakePLLClockBinder --- .../chipyard/src/main/scala/clocking/ClockBinders.scala | 4 +++- generators/chipyard/src/main/scala/example/FlatChipTop.scala | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 6d0ace69..a0dbe482 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -83,7 +83,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters())) - // The order of the connections to clockSelector.clockNode configures what + // The order of the connections to clockSelector.clockNode configures the inputs + // of the clockSelector's clockMux. Default to using the slowClockSource, + // software should enable the PLL, then switch to the pllClockSource clockSelector.clockNode := slowClockSource clockSelector.clockNode := pllClockSource diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index 97ac5032..9e142bda 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -43,7 +43,9 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters())) - // The order of the connections to clockSelector.clockNode configures what + // The order of the connections to clockSelector.clockNode configures the inputs + // of the clockSelector's clockMux. Default to using the slowClockSource, + // software should enable the PLL, then switch to the pllClockSource clockSelector.clockNode := slowClockSource clockSelector.clockNode := pllClockSource From b7b2a62d80fb7249b4a429f886a3ebd668db329e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 8 Apr 2023 14:53:09 -0700 Subject: [PATCH 057/184] Update clocking stuff to chisel 3.5.6 --- generators/chipyard/src/main/scala/clocking/FakePLL.scala | 2 +- .../chipyard/src/main/scala/clocking/TLClockDivider.scala | 2 +- .../chipyard/src/main/scala/clocking/TLClockSelector.scala | 2 +- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/FakePLL.scala b/generators/chipyard/src/main/scala/clocking/FakePLL.scala index a903ced6..ac8f8b44 100644 --- a/generators/chipyard/src/main/scala/clocking/FakePLL.scala +++ b/generators/chipyard/src/main/scala/clocking/FakePLL.scala @@ -2,7 +2,7 @@ package chipyard.clocking import chisel3._ import chisel3.util._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala index b9d62344..00ad45b2 100644 --- a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala +++ b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala @@ -2,7 +2,7 @@ package chipyard.clocking import chisel3._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ diff --git a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala index 22110e62..988b702e 100644 --- a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala +++ b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala @@ -2,7 +2,7 @@ package chipyard.clocking import chisel3._ import chisel3.util._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 1ed215f6..564e07d8 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy._ // A simple config demonstrating how to set up a basic chip in Chipyard From b88e1025e40d29a2e8528c218d9ef6af1c7fb45e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 8 Apr 2023 14:54:25 -0700 Subject: [PATCH 058/184] Add comments on ResetStretchers --- .../chipyard/src/main/scala/clocking/TLClockDivider.scala | 2 ++ .../chipyard/src/main/scala/clocking/TLClockSelector.scala | 1 + 2 files changed, 3 insertions(+) diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala index 00ad45b2..93a476c6 100644 --- a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala +++ b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala @@ -41,6 +41,8 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit // Note this is not synchronized to the output clock, which takes time to appear // so this is still asyncreset + // Stretch the reset for 40 cycles, to give enough time to reset any downstream + // digital logic sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset reg } diff --git a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala index 988b702e..0893f120 100644 --- a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala +++ b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala @@ -59,6 +59,7 @@ class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) e mux.io.sel := sel mux.io.resetAsync := asyncReset.asAsyncReset sinks(i).clock := mux.io.clockOut + // Stretch the reset for 20 cycles, to give time to reset any downstream digital logic sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset reg From de293f5fdf84cf74dc0bb949d457f4c90aa031f9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 8 Apr 2023 14:56:36 -0700 Subject: [PATCH 059/184] Add build of ChipLikeQuadRocketConfig to CI --- .github/scripts/defaults.sh | 3 ++- generators/chipyard/src/main/scala/HarnessClocks.scala | 2 +- .../chipyard/src/main/scala/config/ChipConfigs.scala | 2 +- .../chipyard/src/main/scala/example/FlatChipTop.scala | 8 ++++---- .../chipyard/src/main/scala/example/FlatTestHarness.scala | 2 +- 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 6013d7d4..13bcf116 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -29,7 +29,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone" -grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals" +grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike" grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -53,6 +53,7 @@ mapping["chipyard-cva6"]=" CONFIG=CVA6Config" mapping["chipyard-ibex"]=" CONFIG=IbexConfig" mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" +mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig verilog" mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog" mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" diff --git a/generators/chipyard/src/main/scala/HarnessClocks.scala b/generators/chipyard/src/main/scala/HarnessClocks.scala index f973c292..4b3ebaa5 100644 --- a/generators/chipyard/src/main/scala/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/HarnessClocks.scala @@ -4,7 +4,7 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Field, Parameters, Config} +import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.util.{ResetCatchAndSync} import freechips.rocketchip.prci._ diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 564e07d8..7f875584 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -4,7 +4,7 @@ import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy._ // A simple config demonstrating how to set up a basic chip in Chipyard -class ChipLikeRocketConfig extends Config( +class ChipLikeQuadRocketConfig extends Config( //================================== // Set up TestHarness //================================== diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index 9e142bda..c10baab4 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -2,7 +2,7 @@ package chipyard.example import chisel3._ -import freechips.rocketchip.config.{Field, Parameters} +import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ @@ -102,10 +102,10 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { //========================= // JTAG/Debug //========================= - val debug = system.module.debug.get + val debug = system.debug.get // We never use the PSDIO, so tie it off on-chip - system.module.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } - system.module.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := false.B } } + system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } + system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := false.B } } // Tie off extTrigger debug.extTrigger.foreach { t => diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index a45a4a3b..3954931e 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -4,7 +4,7 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} -import freechips.rocketchip.config.{Field, Parameters} +import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.prci.{ClockSourceAtFreqFromPlusArg, ClockBundle, ClockBundleParameters} import freechips.rocketchip.util.{PlusArg} From 0ffc3c77708d1218f065bf23e152775f68957b50 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 8 Apr 2023 17:19:25 -0700 Subject: [PATCH 060/184] Add some comments on harness/chiptop clocking APIs --- .../chipyard/src/main/scala/HarnessClocks.scala | 11 +++++++++++ .../src/main/scala/clocking/ClockBinders.scala | 7 +++++++ .../src/main/scala/clocking/TLClockDivider.scala | 2 ++ .../src/main/scala/clocking/TLClockSelector.scala | 2 ++ 4 files changed, 22 insertions(+) diff --git a/generators/chipyard/src/main/scala/HarnessClocks.scala b/generators/chipyard/src/main/scala/HarnessClocks.scala index 4b3ebaa5..c256caba 100644 --- a/generators/chipyard/src/main/scala/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/HarnessClocks.scala @@ -13,6 +13,9 @@ import chipyard.iobinders.HasIOBinders import chipyard.clocking.{SimplePllConfiguration, ClockDividerN} import chipyard.HarnessClockInstantiatorKey + +// HarnessClockInstantiators are classes which generate clocks that drive +// TestHarness simulation models and any Clock inputs to the ChipTop trait HarnessClockInstantiator { val _clockMap: LinkedHashMap[String, (Double, ClockBundle)] = LinkedHashMap.empty @@ -23,9 +26,13 @@ trait HarnessClockInstantiator { clockBundle } + // refClock is the clock generated by TestDriver that is + // passed to the TestHarness as its implicit clock def instantiateHarnessClocks(refClock: ClockBundle): Unit } +// The DividerOnlyHarnessClockInstantiator uses synthesizable clock divisors +// to approximate frequency ratios between the requested clocks class DividerOnlyHarnessClockInstantiator extends HarnessClockInstantiator { // connect all clock wires specified to a divider only PLL def instantiateHarnessClocks(refClock: ClockBundle): Unit = { @@ -62,6 +69,10 @@ class DividerOnlyHarnessClockInstantiator extends HarnessClockInstantiator { } } +// The AbsoluteFreqHarnessClockInstantiator uses a Verilog blackbox to +// provide the precise requested frequency. +// This ClockInstantiator cannot be synthesized, run in Verilator, or run in FireSim +// It is useful for VCS/Xcelium-driven RTL simulations class AbsoluteFreqHarnessClockInstantiator extends HarnessClockInstantiator { def instantiateHarnessClocks(refClock: ClockBundle): Unit = { val sinks = _clockMap.map({ case (name, (freq, bundle)) => diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index a0dbe482..5a02277c 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -13,6 +13,9 @@ class ClockWithFreq(val freqMHz: Double) extends Bundle { val clock = Clock() } +// This uses synthesizable clock divisors to approximate frequency rations +// between the requested clocks. This is currently the defualt clock generator "model", +// as it can be used in VCS/Xcelium/Verilator/FireSim class WithDividerOnlyClockGenerator extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { // Connect the implicit clock @@ -52,6 +55,10 @@ class WithDividerOnlyClockGenerator extends OverrideLazyIOBinder({ } }) +// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate +// the requested clocks. This also adds TileLink ClockDivider and ClockSelector +// blocks, which allow memory-mapped control of clock division, and clock muxing +// between the FakePLL and the slow off-chip clock // Note: This will not simulate properly with verilator or firesim class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala index 93a476c6..bc722799 100644 --- a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala +++ b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala @@ -13,6 +13,8 @@ import freechips.rocketchip.util.ElaborationArtefacts import testchipip._ +// This module adds a TileLink memory-mapped clock divider to the clock graph +// The output clock/reset pairs from this module should be synchronized later class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice(s"clk-div-ctrl", Nil) val clockNode = ClockGroupIdentityNode() diff --git a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala index 0893f120..06821ead 100644 --- a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala +++ b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala @@ -36,6 +36,8 @@ case class ClockSelNode()(implicit valName: ValName) uFn = { u => ClockSinkParameters() } ) +// This module adds a TileLink memory-mapped clock mux for each downstream clock domain +// in the clock graph. The output clock/reset should be synchronized downstream class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("clk-sel-ctrl", Nil) val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) From 4b620f117c4a1b351291f060132c834363dcfc22 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Sun, 9 Apr 2023 19:36:56 -0700 Subject: [PATCH 061/184] bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index ee47d2ea..fbfbb713 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ee47d2ea205c7525b21333d3caf835fcd963fa42 +Subproject commit fbfbb71319840f212c1958d82bfce57c11de223e From 1f5e75c7550fed1c28f277d6d68f808102c94ee9 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Sun, 9 Apr 2023 20:14:55 -0700 Subject: [PATCH 062/184] re-bump --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index fbfbb713..59830d7a 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit fbfbb71319840f212c1958d82bfce57c11de223e +Subproject commit 59830d7a5805099f39d33a99804c5b77e697493e From b36909d2f49e78e9ae55e4a48424c0eece623c39 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Mon, 10 Apr 2023 09:37:31 -0700 Subject: [PATCH 063/184] re-bump --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 59830d7a..aa9170af 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 59830d7a5805099f39d33a99804c5b77e697493e +Subproject commit aa9170afe133e74e1c66b0082dc943e272d9e6f0 From 4adb8d91c1382c58865e413a5a358703a7e95a8a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 11 Apr 2023 17:44:24 -0700 Subject: [PATCH 064/184] Fix ChipLikeQuadRocketConfig crossing There needs to be a crossing between sbus/fbus when they are on separate clock domains --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 7f875584..fa08acf7 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -35,6 +35,7 @@ class ChipLikeQuadRocketConfig extends Config( new chipyard.clocking.WithClockGroupsCombinedByName("fbus", "fbus", "pbus") ++ // Set up the crossings + new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between SBUS and FBUS new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS From 344e29a240628e866ce24e81dc29c0ea0887d719 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 11:59:57 -0700 Subject: [PATCH 065/184] Switch ChipLikequadRocketConfig to use the FlatTestHarness in CI --- .github/scripts/defaults.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 13bcf116..83117317 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -53,7 +53,7 @@ mapping["chipyard-cva6"]=" CONFIG=CVA6Config" mapping["chipyard-ibex"]=" CONFIG=IbexConfig" mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" -mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig verilog" +mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog" mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog" mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" From 6a97f2eb972d04385cc7390e2de38f6b8cb4e256 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 10 Apr 2023 15:42:10 -0700 Subject: [PATCH 066/184] Support dmi-based Spike bringup --- .../src/main/resources/csrc/spiketile.cc | 43 ++++++++++++++++--- .../csrc/spiketile_dtm/spiketile_htif_mode.h | 1 + .../csrc/spiketile_tsi/spiketile_htif_mode.h | 1 + .../src/main/scala/HarnessBinders.scala | 5 ++- .../chipyard/src/main/scala/SpikeTile.scala | 19 ++++++-- .../src/main/scala/config/SpikeConfigs.scala | 7 +++ generators/testchipip | 2 +- 7 files changed, 65 insertions(+), 13 deletions(-) create mode 100644 generators/chipyard/src/main/resources/csrc/spiketile_dtm/spiketile_htif_mode.h create mode 100644 generators/chipyard/src/main/resources/csrc/spiketile_tsi/spiketile_htif_mode.h diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index f59e825a..743969e3 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -2,13 +2,20 @@ #include #include #include +#include #include #include #include #include -#include "testchip_tsi.h" +#include "spiketile_htif_mode.h" -extern testchip_tsi_t* tsi; +#if defined(SPIKETILE_HTIF_TSI) +extern htif_t* tsi; +#elif defined(SPIKETILE_HTIF_DTM) +extern htif_t* dtm; +#else +#error "SpikeTile must be used with the TSI or DTM-based HTIF bringup" +#endif enum transfer_t { NToB, @@ -84,6 +91,7 @@ public: void drain_stq(); bool stq_empty() { return st_q.size() == 0; }; + void flush_icache(); const cfg_t &get_cfg() const { return cfg; } const std::map& get_harts() const { return harts; } @@ -334,14 +342,21 @@ extern "C" void spike_tile(int hartid, char* isa, tile_t* tile = tiles[hartid]; chipyard_simif_t* simif = tile->simif; processor_t* proc = tile->proc; - if (!simif->htif && tsi) { - simif->htif = (htif_t*) tsi; - } +#if defined(SPIKETILE_HTIF_TSI) + if (!simif->htif && tsi) + simif->htif = tsi; +#elif defined(SPIKETILE_HTIF_DTM) + if (!simif->htif && dtm) + simif->htif = dtm; +#endif simif->cycle = cycle; if (debug) { proc->halt_request = proc->HR_REGULAR; } + if (!debug && proc->halt_request != proc->HR_NONE) { + proc->halt_request = proc->HR_NONE; + } proc->get_state()->mip->backdoor_write_with_mask(MIP_MTIP, mtip ? MIP_MTIP : 0); proc->get_state()->mip->backdoor_write_with_mask(MIP_MSIP, msip ? MIP_MSIP : 0); @@ -504,6 +519,12 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, tcm = (uint8_t*)malloc(tcm_size); } +void chipyard_simif_t::flush_icache() { + for (auto &w : icache) { + for (size_t i = 0; i < icache_sets; i++) w[i].state = NONE; + } +} + bool chipyard_simif_t::reservable(reg_t addr) { for (auto& r: cacheables) { if (addr >= r.base && addr < r.base + r.size) { @@ -605,6 +626,7 @@ void chipyard_simif_t::handle_mmio_access(reg_t addr, size_t len, mmio_st = type == STORE; if (type == STORE) { assert(len <= 8); + mmio_stdata = 0; memcpy(&mmio_stdata, store_bytes, len); } mmio_len = len; @@ -1075,7 +1097,16 @@ void spike_thread_main(void* arg) tile->max_insns = 0; } } - if (tile->max_insns % 100 == 0) { + if (state->debug_mode) { + // TODO: Fix. This needs to apply the same hack as rocket-chip... + // JALRs in debug mode should flush the ICache. + // There is no API to determine if a JALR was executed, so hack the + // pc of the JALR in the debug rom here instead. + if (state->pc == 0x838) { + simif->flush_icache(); + } + } + if (tile->max_insns % 101 == 0) { // 101 to avoid harmonics with small loops uint64_t old_minstret = state->minstret->read(); uint64_t tohost_addr = simif->htif ? simif->htif->get_tohost_addr() : 0; uint64_t fromhost_addr = simif->htif ? simif->htif->get_fromhost_addr() : 0; diff --git a/generators/chipyard/src/main/resources/csrc/spiketile_dtm/spiketile_htif_mode.h b/generators/chipyard/src/main/resources/csrc/spiketile_dtm/spiketile_htif_mode.h new file mode 100644 index 00000000..5c1c3041 --- /dev/null +++ b/generators/chipyard/src/main/resources/csrc/spiketile_dtm/spiketile_htif_mode.h @@ -0,0 +1 @@ +#define SPIKETILE_HTIF_DTM diff --git a/generators/chipyard/src/main/resources/csrc/spiketile_tsi/spiketile_htif_mode.h b/generators/chipyard/src/main/resources/csrc/spiketile_tsi/spiketile_htif_mode.h new file mode 100644 index 00000000..240e6186 --- /dev/null +++ b/generators/chipyard/src/main/resources/csrc/spiketile_tsi/spiketile_htif_mode.h @@ -0,0 +1 @@ +#define SPIKETILE_HTIF_TSI diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index c39242f9..fde36278 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -252,7 +252,7 @@ class WithSimDebug extends OverrideHarnessBinder({ case d: ClockedDMIIO => val dtm_success = WireInit(false.B) when (dtm_success) { th.success := true.B } - val dtm = Module(new SimDTM).connect(th.buildtopClock, th.buildtopReset.asBool, d, dtm_success) + val dtm = Module(new TestchipSimDTM).connect(th.buildtopClock, th.buildtopReset.asBool, d, dtm_success) case j: JTAGChipIO => val dtm_success = WireInit(false.B) when (dtm_success) { th.success := true.B } @@ -262,7 +262,8 @@ class WithSimDebug extends OverrideHarnessBinder({ j.TCK := jtag_wire.TCK j.TMS := jtag_wire.TMS j.TDI := jtag_wire.TDI - val jtag = Module(new SimJTAG(tickDelay=3)).connect(jtag_wire, th.buildtopClock, th.buildtopReset.asBool, ~(th.buildtopReset.asBool), dtm_success) + val jtag = Module(new SimJTAG(tickDelay=3)) + jtag.connect(jtag_wire, th.buildtopClock, th.buildtopReset.asBool, ~(th.buildtopReset.asBool), dtm_success) } } }) diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index 9aac7421..66d18e7a 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -7,6 +7,7 @@ import chisel3.experimental.{IntParam, StringParam, IO} import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{ExportDebug, DMI} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tilelink._ @@ -189,7 +190,8 @@ class SpikeBlackBox( readonly_uncacheable_regions: String, executable_regions: String, tcm_base: BigInt, - tcm_size: BigInt) extends BlackBox(Map( + tcm_size: BigInt, + use_dtm: Boolean) extends BlackBox(Map( "HARTID" -> IntParam(hartId), "ISA" -> StringParam(isa), "PMPREGIONS" -> IntParam(pmpregions), @@ -302,7 +304,11 @@ class SpikeBlackBox( }) addResource("/vsrc/spiketile.v") addResource("/csrc/spiketile.cc") - + if (use_dtm) { + addResource("/csrc/spiketile_dtm/spiketile_htif_mode.h") + } else { + addResource("/csrc/spiketile_tsi/spiketile_htif_mode.h") + } } class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { @@ -326,13 +332,18 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { val (dcache_tl, dcacheEdge) = outer.dcacheNode.out(0) val (mmio_tl, mmioEdge) = outer.mmioNode.out(0) + // Note: This assumes that if the debug module exposes the ClockedDMI port, + // then the DTM-based bringup with SimDTM will be used. This isn't required to be + // true, but it usually is + val useDTM = p(ExportDebug).protocols.contains(DMI) val spike = Module(new SpikeBlackBox(hartId, isaDTS, tileParams.core.nPMPs, tileParams.icache.get.nSets, tileParams.icache.get.nWays, tileParams.dcache.get.nSets, tileParams.dcache.get.nWays, tileParams.dcache.get.nMSHRs, cacheable_regions, uncacheable_regions, readonly_uncacheable_regions, executable_regions, outer.spikeTileParams.tcmParams.map(_.base).getOrElse(0), - outer.spikeTileParams.tcmParams.map(_.size).getOrElse(0) + outer.spikeTileParams.tcmParams.map(_.size).getOrElse(0), + useDTM )) spike.io.clock := clock.asBool val cycle = RegInit(0.U(64.W)) @@ -421,7 +432,7 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { spike.io.mmio.a.ready := mmio_tl.a.ready mmio_tl.a.valid := spike.io.mmio.a.valid - val log_size = MuxCase(0.U, (0 until 3).map { i => (spike.io.mmio.a.size === (1 << i).U) -> i.U }) + val log_size = (0 until 4).map { i => Mux(spike.io.mmio.a.size === (1 << i).U, i.U, 0.U) }.reduce(_|_) mmio_tl.a.bits := Mux(spike.io.mmio.a.store, mmioEdge.Put(0.U, spike.io.mmio.a.address, log_size, spike.io.mmio.a.data)._2, mmioEdge.Get(0.U, spike.io.mmio.a.address, log_size)._2) diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index cb82360e..b9cd8a96 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -10,6 +10,13 @@ class SpikeConfig extends Config( new chipyard.WithNSpikeCores(1) ++ new chipyard.config.AbstractConfig) +class dmiSpikeConfig extends Config( + new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new chipyard.WithNSpikeCores(1) ++ + new chipyard.config.AbstractConfig) + + // Avoids polling on the UART registers class SpikeFastUARTConfig extends Config( new chipyard.WithNSpikeCores(1) ++ diff --git a/generators/testchipip b/generators/testchipip index ee47d2ea..da5bf77b 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ee47d2ea205c7525b21333d3caf835fcd963fa42 +Subproject commit da5bf77b6eb670001d9234dbfd996b2e7c3ad1ff From e51b3e8c613a4ccb9278c6222f202c46b588b615 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 01:36:40 -0700 Subject: [PATCH 067/184] Fix SpikeTile TCM with loadmem-by-elf --- .../src/main/resources/csrc/spiketile.cc | 89 ++++++++++--------- 1 file changed, 49 insertions(+), 40 deletions(-) diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index 743969e3..c1dea45c 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -3,6 +3,8 @@ #include #include #include +#include +#include #include #include #include @@ -87,7 +89,7 @@ public: void tcm_a(uint64_t address, uint64_t data, uint32_t mask, uint32_t opcode, uint32_t size); bool tcm_d(uint64_t *data); - void loadmem(const char* fname); + void loadmem(size_t base, const char* fname); void drain_stq(); bool stq_empty() { return st_q.size() == 0; }; @@ -117,6 +119,7 @@ public: bool fast_clint; cfg_t cfg; std::map harts; + bool accessed_tofrom_host; private: bool handle_cache_access(reg_t addr, size_t len, uint8_t* load_bytes, @@ -332,7 +335,7 @@ extern "C" void spike_tile(int hartid, char* isa, } } if (loadmem_file != "" && tcm_size > 0) - simif->loadmem(loadmem_file.c_str()); + simif->loadmem(tcm_base, loadmem_file.c_str()); p->reset(); p->get_state()->pc = reset_vector; @@ -365,6 +368,7 @@ extern "C" void spike_tile(int hartid, char* isa, tile->max_insns = ipc; uint64_t pre_insns = proc->get_state()->minstret->read(); + simif->accessed_tofrom_host = false; tile->spike_context.switch_to(); *insns_retired = proc->get_state()->minstret->read() - pre_insns; if (simif->use_stq) { @@ -454,6 +458,7 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, std::vector(), false, 0), + accessed_tofrom_host(false), icache_ways(icache_ways), icache_sets(icache_sets), dcache_ways(dcache_ways), @@ -565,6 +570,12 @@ bool chipyard_simif_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) { bool found = false; bool cacheable = false; bool readonly = false; + reg_t tohost_addr = htif ? htif->get_tohost_addr() : 0; + reg_t fromhost_addr = htif ? htif->get_fromhost_addr() : 0; + if (addr == tohost_addr || addr == fromhost_addr) { + accessed_tofrom_host = true; + } + if (addr >= tcm_base && addr < tcm_base + tcm_size) { memcpy(bytes, tcm + addr - tcm_base, len); return true; @@ -600,6 +611,8 @@ bool chipyard_simif_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) { while (!handle_cache_access(addr, len, bytes, nullptr, LOAD)) { host->switch_to(); } + uint64_t lddata = 0; + memcpy(&lddata, bytes, len); } else { handle_mmio_access(addr, len, bytes, nullptr, LOAD, readonly); } @@ -933,6 +946,13 @@ bool chipyard_simif_t::dcache_c(uint64_t* address, uint64_t* source, int* param, } bool chipyard_simif_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) { + reg_t tohost_addr = htif ? htif->get_tohost_addr() : 0; + reg_t fromhost_addr = htif ? htif->get_fromhost_addr() : 0; + + if (addr == tohost_addr || addr == fromhost_addr) { + accessed_tofrom_host = true; + } + if (addr >= tcm_base && addr < tcm_base + tcm_size) { memcpy(tcm + addr - tcm_base, bytes, len); return true; @@ -958,6 +978,8 @@ bool chipyard_simif_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) return false; } if (cacheable) { + uint64_t temp = 0; + memcpy(&temp, bytes, len); if (use_stq) { assert(len <= 8); uint64_t stdata; @@ -1031,30 +1053,28 @@ bool chipyard_simif_t::tcm_d(uint64_t* data) { return true; } -#define parse_nibble(c) ((c) >= 'a' ? (c)-'a'+10 : (c)-'0') -void chipyard_simif_t::loadmem(const char* fname) { - std::ifstream in(fname); - std::string line; - if (!in.is_open()) { - printf("SpikeTile couldn't open loadmem file %s\n", fname); - abort(); - } - size_t fsize = 0; - size_t start = 0; - while (std::getline(in, line)) { - for (ssize_t i = line.length()-2, j = 0; i >= 0; i -= 2, j++) { - char byte = (parse_nibble(line[i]) << 4) | parse_nibble(line[i+1]); - ssize_t addr = (start + j) % tcm_size; - tcm[addr] = (uint8_t)byte; +void chipyard_simif_t::loadmem(size_t base, const char* fname) { + class loadmem_memif_t : public memif_t { + public: + loadmem_memif_t(chipyard_simif_t* _simif, size_t _start) : memif_t(nullptr), simif(_simif), start(_start) {} + void write(addr_t taddr, size_t len, const void* src) override + { + addr_t addr = taddr - start; + memcpy(simif->tcm + addr, src, len); } - start += line.length()/2; - fsize += line.length()/2; + void read(addr_t taddr, size_t len, void* bytes) override { + assert(false); + } + endianness_t get_target_endianness() const override { + return endianness_little; + } + private: + chipyard_simif_t* simif; + size_t start; + } loadmem_memif(this, tcm_base); - if (fsize > tcm_size) { - fprintf(stderr, "Loadmem file is too large\n"); - abort(); - } - } + reg_t entry; + load_elf(fname, &loadmem_memif, &entry); } bool insn_should_fence(uint64_t bits) { @@ -1082,18 +1102,14 @@ void spike_thread_main(void* arg) // if (insn_should_fence(last_bits) && !simif->stq_empty()) { // host->switch_to(); // } + uint64_t old_minstret = state->minstret->read(); proc->step(1); tile->max_insns--; if (proc->is_waiting_for_interrupt()) { if (simif->fast_clint) { - // uint64_t mip = state->mip->read(); - // uint64_t mie = state->mie->read(); - //printf("Setting MTIP %x %x %x %x %lx\n", simif->cycle, old_minstret, mip, mie, - // state->pc); state->mip->backdoor_write_with_mask(MIP_MTIP, MIP_MTIP); tile->max_insns = tile->max_insns <= 1 ? 0 : 1; } else { - //printf("SpikeTile in WFI\n"); tile->max_insns = 0; } } @@ -1106,17 +1122,10 @@ void spike_thread_main(void* arg) simif->flush_icache(); } } - if (tile->max_insns % 101 == 0) { // 101 to avoid harmonics with small loops - uint64_t old_minstret = state->minstret->read(); - uint64_t tohost_addr = simif->htif ? simif->htif->get_tohost_addr() : 0; - uint64_t fromhost_addr = simif->htif ? simif->htif->get_fromhost_addr() : 0; - auto& mem_read = state->log_mem_read; - reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]); - if ((old_minstret == state->minstret->read()) || - (tohost_addr && mem_read_addr == tohost_addr) || - (fromhost_addr && mem_read_addr == fromhost_addr)) { - tile->max_insns == 0; - } + + // If we get stuck in WFI, or we start polling tohost/fromhost, switch to host thread + if ((old_minstret == state->minstret->read()) || simif->accessed_tofrom_host) { + tile->max_insns = 0; } state->mcycle->write(simif->cycle); } From f5ceab2077c079aeca91678272427514d5315f68 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 01:37:05 -0700 Subject: [PATCH 068/184] Pass base of memory to SimDRAM --- generators/chipyard/src/main/scala/HarnessBinders.scala | 7 +++++-- .../chipyard/src/main/scala/example/FlatTestHarness.scala | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index fde36278..85ba3d5f 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -168,8 +168,9 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({ // connect SimDRAM from the AXI port coming from the harness multi clock axi ram (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) => val memSize = sVal.memParams.size + val memBase = sVal.memParams.base val lineSize = p(CacheBlockBytes) - val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), edge.bundle)).suggestName("simdram") + val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram") mem.io.axi <> axi_port.bits mem.io.clock := axi_port.clock mem.io.reset := axi_port.reset @@ -184,10 +185,12 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBind (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => + // TODO FIX: This currently makes each SimDRAM contian the entire memory space val memSize = p(ExtMem).get.master.size + val memBase = p(ExtMem).get.master.base val lineSize = p(CacheBlockBytes) val clockFreq = p(MemoryBusKey).dtsFrequency.get - val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, edge.bundle)).suggestName("simdram") + val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, edge.bundle)).suggestName("simdram") mem.io.axi <> port.bits // Bug in Chisel implementation. See https://github.com/chipsalliance/chisel3/pull/1781 def Decoupled[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 3954931e..c428a5e9 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -60,8 +60,9 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { // connect SimDRAM from the AXI port coming from the harness multi clock axi ram (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) => val memSize = sVal.memParams.size + val memBase = sVal.memParams.base val lineSize = p(CacheBlockBytes) - val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), edge.bundle)).suggestName("simdram") + val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram") mem.io.axi <> axi_port.bits mem.io.clock := axi_port.clock mem.io.reset := axi_port.reset From 3771e62a2089cccfc5d75f001aea19f4acb78152 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 01:37:29 -0700 Subject: [PATCH 069/184] Default to 2 memory channels in AbstractConfig --- generators/chipyard/src/main/scala/config/AbstractConfig.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index e270c978..5611dad5 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -56,6 +56,7 @@ class AbstractConfig extends Config( new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus + new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ // Default 2 memory channels new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) From 02a10f358b840ad21c2fffde241743b5d2fddb31 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 01:37:47 -0700 Subject: [PATCH 070/184] Add dmiUltraFastSpikeConfig --- .../chipyard/src/main/scala/config/SpikeConfigs.scala | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index b9cd8a96..34413b36 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -13,9 +13,7 @@ class SpikeConfig extends Config( class dmiSpikeConfig extends Config( new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port - new chipyard.WithNSpikeCores(1) ++ - new chipyard.config.AbstractConfig) - + new SpikeConfig) // Avoids polling on the UART registers class SpikeFastUARTConfig extends Config( @@ -36,6 +34,11 @@ class SpikeUltraFastConfig extends Config( new chipyard.config.WithBroadcastManager ++ new chipyard.config.AbstractConfig) +class dmiSpikeUltraFastConfig extends Config( + new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new SpikeUltraFastConfig) + // Add the default firechip devices class SpikeUltraFastDevicesConfig extends Config( new chipyard.harness.WithSimBlockDevice ++ From 4ae38e22d621cd10030757a906ce635333412766 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 01:38:38 -0700 Subject: [PATCH 071/184] Bump riscv-isa-sim for fesvr/dtm fixes --- toolchains/riscv-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index d70ea67d..7470633c 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit d70ea67df7e85a8d92a8baa254afde67c33c43a9 +Subproject commit 7470633c425c2385685f369a8ca9f2c3a629f494 From b3a4c82fd2291d9e7d2702c4720e93cf2b2b86ae Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 01:39:12 -0700 Subject: [PATCH 072/184] Add generate-ckpt script --- scripts/generate-ckpt.sh | 107 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100755 scripts/generate-ckpt.sh diff --git a/scripts/generate-ckpt.sh b/scripts/generate-ckpt.sh new file mode 100755 index 00000000..f4987a24 --- /dev/null +++ b/scripts/generate-ckpt.sh @@ -0,0 +1,107 @@ +#!/bin/bash + +set -ex + +usage() { + echo "Usage: $0 [OPTIONS] -- [SPIKEFLAGS]" + echo "" + echo "Options" + echo " --help -h : Display this message" + echo " -n : Mumber of harts" + echo " -b : Binary to run in spike" + echo " -p : PC to take checkpoint at [default 0x80000000]" + echo " -c : Cycles after PC to take checkpoint at [default 0]" + exit "$1" +} + +NHARTS=1 +BINARY="" +PC="0x80000000" +CYCLES=0 +while [ "$1" != "" ]; +do + case $1 in + -h | --help ) + usage 3 ;; + -n ) + shift + NHARTS=$1 ;; + -b ) + shift + BINARY=$1 ;; + -p ) + shift + PC=$1 ;; + -c ) + shift + CYCLES=$1 ;; + * ) + error "Invalid option $1" + usage 1 ;; + esac + shift +done +BASEMEM="$((0x80000000)):$((0x10000000))" +SPIKEFLAGS="-p$NHARTS --pmpregions=0 --isa=rv64gc -m$BASEMEM" + +rm -rf cmds_tmp.txt +touch cmds_tmp.txt + +echo "Generating state capture spike interactive commands in cmds_tmp.txt" +echo "until pc 0 $PC" >> cmds_tmp.txt +echo "rs $CYCLES" >> cmds_tmp.txt +echo "dump" >> cmds_tmp.txt +for (( h=0; h<$NHARTS; h++ )) +do + echo "pc $h" >> cmds_tmp.txt + echo "priv $h" >> cmds_tmp.txt + echo "reg $h fcsr" >> cmds_tmp.txt + + echo "reg $h stvec" >> cmds_tmp.txt + echo "reg $h sscratch" >> cmds_tmp.txt + echo "reg $h sepc" >> cmds_tmp.txt + echo "reg $h scause" >> cmds_tmp.txt + echo "reg $h stval" >> cmds_tmp.txt + echo "reg $h satp" >> cmds_tmp.txt + + echo "reg $h mstatus" >> cmds_tmp.txt + echo "reg $h medeleg" >> cmds_tmp.txt + echo "reg $h mideleg" >> cmds_tmp.txt + echo "reg $h mie" >> cmds_tmp.txt + echo "reg $h mtvec" >> cmds_tmp.txt + echo "reg $h mscratch" >> cmds_tmp.txt + echo "reg $h mepc" >> cmds_tmp.txt + echo "reg $h mcause" >> cmds_tmp.txt + echo "reg $h mtval" >> cmds_tmp.txt + echo "reg $h mip" >> cmds_tmp.txt + + echo "reg $h mcycle" >> cmds_tmp.txt + echo "reg $h minstret" >> cmds_tmp.txt + + echo "mtime" >> cmds_tmp.txt + echo "mtimecmp $h" >> cmds_tmp.txt + + for (( fr=0; fr<32; fr++ )) + do + echo "freg $h $fr" >> cmds_tmp.txt + done + for (( xr=0; xr<32; xr++ )) + do + echo "reg $h $xr" >> cmds_tmp.txt + done +done +echo "quit" >> cmds_tmp.txt + +#cat cmds_tmp.txt +BASENAME=$(basename -- $BINARY) + +echo "Capturing state at checkpoint to spikeout" +spike -d --debug-cmd=cmds_tmp.txt $SPIKEFLAGS $BINARY 2> $BASENAME.loadarch + +echo "Finding tohost/fromhost in elf file" +TOHOST=$(riscv64-unknown-elf-nm $BINARY | grep tohost | head -c 16) +FROMHOST=$(riscv64-unknown-elf-nm $BINARY | grep fromhost | head -c 16) + +echo "Compiling memory to elf" +riscv64-unknown-elf-objcopy -I binary -O elf64-littleriscv mem.0x80000000.bin $BASENAME.mem.elf +riscv64-unknown-elf-ld -Tdata=0x80000000 -nmagic --defsym tohost=0x$TOHOST --defsym fromhost=0x$FROMHOST -o $BASENAME.loadarch.elf $BASENAME.mem.elf From f28d114f123ac175efdb2b7c098d40e15b8a859b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 01:55:37 -0700 Subject: [PATCH 073/184] Switch to loadmem-by-elf instead of loadmem-by-hex --- common.mk | 38 +++++++++------------ docs/Simulation/Software-RTL-Simulation.rst | 16 +++------ docs/Software/Spike.rst | 2 +- scripts/smartelf2hex.sh | 16 --------- variables.mk | 6 ---- 5 files changed, 22 insertions(+), 56 deletions(-) delete mode 100755 scripts/smartelf2hex.sh diff --git a/common.mk b/common.mk index a4668075..9ba6850e 100644 --- a/common.mk +++ b/common.mk @@ -318,29 +318,25 @@ run-binary-debug: $(SIM_DEBUG_PREREQ) check-binary | $(output_dir) run-fast: run-asm-tests-fast run-bmark-tests-fast ######################################################################################### -# helper rules to run simulator with fast loadmem via hex files +# helper rules to run simulator with fast loadmem ######################################################################################### -$(binary_hex): $(firstword $(BINARY)) | $(output_dir) - $(base_dir)/scripts/smartelf2hex.sh $(firstword $(BINARY)) > $(binary_hex) +run-binary-loadmem: check-binary +run-binary-loadmem: $(SIM_PREREQ) | $(output_dir) +run-binary-loadmem: run-binary +run-binary-loadmem: override SIM_FLAGS += +loadmem=$(BINARY) +run-binary-debug-loadmem: check-binary +run-binary-debug-loadmem: $(SIM_DEBUG_REREQ) | $(output_dir) +run-binary-debug-loadmem: run-binary-debug +run-binary-debug-loadmem: override SIM_FLAGS += +loadmem=$(BINARY) +run-binary-fast-loadmem: check-binary +run-binary-fast-loadmem: $(SIM_PREREQ) | $(output_dir) +run-binary-fast-loadmem: run-binary-fast +run-binary-fast-loadmem: override SIM_FLAGS += +loadmem=$(BINARY) -run-binary-hex: check-binary -run-binary-hex: $(SIM_PREREQ) $(binary_hex) | $(output_dir) -run-binary-hex: run-binary -run-binary-hex: override LOADMEM_ADDR = 80000000 -run-binary-hex: override LOADMEM = $(binary_hex) -run-binary-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) -run-binary-debug-hex: check-binary -run-binary-debug-hex: $(SIM_DEBUG_REREQ) $(binary_hex) | $(output_dir) -run-binary-debug-hex: run-binary-debug -run-binary-debug-hex: override LOADMEM_ADDR = 80000000 -run-binary-debug-hex: override LOADMEM = $(binary_hex) -run-binary-debug-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) -run-binary-fast-hex: check-binary -run-binary-fast-hex: $(SIM_PREREQ) $(binary_hex) | $(output_dir) -run-binary-fast-hex: run-binary-fast -run-binary-fast-hex: override LOADMEM_ADDR = 80000000 -run-binary-fast-hex: override LOADMEM = $(binary_hex) -run-binary-fast-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) +# Legacy targets for backwards compat +run-binary-hex: run-binary-loadmem +run-binary-debug-hex: run-binary-debug-loadmem +run-binary-fast-hex: run-binary-fast-loadmem ######################################################################################### # run assembly/benchmarks rules diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index d62f6f1c..ccbef67c 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -151,25 +151,17 @@ Fast Memory Loading ------------------- The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model. +Loadmem files should be ELF files. In the most common use case, this can be the binary. .. code-block:: shell - make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000 + make run-binary BINARY=test.riscv EXTRA_SIM_FLAGS="+loadmem=test.riscv" -The ``.hex`` file should be a text file with a hexadecimal number on each line. - -.. code-block:: text - - deadbeef - 0123 - -Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. - -A special target that facilitates automatically generating a hex file for an entire elf RISC-V exectuable and then running the simulator with the appropriate flags is also available. +For convenience, special ``-loadmem`` targets are provided to automatically rely on loadmem to read in the binary. .. code-block:: shell - make run-binary-hex BINARY=test.riscv + make run-binary-loadmem BINARY=test.riscv Generating Waveforms ----------------------- diff --git a/docs/Software/Spike.rst b/docs/Software/Spike.rst index 79e41d6e..48487851 100644 --- a/docs/Software/Spike.rst +++ b/docs/Software/Spike.rst @@ -43,7 +43,7 @@ Spike-as-a-Tile can be configured with custom IPC, commit logging, and other beh .. code-block:: shell - make CONFIG=SpikeUltraFastConfig run-binary-hex BINARY=hello.riscv EXTRA_SPIKE_FLAGS="+spike-ipc=10000 +spike-fast-clint +spike-debug" + make CONFIG=SpikeUltraFastConfig run-binary-loadmem BINARY=hello.riscv EXTRA_SPIKE_FLAGS="+spike-ipc=10000 +spike-fast-clint +spike-debug" * ``+spike-ipc=``: Sets the maximum number of instructions Spike can retire in a single "tick", or cycle of the uncore simulation. diff --git a/scripts/smartelf2hex.sh b/scripts/smartelf2hex.sh deleted file mode 100755 index cc2ea2f8..00000000 --- a/scripts/smartelf2hex.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env bash - -# This script find the appropriate arguments to pass to elf2hex by inspecting the given RISC-V elf binary -# First and only argument is the binary to be converted. -# The output of this script should be redirected to a file (as with normal elf2hex). - -binary=$1 -segments=`readelf --segments --wide $binary` -entry_hex=`echo -e "$segments" | grep "Entry point" | cut -f3 -d' ' | sed 's/0x//' | tr [:lower:] [:upper:]` -entry_dec=`bc <<< "ibase=16;$entry_hex"` -length_hex=`echo "$segments" | grep "LOAD\|TLS" | tail -n 1 | tr -s [:space:] | cut -f4,7 -d' '` -length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc` -power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l` -width=64 -depth=$((power_2_length / width)) -elf2hex $width $depth $binary $entry_dec diff --git a/variables.mk b/variables.mk index eb9620f2..ae5de9a0 100644 --- a/variables.mk +++ b/variables.mk @@ -245,15 +245,9 @@ output_dir=$(sim_dir)/output/$(long_name) PERMISSIVE_ON=+permissive PERMISSIVE_OFF=+permissive-off BINARY ?= -LOADMEM ?= -LOADMEM_ADDR ?= 81000000 override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles) -ifneq ($(LOADMEM),) -override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) -endif VERBOSE_FLAGS ?= +verbose sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY)))) -binary_hex= $(sim_out_name).loadmem_hex ######################################################################################### # build output directory for compilation From f7f979ec15b4a16870acae5e1e6def2729191c13 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 02:00:27 -0700 Subject: [PATCH 074/184] Remove -x from generate-ckpt.sh script --- scripts/generate-ckpt.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/generate-ckpt.sh b/scripts/generate-ckpt.sh index f4987a24..0f2672a1 100755 --- a/scripts/generate-ckpt.sh +++ b/scripts/generate-ckpt.sh @@ -1,6 +1,6 @@ #!/bin/bash -set -ex +set -e usage() { echo "Usage: $0 [OPTIONS] -- [SPIKEFLAGS]" From b41806b6a0570bfd829a10a551b524fa6ae2f34d Mon Sep 17 00:00:00 2001 From: joey0320 Date: Sun, 9 Apr 2023 19:36:56 -0700 Subject: [PATCH 075/184] bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index da5bf77b..31836170 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit da5bf77b6eb670001d9234dbfd996b2e7c3ad1ff +Subproject commit 31836170533b804b5ba6d3ff89ceb81eec00212e From 7aaa233d73b2bb913d78e7f34ab2effff0b9005b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 16:22:39 -0700 Subject: [PATCH 076/184] Switch to LOADMEM=1, LOADARCH=loadarch flags --- common.mk | 24 ++++++--------------- docs/Simulation/Software-RTL-Simulation.rst | 9 ++------ docs/Software/Spike.rst | 2 +- variables.mk | 15 +++++++++++++ 4 files changed, 25 insertions(+), 25 deletions(-) diff --git a/common.mk b/common.mk index 9ba6850e..3e785867 100644 --- a/common.mk +++ b/common.mk @@ -319,24 +319,14 @@ run-fast: run-asm-tests-fast run-bmark-tests-fast ######################################################################################### # helper rules to run simulator with fast loadmem +# LEGACY - use LOADMEM=1 instead ######################################################################################### -run-binary-loadmem: check-binary -run-binary-loadmem: $(SIM_PREREQ) | $(output_dir) -run-binary-loadmem: run-binary -run-binary-loadmem: override SIM_FLAGS += +loadmem=$(BINARY) -run-binary-debug-loadmem: check-binary -run-binary-debug-loadmem: $(SIM_DEBUG_REREQ) | $(output_dir) -run-binary-debug-loadmem: run-binary-debug -run-binary-debug-loadmem: override SIM_FLAGS += +loadmem=$(BINARY) -run-binary-fast-loadmem: check-binary -run-binary-fast-loadmem: $(SIM_PREREQ) | $(output_dir) -run-binary-fast-loadmem: run-binary-fast -run-binary-fast-loadmem: override SIM_FLAGS += +loadmem=$(BINARY) - -# Legacy targets for backwards compat -run-binary-hex: run-binary-loadmem -run-binary-debug-hex: run-binary-debug-loadmem -run-binary-fast-hex: run-binary-fast-loadmem +run-binary-hex: run-binary +run-binary-hex: override SIM_FLAGS += +loadmem=$(BINARY) +run-binary-debug-hex: run-binary-debug +run-binary-debug-hex: override SIM_FLAGS += +loadmem=$(BINARY) +run-binary-fast-hex: run-binary-fast +run-binary-fast-hex: override SIM_FLAGS += +loadmem=$(BINARY) ######################################################################################### # run assembly/benchmarks rules diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index ccbef67c..754fa2bb 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -155,13 +155,8 @@ Loadmem files should be ELF files. In the most common use case, this can be the .. code-block:: shell - make run-binary BINARY=test.riscv EXTRA_SIM_FLAGS="+loadmem=test.riscv" - -For convenience, special ``-loadmem`` targets are provided to automatically rely on loadmem to read in the binary. - -.. code-block:: shell - - make run-binary-loadmem BINARY=test.riscv + make run-binary BINARY=test.riscv LOADMEM=test.riscv + make run-binary BINART=test.riscv LOADMEM=1 Generating Waveforms ----------------------- diff --git a/docs/Software/Spike.rst b/docs/Software/Spike.rst index 48487851..e9abe0c0 100644 --- a/docs/Software/Spike.rst +++ b/docs/Software/Spike.rst @@ -43,7 +43,7 @@ Spike-as-a-Tile can be configured with custom IPC, commit logging, and other beh .. code-block:: shell - make CONFIG=SpikeUltraFastConfig run-binary-loadmem BINARY=hello.riscv EXTRA_SPIKE_FLAGS="+spike-ipc=10000 +spike-fast-clint +spike-debug" + make CONFIG=SpikeUltraFastConfig run-binary BINARY=hello.riscv EXTRA_SPIKE_FLAGS="+spike-ipc=10000 +spike-fast-clint +spike-debug" LOADMEM=1 * ``+spike-ipc=``: Sets the maximum number of instructions Spike can retire in a single "tick", or cycle of the uncore simulation. diff --git a/variables.mk b/variables.mk index ae5de9a0..a725c599 100644 --- a/variables.mk +++ b/variables.mk @@ -248,6 +248,21 @@ BINARY ?= override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles) VERBOSE_FLAGS ?= +verbose sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY)))) +LOADMEM ?= +LOADARCH ?= + +ifneq ($(LOADARCH),) +override BINARY = $(LOADARCH)/mem.elf +override SIM_FLAGS += +loadarch=$(LOADARCH)/loadarch +endif + +ifeq ($(LOADMEM),1) +# If LOADMEM=1, assume BINARY is the loadmem elf +override SIM_FLAGS += +loadmem=$(BINARY) +else ifneq ($(LOADMEM),) +# Otherwise, assume the variable points to an elf file +override SIM_FLAGS += +loadmem=$(LOADMEM) +endif ######################################################################################### # build output directory for compilation From 1acad861614487904184e3e2cdc3f28b21114603 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 17:21:21 -0700 Subject: [PATCH 077/184] Generate loadarch checkpoints in directories --- generators/testchipip | 2 +- scripts/generate-ckpt.sh | 84 ++++++++++++++++++++++------------------ variables.mk | 6 ++- 3 files changed, 53 insertions(+), 39 deletions(-) diff --git a/generators/testchipip b/generators/testchipip index 31836170..702daddd 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 31836170533b804b5ba6d3ff89ceb81eec00212e +Subproject commit 702daddd20be7d7e8c29fb46be4608e207a9b8a5 diff --git a/scripts/generate-ckpt.sh b/scripts/generate-ckpt.sh index 0f2672a1..9e8381ba 100755 --- a/scripts/generate-ckpt.sh +++ b/scripts/generate-ckpt.sh @@ -44,64 +44,74 @@ done BASEMEM="$((0x80000000)):$((0x10000000))" SPIKEFLAGS="-p$NHARTS --pmpregions=0 --isa=rv64gc -m$BASEMEM" -rm -rf cmds_tmp.txt -touch cmds_tmp.txt +BASENAME=$(basename -- $BINARY) +DIRNAME=$BASENAME.$PC.$CYCLES.loadarch +echo "Generating loadarch directory $DIRNAME" +rm -rf $DIRNAME +mkdir -p $DIRNAME -echo "Generating state capture spike interactive commands in cmds_tmp.txt" -echo "until pc 0 $PC" >> cmds_tmp.txt -echo "rs $CYCLES" >> cmds_tmp.txt -echo "dump" >> cmds_tmp.txt +LOADARCH_FILE=$DIRNAME/loadarch +RAWMEM_ELF=$DIRNAME/raw.elf +LOADMEM_ELF=$DIRNAME/mem.elf +CMDS_FILE=$DIRNAME/cmds_tmp.txt + +echo "Generating state capture spike interactive commands in $CMDS_FILE" +echo "until pc 0 $PC" >> $CMDS_FILE +echo "rs $CYCLES" >> $CMDS_FILE +echo "dump" >> $CMDS_FILE for (( h=0; h<$NHARTS; h++ )) do - echo "pc $h" >> cmds_tmp.txt - echo "priv $h" >> cmds_tmp.txt - echo "reg $h fcsr" >> cmds_tmp.txt + echo "pc $h" >> $CMDS_FILE + echo "priv $h" >> $CMDS_FILE + echo "reg $h fcsr" >> $CMDS_FILE - echo "reg $h stvec" >> cmds_tmp.txt - echo "reg $h sscratch" >> cmds_tmp.txt - echo "reg $h sepc" >> cmds_tmp.txt - echo "reg $h scause" >> cmds_tmp.txt - echo "reg $h stval" >> cmds_tmp.txt - echo "reg $h satp" >> cmds_tmp.txt + echo "reg $h stvec" >> $CMDS_FILE + echo "reg $h sscratch" >> $CMDS_FILE + echo "reg $h sepc" >> $CMDS_FILE + echo "reg $h scause" >> $CMDS_FILE + echo "reg $h stval" >> $CMDS_FILE + echo "reg $h satp" >> $CMDS_FILE - echo "reg $h mstatus" >> cmds_tmp.txt - echo "reg $h medeleg" >> cmds_tmp.txt - echo "reg $h mideleg" >> cmds_tmp.txt - echo "reg $h mie" >> cmds_tmp.txt - echo "reg $h mtvec" >> cmds_tmp.txt - echo "reg $h mscratch" >> cmds_tmp.txt - echo "reg $h mepc" >> cmds_tmp.txt - echo "reg $h mcause" >> cmds_tmp.txt - echo "reg $h mtval" >> cmds_tmp.txt - echo "reg $h mip" >> cmds_tmp.txt + echo "reg $h mstatus" >> $CMDS_FILE + echo "reg $h medeleg" >> $CMDS_FILE + echo "reg $h mideleg" >> $CMDS_FILE + echo "reg $h mie" >> $CMDS_FILE + echo "reg $h mtvec" >> $CMDS_FILE + echo "reg $h mscratch" >> $CMDS_FILE + echo "reg $h mepc" >> $CMDS_FILE + echo "reg $h mcause" >> $CMDS_FILE + echo "reg $h mtval" >> $CMDS_FILE + echo "reg $h mip" >> $CMDS_FILE - echo "reg $h mcycle" >> cmds_tmp.txt - echo "reg $h minstret" >> cmds_tmp.txt + echo "reg $h mcycle" >> $CMDS_FILE + echo "reg $h minstret" >> $CMDS_FILE - echo "mtime" >> cmds_tmp.txt - echo "mtimecmp $h" >> cmds_tmp.txt + echo "mtime" >> $CMDS_FILE + echo "mtimecmp $h" >> $CMDS_FILE for (( fr=0; fr<32; fr++ )) do - echo "freg $h $fr" >> cmds_tmp.txt + echo "freg $h $fr" >> $CMDS_FILE done for (( xr=0; xr<32; xr++ )) do - echo "reg $h $xr" >> cmds_tmp.txt + echo "reg $h $xr" >> $CMDS_FILE done done -echo "quit" >> cmds_tmp.txt +echo "quit" >> $CMDS_FILE -#cat cmds_tmp.txt -BASENAME=$(basename -- $BINARY) +#cat $CMDS_FILE echo "Capturing state at checkpoint to spikeout" -spike -d --debug-cmd=cmds_tmp.txt $SPIKEFLAGS $BINARY 2> $BASENAME.loadarch +spike -d --debug-cmd=$CMDS_FILE $SPIKEFLAGS $BINARY 2> $LOADARCH_FILE echo "Finding tohost/fromhost in elf file" TOHOST=$(riscv64-unknown-elf-nm $BINARY | grep tohost | head -c 16) FROMHOST=$(riscv64-unknown-elf-nm $BINARY | grep fromhost | head -c 16) echo "Compiling memory to elf" -riscv64-unknown-elf-objcopy -I binary -O elf64-littleriscv mem.0x80000000.bin $BASENAME.mem.elf -riscv64-unknown-elf-ld -Tdata=0x80000000 -nmagic --defsym tohost=0x$TOHOST --defsym fromhost=0x$FROMHOST -o $BASENAME.loadarch.elf $BASENAME.mem.elf +riscv64-unknown-elf-objcopy -I binary -O elf64-littleriscv mem.0x80000000.bin $RAWMEM_ELF +rm -rf mem.0x80000000.bin + +riscv64-unknown-elf-ld -Tdata=0x80000000 -nmagic --defsym tohost=0x$TOHOST --defsym fromhost=0x$FROMHOST -o $LOADMEM_ELF $RAWMEM_ELF +rm -rf $RAWMEM_ELF diff --git a/variables.mk b/variables.mk index a725c599..8a329052 100644 --- a/variables.mk +++ b/variables.mk @@ -247,12 +247,14 @@ PERMISSIVE_OFF=+permissive-off BINARY ?= override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles) VERBOSE_FLAGS ?= +verbose -sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY)))) +OUT_NAME ?= $(subst $() $(),_,$(notdir $(basename $(BINARY)))) LOADMEM ?= LOADARCH ?= ifneq ($(LOADARCH),) override BINARY = $(LOADARCH)/mem.elf +override OUT_NAME = $(shell basename $(LOADARCH)) +override LOADMEM = 1 override SIM_FLAGS += +loadarch=$(LOADARCH)/loadarch endif @@ -264,6 +266,8 @@ else ifneq ($(LOADMEM),) override SIM_FLAGS += +loadmem=$(LOADMEM) endif +sim_out_name = $(output_dir)/$(OUT_NAME) + ######################################################################################### # build output directory for compilation ######################################################################################### From 35320bf13dac23af36ed99344d46aa344c087b72 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 17:50:38 -0700 Subject: [PATCH 078/184] Add CI for checkpoints with dmiRocketConfig --- .github/scripts/run-tests.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index bf9f2585..8516a225 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -33,7 +33,8 @@ case $1 in run_bmark ${mapping[$1]} ;; chipyard-dmirocket) - run_bmark ${mapping[$1]} + $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -c 10000 + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=dhrystone.riscv.0x80000000.10000.loadarch ;; chipyard-boom) run_bmark ${mapping[$1]} From a31685af40f224f68ee1234eaf194e18c80e0b4a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Apr 2023 17:55:07 -0700 Subject: [PATCH 079/184] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 702daddd..c2457e6b 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 702daddd20be7d7e8c29fb46be4608e207a9b8a5 +Subproject commit c2457e6b3c9197eb9d29d71fd893e102278384d3 From 8c78effdf466eeb0d2c09e42d27117e29209e5d2 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 12 Apr 2023 21:53:53 -0700 Subject: [PATCH 080/184] ADD: improve variable definition, add explicit arch flags --- tests/Makefile | 52 ++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 10 deletions(-) diff --git a/tests/Makefile b/tests/Makefile index 8756350d..5628aeac 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -1,7 +1,29 @@ -GCC=riscv64-unknown-elf-gcc -OBJDUMP=riscv64-unknown-elf-objdump -CFLAGS= -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall -LDFLAGS= -static +################################# +# RISCV Toolchain +################################# + +PREFIX = riscv64-unknown-elf- + +GCC = $(PREFIX)gcc +CXX = $(PREFIX)g++ +CP = $(PREFIX)objcopy +OBJDUMP = $(PREFIX)objdump +DG = $(PREFIX)gdb +SIZE = $(PREFIX)size + + +################################# +# Flags +################################# + +# SoC Settings +ARCH = rv64imafdc +ABI = lp64d +ARCHFLAGS = -march=$(ARCH) -mabi=$(ABI) + +CFLAGS = -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall +CFLAGS += $(ARCHFLAGS) +LDFLAGS = -static include libgloss.mk @@ -9,16 +31,16 @@ PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \ streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd \ hello -spiflash.img: spiflash.py - python3 $< .DEFAULT_GOAL := default -.PHONY: default -default: $(addsuffix .riscv,$(PROGRAMS)) spiflash.img -.PHONY: dumps -dumps: $(addsuffix .dump,$(PROGRAMS)) +################################# +# Build +################################# + +spiflash.img: spiflash.py + python3 $< %.o: %.S $(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@ @@ -33,7 +55,17 @@ dumps: $(addsuffix .dump,$(PROGRAMS)) $(OBJDUMP) -D $< > $@ +################################# +# Recipes +################################# + .PHONY: clean clean: rm -f *.riscv *.o *.dump $(if $(libgloss),rm -rf $(libgloss_builddir)/) + +.PHONY: default +default: $(addsuffix .riscv, $(PROGRAMS)) spiflash.img + +.PHONY: dumps +dumps: $(addsuffix .dump, $(PROGRAMS)) From a30b5c4c5144f51a0f6acea784fc60ea6e9ffb3c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 13 Apr 2023 15:15:46 -0700 Subject: [PATCH 081/184] Use __has_include to select between dtm/tsi spiketile --- .../chipyard/src/main/resources/csrc/spiketile.cc | 13 +++++++------ .../src/main/resources/csrc/spiketile_dtm.h | 0 .../csrc/spiketile_dtm/spiketile_htif_mode.h | 1 - .../src/main/resources/csrc/spiketile_tsi.h | 0 .../csrc/spiketile_tsi/spiketile_htif_mode.h | 1 - generators/chipyard/src/main/scala/SpikeTile.scala | 4 ++-- 6 files changed, 9 insertions(+), 10 deletions(-) create mode 100644 generators/chipyard/src/main/resources/csrc/spiketile_dtm.h delete mode 100644 generators/chipyard/src/main/resources/csrc/spiketile_dtm/spiketile_htif_mode.h create mode 100644 generators/chipyard/src/main/resources/csrc/spiketile_tsi.h delete mode 100644 generators/chipyard/src/main/resources/csrc/spiketile_tsi/spiketile_htif_mode.h diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index c1dea45c..3b14079b 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -9,14 +9,14 @@ #include #include #include -#include "spiketile_htif_mode.h" -#if defined(SPIKETILE_HTIF_TSI) +#if __has_include("spiketile_tsi.h") +#define SPIKETILE_HTIF_TSI extern htif_t* tsi; -#elif defined(SPIKETILE_HTIF_DTM) +#endif +#if __has_include("spiketile_dtm.h") +#define SPIKETILE_HTIF_DTM extern htif_t* dtm; -#else -#error "SpikeTile must be used with the TSI or DTM-based HTIF bringup" #endif enum transfer_t { @@ -348,7 +348,8 @@ extern "C" void spike_tile(int hartid, char* isa, #if defined(SPIKETILE_HTIF_TSI) if (!simif->htif && tsi) simif->htif = tsi; -#elif defined(SPIKETILE_HTIF_DTM) +#endif +#if defined(SPIKETILE_HTIF_DTM) if (!simif->htif && dtm) simif->htif = dtm; #endif diff --git a/generators/chipyard/src/main/resources/csrc/spiketile_dtm.h b/generators/chipyard/src/main/resources/csrc/spiketile_dtm.h new file mode 100644 index 00000000..e69de29b diff --git a/generators/chipyard/src/main/resources/csrc/spiketile_dtm/spiketile_htif_mode.h b/generators/chipyard/src/main/resources/csrc/spiketile_dtm/spiketile_htif_mode.h deleted file mode 100644 index 5c1c3041..00000000 --- a/generators/chipyard/src/main/resources/csrc/spiketile_dtm/spiketile_htif_mode.h +++ /dev/null @@ -1 +0,0 @@ -#define SPIKETILE_HTIF_DTM diff --git a/generators/chipyard/src/main/resources/csrc/spiketile_tsi.h b/generators/chipyard/src/main/resources/csrc/spiketile_tsi.h new file mode 100644 index 00000000..e69de29b diff --git a/generators/chipyard/src/main/resources/csrc/spiketile_tsi/spiketile_htif_mode.h b/generators/chipyard/src/main/resources/csrc/spiketile_tsi/spiketile_htif_mode.h deleted file mode 100644 index 240e6186..00000000 --- a/generators/chipyard/src/main/resources/csrc/spiketile_tsi/spiketile_htif_mode.h +++ /dev/null @@ -1 +0,0 @@ -#define SPIKETILE_HTIF_TSI diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index 66d18e7a..c6ec13ae 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -305,9 +305,9 @@ class SpikeBlackBox( addResource("/vsrc/spiketile.v") addResource("/csrc/spiketile.cc") if (use_dtm) { - addResource("/csrc/spiketile_dtm/spiketile_htif_mode.h") + addResource("/csrc/spiketile_dtm.h") } else { - addResource("/csrc/spiketile_tsi/spiketile_htif_mode.h") + addResource("/csrc/spiketile_tsi.h") } } From d2422ec229cf24564e2f86f88b2cd2ca498d0464 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 13 Apr 2023 17:01:19 -0700 Subject: [PATCH 082/184] Fix debug priv trace for boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 1b1f210b..679f3587 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 1b1f210bcf5985c1e1f588c1639d5d0ec2d04998 +Subproject commit 679f358755c57524f18cf46b72fc3fc1ac67f127 From 330a747b542d999b300f2de2fce1ec4e9fd47299 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 13 Apr 2023 17:49:39 -0700 Subject: [PATCH 083/184] Support loadarch+dtm in cosimulation with spike --- .../src/main/resources/csrc/cospike.cc | 68 +++++++++++++++++-- .../src/main/resources/csrc/cospike_dtm.h | 0 .../src/main/resources/vsrc/cospike.v | 11 +-- .../chipyard/src/main/scala/Cospike.scala | 12 ++-- .../src/main/scala/HarnessBinders.scala | 3 +- 5 files changed, 76 insertions(+), 18 deletions(-) create mode 100644 generators/chipyard/src/main/resources/csrc/cospike_dtm.h diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index fa0513d7..66b2cd29 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -6,6 +6,13 @@ #include #include +#if __has_include ("cospike_dtm.h") +#define COSPIKE_DTM +#include "testchip_dtm.h" +extern testchip_dtm_t* dtm; +bool spike_loadarch_done = false; +#endif + #define CLINT_BASE (0x2000000) #define CLINT_SIZE (0x1000) @@ -64,7 +71,8 @@ extern "C" void cospike_cosim(long long int cycle, int raise_exception, int raise_interrupt, unsigned long long int cause, - unsigned long long int wdata) + unsigned long long int wdata, + int priv) { assert(info); if (!sim) { @@ -168,16 +176,60 @@ extern "C" void cospike_cosim(long long int cycle, printf("Fromhost: %lx\n", fromhost_addr); } + if (priv & 0x4) { // debug + return; + } + processor_t* p = sim->get_core(hartid); state_t* s = p->get_state(); +#ifdef COSPIKE_DTM + if (dtm && dtm->loadarch_done && !spike_loadarch_done) { + printf("Restoring spike state from testchip_dtm loadarch\n"); + // copy the loadarch state into the cosim + loadarch_state_t &ls = dtm->loadarch_state[hartid]; + s->pc = ls.pc; + s->prv = ls.prv; +#define RESTORE(CSRID, csr) s->csrmap[CSRID]->write(ls.csr); + RESTORE(CSR_STVEC , stvec); + RESTORE(CSR_SSCRATCH , sscratch); + RESTORE(CSR_SEPC , sepc); + RESTORE(CSR_SCAUSE , scause); + RESTORE(CSR_STVAL , stval); + RESTORE(CSR_SATP , satp); + RESTORE(CSR_MSTATUS , mstatus); + RESTORE(CSR_MEDELEG , medeleg); + RESTORE(CSR_MIDELEG , mideleg); + RESTORE(CSR_MIE , mie); + RESTORE(CSR_MTVEC , mtvec); + RESTORE(CSR_MSCRATCH , mscratch); + RESTORE(CSR_MEPC , mepc); + RESTORE(CSR_MCAUSE , mcause); + RESTORE(CSR_MTVAL , mtval); + RESTORE(CSR_MIP , mip); + RESTORE(CSR_MCYCLE , mcycle); + RESTORE(CSR_MINSTRET , minstret); + for (size_t i = 0; i < 32; i++) { + s->XPR.write(i, ls.XPR[i]); + s->FPR.write(i, { (uint64_t)ls.FPR[i], (uint64_t)-1 }); + } + spike_loadarch_done = true; + p->clear_waiting_for_interrupt(); + } +#endif uint64_t s_pc = s->pc; + uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF; + bool msip_interrupt = interrupt_cause == 0x3; + bool debug_interrupt = interrupt_cause == 0xe; if (raise_interrupt) { printf("%d interrupt %lx\n", cycle, cause); - uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF; - if (interrupt_cause == 3) { + + if (msip_interrupt) { s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP); + } else if (debug_interrupt) { + return; } else { printf("Unknown interrupt %lx\n", interrupt_cause); + abort(); } } if (raise_exception) @@ -189,12 +241,13 @@ extern "C" void cospike_cosim(long long int cycle, } printf("\n"); } - if (valid || raise_interrupt || raise_exception) + if (valid || raise_interrupt || raise_exception) { p->step(1); + } if (valid) { if (s_pc != iaddr) { - printf("%d PC mismatch %lx != %lx\n", cycle, s_pc, iaddr); + printf("%d PC mismatch spike:%lx != dut:%lx\n", cycle, s_pc, iaddr); exit(1); } @@ -247,7 +300,8 @@ extern "C" void cospike_cosim(long long int cycle, printf("Read override %lx\n", mem_read_addr); s->XPR.write(rd, wdata); } else if (wdata != regwrite.second.v[0]) { - printf("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd, regwrite.second.v[0], wdata); + printf("%d wdata mismatch reg %d spike:%lx != dut:%lx addr: %lx\n", + cycle, rd, regwrite.second.v[0], wdata, mem_read_addr); exit(1); } } @@ -255,4 +309,4 @@ extern "C" void cospike_cosim(long long int cycle, } } } -// } + diff --git a/generators/chipyard/src/main/resources/csrc/cospike_dtm.h b/generators/chipyard/src/main/resources/csrc/cospike_dtm.h new file mode 100644 index 00000000..e69de29b diff --git a/generators/chipyard/src/main/resources/vsrc/cospike.v b/generators/chipyard/src/main/resources/vsrc/cospike.v index f9d2322c..824e8d35 100644 --- a/generators/chipyard/src/main/resources/vsrc/cospike.v +++ b/generators/chipyard/src/main/resources/vsrc/cospike.v @@ -16,7 +16,8 @@ import "DPI-C" function void cospike_cosim(input longint cycle, input bit raise_exception, input bit raise_interrupt, input longint cause, - input longint wdata + input longint wdata, + input int priv ); @@ -42,6 +43,7 @@ module SpikeCosim #( input [63:0] trace_0_cause, input trace_0_has_wdata, input [63:0] trace_0_wdata, + input [2:0] trace_0_priv, input trace_1_valid, input [63:0] trace_1_iaddr, @@ -50,7 +52,8 @@ module SpikeCosim #( input trace_1_interrupt, input [63:0] trace_1_cause, input trace_1_has_wdata, - input [63:0] trace_1_wdata + input [63:0] trace_1_wdata, + input [2:0] trace_1_priv ); initial begin @@ -62,12 +65,12 @@ module SpikeCosim #( if (trace_0_valid || trace_0_exception || trace_0_cause) begin cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr, trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause, - trace_0_wdata); + trace_0_wdata, trace_0_priv); end if (trace_1_valid || trace_1_exception || trace_1_cause) begin cospike_cosim(cycle, hartid, trace_1_has_wdata, trace_1_valid, trace_1_iaddr, trace_1_insn, trace_1_exception, trace_1_interrupt, trace_1_cause, - trace_1_wdata); + trace_1_wdata, trace_1_priv); end end end diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala index fffb97d6..cee23413 100644 --- a/generators/chipyard/src/main/scala/Cospike.scala +++ b/generators/chipyard/src/main/scala/Cospike.scala @@ -18,7 +18,8 @@ case class SpikeCosimConfig( mem0_base: BigInt, mem0_size: BigInt, nharts: Int, - bootrom: String + bootrom: String, + has_dtm: Boolean ) class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map( @@ -32,6 +33,7 @@ class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map( { addResource("/csrc/cospike.cc") addResource("/vsrc/cospike.v") + if (cfg.has_dtm) addResource("/csrc/cospike_dtm.h") val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) @@ -46,6 +48,7 @@ class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map( val cause = UInt(64.W) val has_wdata = Bool() val wdata = UInt(64.W) + val priv = UInt(3.W) })) }) } @@ -64,12 +67,8 @@ object SpikeCosim require(trace.numInsns <= 2) cosim.io.cycle := cycle cosim.io.trace.map(t => { + t := DontCare t.valid := false.B - t.iaddr := 0.U - t.insn := 0.U - t.exception := false.B - t.interrupt := false.B - t.cause := 0.U }) cosim.io.hartid := hartid.U for (i <- 0 until trace.numInsns) { @@ -83,6 +82,7 @@ object SpikeCosim cosim.io.trace(i).cause := trace.insns(i).cause cosim.io.trace(i).has_wdata := trace.insns(i).wdata.isDefined.B cosim.io.trace(i).wdata := trace.insns(i).wdata.getOrElse(0.U) + cosim.io.trace(i).priv := trace.insns(i).priv } } } diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 85ba3d5f..3e43dfe6 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -369,7 +369,8 @@ class WithCospike extends ComposeHarnessBinder({ mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)), pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0), nharts = tiles.size, - bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("") + bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""), + has_dtm = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM ) ports.map { p => p.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2, cfg)) } } From 048835e6b41c288b9cd5d82816b054494528574d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 13 Apr 2023 17:49:57 -0700 Subject: [PATCH 084/184] Add dmi/cosim boomconfigs --- .../src/main/scala/config/BoomConfigs.scala | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 4c101403..5544e4c3 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -53,3 +53,18 @@ class MediumBoomCosimConfig extends Config( new chipyard.config.WithTraceIO ++ // enable the traceio new boom.common.WithNMediumBooms(1) ++ new chipyard.config.AbstractConfig) + +class dmiMediumBoomConfig extends Config( + new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new boom.common.WithNMediumBooms(1) ++ + new chipyard.config.AbstractConfig) + +class dmiMediumBoomCosimConfig extends Config( + new chipyard.harness.WithCospike ++ // attach spike-cosim + new chipyard.config.WithTraceIO ++ // enable the traceio + new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new boom.common.WithNMediumBooms(1) ++ + new chipyard.config.AbstractConfig) + From ccb92e016afb31b648b33b6d7a01ea1e5b8f19db Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 13 Apr 2023 17:59:56 -0700 Subject: [PATCH 085/184] Bump spike --- toolchains/riscv-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 7470633c..80603341 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 7470633c425c2385685f369a8ca9f2c3a629f494 +Subproject commit 80603341f6ac62be5abb6b7f1d09eb62bd7f2ff4 From 2ec45b4f6336e7db60fa68c06e39b6ab7e31014c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 13 Apr 2023 18:00:21 -0700 Subject: [PATCH 086/184] Test boom cosim with spike in boom CI --- .github/scripts/defaults.sh | 2 +- .github/scripts/run-tests.sh | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 13bcf116..cc95087d 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -45,7 +45,7 @@ mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig" mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig" mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" -mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig" +mapping["chipyard-boom"]=" CONFIG=dmiMediumBoomCosimConfig" mapping["chipyard-spike"]=" CONFIG=SpikeFastUARTConfig EXTRA_SIM_FLAGS='+spike-ipc=10'" mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 8516a225..9938ca43 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -37,7 +37,8 @@ case $1 in make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=dhrystone.riscv.0x80000000.10000.loadarch ;; chipyard-boom) - run_bmark ${mapping[$1]} + $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -c 10000 + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=dhrystone.riscv.0x80000000.10000.loadarch ;; chipyard-spike) run_bmark ${mapping[$1]} From 240c55193fb0e9a948f7e0f8b0f958ba55ab5645 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 14 Apr 2023 11:32:41 -0700 Subject: [PATCH 087/184] add python script, wip --- scripts/uniqify-module-names.py | 105 ++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100755 scripts/uniqify-module-names.py diff --git a/scripts/uniqify-module-names.py b/scripts/uniqify-module-names.py new file mode 100755 index 00000000..7269c63f --- /dev/null +++ b/scripts/uniqify-module-names.py @@ -0,0 +1,105 @@ +#!/usr/bin/env python3 + +import json +import argparse +import shutil +import os +import sh + + + +parser = argparse.ArgumentParser(description="") +parser.add_argument("--top-filelist", type=str, required=True, help="Abs path to ..top.f") +parser.add_argument("--mod-filelist", type=str, required=True, help="Abs path to ..model.f") +parser.add_argument("--gen-collateral-path", dest="gcpath", type=str, required=True, help="Abs path to the gen-collateral directory") +parser.add_argument("--model-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") +parser.add_argument('--dut', type=str, required=True, help='Name of the DUT module.') +parser.add_argument('--model', type=str, required=True, help='Name of the MODEL module.') +args = parser.parse_args() + + +def get_filelist(filelist): + f = open(filelist, "r") + lines = f.readlines() + f.close() + + fnames = [] + for line in lines: + try: + fname = line.split("/")[-1].replace("\n", "") + fnames.append(fname) + except: + print(f"Something is wrong about this line {line}") + + return fnames + + +def generate_copy(c, sfx): + (cur_name, ext) = os.path.splitext(c) + new_name = cur_name + "_" + sfx + new_file = new_name + ext + + cur_file = os.path.join(args.gcpath, c) + new_file = os.path.join(args.gcpath, new_file) + + shutil.copy(cur_file, new_file) + sh.sed("-i", f"s/{cur_name}/{new_name}/", new_file) + + return new_file + + + +def dfs_update_modules(tree, common_fnames, visited): + # List of direct submodules to update + childs_to_update = list() + for child in tree['instances']: + if (child['module_name'] == args.dut) or (child['module_name'] in visited): + continue + if dfs_update_modules(child, common_fnames, visited): + childs_to_update.append(child['module_name']) + + cur_module = tree['module_name'] + cur_file = cur_module + ".sv" + new_file = None + + # cur_file is in the common list, generate a new file + for c in common_fnames: + if cur_file == c: + new_file = generate_copy(c, "Model") + + # has some child to update, but new_file wasn't generated + if (new_file is None) and len(childs_to_update) > 0: + if cur_module == args.model: + new_file = os.path.join(args.gcpath, cur_file) + else: + new_file = generate_copy(cur_file, "Model") + + if new_file is not None: + print(f"-- {cur_module}") + + for submodule_name in childs_to_update: + print(f"|- {submodule_name}") + sh.sed("-i", f"s/{submodule_name}/{submodule_name}_Model/", new_file) + + visited.add(cur_module) + return (new_file is not None) + + +def main(): + top_fnames = set(get_filelist(args.top_filelist)) + mod_fnames = set(get_filelist(args.mod_filelist)) + + common_fnames = top_fnames.intersection(mod_fnames) + for c in common_fnames: + print(c) + + imhj = open(args.model_hier_json, "r") + imhj_data = json.load(imhj) + + visited = set() + dfs_update_modules(imhj_data, common_fnames, visited) + + + +if __name__ == "__main__": + main() From e59ed50abb7f0d6bf4b1da7669e5cdafc8e27e1d Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 14 Apr 2023 16:44:30 -0700 Subject: [PATCH 088/184] script to unqify modules --- common.mk | 6 +++++ scripts/uniqify-module-names.py | 40 +++++++++++++++++++-------------- 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/common.mk b/common.mk index a4668075..ed02a10e 100644 --- a/common.mk +++ b/common.mk @@ -243,6 +243,12 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL $(SED) -i 's/\.\///' $(TOP_MODS_FILELIST) $(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST) $(SED) -i 's/\.\///' $(BB_MODS_FILELIST) + $(base_dir)/scripts/uniqify-module-names.py \ + --top-filelist $(TOP_MODS_FILELIST) \ + --mod-filelist $(MODEL_MODS_FILELIST) \ + --gen-collateral-path $(GEN_COLLATERAL_DIR) \ + --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ + --dut $(TOP) sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) &: $(BB_MODS_FILELIST) $(MFC_TOP_HRCHY_JSON) $(FINAL_ANNO_FILE) diff --git a/scripts/uniqify-module-names.py b/scripts/uniqify-module-names.py index 7269c63f..a88d4147 100755 --- a/scripts/uniqify-module-names.py +++ b/scripts/uniqify-module-names.py @@ -14,7 +14,6 @@ parser.add_argument("--mod-filelist", type=str, required=True, help="Abs path to parser.add_argument("--gen-collateral-path", dest="gcpath", type=str, required=True, help="Abs path to the gen-collateral directory") parser.add_argument("--model-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") parser.add_argument('--dut', type=str, required=True, help='Name of the DUT module.') -parser.add_argument('--model', type=str, required=True, help='Name of the MODEL module.') args = parser.parse_args() @@ -33,6 +32,9 @@ def get_filelist(filelist): return fnames +def update_filelist(cur_file, new_file): + sh.sed("-i", f"s/\b{cur_file}\b/{new_file}/", os.path.join(args.gcpath, args.mod_filelist)) + def generate_copy(c, sfx): (cur_name, ext) = os.path.splitext(c) @@ -43,43 +45,45 @@ def generate_copy(c, sfx): new_file = os.path.join(args.gcpath, new_file) shutil.copy(cur_file, new_file) - sh.sed("-i", f"s/{cur_name}/{new_name}/", new_file) - + sh.sed("-i", f"s/\b{cur_name}\b/{new_name}/", new_file) return new_file -def dfs_update_modules(tree, common_fnames, visited): +def dfs_update_modules(tree, common_fnames, visited, top_fnames, updated_modules): # List of direct submodules to update childs_to_update = list() for child in tree['instances']: + # We don't have to change stuff that are under the dut if (child['module_name'] == args.dut) or (child['module_name'] in visited): continue - if dfs_update_modules(child, common_fnames, visited): + if dfs_update_modules(child, common_fnames, visited, top_fnames, updated_modules): childs_to_update.append(child['module_name']) + if (child['module_name'] + ".sv") in common_fnames: + child['module_name'] = child['module_name'] + "_Model" + updated_modules.append(child['module_name']) cur_module = tree['module_name'] cur_file = cur_module + ".sv" new_file = None # cur_file is in the common list, generate a new file - for c in common_fnames: - if cur_file == c: - new_file = generate_copy(c, "Model") + if cur_file in common_fnames: + new_file = generate_copy(cur_file, "Model") + update_filelist(cur_file, os.path.basename(new_file)) # has some child to update, but new_file wasn't generated if (new_file is None) and len(childs_to_update) > 0: - if cur_module == args.model: - new_file = os.path.join(args.gcpath, cur_file) - else: - new_file = generate_copy(cur_file, "Model") + new_file = os.path.join(args.gcpath, cur_file) + assert(cur_file not in top_fnames) if new_file is not None: print(f"-- {cur_module}") for submodule_name in childs_to_update: print(f"|- {submodule_name}") - sh.sed("-i", f"s/{submodule_name}/{submodule_name}_Model/", new_file) + if (submodule_name + ".sv") in common_fnames: + sh.sed("-i", f"s/\b{submodule_name}\b/{submodule_name}_Model/", new_file) visited.add(cur_module) return (new_file is not None) @@ -88,16 +92,18 @@ def dfs_update_modules(tree, common_fnames, visited): def main(): top_fnames = set(get_filelist(args.top_filelist)) mod_fnames = set(get_filelist(args.mod_filelist)) - common_fnames = top_fnames.intersection(mod_fnames) - for c in common_fnames: - print(c) imhj = open(args.model_hier_json, "r") imhj_data = json.load(imhj) visited = set() - dfs_update_modules(imhj_data, common_fnames, visited) + updated_modules = list() + dfs_update_modules(imhj_data, common_fnames, visited, top_fnames, updated_modules) + + out_file = open(args.model_hier_json, "w") + json.dump(imhj_data, out_file, indent=2) + out_file.close() From c204e4a3e4132c9014cbe0f943f09decfcd18a19 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 14 Apr 2023 16:44:54 -0700 Subject: [PATCH 089/184] rm print --- scripts/uniqify-module-names.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/scripts/uniqify-module-names.py b/scripts/uniqify-module-names.py index a88d4147..260f8fd3 100755 --- a/scripts/uniqify-module-names.py +++ b/scripts/uniqify-module-names.py @@ -77,11 +77,7 @@ def dfs_update_modules(tree, common_fnames, visited, top_fnames, updated_modules new_file = os.path.join(args.gcpath, cur_file) assert(cur_file not in top_fnames) - if new_file is not None: - print(f"-- {cur_module}") - for submodule_name in childs_to_update: - print(f"|- {submodule_name}") if (submodule_name + ".sv") in common_fnames: sh.sed("-i", f"s/\b{submodule_name}\b/{submodule_name}_Model/", new_file) From 632a8957ffd7666e8fdea566a1ff30b7d913b416 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 14 Apr 2023 21:24:08 -0700 Subject: [PATCH 090/184] add sh to conda env --- conda-reqs/chipyard.yaml | 1 + ...ements-riscv-tools-linux-64.conda-lock.yml | 1137 ++++++++++------- 2 files changed, 698 insertions(+), 440 deletions(-) diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml index 59c5de51..7b928cae 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard.yaml @@ -39,6 +39,7 @@ dependencies: - coreutils - jq - pip + - sh # firemarshal deps - qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index ca4c96d2..22625f5a 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -7,9 +7,9 @@ # Install this environment as "YOURENV" with: # conda-lock install -n YOURENV --file conda-requirements-riscv-tools-linux-64.conda-lock.yml # To update a single package to the latest version compatible with the version constraints in the source: -# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE +# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml +# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/chipyard.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -21,12 +21,14 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 1a7b0ae002798a28682d700644302284790c06503a7d3d04caa019aa74da7123 + linux-64: 94be5f8cad4026c00d3aef6c3690da6cc358bc79c1f7398049754bd17e861420 platforms: - linux-64 sources: - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml + - /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/chipyard.yaml + - /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/riscv-tools.yaml package: - category: main dependencies: {} @@ -185,14 +187,14 @@ package: - category: main dependencies: {} hash: - md5: 7697d37e29669a14b053e82fad22a16b - sha256: ac993fa2774b90befcd6aba55b1c08853b2fa3b818753094c09bebd35fc55532 + md5: 0299e410bfb4300540bdc0012a7985ef + sha256: 8572efb7092c72fe7b73d2a0f1e5e27159a8edea0371e1bef533bcb7d85b19c6 manager: conda name: open_pdks.sky130a optional: false platform: linux-64 - url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.402_1_g12df12e-20230225_164303.tar.bz2 - version: 1.0.402_1_g12df12e + url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.406_0_g0c37b7c-20230412_103222.tar.bz2 + version: 1.0.406_0_g0c37b7c - category: main dependencies: {} hash: @@ -207,14 +209,14 @@ package: - category: main dependencies: {} hash: - md5: 51fc4fcfb19f5d95ffc8c339db5068e8 - sha256: 0bfae0b9962bc0dbf79048f9175b913ed4f53c4310d06708dc7acbb290ad82f6 + md5: 939e3e74d8be4dac89ce83b20de2492a + sha256: 0449138224adfa125b220154408419ec37c06b0b49f63c5954724325903ecf55 manager: conda name: tzdata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2022g-h191b570_0.conda - version: 2022g + url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023c-h71feb2d_0.conda + version: 2023c - category: main dependencies: font-ttf-dejavu-sans-mono: '' @@ -420,25 +422,13 @@ package: libstdcxx-ng: '>=12' hash: md5: 6bfb79319763a11c7423c9d0e0ee00b7 + sha256: null manager: conda name: dromajo optional: false platform: linux-64 url: https://conda.anaconda.org/ucb-bar/linux-64/dromajo-1.0.0-0_h1234567_g6a6e34e.tar.bz2 version: 1.0.0 -- category: main - dependencies: - libgcc-ng: '>=12' - libstdcxx-ng: '>=12' - hash: - md5: c4fbad8d4bddeb3c085f18cbf97fbfad - sha256: b44db0b92ae926b3fbbcd57c179fceb64fa11a9f9d09082e03be58b74dcad832 - manager: conda - name: expat - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/expat-2.5.0-h27087fc_0.tar.bz2 - version: 2.5.0 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -528,17 +518,17 @@ package: version: '1.12' - category: main dependencies: - libgcc-ng: '>=10.3.0' - libstdcxx-ng: '>=10.3.0' + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' hash: - md5: 87473a15119779e021c314249d4b4aed - sha256: 1d7950f3be4637ab915d886304e57731d39a41ab705ffc95c4681655c459374a + md5: 7c8d20d847bb45f56bd941578fcfa146 + sha256: e44cc00eec068e7f7a6dd117ba17bf5d57658729b7b841945546f82505138292 manager: conda name: icu optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/icu-70.1-h27087fc_0.tar.bz2 - version: '70.1' + url: https://conda.anaconda.org/conda-forge/linux-64/icu-72.1-hcb278e6_0.conda + version: '72.1' - category: main dependencies: libgcc-ng: '>=12' @@ -592,14 +582,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: 5cc781fd91968b11a8a7fdbee0982676 - sha256: f9983a8ea03531f2c14bce76c870ca325c0fddf0c4e872bff1f78bc52624179c + md5: 6aa9c9de5542ecb07fdda9ca626252d8 + sha256: 949d84ceea543802c1e085b2aa58f1d6cb5dd8cec5a9abaaf4e8ac65d6094b3a manager: conda name: libdeflate optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libdeflate-1.17-h0b41bf4_0.conda - version: '1.17' + url: https://conda.anaconda.org/conda-forge/linux-64/libdeflate-1.18-h0b41bf4_0.conda + version: '1.18' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -612,6 +602,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libev-4.33-h516909a_1.tar.bz2 version: '4.33' +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 6305a3dd2752c76335295da4e581f2fd + sha256: 74c98a563777ae2ad71f1f74d458a8ab043cee4a513467c159ccf159d0e461f3 + manager: conda + name: libexpat + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libexpat-2.5.0-hcb278e6_1.conda + version: 2.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -648,6 +650,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libiconv-1.17-h166bdaf_0.tar.bz2 version: '1.17' +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 1edd9e67bdb90d78cea97733ff6b54e6 + sha256: b19de7bda34eac4fa931be11fa8d7640cdf1441dfd51c91786586a4a4c64c92f + manager: conda + name: libjpeg-turbo + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libjpeg-turbo-2.1.5.1-h0b41bf4_0.conda + version: 2.1.5.1 - category: main dependencies: libgcc-ng: '>=9.4.0' @@ -736,16 +750,16 @@ package: version: 0.9.10 - category: main dependencies: - libgcc-ng: '>=9.3.0' + libgcc-ng: '>=12' hash: - md5: 772d69f030955d9646d3d0eaf21d859d - sha256: 54f118845498353c936826f8da79b5377d23032bcac8c4a02de2019e26c3f6b3 + md5: 40b61aab5c7ba9ff276c41cfffe6b80b + sha256: 787eb542f055a2b3de553614b25f09eefb0a0931b0c87dbcce6efdfd92f04f18 manager: conda name: libuuid optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libuuid-2.32.1-h7f98852_1000.tar.bz2 - version: 2.32.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libuuid-2.38.1-h0b41bf4_0.conda + version: 2.38.1 - category: main dependencies: libgcc-ng: '>=12' @@ -762,14 +776,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: ac2ccf7323d21f2994e4d1f5da664f37 - sha256: 221f2e138dd264b7394b88f08884d93825d38800a51415059e813c02467abfd1 + md5: 0d4a7508d8c6c65314f2b9c1f56ad408 + sha256: ac3e073ea77803da71eb77e7fcef07defb345bda95eee3327c73ddf85b5714da manager: conda name: libwebp-base optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.2.4-h166bdaf_0.tar.bz2 - version: 1.2.4 + url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.3.0-h0b41bf4_0.conda + version: 1.3.0 - category: main dependencies: libgcc-ng: '>=12' @@ -954,15 +968,15 @@ package: version: '6.0' - category: main dependencies: - libgcc-ng: '>=7.3.0' + libgcc-ng: '>=12' hash: - md5: 2e5f1a8199794b21c9472c1a7f27e21a - sha256: a3ee6c02932fbee32babe39fa6bda9f781d6dc17122d2a90e62ff2b6866a5de8 + md5: 76d6bc123c1c75bf034c412856fcc935 + sha256: e94d0d5f75a5f58165ad8ac64a25df851c77ec6e9bf626c16807dcbd740226c8 manager: conda name: which optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/which-2.21-h516909a_0.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/which-2.21-h0b41bf4_1.conda version: '2.21' - category: main dependencies: @@ -1135,6 +1149,19 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/dtc-1.6.1-h166bdaf_2.tar.bz2 version: 1.6.1 +- category: main + dependencies: + libexpat: 2.5.0 hcb278e6_1 + libgcc-ng: '>=12' + hash: + md5: 8b9b5aca60558d02ddaa09d599e55920 + sha256: 36dfeb4375059b3bba75ce9b38c29c69fd257342a79e6cf20e9f25c1523f785f + manager: conda + name: expat + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/expat-2.5.0-hcb278e6_1.conda + version: 2.5.0 - category: main dependencies: gettext: '' @@ -1373,20 +1400,20 @@ package: version: '1.13' - category: main dependencies: - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' libiconv: '>=1.17,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' xz: '>=5.2.6,<6.0a0' hash: - md5: bb808b654bdc3c783deaf107a2ffb503 - sha256: d4170f1fe356768758b13a51db123f990bff81b0eae0d5a0ba11c7ca6b9536f4 + md5: 241845899caff54ac1d2b3102ad988cf + sha256: 624b6e29e23a51353cff2aff7364c42b831139afd131d239e79f60aea4dae887 manager: conda name: libxml2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.3-hca2bb57_4.conda - version: 2.10.3 + url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.4-hfdac1af_0.conda + version: 2.10.4 - category: main dependencies: libgcc-ng: '>=7.3.0' @@ -1472,14 +1499,14 @@ package: libgcc-ng: '>=12' ncurses: '>=6.3,<7.0a0' hash: - md5: db2ebbe2943aae81ed051a6a9af8e0fa - sha256: f5f383193bdbe01c41cb0d6f99fec68e820875e842e6e8b392dbe1a9b6c43ed8 + md5: 47d31b792659ce70f470b5c82fdfb7a4 + sha256: 5435cf39d039387fbdc977b0a762357ea909a7694d9528ab40f005e9208744d7 manager: conda name: readline optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.1.2-h0f457ee_0.tar.bz2 - version: 8.1.2 + url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.2-h8228510_1.conda + version: '8.2' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1589,17 +1616,17 @@ package: version: '2.71' - category: main dependencies: - libgcc-ng: '>=10.3.0' - readline: '>=8.1,<9.0a0' + libgcc-ng: '>=12' + readline: '>=8.2,<9.0a0' hash: - md5: 54d1a374b75f14ecc58aea8c4236c0c3 - sha256: 6415903ad8774fc0f1bf5b156ae0b6f9988427a0f14bb35467c5938f05fe8707 + md5: 23b559a791d63ba4f51906763eb6bc53 + sha256: a7b2ea50068d86ac6e3749f76b118b15947d3f5ce48535eb5ab2ff7e22659c49 manager: conda name: bash optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.1.16-hd863ed2_0.tar.bz2 - version: 5.1.16 + url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.2.15-hfbf034d_0.conda + version: 5.2.15 - category: main dependencies: flex: '' @@ -1685,13 +1712,13 @@ package: dependencies: gcc_impl_linux-64: 12.2.0.* hash: - md5: b4d86475bd1a21d139ea78770f606471 - sha256: 3cfb989723f8e115d35553c2b1d899b0f4185fc0551a996b9ff4037083a36432 + md5: c241b4f6676222c2feefc9dc4b9d1728 + sha256: f4b4184cc3e0864abadfc5b06ae869b479e736ff1dc46723967256d11b5bc7c4 manager: conda name: gcc optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_11.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_12.conda version: 12.2.0 - category: main dependencies: @@ -1820,23 +1847,39 @@ package: version: 15.0.7 - category: main dependencies: - jpeg: '>=9e,<10a' - lerc: '>=4.0.0,<5.0a0' - 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caacb23e1b95fbdd8115be69228f9c82068ed87bf57f055027e31d093ae6a1a2 manager: conda name: libtiff optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libtiff-4.5.0-h6adf6a1_2.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libtiff-4.5.0-ha587672_6.conda version: 4.5.0 - category: main dependencies: @@ -1881,20 +1924,20 @@ package: libuuid: '>=2.32.1,<3.0a0' libzlib: '>=1.2.13,<1.3.0a0' ncurses: '>=6.3,<7.0a0' - openssl: '>=3.0.7,<4.0a0' - readline: '>=8.1.2,<9.0a0' + openssl: '>=3.1.0,<4.0a0' + readline: '>=8.2,<9.0a0' tk: '>=8.6.12,<8.7.0a0' tzdata: '' xz: '>=5.2.6,<6.0a0' hash: - md5: 3cb3e91b3fe66baa68a12c85f39b9b40 - sha256: 073878d7cc9c7e25cf04983d02e6d44b531d47e0166258cbce964dd78bb716a9 + md5: de25afc7041c103c7f510c746bb63435 + sha256: 67748307da3fa057d17d4e991f3c60f87595a517b98f4b323a17b5f3dc287159 manager: conda name: python optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/python-3.10.9-he550d4f_0_cpython.conda - version: 3.10.9 + url: https://conda.anaconda.org/conda-forge/linux-64/python-3.10.10-he550d4f_0_cpython.conda + version: 3.10.10 - category: main dependencies: libgcc-ng: '>=12' @@ -1990,14 +2033,14 @@ package: dependencies: python: '>=3.6' hash: - md5: b3c15cb1d45fd10bc6f652bbc51e023a - sha256: 8dbc6de55113ea67a64f0be5d16ba939d1b58a25dbd9a5cc62b571cef24ef85c + md5: 99b19895abe40280358488acb9589532 + sha256: 2b273efc522834e4c8563da7998b9b683eed467660fe8a5a3c24d58aaa85a9cb manager: conda name: argcomplete optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.2-pyhd8ed1ab_0.conda - version: 3.0.2 + url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.5-pyhd8ed1ab_0.conda + version: 3.0.5 - category: main dependencies: libgcc-ng: '>=12' @@ -2203,14 +2246,14 @@ package: dependencies: python: '>=3.7' hash: - md5: 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https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.3.0-pyhd8ed1ab_1.conda - version: 2023.3.0 + url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.4.0-pyh1a96a4e_0.conda + version: 2023.4.0 - category: main dependencies: - jpeg: '>=9e,<10a' libgcc-ng: '>=12' libglib: '>=2.74.1,<3.0a0' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libtiff: '>=4.5.0,<4.6.0a0' + libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 1a109126a43003d65b39c1cad656bc9b - sha256: a27f49d85e0a730374cc77606e9484b23b0f3edf32df1994b6d7ff5dd44aef92 + md5: ee8220db21db8094998005990418fe5b + sha256: 7acc699871310e9a89aaa7e90de9ac949e2fa649232c8a8dfcafa67e8f36a266 manager: conda name: gdk-pixbuf optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gdk-pixbuf-2.42.10-h05c8ddd_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/gdk-pixbuf-2.42.10-h6b639ba_2.conda version: 2.42.10 - category: main dependencies: @@ -2305,13 +2349,13 @@ package: gcc: 12.2.0.* gxx_impl_linux-64: 12.2.0.* hash: - md5: 2b54322e0dbb1345d64913e8b20b7d7c - sha256: f6c390055f2846d6013160c41dece0973daf577c5f1aaa73ff5dcf597b35d0ec + md5: 56e0d282569b6cd349035a1bb5efae47 + sha256: b428f0af395194cb327fb212167efc3a837866d11b9f1a8bbad7e953c595c6cb manager: conda name: gxx optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_11.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_12.conda version: 12.2.0 - category: main dependencies: @@ -2439,17 +2483,31 @@ package: version: 1.4.4 - category: main dependencies: - jpeg: '>=9e,<10a' libgcc-ng: '>=12' + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 + hash: + md5: 8664f43451412071a7111211fe7e38f2 + sha256: a26e8c55b8d1b17e784c6e2ffa75ed4dec4a335c7df17f183dcc9c5149d6cd70 + manager: conda + name: lazy-object-proxy + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/lazy-object-proxy-1.9.0-py310h1fa729e_0.conda + version: 1.9.0 +- category: main + dependencies: + libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libtiff: '>=4.5.0,<4.6.0a0' hash: - md5: aa8840cdf17ef0c6084d1e24abc7a28b - sha256: 443e926b585528112ec6aa4d85bf087722914ed8d85a2f75ae47c023c55c4238 + md5: 980d8aca0bc23ca73fa8caa3e7c84c28 + sha256: 0d88e0e7f8dbf8f01788e21dd63dd49b89433ce7dfd10f53839441396f6481cd manager: conda name: lcms2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-hfd0df8a_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-haa2dc70_1.conda version: '2.15' - category: main dependencies: @@ -2469,18 +2527,31 @@ package: - category: main dependencies: libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.1,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: a3a0f7a6f0885f5e1e0ec691566afb77 - sha256: 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dependencies: cryptography: '' @@ -4766,20 +5007,21 @@ package: version: 2.54.4 - category: main dependencies: - jsonschema: '>=3.2.0,<5.0.0' - openapi-schema-validator: '>=0.2.0,<0.3.0' + importlib_resources: '>=5.8.0,<6.0.0' + jsonschema: '>=4.0.0,<4.18.0' + jsonschema-spec: '>=0.1.1,<0.2.0' + lazy-object-proxy: '>=1.7.1,<2.0.0' + openapi-schema-validator: '>=0.4.2,<0.5' python: '>=3.7' - pyyaml: '>=5.1' - setuptools: '' hash: - md5: 5ff3ff67d18fd4938c4ae38c3baf21bb - sha256: 11f24d36001aaba0a7197ff7b9a07ab943d05f969b13e5a9c4ffec13eca19cd0 + md5: a6e9e3fc7321a5fa6a9344c366e85fac + sha256: db9346beb615afab028631b35752ab12c7172455016aba29d9f8da280431c517 manager: conda name: openapi-spec-validator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/openapi-spec-validator-0.4.0-pyhd8ed1ab_1.tar.bz2 - version: 0.4.0 + url: https://conda.anaconda.org/conda-forge/noarch/openapi-spec-validator-0.5.6-pyhd8ed1ab_0.conda + version: 0.5.6 - category: main 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+ source: null url: https://files.pythonhosted.org/packages/e6/88/8a05e7ad0bb823246b2add3d2e97f990c41c71a40762c8db77a4bd78eedf/mock-5.0.1-py3-none-any.whl version: 5.0.1 - dependencies: {} @@ -5419,6 +5664,7 @@ package: manager: pip name: pyyaml platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/02/25/6ba9f6bb50a3d4fbe22c1a02554dc670682a07c8701d1716d19ddea2c940/PyYAML-6.0-cp310-cp310-manylinux_2_5_x86_64.manylinux1_x86_64.manylinux_2_12_x86_64.manylinux2010_x86_64.whl version: '6.0' - category: main @@ -5430,6 +5676,7 @@ package: name: asttokens optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/f3/e1/64679d9d0759db5b182222c81ff322c2fe2c31e156a59afd6e9208c960e5/asttokens-2.2.1-py2.py3-none-any.whl version: 2.2.1 - category: main @@ -5441,6 +5688,7 @@ package: name: gdspy optional: false platform: linux-64 + source: null url: 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-5525,6 +5781,7 @@ package: name: pylddwrap optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/c9/12/4afd6542c43cd20271f0e53bf0211decc10079a76a41e53c0288025a7b85/pylddwrap-1.2.2.tar.gz version: 1.2.2 version: 1 From 611de45cb19946aa606e9b34a8069759f7eb9f21 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Sun, 16 Apr 2023 10:10:21 -0700 Subject: [PATCH 091/184] update conda-lock file again --- ...ements-riscv-tools-linux-64.conda-lock.yml | 84 ++++++++----------- 1 file changed, 36 insertions(+), 48 deletions(-) diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index 22625f5a..9e25cb5f 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -7,9 +7,9 @@ # Install this environment as "YOURENV" with: # conda-lock install -n YOURENV --file conda-requirements-riscv-tools-linux-64.conda-lock.yml # To update a single package to the latest version compatible with the version constraints in the source: -# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE +# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/chipyard.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml +# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/chipyard.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/riscv-tools.yaml -f /Users/joonhohwangbo/Documents/UCB-BAR/coding/chipyard/conda-reqs/chipyard.yaml -f /Users/joonhohwangbo/Documents/UCB-BAR/coding/chipyard/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -21,7 +21,7 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 94be5f8cad4026c00d3aef6c3690da6cc358bc79c1f7398049754bd17e861420 + linux-64: 661e3655416e9e5de13d6b7ef41dd4f18c6e4725072890cdc12d17cdbde356bc platforms: - linux-64 sources: @@ -29,6 +29,8 @@ metadata: - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml - /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/chipyard.yaml - /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/riscv-tools.yaml + - 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botocore: '>=1.29.113,<1.30.0' + botocore: '>=1.29.114,<1.30.0' jmespath: '>=0.7.1,<2.0.0' python: '>=3.7' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: df6d2b9af30a1cca57b65514af77aeb9 - sha256: 166352179c0be643a1b103a3e504f8704cbc528bf7d9723b28429cbf3ee36bfe + md5: e848c71388d684b223b6cc487acb0ff9 + sha256: 7e268ec2c2783d23a32f02170fec03edce32b4ba81a36b410399537d38a343b1 manager: conda name: boto3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.113-pyhd8ed1ab_0.conda - version: 1.26.113 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.114-pyhd8ed1ab_0.conda + version: 1.26.114 - category: main dependencies: cachecontrol: 0.12.11 pyhd8ed1ab_1 @@ -5655,7 +5654,6 @@ package: name: mock optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/e6/88/8a05e7ad0bb823246b2add3d2e97f990c41c71a40762c8db77a4bd78eedf/mock-5.0.1-py3-none-any.whl version: 5.0.1 - dependencies: {} @@ -5664,7 +5662,6 @@ package: manager: pip name: pyyaml platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/02/25/6ba9f6bb50a3d4fbe22c1a02554dc670682a07c8701d1716d19ddea2c940/PyYAML-6.0-cp310-cp310-manylinux_2_5_x86_64.manylinux1_x86_64.manylinux_2_12_x86_64.manylinux2010_x86_64.whl version: '6.0' - category: main @@ -5676,7 +5673,6 @@ package: name: asttokens optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/f3/e1/64679d9d0759db5b182222c81ff322c2fe2c31e156a59afd6e9208c960e5/asttokens-2.2.1-py2.py3-none-any.whl version: 2.2.1 - category: main @@ -5688,7 +5684,6 @@ package: name: gdspy optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/1d/e4/97b8add92fbec2a9890ad4777272e9a9e4d7a0ceeac42b7e1febe94f0e86/gdspy-1.4.zip version: '1.4' - category: main @@ -5701,7 +5696,6 @@ package: name: paramiko-ng optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/9f/53/1ac75eab589149b1e02e38185ecebf09e1b805fc3fdeadbc16d1a2b7d208/paramiko_ng-2.8.10-py2.py3-none-any.whl version: 2.8.10 - category: main @@ -5713,7 +5707,6 @@ package: name: ruamel.yaml optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/9e/cb/938214ac358fbef7058343b3765c79a1b7ed0c366f7f992ce7ff38335652/ruamel.yaml-0.17.21-py3-none-any.whl version: 0.17.21 - category: main @@ -5726,7 +5719,6 @@ package: name: sure optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/dd/ae/eb28ee3b6768e51cb938abcf521cb678217203f33385a2df54d3f23331c5/sure-2.0.1.tar.gz version: 2.0.1 - category: main @@ -5739,7 +5731,6 @@ package: name: fab-classic optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/6b/0f/efc537eebfd2a2c470250c0ac8bd8a05ffc13d95a7fb22021367890d7c46/fab_classic-1.19.2-py2.py3-none-any.whl version: 1.19.2 - category: main @@ -5755,7 +5746,6 @@ package: name: hammer-vlsi optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/53/39/18367e6fb4f20e9ae4fb3097f7b80704ff5cccf62980ea2871ba1d817a74/hammer_vlsi-1.1.0-py3-none-any.whl version: 1.1.0 - category: main @@ -5768,7 +5758,6 @@ package: name: icontract optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/d8/91/9756e7cf0b155e80bf9a62beffdd1dec4afce43cc6ab7f432f2267c62762/icontract-2.6.2-py3-none-any.whl version: 2.6.2 - category: main @@ -5781,7 +5770,6 @@ package: name: pylddwrap optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/c9/12/4afd6542c43cd20271f0e53bf0211decc10079a76a41e53c0288025a7b85/pylddwrap-1.2.2.tar.gz version: 1.2.2 version: 1 From bb6f8be801537aa538bfc8928b823d8b934d93c4 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Mon, 17 Apr 2023 10:05:11 -0700 Subject: [PATCH 092/184] bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index aa9170af..66ff09f6 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit aa9170afe133e74e1c66b0082dc943e272d9e6f0 +Subproject commit 66ff09f611b7b3af7d9413f216fe9890875b727c From 04f4260901e7a0a740074a4ffebd67a6b31fe5e8 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Mon, 17 Apr 2023 10:05:30 -0700 Subject: [PATCH 093/184] rm wrong assertion --- scripts/uniqify-module-names.py | 1 - 1 file changed, 1 deletion(-) diff --git a/scripts/uniqify-module-names.py b/scripts/uniqify-module-names.py index 260f8fd3..d6fd6929 100755 --- a/scripts/uniqify-module-names.py +++ b/scripts/uniqify-module-names.py @@ -75,7 +75,6 @@ def dfs_update_modules(tree, common_fnames, visited, top_fnames, updated_modules # has some child to update, but new_file wasn't generated if (new_file is None) and len(childs_to_update) > 0: new_file = os.path.join(args.gcpath, cur_file) - assert(cur_file not in top_fnames) for submodule_name in childs_to_update: if (submodule_name + ".sv") in common_fnames: From 07e19e5bb80f5fff0f5feb05c910c3515c06b782 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 11:56:12 -0700 Subject: [PATCH 094/184] Increase debug module data capacity --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 1 + .../src/main/scala/config/fragments/PeripheralFragments.scala | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 5611dad5..ef02f468 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -48,6 +48,7 @@ class AbstractConfig extends Config( new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM + new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 7ac7f569..56cd3bb6 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -87,3 +87,7 @@ class WithExtMemIdBits(n: Int) extends Config((site, here, up) => { class WithNoPLIC extends Config((site, here, up) => { case PLICKey => None }) + +class WithDebugModuleAbstractDataWords(words: Int = 16) extends Config((site, here, up) => { + case DebugModuleKey => up(DebugModuleKey).map(_.copy(nAbstractDataWords=words)) +}) From 83dda916dc93df1f8841d975a9d271077bc5f3aa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 13:19:16 -0700 Subject: [PATCH 095/184] Support vector state in checkpoints --- scripts/generate-ckpt.sh | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/scripts/generate-ckpt.sh b/scripts/generate-ckpt.sh index 9e8381ba..1ba83b12 100755 --- a/scripts/generate-ckpt.sh +++ b/scripts/generate-ckpt.sh @@ -11,6 +11,7 @@ usage() { echo " -b : Binary to run in spike" echo " -p : PC to take checkpoint at [default 0x80000000]" echo " -c : Cycles after PC to take checkpoint at [default 0]" + echo " -m : ISA to pass to spike for checkpoint generation [defualt rv64gc]" exit "$1" } @@ -18,6 +19,7 @@ NHARTS=1 BINARY="" PC="0x80000000" CYCLES=0 +ISA="rv64gc" while [ "$1" != "" ]; do case $1 in @@ -35,6 +37,9 @@ do -c ) shift CYCLES=$1 ;; + -m ) + shift + ISA=$1 ;; * ) error "Invalid option $1" usage 1 ;; @@ -42,7 +47,7 @@ do shift done BASEMEM="$((0x80000000)):$((0x10000000))" -SPIKEFLAGS="-p$NHARTS --pmpregions=0 --isa=rv64gc -m$BASEMEM" +SPIKEFLAGS="-p$NHARTS --pmpregions=0 --isa=$ISA -m$BASEMEM" BASENAME=$(basename -- $BINARY) DIRNAME=$BASENAME.$PC.$CYCLES.loadarch @@ -54,6 +59,7 @@ LOADARCH_FILE=$DIRNAME/loadarch RAWMEM_ELF=$DIRNAME/raw.elf LOADMEM_ELF=$DIRNAME/mem.elf CMDS_FILE=$DIRNAME/cmds_tmp.txt +SPIKECMD_FILE=$DIRNAME/spikecmd.sh echo "Generating state capture spike interactive commands in $CMDS_FILE" echo "until pc 0 $PC" >> $CMDS_FILE @@ -65,6 +71,12 @@ do echo "priv $h" >> $CMDS_FILE echo "reg $h fcsr" >> $CMDS_FILE + echo "reg $h vstart" >> $CMDS_FILE + echo "reg $h vxsat" >> $CMDS_FILE + echo "reg $h vxrm" >> $CMDS_FILE + echo "reg $h vcsr" >> $CMDS_FILE + echo "reg $h vtype" >> $CMDS_FILE + echo "reg $h stvec" >> $CMDS_FILE echo "reg $h sscratch" >> $CMDS_FILE echo "reg $h sepc" >> $CMDS_FILE @@ -97,14 +109,18 @@ do do echo "reg $h $xr" >> $CMDS_FILE done + echo "vreg $h" >> $CMDS_FILE done echo "quit" >> $CMDS_FILE #cat $CMDS_FILE +echo "spike -d --debug-cmd=$CMDS_FILE $SPIKEFLAGS $BINARY" > $SPIKECMD_FILE + echo "Capturing state at checkpoint to spikeout" spike -d --debug-cmd=$CMDS_FILE $SPIKEFLAGS $BINARY 2> $LOADARCH_FILE + echo "Finding tohost/fromhost in elf file" TOHOST=$(riscv64-unknown-elf-nm $BINARY | grep tohost | head -c 16) FROMHOST=$(riscv64-unknown-elf-nm $BINARY | grep fromhost | head -c 16) From a7a441b6a8331951c917f816634f0c047608c3b2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 13:25:19 -0700 Subject: [PATCH 096/184] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index c2457e6b..efaa073f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit c2457e6b3c9197eb9d29d71fd893e102278384d3 +Subproject commit efaa073f5b7cd1d6e976a67591243b3d6298d0af From 8c47f50a73f08968940905093b08a87a66d70db2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 14:07:37 -0700 Subject: [PATCH 097/184] Restore vector state as well for cosim loadarch --- .../chipyard/src/main/resources/csrc/cospike.cc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index 66b2cd29..1c6cd58f 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -189,7 +189,14 @@ extern "C" void cospike_cosim(long long int cycle, loadarch_state_t &ls = dtm->loadarch_state[hartid]; s->pc = ls.pc; s->prv = ls.prv; + s->csrmap[CSR_MSTATUS]->write(s->csrmap[CSR_MSTATUS]->read() | MSTATUS_VS | MSTATUS_XS | MSTATUS_FS); #define RESTORE(CSRID, csr) s->csrmap[CSRID]->write(ls.csr); + RESTORE(CSR_FCSR , fcsr); + RESTORE(CSR_VSTART , vstart); + RESTORE(CSR_VXSAT , vxsat); + RESTORE(CSR_VXRM , vxrm); + RESTORE(CSR_VCSR , vcsr); + RESTORE(CSR_VTYPE , vtype); RESTORE(CSR_STVEC , stvec); RESTORE(CSR_SSCRATCH , sscratch); RESTORE(CSR_SEPC , sepc); @@ -208,9 +215,18 @@ extern "C" void cospike_cosim(long long int cycle, RESTORE(CSR_MIP , mip); RESTORE(CSR_MCYCLE , mcycle); RESTORE(CSR_MINSTRET , minstret); + if (ls.VLEN != p->VU.VLEN) { + printf("VLEN mismatch loadarch: $d != spike: $d\n", ls.VLEN, p->VU.VLEN); + abort(); + } + if (ls.ELEN != p->VU.ELEN) { + printf("ELEN mismatch loadarch: $d != spike: $d\n", ls.ELEN, p->VU.ELEN); + abort(); + } for (size_t i = 0; i < 32; i++) { s->XPR.write(i, ls.XPR[i]); s->FPR.write(i, { (uint64_t)ls.FPR[i], (uint64_t)-1 }); + memcpy(p->VU.reg_file + i * ls.VLEN / 8, ls.VPR[i], ls.VLEN / 8); } spike_loadarch_done = true; p->clear_waiting_for_interrupt(); From ad9ea333d1dfa8f6cef4da5401eb086a42dffb94 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 10 Apr 2023 15:35:53 -0700 Subject: [PATCH 098/184] Bump TestChipIp to improve default serial_tl behavior --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 1 - generators/testchipip | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index fa08acf7..2d6cb206 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -39,7 +39,6 @@ class ChipLikeQuadRocketConfig extends Config( new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS - new testchipip.WithSerialTLAsyncResetQueue ++ // Add Async reset queue to block ready while in reset new chipyard.config.AbstractConfig) diff --git a/generators/testchipip b/generators/testchipip index aa9170af..0d943d04 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit aa9170afe133e74e1c66b0082dc943e272d9e6f0 +Subproject commit 0d943d04b5510a3ee86f5145db6a4de80987bc5e From c6bf50bc9d166946cd4af37c4abb9c595d19562e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 16:20:52 -0700 Subject: [PATCH 099/184] Update verilator's emulator.cc SIM_FILE_REQS --- generators/testchipip | 2 +- sims/verilator/Makefile | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/testchipip b/generators/testchipip index efaa073f..e830ecf6 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit efaa073f5b7cd1d6e976a67591243b3d6298d0af +Subproject commit e830ecf6ca591370ae818a6a8aa139d0676b801a diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index d48da28e..96f37237 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -60,7 +60,8 @@ SIM_FILE_REQS += \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_dtm.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_dtm.h \ $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc From 4038217ae9078362712e3370063c16d5214f25de Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 17:56:44 -0700 Subject: [PATCH 100/184] Serial-TL backing memory configs should use 1 memory channel --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 1 + generators/chipyard/src/main/scala/config/RocketConfigs.scala | 1 + 2 files changed, 2 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 7f875584..d98cf490 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -24,6 +24,7 @@ class ChipLikeQuadRocketConfig extends Config( new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness new chipyard.config.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel //================================== // Set up clock./reset diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 8ed4acdc..965a81fc 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -125,6 +125,7 @@ class MulticlockAXIOverSerialConfig extends Config( new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory new freechips.rocketchip.subsystem.WithNBigCores(2) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel new chipyard.config.AbstractConfig) // DOC include end: MulticlockAXIOverSerialConfig From cf87641031e59305683684a840bb05b1171445db Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 18 Apr 2023 09:50:16 -0700 Subject: [PATCH 101/184] Fix LOADARCH CI tests --- .github/scripts/run-tests.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 9938ca43..8448be9a 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -34,11 +34,11 @@ case $1 in ;; chipyard-dmirocket) $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -c 10000 - make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=dhrystone.riscv.0x80000000.10000.loadarch + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch ;; chipyard-boom) $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -c 10000 - make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=dhrystone.riscv.0x80000000.10000.loadarch + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch ;; chipyard-spike) run_bmark ${mapping[$1]} From 383a0fee964a08c659661321bb14f3a9b605104b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 19 Apr 2023 11:44:20 -0700 Subject: [PATCH 102/184] Bump testchipip to standardize tlserdes bundle params --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 0d943d04..efdef967 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 0d943d04b5510a3ee86f5145db6a4de80987bc5e +Subproject commit efdef967720ac836cf007f361371f095fbdce4ea From 104a5299a972b5b5ed105f60559c622348580518 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 19 Apr 2023 19:52:46 -0700 Subject: [PATCH 103/184] Fix typos --- docs/Simulation/Software-RTL-Simulation.rst | 7 ++++++- .../src/main/scala/HarnessBinders.scala | 2 +- scripts/generate-ckpt.sh | 18 ++++++++---------- variables.mk | 2 ++ 4 files changed, 17 insertions(+), 12 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 754fa2bb..580a5d2e 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -156,7 +156,12 @@ Loadmem files should be ELF files. In the most common use case, this can be the .. code-block:: shell make run-binary BINARY=test.riscv LOADMEM=test.riscv - make run-binary BINART=test.riscv LOADMEM=1 + +Usually the ``LOADMEM`` ELF is the same as the ``BINARY`` ELF, so ``LOADMEM=1`` can be used as a shortcut. + +.. code-block:: shell + + make run-binary BINARY=test.riscv LOADMEM=1 Generating Waveforms ----------------------- diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 3e43dfe6..3f167aa3 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -185,7 +185,7 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBind (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => - // TODO FIX: This currently makes each SimDRAM contian the entire memory space + // TODO FIX: This currently makes each SimDRAM contain the entire memory space val memSize = p(ExtMem).get.master.size val memBase = p(ExtMem).get.master.base val lineSize = p(CacheBlockBytes) diff --git a/scripts/generate-ckpt.sh b/scripts/generate-ckpt.sh index 1ba83b12..98cb215e 100755 --- a/scripts/generate-ckpt.sh +++ b/scripts/generate-ckpt.sh @@ -7,18 +7,18 @@ usage() { echo "" echo "Options" echo " --help -h : Display this message" - echo " -n : Mumber of harts" + echo " -n : Number of harts" echo " -b : Binary to run in spike" echo " -p : PC to take checkpoint at [default 0x80000000]" - echo " -c : Cycles after PC to take checkpoint at [default 0]" - echo " -m : ISA to pass to spike for checkpoint generation [defualt rv64gc]" + echo " -i : Instructions after PC to take checkpoint at [default 0]" + echo " -m : ISA to pass to spike for checkpoint generation [default rv64gc]" exit "$1" } NHARTS=1 BINARY="" PC="0x80000000" -CYCLES=0 +INSNS=0 ISA="rv64gc" while [ "$1" != "" ]; do @@ -34,9 +34,9 @@ do -p ) shift PC=$1 ;; - -c ) + -i ) shift - CYCLES=$1 ;; + INSNS=$1 ;; -m ) shift ISA=$1 ;; @@ -50,7 +50,7 @@ BASEMEM="$((0x80000000)):$((0x10000000))" SPIKEFLAGS="-p$NHARTS --pmpregions=0 --isa=$ISA -m$BASEMEM" BASENAME=$(basename -- $BINARY) -DIRNAME=$BASENAME.$PC.$CYCLES.loadarch +DIRNAME=$BASENAME.$PC.$INSNS.loadarch echo "Generating loadarch directory $DIRNAME" rm -rf $DIRNAME mkdir -p $DIRNAME @@ -63,7 +63,7 @@ SPIKECMD_FILE=$DIRNAME/spikecmd.sh echo "Generating state capture spike interactive commands in $CMDS_FILE" echo "until pc 0 $PC" >> $CMDS_FILE -echo "rs $CYCLES" >> $CMDS_FILE +echo "rs $INSNS" >> $CMDS_FILE echo "dump" >> $CMDS_FILE for (( h=0; h<$NHARTS; h++ )) do @@ -113,8 +113,6 @@ do done echo "quit" >> $CMDS_FILE -#cat $CMDS_FILE - echo "spike -d --debug-cmd=$CMDS_FILE $SPIKEFLAGS $BINARY" > $SPIKECMD_FILE echo "Capturing state at checkpoint to spikeout" diff --git a/variables.mk b/variables.mk index 8a329052..b09264b5 100644 --- a/variables.mk +++ b/variables.mk @@ -25,6 +25,8 @@ HELP_PROJECT_VARIABLES = \ HELP_SIMULATION_VARIABLES = \ " BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \ +" LOADMEM = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \ +" LOADARCH = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \ " VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \ " timeout_cycles = number of clock cycles before simulator times out, defaults to 10000000" \ " bmark_timeout_cycles = number of clock cycles before benchmark simulator times out, defaults to 100000000" From 4a712a7de5252926bb039d97b56db288b90d7f29 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 19 Apr 2023 20:09:14 -0700 Subject: [PATCH 104/184] Add doc page on architectural checkpoints --- .../Architectural-Checkpoints.rst | 39 +++++++++++++++++++ docs/Advanced-Concepts/index.rst | 1 + 2 files changed, 40 insertions(+) create mode 100644 docs/Advanced-Concepts/Architectural-Checkpoints.rst diff --git a/docs/Advanced-Concepts/Architectural-Checkpoints.rst b/docs/Advanced-Concepts/Architectural-Checkpoints.rst new file mode 100644 index 00000000..490bddc5 --- /dev/null +++ b/docs/Advanced-Concepts/Architectural-Checkpoints.rst @@ -0,0 +1,39 @@ +.. _checkpointing: + +Architectural Checkpoints +========================= + +Chipyard supports generating architectural checkpoints using Spike. +These checkpoints contain a snapshot of the architectural state of a RISC-V SoC at some point in the execution of a program. +The checkpoints include the contents of cacheable memory, core architectural registers, and core CSRs. +RTL simulations of SoCs can resume execution from checkpoints after restoring the architectural state. + +.. note:: + Currently, only checkpoints of single-core systems are supported + +Generating Checkpoints +------------------------ + +``scripts/generate-ckpt.sh`` is a script that runs spike with the right commands to generate an architectural checkpoint +``scripts/generate-ckpt.sh -h`` lists options for checkpoint generation. + +Example: run the ``hello.riscv`` binary for 1000 instructions before generating a checkpoint. +This should produce a directory named ``hello.riscv.0x80000000.1000.loadarch`` + +.. code:: + + scripts/generate-ckpt.sh -b tests/hello.riscv -i 1000 + + +Loading Checkpoints in RTL Simulation +-------------------------------------- + +Checkpoints can be loaded in RTL simulations with the ``LOADARCH`` flag. +The target config **MUST** use dmi-based bringup (as opposed to the default TSI-based bringup), and support fast ``LOADMEM``. +The target config should also match the architectural configuration of however spike was configured when generating the checkpoint. + +.. code:: + + cd sims/vcs + make CONFIG=dmiRocketConfig run-binary LOADARCH=../../hello.riscv.0x80000000.1000.loadarch + diff --git a/docs/Advanced-Concepts/index.rst b/docs/Advanced-Concepts/index.rst index b67bbbb3..d5455ddb 100644 --- a/docs/Advanced-Concepts/index.rst +++ b/docs/Advanced-Concepts/index.rst @@ -16,3 +16,4 @@ They expect you to know about Chisel, Parameters, configs, etc. CDEs Harness-Clocks Managing-Published-Scala-Dependencies + Architectural-Checkpoints From a31b061770fb8e7a81f3ca8b14e9a4973ec91be6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 19 Apr 2023 23:37:44 -0700 Subject: [PATCH 105/184] CI: Fix checkpoint generation --- .github/scripts/run-tests.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 8448be9a..0f5cb517 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -33,11 +33,11 @@ case $1 in run_bmark ${mapping[$1]} ;; chipyard-dmirocket) - $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -c 10000 + $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000 make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch ;; chipyard-boom) - $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -c 10000 + $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000 make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch ;; chipyard-spike) From 6a4e2f583dd55b75f1c41f8d4060b9b48413c72e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 19 Apr 2023 23:43:43 -0700 Subject: [PATCH 106/184] Add output directory flag to loadarch generate script --- scripts/generate-ckpt.sh | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/scripts/generate-ckpt.sh b/scripts/generate-ckpt.sh index 98cb215e..0f8b1e8b 100755 --- a/scripts/generate-ckpt.sh +++ b/scripts/generate-ckpt.sh @@ -3,7 +3,7 @@ set -e usage() { - echo "Usage: $0 [OPTIONS] -- [SPIKEFLAGS]" + echo "Usage: $0 [OPTIONS]" echo "" echo "Options" echo " --help -h : Display this message" @@ -12,6 +12,7 @@ usage() { echo " -p : PC to take checkpoint at [default 0x80000000]" echo " -i : Instructions after PC to take checkpoint at [default 0]" echo " -m : ISA to pass to spike for checkpoint generation [default rv64gc]" + echo " -o : Output directory to store the checkpoint in. [default ...loadarch]" exit "$1" } @@ -20,6 +21,7 @@ BINARY="" PC="0x80000000" INSNS=0 ISA="rv64gc" +OUTPATH="" while [ "$1" != "" ]; do case $1 in @@ -40,26 +42,33 @@ do -m ) shift ISA=$1 ;; + -o ) + shift + OUTPATH=$1 ;; * ) error "Invalid option $1" usage 1 ;; esac shift done + BASEMEM="$((0x80000000)):$((0x10000000))" SPIKEFLAGS="-p$NHARTS --pmpregions=0 --isa=$ISA -m$BASEMEM" - BASENAME=$(basename -- $BINARY) -DIRNAME=$BASENAME.$PC.$INSNS.loadarch -echo "Generating loadarch directory $DIRNAME" -rm -rf $DIRNAME -mkdir -p $DIRNAME -LOADARCH_FILE=$DIRNAME/loadarch -RAWMEM_ELF=$DIRNAME/raw.elf -LOADMEM_ELF=$DIRNAME/mem.elf -CMDS_FILE=$DIRNAME/cmds_tmp.txt -SPIKECMD_FILE=$DIRNAME/spikecmd.sh +if [ -z "$OUTPATH" ] ; then + OUTPATH=$BASENAME.$PC.$INSNS.loadarch +fi + +echo "Generating loadarch directory $OUTPATH" +rm -rf $OUTPATH +mkdir -p $OUTPATH + +LOADARCH_FILE=$OUTPATH/loadarch +RAWMEM_ELF=$OUTPATH/raw.elf +LOADMEM_ELF=$OUTPATH/mem.elf +CMDS_FILE=$OUTPATH/cmds_tmp.txt +SPIKECMD_FILE=$OUTPATH/spikecmd.sh echo "Generating state capture spike interactive commands in $CMDS_FILE" echo "until pc 0 $PC" >> $CMDS_FILE @@ -129,3 +138,4 @@ rm -rf mem.0x80000000.bin riscv64-unknown-elf-ld -Tdata=0x80000000 -nmagic --defsym tohost=0x$TOHOST --defsym fromhost=0x$FROMHOST -o $LOADMEM_ELF $RAWMEM_ELF rm -rf $RAWMEM_ELF + From 9f9478c10e2fe219d75c9740817030bc05b6fc58 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 19 Apr 2023 23:47:27 -0700 Subject: [PATCH 107/184] Add both dmiBoom and normalBoom tests to CI --- .github/scripts/defaults.sh | 5 +++-- .github/scripts/run-tests.sh | 3 +++ .github/workflows/chipyard-run-tests.yml | 24 ++++++++++++++++++++++++ 3 files changed, 30 insertions(+), 2 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 1f75ed08..176d20d5 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -29,7 +29,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone" -grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike" +grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike" grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -45,7 +45,8 @@ mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig" mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig" mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" -mapping["chipyard-boom"]=" CONFIG=dmiMediumBoomCosimConfig" +mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig" +mapping["chipyard-dmiboom"]=" CONFIG=dmiMediumBoomCosimConfig" mapping["chipyard-spike"]=" CONFIG=SpikeFastUARTConfig EXTRA_SIM_FLAGS='+spike-ipc=10'" mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 0f5cb517..d08614d7 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -37,6 +37,9 @@ case $1 in make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch ;; chipyard-boom) + run_bmark ${mapping[$1]} + ;; + chipyard-dmiboom) $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000 make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index f7917e92..d357637c 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -603,6 +603,29 @@ jobs: group-key: "group-peripherals" project-key: "chipyard-dmirocket" + chipyard-dmiboom-run-tests: + name: chipyard-dmiboom-run-tests + needs: prepare-chipyard-peripherals + runs-on: self-hosted + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-peripherals" + project-key: "chipyard-dmiboom" + chipyard-spiflashwrite-run-tests: name: chipyard-spiflashwrite-run-tests needs: prepare-chipyard-peripherals @@ -944,6 +967,7 @@ jobs: chipyard-cva6-run-tests, chipyard-ibex-run-tests, chipyard-sodor-run-tests, + chipyard-dmiboom-run-tests, chipyard-dmirocket-run-tests, chipyard-spiflashwrite-run-tests, chipyard-manyperipherals-run-tests, From 6701b85f27d5e7ea240d947ed152e4b139e895b6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 19 Apr 2023 23:48:14 -0700 Subject: [PATCH 108/184] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index c8ae4395..b192ac11 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit c8ae43950b481a9368d32a2e4bc0a5aaaa3c5e70 +Subproject commit b192ac11d2e88579f9d1329578e88de5c5c1fde4 From b6e6997d1e6f6f32f47fa744730997277c0388b7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Apr 2023 11:56:36 -0700 Subject: [PATCH 109/184] Add tutorial software --- software/tutorial/.gitignore | 1 + software/tutorial/build.sh | 21 +++++++++++++++++++ .../marshal-configs/mobilenet-baremetal.yaml | 8 +++++++ .../marshal-configs/resnet50-baremetal.yaml | 8 +++++++ .../resnet50-linux-interactive.yaml | 8 +++++++ .../marshal-configs/resnet50-linux.yaml | 9 ++++++++ 6 files changed, 55 insertions(+) create mode 100644 software/tutorial/.gitignore create mode 100755 software/tutorial/build.sh create mode 100644 software/tutorial/marshal-configs/mobilenet-baremetal.yaml create mode 100644 software/tutorial/marshal-configs/resnet50-baremetal.yaml create mode 100644 software/tutorial/marshal-configs/resnet50-linux-interactive.yaml create mode 100644 software/tutorial/marshal-configs/resnet50-linux.yaml diff --git a/software/tutorial/.gitignore b/software/tutorial/.gitignore new file mode 100644 index 00000000..08047cf6 --- /dev/null +++ b/software/tutorial/.gitignore @@ -0,0 +1 @@ +overlay diff --git a/software/tutorial/build.sh b/software/tutorial/build.sh new file mode 100755 index 00000000..d84c5c3b --- /dev/null +++ b/software/tutorial/build.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +set -ex + +CYDIR=$(git rev-parse --show-toplevel) +G_DIR=$CYDIR/generators/gemmini/software/gemmini-rocc-tests +O_DIR=$CYDIR/software/tutorial/overlay/root + +echo "Building Gemmini RoCC tests" +cd $G_DIR + +./build.sh imagenet +cd build +rm -rf $O_DIR +mkdir -p $O_DIR +cp -r imagenet/resnet50-baremetal $O_DIR/ +cp -r imagenet/resnet50-linux $O_DIR/ +cp -r imagenet/mobilenet-baremetal $O_DIR/ +cp -r imagenet/mobilenet-linux $O_DIR/ + +echo "Complete!" diff --git a/software/tutorial/marshal-configs/mobilenet-baremetal.yaml b/software/tutorial/marshal-configs/mobilenet-baremetal.yaml new file mode 100644 index 00000000..3b2df3e6 --- /dev/null +++ b/software/tutorial/marshal-configs/mobilenet-baremetal.yaml @@ -0,0 +1,8 @@ +{ + "name" : "mobilenet-baremetal", + "base" : "bare-base.json", + "workdir" : "..", + "host-init" : "build.sh", + "bin" : "overlay/root/mobilenet-baremetal", + "spike-args" : "--extension=gemmini" +} diff --git a/software/tutorial/marshal-configs/resnet50-baremetal.yaml b/software/tutorial/marshal-configs/resnet50-baremetal.yaml new file mode 100644 index 00000000..f4b00630 --- /dev/null +++ b/software/tutorial/marshal-configs/resnet50-baremetal.yaml @@ -0,0 +1,8 @@ +{ + "name" : "resnet50-baremetal", + "base" : "bare-base.json", + "workdir" : "..", + "host-init" : "build.sh", + "bin" : "overlay/root/resnet50-baremetal", + "spike-args" : "--extension=gemmini" +} diff --git a/software/tutorial/marshal-configs/resnet50-linux-interactive.yaml b/software/tutorial/marshal-configs/resnet50-linux-interactive.yaml new file mode 100644 index 00000000..4dff0843 --- /dev/null +++ b/software/tutorial/marshal-configs/resnet50-linux-interactive.yaml @@ -0,0 +1,8 @@ +{ + "name" : "resnet50-linux-interactive", + "base" : "br-base.json", + "workdir" : "..", + "host-init" : "build.sh", + "overlay" : "overlay", + "spike-args" : "--extension=gemmini" +} diff --git a/software/tutorial/marshal-configs/resnet50-linux.yaml b/software/tutorial/marshal-configs/resnet50-linux.yaml new file mode 100644 index 00000000..372e1e2b --- /dev/null +++ b/software/tutorial/marshal-configs/resnet50-linux.yaml @@ -0,0 +1,9 @@ +{ + "name" : "resnet50-linux", + "base" : "br-base.json", + "workdir" : "..", + "host-init" : "build.sh", + "overlay" : "overlay", + "command" : "/root/resnet50-linux", + "spike-args" : "--extension=gemmini" +} From d9d1efd6b3c8cfa4fa2b5d53513ae664d4e9a8a7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Apr 2023 12:03:24 -0700 Subject: [PATCH 110/184] Update FS --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 8c85960b..8c301ad5 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 8c85960b939a0090de30a31936981972874d979d +Subproject commit 8c301ad57ba962bf61838308b09121fcda6e190c From 2bf8f258adf175b929a04e0493b665830a681b8b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Apr 2023 13:22:19 -0700 Subject: [PATCH 111/184] Bump Gemmini --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 965ea0b3..80e7376c 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 965ea0b3c5ffd7b68e6bf5a50ea9ff0750a5b988 +Subproject commit 80e7376cf554ed302975d72ed091ac86a9e553e8 From e2cf26ed9351d5cabfc481e99711dc30af4d0db2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Apr 2023 13:27:36 -0700 Subject: [PATCH 112/184] Bump Changelog --- CHANGELOG.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3644fa29..6867e1d2 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,30 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.9.1] - 2023-04-21 + +Various fixes for Linux boot, More Chip/bringup examples, Chisel 3.5.6 bump + +### Added +* QoL improvement to IOBinders + custom ChipTop example by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1399 +* PLL integration example + FlatChipTop/TestHarness by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1427 +* Bump TestChipIp to improve default serial_tl behavior by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1435 +* Bump testchipip to standardize TL serdesser bundle params by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1446 + +### Changed +* New Scala-based Config Finder by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1424 +* Bump to latest rocket-chip/chisel3.5.6 by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1411 +* Resolve merge conflicts in chisel3.5.6 bump by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1430 +* bump testchipip by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1434 +* ADD: improve Makefile in tests/, add explicit arch flags by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1439 +* Various submodule bumps by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1448 + +### Fixed +* Various improvements and fixes by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1420 +* Ensure conda cleanup regex properly filters out non-numeric chars by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1425 +* Fix ChipLikeQuadRocketConfig crossing by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1436 +* Uniquify module names that are common to Top & Model by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1442 + ## [1.9.0] - 2023-03-23 Faster FIRRTL build support work CIRCT. New software support for RISC-V GCC12 and Linux 6.2. Various bumps and fixes of all submodules. From 9ce0467bd3808b133ce8c1eb0b6548bce468b007 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 20 Apr 2023 14:26:38 -0700 Subject: [PATCH 113/184] fixes --- common.mk | 5 ++- scripts/uniqify-module-names.py | 68 ++++++++++++++++----------------- variables.mk | 1 + vlsi/sim.mk | 2 +- 4 files changed, 38 insertions(+), 38 deletions(-) diff --git a/common.mk b/common.mk index ed02a10e..e507140a 100644 --- a/common.mk +++ b/common.mk @@ -248,6 +248,7 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL --mod-filelist $(MODEL_MODS_FILELIST) \ --gen-collateral-path $(GEN_COLLATERAL_DIR) \ --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ + --out-model-hier-json $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) \ --dut $(TOP) sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST) @@ -259,10 +260,10 @@ $(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) &: $(BB_MODS_FILELIST) $(MFC_T --out-top-bb-f $(TOP_BB_MODS_FILELIST) \ --out-model-bb-f $(MODEL_BB_MODS_FILELIST) -$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JSON) +$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) $(base_dir)/scripts/split-mems-conf.py \ --in-smems-conf $(MFC_SMEMS_CONF) \ - --in-model-hrchy-json $(MFC_MODEL_HRCHY_JSON) \ + --in-model-hrchy-json $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) \ --dut-module-name $(TOP) \ --model-module-name $(MODEL) \ --out-dut-smems-conf $(TOP_SMEMS_CONF) \ diff --git a/scripts/uniqify-module-names.py b/scripts/uniqify-module-names.py index d6fd6929..858c0a19 100755 --- a/scripts/uniqify-module-names.py +++ b/scripts/uniqify-module-names.py @@ -5,7 +5,7 @@ import argparse import shutil import os import sh - +import datetime parser = argparse.ArgumentParser(description="") @@ -13,28 +13,35 @@ parser.add_argument("--top-filelist", type=str, required=True, help="Abs path to parser.add_argument("--mod-filelist", type=str, required=True, help="Abs path to ..model.f") parser.add_argument("--gen-collateral-path", dest="gcpath", type=str, required=True, help="Abs path to the gen-collateral directory") parser.add_argument("--model-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") +parser.add_argument("--out-model-hier-json", type=str, required=True, help="Path to updated hierarchy JSON emitted by this script.") parser.add_argument('--dut', type=str, required=True, help='Name of the DUT module.') args = parser.parse_args() +MODEL_SFX=str(datetime.date.today().year) + +def bash(cmd): + fail = os.system(cmd) + if fail: + print(f'[*] failed to execute {cmd}') + sys.exit(1) + else: + print(cmd) + def get_filelist(filelist): - f = open(filelist, "r") - lines = f.readlines() - f.close() - fnames = [] - for line in lines: - try: - fname = line.split("/")[-1].replace("\n", "") - fnames.append(fname) - except: - print(f"Something is wrong about this line {line}") - + with open(filelist) as f: + lines = f.readlines() + for line in lines: + try: + fname = line.split("/")[-1].strip() + fnames.append(fname) + except: + print(f"Something is wrong about this line '{line}'") return fnames def update_filelist(cur_file, new_file): - sh.sed("-i", f"s/\b{cur_file}\b/{new_file}/", os.path.join(args.gcpath, args.mod_filelist)) - + bash(f"echo \"{args.gcpath}/{new_file}\" >> {os.path.join(args.gcpath, args.mod_filelist)}") def generate_copy(c, sfx): (cur_name, ext) = os.path.splitext(c) @@ -45,23 +52,20 @@ def generate_copy(c, sfx): new_file = os.path.join(args.gcpath, new_file) shutil.copy(cur_file, new_file) - sh.sed("-i", f"s/\b{cur_name}\b/{new_name}/", new_file) + bash(f"sed -i s/\"module {cur_name}\"/\"module {new_name}\"/ {new_file}") return new_file - - -def dfs_update_modules(tree, common_fnames, visited, top_fnames, updated_modules): +def dfs_update_modules(tree, common_fnames, visited, top_fnames): # List of direct submodules to update childs_to_update = list() for child in tree['instances']: # We don't have to change stuff that are under the dut if (child['module_name'] == args.dut) or (child['module_name'] in visited): continue - if dfs_update_modules(child, common_fnames, visited, top_fnames, updated_modules): + if dfs_update_modules(child, common_fnames, visited, top_fnames): childs_to_update.append(child['module_name']) if (child['module_name'] + ".sv") in common_fnames: - child['module_name'] = child['module_name'] + "_Model" - updated_modules.append(child['module_name']) + child['module_name'] = child['module_name'] + "_" + MODEL_SFX cur_module = tree['module_name'] cur_file = cur_module + ".sv" @@ -69,7 +73,7 @@ def dfs_update_modules(tree, common_fnames, visited, top_fnames, updated_modules # cur_file is in the common list, generate a new file if cur_file in common_fnames: - new_file = generate_copy(cur_file, "Model") + new_file = generate_copy(cur_file, MODEL_SFX) update_filelist(cur_file, os.path.basename(new_file)) # has some child to update, but new_file wasn't generated @@ -78,29 +82,23 @@ def dfs_update_modules(tree, common_fnames, visited, top_fnames, updated_modules for submodule_name in childs_to_update: if (submodule_name + ".sv") in common_fnames: - sh.sed("-i", f"s/\b{submodule_name}\b/{submodule_name}_Model/", new_file) + bash(f"sed -i s/\"{submodule_name}\"/\"{submodule_name}_{MODEL_SFX}\"/ {new_file}") visited.add(cur_module) return (new_file is not None) - def main(): top_fnames = set(get_filelist(args.top_filelist)) mod_fnames = set(get_filelist(args.mod_filelist)) common_fnames = top_fnames.intersection(mod_fnames) - imhj = open(args.model_hier_json, "r") - imhj_data = json.load(imhj) - - visited = set() - updated_modules = list() - dfs_update_modules(imhj_data, common_fnames, visited, top_fnames, updated_modules) - - out_file = open(args.model_hier_json, "w") - json.dump(imhj_data, out_file, indent=2) - out_file.close() - + with open(args.model_hier_json) as imhj: + imhj_data = json.load(imhj) + with open(args.out_model_hier_json, "w+") as out_file: + visited = set() + dfs_update_modules(imhj_data, common_fnames, visited, top_fnames) + json.dump(imhj_data, out_file, indent=2) if __name__ == "__main__": main() diff --git a/variables.mk b/variables.mk index eb9620f2..1f659ac7 100644 --- a/variables.mk +++ b/variables.mk @@ -162,6 +162,7 @@ SFC_ANNO_FILE ?= $(build_dir)/$(long_name).sfc.anno.json # firtool compiler outputs MFC_TOP_HRCHY_JSON ?= $(build_dir)/top_module_hierarchy.json MFC_MODEL_HRCHY_JSON ?= $(build_dir)/model_module_hierarchy.json +MFC_MODEL_HRCHY_JSON_UNIQUIFIED ?= $(build_dir)/model_module_hierarchy.uniquified.json MFC_SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf # hardcoded firtool outputs MFC_FILELIST = $(GEN_COLLATERAL_DIR)/filelist.f diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 1f5b530d..13a7fcc3 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files) echo " top_module: $(VLSI_TOP)" >> $@ echo " tb_name: ''" >> $@ # don't specify -top echo " input_files:" >> $@ - for x in $$(comm -23 <(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) <(sort $(VLSI_RTL))) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ + for x in $$(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@ From 482f91d0e5707c8538e8ba5696886d837c8a5f83 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Apr 2023 14:48:54 -0700 Subject: [PATCH 114/184] Clear screen on prompt [ci skip] --- scripts/build-setup.sh | 1 + scripts/init-submodules-no-riscv-tools-nolog.sh | 1 + 2 files changed, 2 insertions(+) diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index aa78942b..262b3a19 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -91,6 +91,7 @@ run_step() { # Check for this, since many users will be attempting to use this with gemmini if [ $TOOLCHAIN_TYPE == "esp-tools" ]; then while true; do + printf '\033[2J' read -p "WARNING: You are trying to install the esp-tools toolchain."$'\n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate case "$validate" in y | Y) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 3f939bc2..b3426288 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -65,6 +65,7 @@ restore_bash_options if [ "$git_tag_rc" -ne 0 ]; then if [ "$FORCE" == false ]; then while true; do + printf '\033[2J' read -p "WARNING: You are not on an official release of Chipyard."$'\n'"Type \"y\" to continue if this is intended or \"n\" if not: " validate case "$validate" in y | Y) From 91ccc7b25de72f1003c2210c6d700b2e3b300838 Mon Sep 17 00:00:00 2001 From: Tianrui Wei Date: Thu, 20 Apr 2023 15:34:53 -0700 Subject: [PATCH 115/184] feat: cospike changes Signed-off-by: Tianrui Wei --- .../src/main/resources/csrc/cospike.cc | 199 ++++++++++++------ 1 file changed, 137 insertions(+), 62 deletions(-) diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index 1c6cd58f..d637c45a 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -1,3 +1,4 @@ +#include #include #include #include @@ -5,6 +6,12 @@ #include #include #include +#include +#include +#include +#include +#include +#include #if __has_include ("cospike_dtm.h") #define COSPIKE_DTM @@ -72,10 +79,10 @@ extern "C" void cospike_cosim(long long int cycle, int raise_interrupt, unsigned long long int cause, unsigned long long int wdata, - int priv) + int priv) { assert(info); - if (!sim) { + if (unlikely(!sim)) { printf("Configuring spike cosim\n"); std::vector mem_cfg; std::vector hartids; @@ -87,7 +94,7 @@ extern "C" void cospike_cosim(long long int cycle, nullptr, info->isa.c_str(), "MSU", - "vlen:128,elen:64", + "vlen:512,elen:64", false, endianness_little, info->pmpregions, @@ -104,6 +111,27 @@ extern "C" void cospike_cosim(long long int cycle, uint64_t default_boot_addr = 0x80000000; boot_addr_reg->store(0, 8, (const uint8_t*)(&default_boot_addr)); + for (auto& mem : mems) { + if (mem.first == info->mem0_base) { + std::string path_name = "chipyard-cosim-" + std::to_string(getpid()); + ssize_t mem_size = mem.second->size(); + int shared_fd = shm_open(path_name.c_str(), O_EXCL | O_RDWR, 0600); + if (shared_fd < 0) { + std::perror("[mm_t] shm_open for backing storage failed"); + exit(-1); + } + uint8_t *data = (uint8_t *) mmap( + NULL, mem_size, PROT_READ|PROT_WRITE, MAP_SHARED|MAP_ANONYMOUS, shared_fd, 0); + if (data == MAP_FAILED) { + std::perror("[mm_t] mmap for backing storage failed"); + exit(-1); + } + mem.second->store(0, mem_size,(const uint8_t *) data); + munmap(data, mem_size); + close(shared_fd); + } + } + // Don't actually build a clint mem_t* clint_mem = new mem_t(CLINT_SIZE); @@ -144,7 +172,7 @@ extern "C" void cospike_cosim(long long int cycle, .support_impebreak = true }; - printf("%s\n", info->isa.c_str()); + printf("isa string is %s\n", info->isa.c_str()); for (int i = 0; i < htif_args.size(); i++) { printf("%s\n", htif_args[i].c_str()); } @@ -154,7 +182,7 @@ extern "C" void cospike_cosim(long long int cycle, plugin_devices, htif_args, dm_config, - nullptr, + "cospike.log", false, nullptr, false, @@ -174,6 +202,8 @@ extern "C" void cospike_cosim(long long int cycle, fromhost_addr = ((htif_t*)sim)->get_fromhost_addr(); printf("Tohost : %lx\n", tohost_addr); printf("Fromhost: %lx\n", fromhost_addr); + printf("Memory base : %lx\n", info->mem0_base); + printf("Memory Size : %lx\n", info->mem0_size); } if (priv & 0x4) { // debug @@ -253,76 +283,121 @@ extern "C" void cospike_cosim(long long int cycle, if (valid) { printf("%d Cosim: %lx", cycle, iaddr); if (has_wdata) { - printf(" %lx", wdata); + printf(" s: %lx", wdata); } printf("\n"); } if (valid || raise_interrupt || raise_exception) { p->step(1); +#ifdef SPIKE_DEBUG + printf("spike pc is %lx\n", s->pc); + printf("spike mstatus is %lx\n", s->mstatus->read()); + printf("spike mip is %lx\n", s->mip->read()); + printf("spike mie is %lx\n", s->mie->read()); +#endif } if (valid) { if (s_pc != iaddr) { - printf("%d PC mismatch spike:%lx != dut:%lx\n", cycle, s_pc, iaddr); + printf("%d PC mismatch spike %llx != DUT %llx\n", cycle, s_pc, iaddr); +#ifdef SPIKE_DEBUG + printf("spike mstatus is %lx\n", s->mstatus->read()); + printf("spike mcause is %lx\n", s->mcause->read()); + printf("spike mtval is %lx\n" , s->mtval->read()); + printf("spike mtinst is %lx\n", s->mtinst->read()); +#endif exit(1); } - // Try to remember magic_mem addrs, and ignore these in the future - auto& mem_write = s->log_mem_write; - if (!mem_write.empty() && tohost_addr && std::get<0>(mem_write[0]) == tohost_addr) { - reg_t wdata = std::get<1>(mem_write[0]); - if (wdata >= info->mem0_base && wdata < (info->mem0_base + info->mem0_size)) { - printf("Probable magic mem %x\n", wdata); - magic_addrs.insert(wdata); - } - } - if (has_wdata) { - auto& log = s->log_reg_write; - auto& mem_read = s->log_mem_read; - reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]); - for (auto regwrite : log) { - int rd = regwrite.first >> 4; - int type = regwrite.first & 0xf; - // 0 => int - // 1 => fp - // 2 => vec - // 3 => vec hint - // 4 => csr - if ((rd != 0 && type == 0) || type == 1) { - // Override reads from some CSRs - uint64_t csr_addr = (insn >> 20) & 0xfff; - bool csr_read = (insn & 0x7f) == 0x73; - if (csr_read) printf("CSR read %lx\n", csr_addr); - if (csr_read && ( - (csr_addr == 0x301) || // misa - (csr_addr == 0xf13) || // mimpid - (csr_addr == 0xf12) || // marchid - (csr_addr == 0xf11) || // mvendorid - (csr_addr == 0xb00) || // mcycle - (csr_addr == 0xb02) || // minstret - (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr - )) { - printf("CSR override\n"); - s->XPR.write(rd, wdata); - } else if (!mem_read.empty() && ((magic_addrs.count(mem_read_addr) || - (tohost_addr && mem_read_addr == tohost_addr) || - (fromhost_addr && mem_read_addr == fromhost_addr) || - (CLINT_BASE <= mem_read_addr && mem_read_addr < (CLINT_BASE + CLINT_SIZE)) - ))) { - // Don't check reads from tohost, reads from magic memory, or reads from clint - // Technically this could be buggy because log_mem_read only reports vaddrs, but - // no software ever should access tohost/fromhost/clint with vaddrs anyways - printf("Read override %lx\n", mem_read_addr); - s->XPR.write(rd, wdata); - } else if (wdata != regwrite.second.v[0]) { - printf("%d wdata mismatch reg %d spike:%lx != dut:%lx addr: %lx\n", - cycle, rd, regwrite.second.v[0], wdata, mem_read_addr); - exit(1); - } - } - } + auto& mem_write = s->log_mem_write; + auto& log = s->log_reg_write; + auto& mem_read = s->log_mem_read; + + + for (auto memwrite : mem_write) { + reg_t waddr = std::get<0>(memwrite); + uint64_t w_data = std::get<1>(memwrite); + if (waddr == CLINT_BASE && w_data == 0) { + s->mip->backdoor_write_with_mask(MIP_MSIP, 0); + } + // Try to remember magic_mem addrs, and ignore these in the future + if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { + printf("Probable magic mem %lx\n", w_data); + magic_addrs.insert(w_data); } } -} + bool scalar_wb = false; + bool vector_wb = false; + uint32_t vector_cnt = 0; + + for (auto ®write : log) { + + // if (regwrite.first == 0) continue; + + //TODO: scaling to multi issue reads? + reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]); + + int rd = regwrite.first >> 4; + int type = regwrite.first & 0xf; + + // 0 => int + // 1 => fp + // 2 => vec + // 3 => vec hint + // 4 => csr + + bool ignore_read = (!mem_read.empty() && + ((magic_addrs.count(mem_read_addr) || + (tohost_addr && mem_read_addr == tohost_addr) || + (fromhost_addr && mem_read_addr == fromhost_addr) || + (CLINT_BASE <= mem_read_addr && + mem_read_addr < (CLINT_BASE + CLINT_SIZE))))); + + // check the type is compliant with writeback first + if ((type == 0 || type == 1)) + scalar_wb = true; + if (type == 2) { + vector_wb = true; + } + if (type == 3) continue; + + + if ((rd != 0 && type == 0) || type == 1) { + // Override reads from some CSRs + uint64_t csr_addr = (insn >> 20) & 0xfff; + bool csr_read = (insn & 0x7f) == 0x73; + if (csr_read) + printf("CSR read %lx\n", csr_addr); + if (csr_read && ((csr_addr == 0xf13) || // mimpid + (csr_addr == 0xf12) || // marchid + (csr_addr == 0xf11) || // mvendorid + (csr_addr == 0xb00) || // mcycle + (csr_addr == 0xb02) || // minstret + (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr + )) { + printf("CSR override\n"); + s->XPR.write(rd, wdata); + } else if (ignore_read) { + // Don't check reads from tohost, reads from magic memory, or reads + // from clint Technically this could be buggy because log_mem_read + // only reports vaddrs, but no software ever should access + // tohost/fromhost/clint with vaddrs anyways + printf("Read override %lx\n", mem_read_addr); + s->XPR.write(rd, wdata); + } else if (wdata != regwrite.second.v[0]) { + printf("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd, + regwrite.second.v[0], wdata); + exit(1); + } + } + + } + } + + if (scalar_wb ^ has_wdata) { + printf("Scalar behavior divergence between spike and DUT\n"); + exit(-1); + } +} From c5002ab9d336f79720d44a95b33a1484300745a3 Mon Sep 17 00:00:00 2001 From: Tianrui Wei Date: Thu, 20 Apr 2023 23:03:48 +0000 Subject: [PATCH 116/184] fix: address comments Signed-off-by: Tianrui Wei --- .../src/main/resources/csrc/cospike.cc | 94 ++++++++++++------- 1 file changed, 59 insertions(+), 35 deletions(-) diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index d637c45a..fdd3978f 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -34,6 +34,7 @@ typedef struct system_info_t { system_info_t* info = NULL; sim_t* sim = NULL; +bool cospike_debug; reg_t tohost_addr = 0; reg_t fromhost_addr = 0; std::set magic_addrs; @@ -94,7 +95,7 @@ extern "C" void cospike_cosim(long long int cycle, nullptr, info->isa.c_str(), "MSU", - "vlen:512,elen:64", + "vlen:128,elen:64", false, endianness_little, info->pmpregions, @@ -111,27 +112,6 @@ extern "C" void cospike_cosim(long long int cycle, uint64_t default_boot_addr = 0x80000000; boot_addr_reg->store(0, 8, (const uint8_t*)(&default_boot_addr)); - for (auto& mem : mems) { - if (mem.first == info->mem0_base) { - std::string path_name = "chipyard-cosim-" + std::to_string(getpid()); - ssize_t mem_size = mem.second->size(); - int shared_fd = shm_open(path_name.c_str(), O_EXCL | O_RDWR, 0600); - if (shared_fd < 0) { - std::perror("[mm_t] shm_open for backing storage failed"); - exit(-1); - } - uint8_t *data = (uint8_t *) mmap( - NULL, mem_size, PROT_READ|PROT_WRITE, MAP_SHARED|MAP_ANONYMOUS, shared_fd, 0); - if (data == MAP_FAILED) { - std::perror("[mm_t] mmap for backing storage failed"); - exit(-1); - } - mem.second->store(0, mem_size,(const uint8_t *) data); - munmap(data, mem_size); - close(shared_fd); - } - } - // Don't actually build a clint mem_t* clint_mem = new mem_t(CLINT_SIZE); @@ -146,7 +126,7 @@ extern "C" void cospike_cosim(long long int cycle, abort(); std::vector htif_args; bool in_permissive = false; - bool cospike_debug = false; + cospike_debug = false; for (int i = 1; i < vinfo.argc; i++) { std::string arg(vinfo.argv[i]); if (arg == "+permissive") { @@ -289,23 +269,23 @@ extern "C" void cospike_cosim(long long int cycle, } if (valid || raise_interrupt || raise_exception) { p->step(1); -#ifdef SPIKE_DEBUG - printf("spike pc is %lx\n", s->pc); - printf("spike mstatus is %lx\n", s->mstatus->read()); - printf("spike mip is %lx\n", s->mip->read()); - printf("spike mie is %lx\n", s->mie->read()); -#endif + if (unlikely(cospike_debug)) { + printf("spike pc is %lx\n", s->pc); + printf("spike mstatus is %lx\n", s->mstatus->read()); + printf("spike mip is %lx\n", s->mip->read()); + printf("spike mie is %lx\n", s->mie->read()); + } } if (valid) { if (s_pc != iaddr) { printf("%d PC mismatch spike %llx != DUT %llx\n", cycle, s_pc, iaddr); -#ifdef SPIKE_DEBUG - printf("spike mstatus is %lx\n", s->mstatus->read()); - printf("spike mcause is %lx\n", s->mcause->read()); - printf("spike mtval is %lx\n" , s->mtval->read()); - printf("spike mtinst is %lx\n", s->mtinst->read()); -#endif + if (unlikely(cospike_debug)) { + printf("spike mstatus is %lx\n", s->mstatus->read()); + printf("spike mcause is %lx\n", s->mcause->read()); + printf("spike mtval is %lx\n" , s->mtval->read()); + printf("spike mtinst is %lx\n", s->mtinst->read()); + } exit(1); } @@ -315,11 +295,37 @@ extern "C" void cospike_cosim(long long int cycle, auto& mem_read = s->log_mem_read; +<<<<<<< HEAD for (auto memwrite : mem_write) { reg_t waddr = std::get<0>(memwrite); uint64_t w_data = std::get<1>(memwrite); if (waddr == CLINT_BASE && w_data == 0) { s->mip->backdoor_write_with_mask(MIP_MSIP, 0); +||||||| constructed merge base + for (auto memwrite : mem_write) { + reg_t waddr = std::get<0>(memwrite); + uint64_t w_data = std::get<1>(memwrite); + if (waddr == CLINT_BASE && w_data == 0) { + s->mip->backdoor_write_with_mask(MIP_MSIP, 0); + } + // Try to remember magic_mem addrs, and ignore these in the future + if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { + printf("Probable magic mem %lx\n", w_data); + magic_addrs.insert(w_data); + } +======= + for (auto memwrite : mem_write) { + reg_t waddr = std::get<0>(memwrite); + uint64_t w_data = std::get<1>(memwrite); + if ((waddr == CLINT_BASE + 4*hartid) && w_data == 0) { + s->mip->backdoor_write_with_mask(MIP_MSIP, 0); + } + // Try to remember magic_mem addrs, and ignore these in the future + if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { + printf("Probable magic mem %lx\n", w_data); + magic_addrs.insert(w_data); + } +>>>>>>> fix: address comments } // Try to remember magic_mem addrs, and ignore these in the future if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { @@ -396,8 +402,26 @@ extern "C" void cospike_cosim(long long int cycle, } } +<<<<<<< HEAD if (scalar_wb ^ has_wdata) { printf("Scalar behavior divergence between spike and DUT\n"); exit(-1); +||||||| constructed merge base + if (vector_wb ^ has_vwdata) { + printf("vector behavior divergence between spike and DUT\n"); + exit(-1); + } +#ifdef SPIKE_DEBUG + if (vector_wb) { + printf("vector_cnt = %x\n", vector_cnt); + printf("vector_pre = %x\n", vector_pre); + } +#endif +======= + if (vector_wb ^ has_vwdata) { + printf("vector behavior divergence between spike and DUT\n"); + exit(-1); + } +>>>>>>> fix: address comments } } From 41592fdad1c02b17da59054a8f156b3c13bbfd2e Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 20 Apr 2023 16:16:51 -0700 Subject: [PATCH 117/184] address comments --- common.mk | 3 ++- scripts/uniqify-module-names.py | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/common.mk b/common.mk index e507140a..213e37e5 100644 --- a/common.mk +++ b/common.mk @@ -249,7 +249,8 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL --gen-collateral-path $(GEN_COLLATERAL_DIR) \ --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ --out-model-hier-json $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) \ - --dut $(TOP) + --dut $(TOP) \ + --model $(MODEL) sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) &: $(BB_MODS_FILELIST) $(MFC_TOP_HRCHY_JSON) $(FINAL_ANNO_FILE) diff --git a/scripts/uniqify-module-names.py b/scripts/uniqify-module-names.py index 858c0a19..b573dfc6 100755 --- a/scripts/uniqify-module-names.py +++ b/scripts/uniqify-module-names.py @@ -4,7 +4,6 @@ import json import argparse import shutil import os -import sh import datetime @@ -14,11 +13,12 @@ parser.add_argument("--mod-filelist", type=str, required=True, help="Abs path to parser.add_argument("--gen-collateral-path", dest="gcpath", type=str, required=True, help="Abs path to the gen-collateral directory") parser.add_argument("--model-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") parser.add_argument("--out-model-hier-json", type=str, required=True, help="Path to updated hierarchy JSON emitted by this script.") -parser.add_argument('--dut', type=str, required=True, help='Name of the DUT module.') +parser.add_argument("--dut", type=str, required=True, help="Name of the DUT module.") +parser.add_argument("--model", type=str, required=True, help="Name of the Model module.") args = parser.parse_args() -MODEL_SFX=str(datetime.date.today().year) +MODEL_SFX=args.model + "_UNIQUIFIED" def bash(cmd): fail = os.system(cmd) From 10e641344bd77f270bc9046be3d3805393250b6e Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 20 Apr 2023 16:17:40 -0700 Subject: [PATCH 118/184] Revert "update conda-lock file again" This reverts commit 611de45cb19946aa606e9b34a8069759f7eb9f21. --- ...ements-riscv-tools-linux-64.conda-lock.yml | 84 +++++++++++-------- 1 file changed, 48 insertions(+), 36 deletions(-) diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index 9e25cb5f..22625f5a 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -7,9 +7,9 @@ # Install this environment as "YOURENV" with: # conda-lock install -n YOURENV --file conda-requirements-riscv-tools-linux-64.conda-lock.yml # To update a single package to the latest version compatible with the version constraints in the source: -# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE +# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/chipyard.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/riscv-tools.yaml -f /Users/joonhohwangbo/Documents/UCB-BAR/coding/chipyard/conda-reqs/chipyard.yaml -f /Users/joonhohwangbo/Documents/UCB-BAR/coding/chipyard/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml +# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/chipyard.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -21,7 +21,7 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 661e3655416e9e5de13d6b7ef41dd4f18c6e4725072890cdc12d17cdbde356bc + linux-64: 94be5f8cad4026c00d3aef6c3690da6cc358bc79c1f7398049754bd17e861420 platforms: - linux-64 sources: @@ -29,8 +29,6 @@ metadata: - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml - /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/chipyard.yaml - /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/riscv-tools.yaml - - /Users/joonhohwangbo/Documents/UCB-BAR/coding/chipyard/conda-reqs/chipyard.yaml - - /Users/joonhohwangbo/Documents/UCB-BAR/coding/chipyard/conda-reqs/riscv-tools.yaml package: - category: main dependencies: {} @@ -424,6 +422,7 @@ package: libstdcxx-ng: '>=12' hash: md5: 6bfb79319763a11c7423c9d0e0ee00b7 + sha256: null manager: conda name: dromajo optional: false @@ -3818,14 +3817,14 @@ package: python: '>=3.8' zipp: '>=0.5' hash: - md5: b3c9bdaa68a0ba7549f67e7f5c766c83 - sha256: f51cfdafac71f7a3bb6e12cc68d7218de29391dd0798768b7775dea444bbdcae + md5: c63decd397ca639c4b17f6ea5d26bd4d + sha256: 26a56c66c95389e9e2bd95e88f023fd94d4a60e4817bcbe4103f6220d0c17d86 manager: conda name: importlib-metadata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.4.1-pyha770c72_0.conda - version: 6.4.1 + url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.3.0-pyha770c72_0.conda + version: 6.3.0 - category: main dependencies: python: '>=3.7' @@ -4006,14 +4005,14 @@ package: setuptools: '' wheel: '' hash: - md5: 9ccbacfd1cbfa0be00cc345fe5ad8816 - sha256: 781992f04a8c765b1ad29b54fc9f76c12b0864f9defd2869eeb5edff15b51546 + md5: 8025ca83b8ba5430b640b83917c2a6f7 + sha256: e1698cbf4964cd60a2885c0edbc654133cd0db5ac4cb568412250e577dbc42ad manager: conda name: pip optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pip-23.1-pyhd8ed1ab_0.conda - version: '23.1' + url: https://conda.anaconda.org/conda-forge/noarch/pip-23.0.1-pyhd8ed1ab_0.conda + version: 23.0.1 - category: main dependencies: python: '>=3.6' @@ -4368,16 +4367,16 @@ package: version: 6.0.0 - category: main dependencies: - importlib-metadata: '>=6.4.1,<6.4.2.0a0' + importlib-metadata: '>=6.3.0,<6.3.1.0a0' hash: - md5: 15b0c51cb977c0243b750687eff917b6 - sha256: 369e704eec7eca35dc10344113c778248b71c26fd17bec51412ca184808966ef + md5: 1dee0ac2ed01030b56bdd33eabebc42f + sha256: 0aee044df634fb4d652ecf117b17ab2dd24f8f863334d3010c37e3a96989f0fa manager: conda name: importlib_metadata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-6.4.1-hd8ed1ab_0.conda - version: 6.4.1 + url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-6.3.0-hd8ed1ab_0.conda + version: 6.3.0 - category: main dependencies: attrs: '>=17.4.0' @@ -4403,6 +4402,7 @@ package: libzlib: '>=1.2.12,<1.3.0a0' hash: md5: 5b3ed39ee3809d63d347b649de0a45f8 + sha256: null manager: conda name: libdwarf optional: false @@ -4621,14 +4621,14 @@ package: types-awscrt: '' typing_extensions: '' hash: - md5: d981f03fa455593256ffa348118cd7d1 - sha256: cd2c92d0ab21305cd1afc9c503495564cf56397816af0a12c84c35fbfc849fba + md5: 39387401b8d302b94a16bb2cf77f6ff8 + sha256: 8deed72652219ab079ec5fd0bae5327a947622dcc40210e88837b62703780ecc manager: conda name: botocore-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.114-pyhd8ed1ab_0.conda - version: 1.29.114 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.113-pyhd8ed1ab_0.conda + version: 1.29.113 - category: main dependencies: clang-format: 16.0.1 default_h62803fd_0 @@ -4723,6 +4723,7 @@ package: libzlib: '>=1.2.12,<1.3.0a0' hash: md5: 899c511688e6c41cb51c2921a8d25e63 + sha256: null manager: conda name: libdwarf-dev optional: false @@ -5076,14 +5077,14 @@ package: python-dateutil: '>=2.1,<3.0.0' urllib3: '>=1.25.4,<1.27' hash: - md5: 3c403408336b409bc12867c0f1416771 - sha256: fd55f823f5649529d84162f4c1543b9fe6308b8d781078aff59a79b6d52e4e50 + md5: 28e3074f0184e908a78dd99ad7206916 + sha256: 3812de59fe902fbd6ca6096bdfd02ccd8300a460948979071e7e45bc7ebbb66c manager: conda name: botocore optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.114-pyhd8ed1ab_0.conda - version: 1.29.114 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.113-pyhd8ed1ab_0.conda + version: 1.29.113 - category: main dependencies: cairo: '>=1.16.0,<2.0a0' @@ -5330,7 +5331,7 @@ package: version: 5.1.1 - category: main dependencies: - botocore: 1.29.114 + botocore: 1.29.113 colorama: '>=0.2.5,<0.4.5' docutils: '>=0.10,<0.17' python: '>=3.10,<3.11.0a0' @@ -5339,29 +5340,29 @@ package: rsa: '>=3.1.2,<4.8' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: 6018d1a712d1982015b748e26975fa80 - sha256: cce05269e07a7709bf1c6808fe771997aebeff75431c0e1592fca2d4154c9ddb + md5: 3e9e90cd2b4355932b94898eda78783d + sha256: 6eda3942ffb8bd320e5b2ee0538bdb6b2333835653f2990666dc660c4fd3b6ee manager: conda name: awscli optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.114-py310hff52083_0.conda - version: 1.27.114 + url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.113-py310hff52083_0.conda + version: 1.27.113 - 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category: main @@ -5673,6 +5676,7 @@ package: name: asttokens optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/f3/e1/64679d9d0759db5b182222c81ff322c2fe2c31e156a59afd6e9208c960e5/asttokens-2.2.1-py2.py3-none-any.whl version: 2.2.1 - category: main @@ -5684,6 +5688,7 @@ package: name: gdspy optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/1d/e4/97b8add92fbec2a9890ad4777272e9a9e4d7a0ceeac42b7e1febe94f0e86/gdspy-1.4.zip version: '1.4' - category: main @@ -5696,6 +5701,7 @@ package: name: paramiko-ng optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/9f/53/1ac75eab589149b1e02e38185ecebf09e1b805fc3fdeadbc16d1a2b7d208/paramiko_ng-2.8.10-py2.py3-none-any.whl version: 2.8.10 - category: main @@ -5707,6 +5713,7 @@ package: name: ruamel.yaml optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/9e/cb/938214ac358fbef7058343b3765c79a1b7ed0c366f7f992ce7ff38335652/ruamel.yaml-0.17.21-py3-none-any.whl version: 0.17.21 - category: main @@ -5719,6 +5726,7 @@ package: name: sure optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/dd/ae/eb28ee3b6768e51cb938abcf521cb678217203f33385a2df54d3f23331c5/sure-2.0.1.tar.gz version: 2.0.1 - category: main @@ -5731,6 +5739,7 @@ package: name: fab-classic optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/6b/0f/efc537eebfd2a2c470250c0ac8bd8a05ffc13d95a7fb22021367890d7c46/fab_classic-1.19.2-py2.py3-none-any.whl version: 1.19.2 - category: main @@ -5746,6 +5755,7 @@ package: name: hammer-vlsi optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/53/39/18367e6fb4f20e9ae4fb3097f7b80704ff5cccf62980ea2871ba1d817a74/hammer_vlsi-1.1.0-py3-none-any.whl version: 1.1.0 - category: main @@ -5758,6 +5768,7 @@ package: name: icontract optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/d8/91/9756e7cf0b155e80bf9a62beffdd1dec4afce43cc6ab7f432f2267c62762/icontract-2.6.2-py3-none-any.whl version: 2.6.2 - category: main @@ -5770,6 +5781,7 @@ package: name: pylddwrap optional: false platform: linux-64 + source: null url: https://files.pythonhosted.org/packages/c9/12/4afd6542c43cd20271f0e53bf0211decc10079a76a41e53c0288025a7b85/pylddwrap-1.2.2.tar.gz version: 1.2.2 version: 1 From 776419e6aebd95a8afe70812dff7c96a0987dccb Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 20 Apr 2023 16:17:52 -0700 Subject: [PATCH 119/184] Revert "add sh to conda env" This reverts commit 632a8957ffd7666e8fdea566a1ff30b7d913b416. --- conda-reqs/chipyard.yaml | 1 - ...ements-riscv-tools-linux-64.conda-lock.yml | 1135 +++++++---------- 2 files changed, 439 insertions(+), 697 deletions(-) diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml index 7b928cae..59c5de51 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard.yaml @@ -39,7 +39,6 @@ dependencies: - coreutils - jq - pip - - sh # firemarshal deps - qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index 22625f5a..ca4c96d2 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -7,9 +7,9 @@ # Install this environment as "YOURENV" with: # conda-lock install -n YOURENV --file conda-requirements-riscv-tools-linux-64.conda-lock.yml # To update a single package to the latest version compatible with the version constraints in the source: -# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE +# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/chipyard.yaml -f /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml +# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -21,14 +21,12 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 94be5f8cad4026c00d3aef6c3690da6cc358bc79c1f7398049754bd17e861420 + linux-64: 1a7b0ae002798a28682d700644302284790c06503a7d3d04caa019aa74da7123 platforms: - linux-64 sources: - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml - - /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/chipyard.yaml - - /scratch/joonho.whangbo/coding/circt-fix-cy/conda-reqs/riscv-tools.yaml package: - category: main dependencies: {} @@ -187,14 +185,14 @@ package: - category: main dependencies: {} hash: - md5: 0299e410bfb4300540bdc0012a7985ef - sha256: 8572efb7092c72fe7b73d2a0f1e5e27159a8edea0371e1bef533bcb7d85b19c6 + md5: 7697d37e29669a14b053e82fad22a16b + sha256: ac993fa2774b90befcd6aba55b1c08853b2fa3b818753094c09bebd35fc55532 manager: conda name: open_pdks.sky130a optional: false platform: linux-64 - url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.406_0_g0c37b7c-20230412_103222.tar.bz2 - version: 1.0.406_0_g0c37b7c + url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.402_1_g12df12e-20230225_164303.tar.bz2 + version: 1.0.402_1_g12df12e - category: main dependencies: {} hash: @@ -209,14 +207,14 @@ package: - category: main dependencies: {} hash: - md5: 939e3e74d8be4dac89ce83b20de2492a - sha256: 0449138224adfa125b220154408419ec37c06b0b49f63c5954724325903ecf55 + md5: 51fc4fcfb19f5d95ffc8c339db5068e8 + sha256: 0bfae0b9962bc0dbf79048f9175b913ed4f53c4310d06708dc7acbb290ad82f6 manager: conda name: tzdata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023c-h71feb2d_0.conda - version: 2023c + url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2022g-h191b570_0.conda + version: 2022g - category: main dependencies: font-ttf-dejavu-sans-mono: '' @@ -422,13 +420,25 @@ package: libstdcxx-ng: '>=12' hash: md5: 6bfb79319763a11c7423c9d0e0ee00b7 - sha256: null manager: conda name: dromajo optional: false platform: linux-64 url: https://conda.anaconda.org/ucb-bar/linux-64/dromajo-1.0.0-0_h1234567_g6a6e34e.tar.bz2 version: 1.0.0 +- category: main + dependencies: + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' + hash: + md5: c4fbad8d4bddeb3c085f18cbf97fbfad + sha256: b44db0b92ae926b3fbbcd57c179fceb64fa11a9f9d09082e03be58b74dcad832 + manager: conda + name: expat + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/expat-2.5.0-h27087fc_0.tar.bz2 + version: 2.5.0 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -518,17 +528,17 @@ package: version: '1.12' - category: main dependencies: - libgcc-ng: '>=12' - libstdcxx-ng: '>=12' + libgcc-ng: '>=10.3.0' + libstdcxx-ng: '>=10.3.0' hash: - md5: 7c8d20d847bb45f56bd941578fcfa146 - sha256: e44cc00eec068e7f7a6dd117ba17bf5d57658729b7b841945546f82505138292 + md5: 87473a15119779e021c314249d4b4aed + sha256: 1d7950f3be4637ab915d886304e57731d39a41ab705ffc95c4681655c459374a manager: conda name: icu optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/icu-72.1-hcb278e6_0.conda - version: '72.1' + url: https://conda.anaconda.org/conda-forge/linux-64/icu-70.1-h27087fc_0.tar.bz2 + version: '70.1' - category: main dependencies: libgcc-ng: '>=12' @@ -582,14 +592,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: 6aa9c9de5542ecb07fdda9ca626252d8 - sha256: 949d84ceea543802c1e085b2aa58f1d6cb5dd8cec5a9abaaf4e8ac65d6094b3a + md5: 5cc781fd91968b11a8a7fdbee0982676 + sha256: f9983a8ea03531f2c14bce76c870ca325c0fddf0c4e872bff1f78bc52624179c manager: conda name: libdeflate optional: false platform: linux-64 - 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version: '8.2' + url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.1.2-h0f457ee_0.tar.bz2 + version: 8.1.2 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1616,17 +1589,17 @@ package: version: '2.71' - category: main dependencies: - libgcc-ng: '>=12' - readline: '>=8.2,<9.0a0' + libgcc-ng: '>=10.3.0' + readline: '>=8.1,<9.0a0' hash: - md5: 23b559a791d63ba4f51906763eb6bc53 - sha256: a7b2ea50068d86ac6e3749f76b118b15947d3f5ce48535eb5ab2ff7e22659c49 + md5: 54d1a374b75f14ecc58aea8c4236c0c3 + sha256: 6415903ad8774fc0f1bf5b156ae0b6f9988427a0f14bb35467c5938f05fe8707 manager: conda name: bash optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.2.15-hfbf034d_0.conda - version: 5.2.15 + url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.1.16-hd863ed2_0.tar.bz2 + version: 5.1.16 - category: main dependencies: flex: '' @@ -1712,13 +1685,13 @@ package: dependencies: gcc_impl_linux-64: 12.2.0.* hash: - md5: c241b4f6676222c2feefc9dc4b9d1728 - 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url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.5-pyhd8ed1ab_0.conda - version: 3.0.5 + url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.2-pyhd8ed1ab_0.conda + version: 3.0.2 - category: main dependencies: libgcc-ng: '>=12' @@ -2246,14 +2203,14 @@ package: dependencies: python: '>=3.7' hash: - md5: ec5503e4e3142adde6061c54db438b51 - sha256: ceb2394be6276bb321e05741094568efc0421374713ff3c8226c09283ea2af65 + md5: 6f90f1dc834447823b11d155726fcb37 + sha256: 6a6901f20c5b4d81aebd25a0645b3578ebb6a323f9fd7e87ee05ecbcfe19069e manager: conda name: filelock optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.11.0-pyhd8ed1ab_0.conda - version: 3.11.0 + url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.10.0-pyhd8ed1ab_0.conda + version: 3.10.0 - category: main dependencies: expat: '>=2.5.0,<3.0a0' @@ -2288,30 +2245,29 @@ package: dependencies: python: '>=3.8' hash: - md5: a993e42df87a292d8fd7396a2e2a8d75 - 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category: main dependencies: @@ -2349,13 +2305,13 @@ package: gcc: 12.2.0.* gxx_impl_linux-64: 12.2.0.* hash: - md5: 56e0d282569b6cd349035a1bb5efae47 - sha256: b428f0af395194cb327fb212167efc3a837866d11b9f1a8bbad7e953c595c6cb + md5: 2b54322e0dbb1345d64913e8b20b7d7c + sha256: f6c390055f2846d6013160c41dece0973daf577c5f1aaa73ff5dcf597b35d0ec manager: conda name: gxx optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_12.conda + url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_11.tar.bz2 version: 12.2.0 - category: main dependencies: @@ -2483,31 +2439,17 @@ package: version: 1.4.4 - category: main dependencies: + jpeg: '>=9e,<10a' libgcc-ng: '>=12' - python: '>=3.10,<3.11.0a0' - python_abi: 3.10.* *_cp310 - hash: - md5: 8664f43451412071a7111211fe7e38f2 - sha256: a26e8c55b8d1b17e784c6e2ffa75ed4dec4a335c7df17f183dcc9c5149d6cd70 - manager: conda - name: lazy-object-proxy - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/lazy-object-proxy-1.9.0-py310h1fa729e_0.conda - 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category: main dependencies: python: '' @@ -3493,23 +3353,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libxrender-0.9.10-h7f98852_1003.tar.bz2 version: 0.9.10 -- category: main - dependencies: - libgcc-ng: '>=9.3.0' - xorg-kbproto: '' - xorg-libice: 1.0.* - xorg-libsm: 1.2.* - xorg-libx11: '>=1.7.0,<2.0a0' - xorg-xproto: '' - hash: - md5: 60d6eec5273f1c9af096c10c268912e3 - sha256: 25bfc4d86df3498b88aac2f02ecf65e739bf99a687805c31a635df6f2e60a163 - manager: conda - name: xorg-libxt - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libxt-1.2.1-h7f98852_2.tar.bz2 - version: 1.2.1 - category: main dependencies: python: '>=3.7' @@ -3563,30 +3406,30 @@ package: version: 2.12.1 - category: main dependencies: - fontconfig: '>=2.14.2,<3.0a0' + fontconfig: '>=2.13.96,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' - icu: '>=72.1,<73.0a0' + icu: '>=70.1,<71.0a0' libgcc-ng: '>=12' - libglib: '>=2.74.1,<3.0a0' - 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category: main dependencies: python: '>=3.6' @@ -4045,19 +3891,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/ucb-bar/linux-64/qemu-5.0.0-hb15d774_0.tar.bz2 version: 5.0.0 -- category: main - dependencies: - python: '>=3.5' - six: '' - hash: - md5: fed45fc5ea0813240707998abe49f520 - sha256: 7c7052b51de0b5c558f890bb11f8b5edbb9934a653d76be086b1182b9f54185d - manager: conda - name: rfc3339-validator - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/rfc3339-validator-0.1.4-pyhd8ed1ab_0.tar.bz2 - version: 0.1.4 - category: main dependencies: pyasn1: '>=0.1.3' @@ -4089,32 +3922,17 @@ package: version: 0.17.21 - category: main dependencies: - __unix: '' - gmpy2: '>=2.0.8' - mpmath: '>=0.19' - python: '>=3.8' + python: '>=3.6' + typing: '>=3.6,<4.0' hash: - md5: 3893579a690fcd781c3dcedfd019bb9f - sha256: 8b5eb459c905758f96829ad93eb118f9b7cbbad8e9bc2b3328552abb7c658ec4 - manager: conda - name: sympy - optional: false - platform: linux-64 - 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version: 1.26.104 + url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.62-pyhd8ed1ab_0.conda + version: 1.26.62 - category: main dependencies: boto3: '' python: '>=3.6' typing-extensions: '' hash: - md5: 93e899cf501d962cfd1b251a45416825 - sha256: ef57856f4313eac453b53a119cedf121bd16fc98c64beaee8e3309959673daea + md5: a0ead2e95ffa5942c419234c15463344 + sha256: 7e7bb339939a50d9e682c01938062d2d4e1157a7b034d7f91e44e11d98c0d05d manager: conda name: mypy_boto3_ec2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.106-pyhd8ed1ab_0.conda - version: 1.26.106 -- category: main - dependencies: - boto3: '' - fsspec: '>=0.6.0' - python: '>=3.5' - hash: - md5: ead328eb12f01d88706126ba061e7a69 - sha256: 7a4cb574ff7edf773e5e4c396733dcb08ffcfd6e4f8b27e5b84b35fd4666ef5b - manager: conda - name: s3fs - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/s3fs-0.4.2-py_0.tar.bz2 - version: 0.4.2 + url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.91-pyhd8ed1ab_0.conda + version: 1.26.91 - category: main dependencies: docutils: <0.19 @@ -5590,26 +5348,24 @@ package: version: 1.2.0 - category: main dependencies: - aws-sam-translator: '>=1.62.0' + aws-sam-translator: '>=1.55.0' jschema-to-python: ~=1.2.3 jsonpatch: '' jsonschema: '>=3.0,<5' junit-xml: ~=1.9 - networkx: ~=2.4,<4 + networkx: ~=2.4 python: '>=3.7' pyyaml: '>5.4' - regex: '' sarif-om: ~=1.0.4 - sympy: '>=1.0.0' hash: - md5: 8a4bfed09432193675e0b0811f238162 - sha256: 7baaba7cca293448921fcc8afb7bb61a745dc830f4d616f4221fc061824d8102 + md5: 97bf916949bb4eb9f69c77d365a4da72 + sha256: 7d8c32e83b839abbb4c2a6b476b2a4a60f03394ac6156740f81abba64dbcf756 manager: conda name: cfn-lint optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.77.0-pyhd8ed1ab_0.conda - version: 0.77.0 + url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.75.1-pyhd8ed1ab_0.conda + version: 0.75.1 - category: main dependencies: aws-xray-sdk: '!=0.96,>=0.93' @@ -5639,14 +5395,14 @@ package: werkzeug: <2.2.0,>=0.5 xmltodict: '' hash: - md5: 32f26257ac824d26493bf387694eb35d - sha256: 86f6ae6a96d28ca6e1e72790e1bf6d33b2ec1ba9274619283d29a593a34494fe + md5: 702e5d281f691be1bec2f23d1f24fee8 + sha256: 5f7094094ef361b135068b12facdf34c18d2b285c4bd87a935ab1c7e633990ee manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.7-pyhd8ed1ab_0.conda - version: 4.1.7 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.5-pyhd8ed1ab_0.conda + version: 4.1.5 - category: main dependencies: {} hash: @@ -5655,7 +5411,6 @@ package: name: mock optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/e6/88/8a05e7ad0bb823246b2add3d2e97f990c41c71a40762c8db77a4bd78eedf/mock-5.0.1-py3-none-any.whl version: 5.0.1 - dependencies: {} @@ -5664,7 +5419,6 @@ package: manager: pip name: pyyaml platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/02/25/6ba9f6bb50a3d4fbe22c1a02554dc670682a07c8701d1716d19ddea2c940/PyYAML-6.0-cp310-cp310-manylinux_2_5_x86_64.manylinux1_x86_64.manylinux_2_12_x86_64.manylinux2010_x86_64.whl version: '6.0' - category: main @@ -5676,7 +5430,6 @@ package: name: asttokens optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/f3/e1/64679d9d0759db5b182222c81ff322c2fe2c31e156a59afd6e9208c960e5/asttokens-2.2.1-py2.py3-none-any.whl version: 2.2.1 - category: main @@ -5688,7 +5441,6 @@ package: name: gdspy optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/1d/e4/97b8add92fbec2a9890ad4777272e9a9e4d7a0ceeac42b7e1febe94f0e86/gdspy-1.4.zip version: '1.4' - category: main @@ -5701,19 +5453,15 @@ package: name: paramiko-ng optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/9f/53/1ac75eab589149b1e02e38185ecebf09e1b805fc3fdeadbc16d1a2b7d208/paramiko_ng-2.8.10-py2.py3-none-any.whl version: 2.8.10 -- category: main - dependencies: +- dependencies: ruamel.yaml.clib: '>=0.2.6' hash: sha256: 742b35d3d665023981bd6d16b3d24248ce5df75fdb4e2924e93a05c1f8b61ca7 manager: pip name: ruamel.yaml - optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/9e/cb/938214ac358fbef7058343b3765c79a1b7ed0c366f7f992ce7ff38335652/ruamel.yaml-0.17.21-py3-none-any.whl version: 0.17.21 - category: main @@ -5726,7 +5474,6 @@ package: name: sure optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/dd/ae/eb28ee3b6768e51cb938abcf521cb678217203f33385a2df54d3f23331c5/sure-2.0.1.tar.gz version: 2.0.1 - category: main @@ -5739,7 +5486,6 @@ package: name: fab-classic optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/6b/0f/efc537eebfd2a2c470250c0ac8bd8a05ffc13d95a7fb22021367890d7c46/fab_classic-1.19.2-py2.py3-none-any.whl version: 1.19.2 - category: main @@ -5755,7 +5501,6 @@ package: name: hammer-vlsi optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/53/39/18367e6fb4f20e9ae4fb3097f7b80704ff5cccf62980ea2871ba1d817a74/hammer_vlsi-1.1.0-py3-none-any.whl version: 1.1.0 - category: main @@ -5768,7 +5513,6 @@ package: name: icontract optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/d8/91/9756e7cf0b155e80bf9a62beffdd1dec4afce43cc6ab7f432f2267c62762/icontract-2.6.2-py3-none-any.whl version: 2.6.2 - category: main @@ -5781,7 +5525,6 @@ package: name: pylddwrap optional: false platform: linux-64 - source: null url: https://files.pythonhosted.org/packages/c9/12/4afd6542c43cd20271f0e53bf0211decc10079a76a41e53c0288025a7b85/pylddwrap-1.2.2.tar.gz version: 1.2.2 version: 1 From 64e8f334ac7596e1916d4778d97b54b847c335e2 Mon Sep 17 00:00:00 2001 From: Tianrui Wei Date: Thu, 20 Apr 2023 16:15:28 -0700 Subject: [PATCH 120/184] fix: address comments Signed-off-by: Tianrui Wei --- .../src/main/resources/csrc/cospike.cc | 53 ++----------------- 1 file changed, 5 insertions(+), 48 deletions(-) diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index fdd3978f..1b4cdb93 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -290,30 +290,10 @@ extern "C" void cospike_cosim(long long int cycle, } - auto& mem_write = s->log_mem_write; - auto& log = s->log_reg_write; - auto& mem_read = s->log_mem_read; + auto& mem_write = s->log_mem_write; + auto& log = s->log_reg_write; + auto& mem_read = s->log_mem_read; - -<<<<<<< HEAD - for (auto memwrite : mem_write) { - reg_t waddr = std::get<0>(memwrite); - uint64_t w_data = std::get<1>(memwrite); - if (waddr == CLINT_BASE && w_data == 0) { - s->mip->backdoor_write_with_mask(MIP_MSIP, 0); -||||||| constructed merge base - for (auto memwrite : mem_write) { - reg_t waddr = std::get<0>(memwrite); - uint64_t w_data = std::get<1>(memwrite); - if (waddr == CLINT_BASE && w_data == 0) { - s->mip->backdoor_write_with_mask(MIP_MSIP, 0); - } - // Try to remember magic_mem addrs, and ignore these in the future - if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { - printf("Probable magic mem %lx\n", w_data); - magic_addrs.insert(w_data); - } -======= for (auto memwrite : mem_write) { reg_t waddr = std::get<0>(memwrite); uint64_t w_data = std::get<1>(memwrite); @@ -325,7 +305,6 @@ extern "C" void cospike_cosim(long long int cycle, printf("Probable magic mem %lx\n", w_data); magic_addrs.insert(w_data); } ->>>>>>> fix: address comments } // Try to remember magic_mem addrs, and ignore these in the future if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { @@ -340,8 +319,6 @@ extern "C" void cospike_cosim(long long int cycle, for (auto ®write : log) { - // if (regwrite.first == 0) continue; - //TODO: scaling to multi issue reads? reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]); @@ -399,29 +376,9 @@ extern "C" void cospike_cosim(long long int cycle, } } - } - } - -<<<<<<< HEAD - if (scalar_wb ^ has_wdata) { - printf("Scalar behavior divergence between spike and DUT\n"); - exit(-1); -||||||| constructed merge base - if (vector_wb ^ has_vwdata) { - printf("vector behavior divergence between spike and DUT\n"); + if (scalar_wb ^ has_wdata) { + printf("Scalar behavior divergence between spike and DUT\n"); exit(-1); } -#ifdef SPIKE_DEBUG - if (vector_wb) { - printf("vector_cnt = %x\n", vector_cnt); - printf("vector_pre = %x\n", vector_pre); - } -#endif -======= - if (vector_wb ^ has_vwdata) { - printf("vector behavior divergence between spike and DUT\n"); - exit(-1); - } ->>>>>>> fix: address comments } } From a69f4163aff521daa5a204667c3ba3daf0a9fa4d Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 20 Apr 2023 16:32:13 -0700 Subject: [PATCH 121/184] bump to Hammer 1.1.1 --- conda-reqs/chipyard.yaml | 2 +- ...irements-esp-tools-linux-64.conda-lock.yml | 1037 ++++++++-------- ...ements-riscv-tools-linux-64.conda-lock.yml | 1044 +++++++++-------- 3 files changed, 1143 insertions(+), 940 deletions(-) diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml index 59c5de51..25e5f1a5 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard.yaml @@ -103,7 +103,7 @@ dependencies: - sty - open_pdks.sky130a - pip: - - hammer-vlsi[asap7]==1.1.0 + - hammer-vlsi[asap7]==1.1.1 # doc requirements - sphinx diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml index 6c22731e..7a0c7cd8 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml @@ -21,7 +21,7 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: cee2f923f616452b736c4314db2e791c5402803fdf7a7e344bb8233950f19b67 + linux-64: 3794abe8e222921d310bbd60f30fea775b80f7533f7a57d57c11bb3640a3643a platforms: - linux-64 sources: @@ -185,14 +185,14 @@ package: - category: main dependencies: {} hash: - md5: 7697d37e29669a14b053e82fad22a16b - sha256: ac993fa2774b90befcd6aba55b1c08853b2fa3b818753094c09bebd35fc55532 + md5: 0299e410bfb4300540bdc0012a7985ef + sha256: 8572efb7092c72fe7b73d2a0f1e5e27159a8edea0371e1bef533bcb7d85b19c6 manager: conda name: open_pdks.sky130a optional: false platform: linux-64 - url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.402_1_g12df12e-20230225_164303.tar.bz2 - version: 1.0.402_1_g12df12e + url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.406_0_g0c37b7c-20230412_103222.tar.bz2 + version: 1.0.406_0_g0c37b7c - category: main dependencies: {} hash: @@ -207,14 +207,14 @@ package: - category: main dependencies: {} hash: - md5: 51fc4fcfb19f5d95ffc8c339db5068e8 - sha256: 0bfae0b9962bc0dbf79048f9175b913ed4f53c4310d06708dc7acbb290ad82f6 + md5: 939e3e74d8be4dac89ce83b20de2492a + sha256: 0449138224adfa125b220154408419ec37c06b0b49f63c5954724325903ecf55 manager: conda name: tzdata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2022g-h191b570_0.conda - version: 2022g + url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023c-h71feb2d_0.conda + version: 2023c - category: main dependencies: font-ttf-dejavu-sans-mono: '' @@ -394,14 +394,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - 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version: 2.5.0 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -528,17 +515,17 @@ package: version: '1.12' - category: main dependencies: - libgcc-ng: '>=10.3.0' - libstdcxx-ng: '>=10.3.0' + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' hash: - md5: 87473a15119779e021c314249d4b4aed - sha256: 1d7950f3be4637ab915d886304e57731d39a41ab705ffc95c4681655c459374a + md5: 7c8d20d847bb45f56bd941578fcfa146 + sha256: e44cc00eec068e7f7a6dd117ba17bf5d57658729b7b841945546f82505138292 manager: conda name: icu optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/icu-70.1-h27087fc_0.tar.bz2 - version: '70.1' + url: https://conda.anaconda.org/conda-forge/linux-64/icu-72.1-hcb278e6_0.conda + version: '72.1' - category: main dependencies: libgcc-ng: '>=12' @@ -592,14 +579,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: 5cc781fd91968b11a8a7fdbee0982676 - sha256: f9983a8ea03531f2c14bce76c870ca325c0fddf0c4e872bff1f78bc52624179c + md5: 6aa9c9de5542ecb07fdda9ca626252d8 + sha256: 949d84ceea543802c1e085b2aa58f1d6cb5dd8cec5a9abaaf4e8ac65d6094b3a manager: conda name: libdeflate optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libdeflate-1.17-h0b41bf4_0.conda - version: '1.17' + url: https://conda.anaconda.org/conda-forge/linux-64/libdeflate-1.18-h0b41bf4_0.conda + version: '1.18' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -612,6 +599,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libev-4.33-h516909a_1.tar.bz2 version: '4.33' +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 6305a3dd2752c76335295da4e581f2fd + sha256: 74c98a563777ae2ad71f1f74d458a8ab043cee4a513467c159ccf159d0e461f3 + manager: conda + name: libexpat + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libexpat-2.5.0-hcb278e6_1.conda + version: 2.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -648,6 +647,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libiconv-1.17-h166bdaf_0.tar.bz2 version: '1.17' +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 1edd9e67bdb90d78cea97733ff6b54e6 + sha256: b19de7bda34eac4fa931be11fa8d7640cdf1441dfd51c91786586a4a4c64c92f + manager: conda + name: libjpeg-turbo + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libjpeg-turbo-2.1.5.1-h0b41bf4_0.conda + version: 2.1.5.1 - category: main dependencies: libgcc-ng: '>=9.4.0' @@ -736,16 +747,16 @@ package: version: 0.9.10 - category: main dependencies: - libgcc-ng: '>=9.3.0' + libgcc-ng: '>=12' hash: - md5: 772d69f030955d9646d3d0eaf21d859d - sha256: 54f118845498353c936826f8da79b5377d23032bcac8c4a02de2019e26c3f6b3 + md5: 40b61aab5c7ba9ff276c41cfffe6b80b + sha256: 787eb542f055a2b3de553614b25f09eefb0a0931b0c87dbcce6efdfd92f04f18 manager: conda name: libuuid optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libuuid-2.32.1-h7f98852_1000.tar.bz2 - version: 2.32.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libuuid-2.38.1-h0b41bf4_0.conda + version: 2.38.1 - category: main dependencies: libgcc-ng: '>=12' @@ -762,14 +773,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: ac2ccf7323d21f2994e4d1f5da664f37 - sha256: 221f2e138dd264b7394b88f08884d93825d38800a51415059e813c02467abfd1 + md5: 0d4a7508d8c6c65314f2b9c1f56ad408 + sha256: ac3e073ea77803da71eb77e7fcef07defb345bda95eee3327c73ddf85b5714da manager: conda name: libwebp-base optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.2.4-h166bdaf_0.tar.bz2 - version: 1.2.4 + url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.3.0-h0b41bf4_0.conda + version: 1.3.0 - category: main dependencies: libgcc-ng: '>=12' @@ -954,15 +965,15 @@ package: version: '6.0' - category: main dependencies: - libgcc-ng: '>=7.3.0' + libgcc-ng: '>=12' hash: - md5: 2e5f1a8199794b21c9472c1a7f27e21a - sha256: a3ee6c02932fbee32babe39fa6bda9f781d6dc17122d2a90e62ff2b6866a5de8 + md5: 76d6bc123c1c75bf034c412856fcc935 + sha256: e94d0d5f75a5f58165ad8ac64a25df851c77ec6e9bf626c16807dcbd740226c8 manager: conda name: which optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/which-2.21-h516909a_0.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/which-2.21-h0b41bf4_1.conda version: '2.21' - category: main dependencies: @@ -1135,6 +1146,19 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/dtc-1.6.1-h166bdaf_2.tar.bz2 version: 1.6.1 +- category: main + dependencies: + libexpat: 2.5.0 hcb278e6_1 + libgcc-ng: '>=12' + hash: + md5: 8b9b5aca60558d02ddaa09d599e55920 + sha256: 36dfeb4375059b3bba75ce9b38c29c69fd257342a79e6cf20e9f25c1523f785f + manager: conda + name: expat + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/expat-2.5.0-hcb278e6_1.conda + version: 2.5.0 - category: main dependencies: gettext: '' @@ -1373,20 +1397,20 @@ package: version: '1.13' - category: main dependencies: - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' libiconv: '>=1.17,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' xz: '>=5.2.6,<6.0a0' hash: - md5: bb808b654bdc3c783deaf107a2ffb503 - sha256: d4170f1fe356768758b13a51db123f990bff81b0eae0d5a0ba11c7ca6b9536f4 + md5: 241845899caff54ac1d2b3102ad988cf + sha256: 624b6e29e23a51353cff2aff7364c42b831139afd131d239e79f60aea4dae887 manager: conda name: libxml2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.3-hca2bb57_4.conda - version: 2.10.3 + url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.4-hfdac1af_0.conda + version: 2.10.4 - category: main dependencies: libgcc-ng: '>=7.3.0' @@ -1472,14 +1496,14 @@ package: libgcc-ng: '>=12' ncurses: '>=6.3,<7.0a0' hash: - md5: db2ebbe2943aae81ed051a6a9af8e0fa - sha256: f5f383193bdbe01c41cb0d6f99fec68e820875e842e6e8b392dbe1a9b6c43ed8 + md5: 47d31b792659ce70f470b5c82fdfb7a4 + sha256: 5435cf39d039387fbdc977b0a762357ea909a7694d9528ab40f005e9208744d7 manager: conda name: readline optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.1.2-h0f457ee_0.tar.bz2 - version: 8.1.2 + url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.2-h8228510_1.conda + version: '8.2' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1589,17 +1613,17 @@ package: version: '2.71' - category: main dependencies: - libgcc-ng: '>=10.3.0' - readline: '>=8.1,<9.0a0' + libgcc-ng: '>=12' + readline: '>=8.2,<9.0a0' hash: - md5: 54d1a374b75f14ecc58aea8c4236c0c3 - sha256: 6415903ad8774fc0f1bf5b156ae0b6f9988427a0f14bb35467c5938f05fe8707 + md5: 23b559a791d63ba4f51906763eb6bc53 + sha256: a7b2ea50068d86ac6e3749f76b118b15947d3f5ce48535eb5ab2ff7e22659c49 manager: conda name: bash optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.1.16-hd863ed2_0.tar.bz2 - version: 5.1.16 + url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.2.15-hfbf034d_0.conda + version: 5.2.15 - category: main dependencies: flex: '' @@ -1685,13 +1709,13 @@ package: dependencies: gcc_impl_linux-64: 12.2.0.* hash: - md5: b4d86475bd1a21d139ea78770f606471 - sha256: 3cfb989723f8e115d35553c2b1d899b0f4185fc0551a996b9ff4037083a36432 + md5: c241b4f6676222c2feefc9dc4b9d1728 + sha256: f4b4184cc3e0864abadfc5b06ae869b479e736ff1dc46723967256d11b5bc7c4 manager: conda name: gcc optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_11.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_12.conda version: 12.2.0 - category: main dependencies: @@ -1782,14 +1806,14 @@ package: libzlib: '>=1.2.13,<1.3.0a0' pcre2: '>=10.40,<10.41.0a0' hash: - md5: ed5349aa96776e00b34eccecf4a948fe - sha256: 3cbad3d63cff2dd9ac1dc9cce54fd3d657f3aff53df41bfe5bae9d760562a5af + md5: 984fc0159591041a411d96718e7073d0 + sha256: afac276054c6fc2959347e7e1da211554f5cc4efbdda6d1f29b6d98919eae833 manager: conda name: libglib optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.74.1-h606061b_1.tar.bz2 - version: 2.74.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.76.1-ha491796_0.conda + version: 2.76.1 - category: main dependencies: libblas: 3.9.0 16_linux64_openblas @@ -1820,23 +1844,39 @@ package: version: 15.0.7 - category: main dependencies: - jpeg: '>=9e,<10a' - lerc: '>=4.0.0,<5.0a0' - libdeflate: '>=1.17,<1.18.0a0' libgcc-ng: '>=12' libstdcxx-ng: '>=12' - libwebp-base: '>=1.2.4,<2.0a0' + libxml2: '>=2.10.3,<2.11.0a0' + libzlib: '>=1.2.13,<1.3.0a0' + zstd: '>=1.5.2,<1.6.0a0' + hash: + md5: 716f4c806c384ee7bf1647814516c241 + sha256: 95a7e646c035b2515c69af0c47acf1840557160123f8ee6441d8b0f254098342 + manager: conda + name: libllvm16 + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libllvm16-16.0.1-hadd5161_0.conda + version: 16.0.1 +- category: main + dependencies: + lerc: '>=4.0.0,<5.0a0' + libdeflate: '>=1.18,<1.19.0a0' + libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' + libstdcxx-ng: '>=12' + libwebp-base: '>=1.3.0,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' xz: '>=5.2.6,<6.0a0' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 2e648a34072eb39d7c4fc2a9981c5f0c - sha256: e3e18d91fb282b61288d4fd2574dfa31f7ae90ef2737f96722fb6ad3257862ee + md5: 4e5ee4b062c21519efbee7e2ae608748 + sha256: caacb23e1b95fbdd8115be69228f9c82068ed87bf57f055027e31d093ae6a1a2 manager: conda name: libtiff optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libtiff-4.5.0-h6adf6a1_2.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libtiff-4.5.0-ha587672_6.conda version: 4.5.0 - category: main dependencies: @@ -1990,14 +2030,14 @@ package: dependencies: python: '>=3.6' hash: - md5: b3c15cb1d45fd10bc6f652bbc51e023a - sha256: 8dbc6de55113ea67a64f0be5d16ba939d1b58a25dbd9a5cc62b571cef24ef85c + md5: 99b19895abe40280358488acb9589532 + sha256: 2b273efc522834e4c8563da7998b9b683eed467660fe8a5a3c24d58aaa85a9cb manager: conda name: argcomplete optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.2-pyhd8ed1ab_0.conda - version: 3.0.2 + url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.5-pyhd8ed1ab_0.conda + version: 3.0.5 - category: main dependencies: libgcc-ng: '>=12' @@ -2220,14 +2260,14 @@ package: dependencies: python: '>=3.7' hash: - md5: 6f90f1dc834447823b11d155726fcb37 - sha256: 6a6901f20c5b4d81aebd25a0645b3578ebb6a323f9fd7e87ee05ecbcfe19069e + md5: 650f18a56f366dbf419c15b543592c2d + sha256: 68db3a6280d6786be76f2c7c6cf41dd878c5d1a24f5de10f7f0af82c6fcfade6 manager: conda name: filelock optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.10.0-pyhd8ed1ab_0.conda - version: 3.10.0 + url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.12.0-pyhd8ed1ab_0.conda + version: 3.12.0 - category: main dependencies: expat: '>=2.5.0,<3.0a0' @@ -2262,29 +2302,30 @@ package: dependencies: python: '>=3.8' hash: - md5: 0db48a2f5a68e28e5af8d3df276f2255 - sha256: dfcee90620d13f4f667664620191d780c79ec7e9ba9908cd771d24a1361e0cc9 + md5: a993e42df87a292d8fd7396a2e2a8d75 + sha256: c2a5db01537aae91a54dbd163b85421de2b623c75803af4e38ea01ba000317d1 manager: conda name: fsspec optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.3.0-pyhd8ed1ab_1.conda - version: 2023.3.0 + url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.4.0-pyh1a96a4e_0.conda + version: 2023.4.0 - category: main dependencies: - jpeg: '>=9e,<10a' libgcc-ng: '>=12' libglib: '>=2.74.1,<3.0a0' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libtiff: '>=4.5.0,<4.6.0a0' + libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 1a109126a43003d65b39c1cad656bc9b - sha256: a27f49d85e0a730374cc77606e9484b23b0f3edf32df1994b6d7ff5dd44aef92 + md5: ee8220db21db8094998005990418fe5b + sha256: 7acc699871310e9a89aaa7e90de9ac949e2fa649232c8a8dfcafa67e8f36a266 manager: conda name: gdk-pixbuf optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gdk-pixbuf-2.42.10-h05c8ddd_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/gdk-pixbuf-2.42.10-h6b639ba_2.conda version: 2.42.10 - category: main dependencies: @@ -2322,13 +2363,13 @@ package: gcc: 12.2.0.* gxx_impl_linux-64: 12.2.0.* hash: - md5: 2b54322e0dbb1345d64913e8b20b7d7c - sha256: f6c390055f2846d6013160c41dece0973daf577c5f1aaa73ff5dcf597b35d0ec + md5: 56e0d282569b6cd349035a1bb5efae47 + sha256: b428f0af395194cb327fb212167efc3a837866d11b9f1a8bbad7e953c595c6cb manager: conda name: gxx optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_11.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_12.conda version: 12.2.0 - category: main dependencies: @@ -2456,17 +2497,17 @@ package: version: 1.4.4 - category: main dependencies: - jpeg: '>=9e,<10a' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libtiff: '>=4.5.0,<4.6.0a0' hash: - md5: aa8840cdf17ef0c6084d1e24abc7a28b - sha256: 443e926b585528112ec6aa4d85bf087722914ed8d85a2f75ae47c023c55c4238 + md5: 980d8aca0bc23ca73fa8caa3e7c84c28 + sha256: 0d88e0e7f8dbf8f01788e21dd63dd49b89433ce7dfd10f53839441396f6481cd manager: conda name: lcms2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-hfd0df8a_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-haa2dc70_1.conda version: '2.15' - category: main dependencies: @@ -2486,18 +2527,31 @@ package: - category: main dependencies: libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.1,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: a3a0f7a6f0885f5e1e0ec691566afb77 - sha256: e48481c37d02aefeddcfac20d48cf13b838c5f7b9018300fa7eac404d30f3d7f + md5: 2c00ecf8081a8f23043b055a68d7ba90 + sha256: 5f3eb78832674b8038dd65c80d09837a01f3300bf516370fc16650f33b8b87ed + manager: conda + name: libclang-cpp16 + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libclang-cpp16-16.0.1-default_h62803fd_0.conda + version: 16.0.1 +- category: main + dependencies: + libgcc-ng: '>=12' + libllvm16: '>=16.0.1,<16.1.0a0' + libstdcxx-ng: '>=12' + hash: + md5: 48c2eb0c9988c76ad34c47910fee3077 + sha256: aa4a685e98221cee06b6de93c9ac8efc329c648fdbbffbdd02f41cb1d228b3d8 manager: conda name: libclang13 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libclang13-15.0.7-default_h3e3d535_1.conda - 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version: 1.26.25.8 + url: https://conda.anaconda.org/conda-forge/noarch/types-urllib3-1.26.25.10-pyhd8ed1ab_0.conda + version: 1.26.25.10 - category: main dependencies: python: '>=3' @@ -3217,24 +3295,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/verilator-4.226-he0ac6c6_1.tar.bz2 version: '4.226' -- category: main - dependencies: - gettext: '>=0.21.1,<1.0a0' - libgcc-ng: '>=12' - libstdcxx-ng: '>=12' - ncurses: '>=6.3,<7.0a0' - perl: '>=5.32.1,<5.33.0a0 *_perl5' - python: '>=3.9,<3.10.0a0' - python_abi: 3.9.* *_cp39 - hash: - md5: 8f23fe6252f0db61a467fc68235a6c6c - sha256: 1ff7b1aa32d188658e797ba09579afc9712ef00a5b10700ebc10d57155dcd299 - manager: conda - name: vim - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/vim-9.0.0814-py39pl5321h20e6244_0.tar.bz2 - version: 9.0.0814 - category: main dependencies: python: '' @@ -3259,18 +3319,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/websocket-client-1.5.1-pyhd8ed1ab_0.conda version: 1.5.1 -- category: main - dependencies: - python: '>=3.7' - hash: - md5: 6dfc61103f2c33a6c875b93d82875c10 - sha256: 3e08e7a72a01fa53e4d2e2dedde32b3300dc9d12c91d7b5248d458ecfa0bd439 - manager: conda - name: werkzeug - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/werkzeug-2.1.2-pyhd8ed1ab_1.tar.bz2 - version: 2.1.2 - category: main dependencies: python: '>=3.7' @@ -3351,6 +3399,23 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libxrender-0.9.10-h7f98852_1003.tar.bz2 version: 0.9.10 +- category: main + dependencies: + libgcc-ng: '>=9.3.0' + xorg-kbproto: '' + xorg-libice: 1.0.* + xorg-libsm: 1.2.* + xorg-libx11: '>=1.7.0,<2.0a0' + xorg-xproto: '' + hash: + md5: 60d6eec5273f1c9af096c10c268912e3 + sha256: 25bfc4d86df3498b88aac2f02ecf65e739bf99a687805c31a635df6f2e60a163 + manager: conda + name: xorg-libxt + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libxt-1.2.1-h7f98852_2.tar.bz2 + version: 1.2.1 - category: main dependencies: python: '>=3.7' @@ -3404,30 +3469,30 @@ package: version: 2.12.1 - category: main dependencies: - fontconfig: '>=2.13.96,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' - libglib: '>=2.72.1,<3.0a0' - libpng: '>=1.6.38,<1.7.0a0' + libglib: '>=2.74.1,<3.0a0' + libpng: '>=1.6.39,<1.7.0a0' libxcb: '>=1.13,<1.14.0a0' - libzlib: '>=1.2.12,<1.3.0a0' + libzlib: '>=1.2.13,<1.3.0a0' pixman: '>=0.40.0,<1.0a0' xorg-libice: '' xorg-libsm: '' - xorg-libx11: '' - xorg-libxext: '' + xorg-libx11: '>=1.8.4,<2.0a0' + xorg-libxext: '>=1.3.4,<2.0a0' xorg-libxrender: '' - zlib: '>=1.2.12,<1.3.0a0' + zlib: '' hash: - md5: d1a88f3ed5b52e1024b80d4bcd26a7a0 - sha256: f062cf56e6e50d3ad4b425ebb3765ca9138c6ebc52e6a42d1377de8bc8d954f6 + md5: 0c944213e40c9e4aa32292776b9c6903 + sha256: 0be3064cb30e3e69a47370abae85b2780cd81fbca00cbd17076d40c0f6302fdb manager: conda name: cairo optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/cairo-1.16.0-ha61ee94_1014.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/cairo-1.16.0-h35add3b_1015.conda version: 1.16.0 - category: main dependencies: @@ -3461,6 +3526,21 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-15-15.0.7-default_had23c3d_1.conda version: 15.0.7 +- category: main + dependencies: + libclang-cpp16: '>=16.0.1,<16.1.0a0' + libgcc-ng: '>=12' + libllvm16: '>=16.0.1,<16.1.0a0' + libstdcxx-ng: '>=12' + hash: + md5: cc2343dad8afb0b3d9cc368da2d58e22 + sha256: a3ae4c803ff00cdf74984c02ac8279e39861bb4aad16854c18a81792936714ac + manager: conda + name: clang-format-16 + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-16-16.0.1-default_h62803fd_0.conda + version: 16.0.1 - category: main dependencies: click: '' @@ -3491,8 +3571,9 @@ package: - category: main dependencies: bzip2: '>=1.0.8,<2.0a0' - expat: '>=2.5.0,<3.0a0' - libcurl: '>=7.88.1,<8.0a0' + expat: '' + libcurl: '>=7.88.1,<9.0a0' + libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libstdcxx-ng: '>=12' libuv: '' @@ -3503,14 +3584,14 @@ package: zlib: '' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 02142080aee43c8ef90db543ffbc13dd - sha256: cbd17c0375a021b7de854e0841f3f1b28b1359bc52bdc0ba5aabaee0f65a0b7d + md5: 6edec767268ad8451d27bb65f38c7ea4 + sha256: 3bb9d7c35d5297d85516769eb0517c83f7fc2ed7ab944a8c028871bb375bed51 manager: conda name: cmake optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/cmake-3.26.0-h077f3f9_0.conda - version: 3.26.0 + url: https://conda.anaconda.org/conda-forge/linux-64/cmake-3.26.3-h077f3f9_0.conda + version: 3.26.3 - category: main dependencies: libgcc-ng: '>=12' @@ -3563,7 +3644,7 @@ package: dependencies: bzip2: '>=1.0.8,<2.0a0' libarchive: '>=3.5.2,<3.6.0a0' - libcurl: '>=7.82.0,<8.0a0' + libcurl: '>=7.82.0,<9.0a0' libgcc-ng: '>=10.3.0' libmicrohttpd: '>=0.9.75,<0.10.0a0' libstdcxx-ng: '>=10.3.0' @@ -3589,14 +3670,14 @@ package: python_abi: 3.9.* *_cp39 unicodedata2: '>=14.0.0' hash: - md5: f87853cd6f76c4b8014b41fa522e5bda - sha256: 2c9ca5aba1d6d038b60f77b73e533e81feee882cd4f22e99bdaa77fd7bfcc7cc + md5: 9232b3b2cc83a304c8210a092e8ba4a5 + sha256: 08b6feeebcdd6ccb61cdb794eec806be7765dc4d601d4ec051aea721fa439aa4 manager: conda name: fonttools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/fonttools-4.39.2-py39h72bdee0_0.conda - version: 4.39.2 + url: https://conda.anaconda.org/conda-forge/linux-64/fonttools-4.39.3-py39h72bdee0_0.conda + version: 4.39.3 - category: main dependencies: python: '>=3.4' @@ -3642,14 +3723,14 @@ package: python: '>=3.8' zipp: '>=0.5' hash: - md5: 30b3127c385ca2ed5ef87f3d53d466bc - sha256: 4fe127138487a2aa171862407605f0cd601d005f85e0eee7f38c770b407e4145 + md5: ab2f9216e346f43599af3f7839931da1 + sha256: 1854da61b10c601bae3497e0d457b1bb029715d4bcabb5594199519de7c72f5a manager: conda name: importlib-metadata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.1.0-pyha770c72_0.conda - version: 6.1.0 + url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.5.0-pyha770c72_0.conda + version: 6.5.0 - category: main dependencies: python: '>=3.7' @@ -3734,26 +3815,26 @@ package: - category: main dependencies: expat: '>=2.5.0,<3.0a0' - fontconfig: '>=2.14.1,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' - icu: '>=70.1,<71.0a0' - jpeg: '>=9e,<10a' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libtiff: '>=4.5.0,<4.6.0a0' libwebp: '' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' zlib: '' hash: - md5: 82ef57611ace65b59db35a9687264572 - sha256: 6674781023188deeda7752e5dc429a54fd1639c9d61cbb25296cbbb55367884a + md5: ef06bee47510a7f5db3c2297a51d6ce2 + sha256: 6335db21afc72f86cf4ee0298acde3af950087db2b24df3d28a81c7d24574244 manager: conda name: libgd optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgd-2.3.3-h5aea950_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libgd-2.3.3-hfa28ad5_6.conda version: 2.3.3 - category: main dependencies: @@ -3780,14 +3861,14 @@ package: tomli: '>=1.1.0' typing_extensions: '>=3.10' hash: - md5: e25a18721970f7bb80a0d602ef3c72ad - sha256: 1ff6a68e7c511e2bb70b51466134706e33a322a3ef2544c7adc3524bd51624f1 + md5: 340cfe1633c018c5abf0099d7c307ab4 + sha256: 682fd2b43cf9bb66813d44b70535684670c33ca4a44e6c0e76540c496cb632c5 manager: conda name: mypy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/mypy-1.1.1-py39h72bdee0_0.conda - version: 1.1.1 + url: https://conda.anaconda.org/conda-forge/linux-64/mypy-1.2.0-py39h72bdee0_0.conda + version: 1.2.0 - category: main dependencies: python: 2.7|>=3.7 @@ -3804,11 +3885,11 @@ package: - category: main dependencies: freetype: '>=2.12.1,<3.0a0' - jpeg: '>=9e,<10a' - lcms2: '>=2.14,<3.0a0' + lcms2: '>=2.15,<3.0a0' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libtiff: '>=4.5.0,<4.6.0a0' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' libxcb: '>=1.13,<1.14.0a0' libzlib: '>=1.2.13,<1.3.0a0' openjpeg: '>=2.5.0,<3.0a0' @@ -3816,60 +3897,28 @@ package: python_abi: 3.9.* *_cp39 tk: '>=8.6.12,<8.7.0a0' hash: - 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category: main dependencies: cryptography: '' @@ -4695,19 +4795,18 @@ package: - category: main dependencies: distlib: <1,>=0.3.6 - filelock: <4,>=3.4.1 - importlib-metadata: '>=4.8.3' - platformdirs: <4,>=2.4 - python: '>=3.7' + filelock: <4,>=3.11 + platformdirs: <4,>=3.2 + python: '>=3.8' hash: - md5: cb9a711f7c9f3074fe522e5a34481e60 - sha256: 28540cdda9279d7daeb8f2deec6f1128869ba90742a966e488b692e8083c5349 + md5: 054007ab693cb77a029ea4f1f12f34a7 + sha256: acb9f18ef811cda29690d41e0e7c54f7088d35e6b5aa5db6403d13c9eb18336a manager: conda name: virtualenv optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.21.0-pyhd8ed1ab_0.conda - version: 20.21.0 + url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.22.0-pyhd8ed1ab_0.conda + version: 20.22.0 - category: main dependencies: conda-package-streaming: '>=0.7.0' @@ -4773,22 +4872,22 @@ package: version: 23.13.1 - category: main dependencies: - cairo: '>=1.16.0,<2.0.0a0' - gdk-pixbuf: '>=2.42.8,<3.0a0' - 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cryptography: '>=0.6,<41' + cryptography: '>=0.6,<43' pyjwt: '>=1.0.0,<3' python: '>=3.6' requests: '>=2.0.0,<3' hash: - md5: 9304c2492b162934f748d061be0042e8 - sha256: a516cdfa79d90f678507c986da24d5d9979083d90337eeaa17fdd7f3d2e1a976 + md5: 24c290ee3278fd9a33b00cd1f8d1db0f + sha256: 7f4cc4d6383263ad9cc69dc83bb5dd5d4a309ebe53f117e1d14ffd76f31939de manager: conda name: msal optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/msal-1.21.0-pyhd8ed1ab_0.conda - version: 1.21.0 + url: https://conda.anaconda.org/conda-forge/noarch/msal-1.22.0-pyhd8ed1ab_0.conda + version: 1.22.0 - category: main dependencies: graphviz: '>=2.46.1' @@ -5114,7 +5214,7 @@ package: version: 5.1.1 - category: main dependencies: - botocore: 1.27.59 + botocore: 1.29.116 colorama: '>=0.2.5,<0.4.5' docutils: '>=0.10,<0.17' python: '>=3.9,<3.10.0a0' @@ -5123,29 +5223,29 @@ package: rsa: '>=3.1.2,<4.8' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: fa62dd9ed5d234c493ff14914d43f332 - sha256: 61483c628f9751a038d5634ce8ba2ed7ab484ffad50a7e7da13c2e3b30f93eae + md5: 7ff7995ef5ae66e3f40ecf8715f94af9 + sha256: 075259e8d6df02f58a7d4b0a981ea0713936de293758f77d874dfaead449ad55 manager: conda name: awscli optional: false platform: linux-64 - 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version: 2023.3.0 - category: main dependencies: livereload: '>=2.3.0' @@ -5286,14 +5371,14 @@ package: python: '' typing_extensions: '' hash: - md5: 009fa15810ae5d376e1bd29ab93c1081 - sha256: 380426f97ae074ad86a1b52bb106e1f10e868bc8b7c575bea6ea5ac7725bc84d + md5: cfd95e43a27c0af1a206f7557d7f132e + sha256: 02570a9062717ec9b3293199ab8e8983c92f2320f5f8066ef541929a1166d9f1 manager: conda name: boto3-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.95-pyhd8ed1ab_0.conda - version: 1.26.95 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.117-pyhd8ed1ab_0.conda + version: 1.26.117 - category: main dependencies: cachecontrol-with-filecache: '>=0.12.9' @@ -5334,28 +5419,42 @@ package: python: '>=3.6' typing-extensions: '' hash: - md5: 0c79de238c80f668f5a4e85a2ca1dced - sha256: 348b0bdb9d9fcfdfc24c43ea93a29e2c5aba7f8d0e5570517e965c758c380419 + md5: cfc72b1b83d1b8503b1071455534ebac + sha256: 1df5aa62e1fc8d498a37f30723d15a1626dc9b686603e79b4b44ba6c95f8f659 manager: conda name: mypy-boto3-s3 optional: false platform: linux-64 - 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category: main dependencies: docutils: <0.19 @@ -5396,18 +5495,18 @@ package: aws-xray-sdk: '!=0.96,>=0.93' boto3: '>=1.9.201' botocore: '>=1.12.201' - cfn-lint: '>=0.4.0' + cfn-lint: '>=0.40.0' cryptography: '>=3.3.1' docker-py: '>=2.5.1' - flask: '' + flask: '!=2.2.0,!=2.2.1' flask_cors: '' graphql-core: '' idna: '>=2.5,<4' importlib_metadata: '' jinja2: '>=2.10.1' jsondiff: '>=1.1.2' - openapi-spec-validator: '' - pyparsing: '' + openapi-spec-validator: '>=0.2.8' + pyparsing: '>=3.0.7' python: '>=3.3' python-dateutil: '>=2.1,<3.0.0' python-jose: '>=3.1.0,<4.0.0' @@ -5417,17 +5516,17 @@ package: responses: '>=0.9.0' setuptools: '' sshpubkeys: '>=3.1.0' - werkzeug: <2.2.0,>=0.5 + werkzeug: '>=0.5,!=2.2.0,!=2.2.1' xmltodict: '' hash: - md5: 702e5d281f691be1bec2f23d1f24fee8 - sha256: 5f7094094ef361b135068b12facdf34c18d2b285c4bd87a935ab1c7e633990ee + md5: c4172149b03b032cd60cc79f1484a1dd + sha256: 5891a5ce23d274406bda81e202ddc303d30a3355c01c7d9ae461fc5313247e9d manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.5-pyhd8ed1ab_0.conda - version: 4.1.5 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.7-pyhd8ed1ab_2.conda + version: 4.1.7 - category: main dependencies: {} hash: @@ -5480,12 +5579,14 @@ package: platform: linux-64 url: https://files.pythonhosted.org/packages/9f/53/1ac75eab589149b1e02e38185ecebf09e1b805fc3fdeadbc16d1a2b7d208/paramiko_ng-2.8.10-py2.py3-none-any.whl version: 2.8.10 -- dependencies: +- category: main + dependencies: ruamel.yaml.clib: '>=0.2.6' hash: sha256: 742b35d3d665023981bd6d16b3d24248ce5df75fdb4e2924e93a05c1f8b61ca7 manager: pip name: ruamel.yaml + optional: false platform: linux-64 url: https://files.pythonhosted.org/packages/9e/cb/938214ac358fbef7058343b3765c79a1b7ed0c366f7f992ce7ff38335652/ruamel.yaml-0.17.21-py3-none-any.whl version: 0.17.21 @@ -5521,13 +5622,13 @@ package: pyyaml: '>=6.0,<7.0' ruamel.yaml: '>=0.17.21,<0.18.0' hash: - sha256: 638a6b8c3e631f85f235acf02d3bef35a0a6d7da2ec9fef17420d5dd2ce66678 + sha256: f4fb4dd5f7fac1f2206a25d0949024046fe8f855198e8edbd5206fa9d58ab05f manager: pip name: hammer-vlsi optional: false platform: linux-64 - url: https://files.pythonhosted.org/packages/53/39/18367e6fb4f20e9ae4fb3097f7b80704ff5cccf62980ea2871ba1d817a74/hammer_vlsi-1.1.0-py3-none-any.whl - version: 1.1.0 + url: https://files.pythonhosted.org/packages/0a/da/1897421311c6332655e2f73d02d8c914ecb724198a1988aacd8f4c61ae6e/hammer_vlsi-1.1.1-py3-none-any.whl + version: 1.1.1 - category: main dependencies: asttokens: '>=2,<3' diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index ca4c96d2..1fbce68b 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -21,7 +21,7 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 1a7b0ae002798a28682d700644302284790c06503a7d3d04caa019aa74da7123 + linux-64: 3d155013008436d15b7f1d8d02c2aa15cfa96a5619d70b0a018c7ff253303935 platforms: - linux-64 sources: @@ -185,14 +185,14 @@ package: - category: main dependencies: {} hash: - md5: 7697d37e29669a14b053e82fad22a16b - sha256: ac993fa2774b90befcd6aba55b1c08853b2fa3b818753094c09bebd35fc55532 + md5: 0299e410bfb4300540bdc0012a7985ef + sha256: 8572efb7092c72fe7b73d2a0f1e5e27159a8edea0371e1bef533bcb7d85b19c6 manager: conda name: open_pdks.sky130a optional: false platform: linux-64 - url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.402_1_g12df12e-20230225_164303.tar.bz2 - version: 1.0.402_1_g12df12e + url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.406_0_g0c37b7c-20230412_103222.tar.bz2 + version: 1.0.406_0_g0c37b7c - category: main dependencies: {} hash: @@ -207,14 +207,14 @@ package: - category: main dependencies: {} hash: - md5: 51fc4fcfb19f5d95ffc8c339db5068e8 - sha256: 0bfae0b9962bc0dbf79048f9175b913ed4f53c4310d06708dc7acbb290ad82f6 + md5: 939e3e74d8be4dac89ce83b20de2492a + sha256: 0449138224adfa125b220154408419ec37c06b0b49f63c5954724325903ecf55 manager: conda name: tzdata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2022g-h191b570_0.conda - version: 2022g + url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023c-h71feb2d_0.conda + version: 2023c - category: main dependencies: font-ttf-dejavu-sans-mono: '' @@ -394,14 +394,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: 80968e6760b2448f739cd32b1324d07d - sha256: c8b52559c1867ad59510c9479a15581cbfda0a7857a33ff2fce03a76a0775cfb + md5: 2975fe44881f8dce5c3759b53abf11d1 + sha256: 1c65245dc63a3f5a57040074c61baa2ae9dcb401753503712401867b02c6dcab manager: conda name: coreutils optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/coreutils-9.2-h0b41bf4_0.conda - version: '9.2' + url: https://conda.anaconda.org/conda-forge/linux-64/coreutils-9.3-h0b41bf4_0.conda + version: '9.3' - category: main dependencies: libgcc-ng: '>=7.3.0' @@ -426,19 +426,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/ucb-bar/linux-64/dromajo-1.0.0-0_h1234567_g6a6e34e.tar.bz2 version: 1.0.0 -- category: main - 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category: main dependencies: libgcc-ng: '>=12' @@ -592,14 +579,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: 5cc781fd91968b11a8a7fdbee0982676 - sha256: f9983a8ea03531f2c14bce76c870ca325c0fddf0c4e872bff1f78bc52624179c + md5: 6aa9c9de5542ecb07fdda9ca626252d8 + sha256: 949d84ceea543802c1e085b2aa58f1d6cb5dd8cec5a9abaaf4e8ac65d6094b3a manager: conda name: libdeflate optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libdeflate-1.17-h0b41bf4_0.conda - version: '1.17' + url: https://conda.anaconda.org/conda-forge/linux-64/libdeflate-1.18-h0b41bf4_0.conda + version: '1.18' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -612,6 +599,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libev-4.33-h516909a_1.tar.bz2 version: '4.33' +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 6305a3dd2752c76335295da4e581f2fd + sha256: 74c98a563777ae2ad71f1f74d458a8ab043cee4a513467c159ccf159d0e461f3 + manager: conda + name: libexpat + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libexpat-2.5.0-hcb278e6_1.conda + version: 2.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -648,6 +647,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libiconv-1.17-h166bdaf_0.tar.bz2 version: '1.17' +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 1edd9e67bdb90d78cea97733ff6b54e6 + sha256: b19de7bda34eac4fa931be11fa8d7640cdf1441dfd51c91786586a4a4c64c92f + manager: conda + name: libjpeg-turbo + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libjpeg-turbo-2.1.5.1-h0b41bf4_0.conda + version: 2.1.5.1 - category: main dependencies: libgcc-ng: '>=9.4.0' @@ -736,16 +747,16 @@ package: version: 0.9.10 - category: main dependencies: - libgcc-ng: '>=9.3.0' + libgcc-ng: '>=12' hash: - md5: 772d69f030955d9646d3d0eaf21d859d - sha256: 54f118845498353c936826f8da79b5377d23032bcac8c4a02de2019e26c3f6b3 + md5: 40b61aab5c7ba9ff276c41cfffe6b80b + sha256: 787eb542f055a2b3de553614b25f09eefb0a0931b0c87dbcce6efdfd92f04f18 manager: conda name: libuuid optional: false platform: linux-64 - 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category: main dependencies: gettext: '' @@ -1373,20 +1397,20 @@ package: version: '1.13' - category: main dependencies: - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' libiconv: '>=1.17,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' xz: '>=5.2.6,<6.0a0' hash: - md5: bb808b654bdc3c783deaf107a2ffb503 - sha256: d4170f1fe356768758b13a51db123f990bff81b0eae0d5a0ba11c7ca6b9536f4 + md5: 241845899caff54ac1d2b3102ad988cf + sha256: 624b6e29e23a51353cff2aff7364c42b831139afd131d239e79f60aea4dae887 manager: conda name: libxml2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.3-hca2bb57_4.conda - version: 2.10.3 + url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.4-hfdac1af_0.conda + version: 2.10.4 - category: main dependencies: libgcc-ng: '>=7.3.0' @@ -1472,14 +1496,14 @@ package: libgcc-ng: '>=12' ncurses: '>=6.3,<7.0a0' hash: - md5: db2ebbe2943aae81ed051a6a9af8e0fa - sha256: f5f383193bdbe01c41cb0d6f99fec68e820875e842e6e8b392dbe1a9b6c43ed8 + md5: 47d31b792659ce70f470b5c82fdfb7a4 + sha256: 5435cf39d039387fbdc977b0a762357ea909a7694d9528ab40f005e9208744d7 manager: conda name: readline optional: false platform: linux-64 - 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version: 2.1.2 - category: main dependencies: python: '>=3.7' @@ -3353,6 +3401,23 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libxrender-0.9.10-h7f98852_1003.tar.bz2 version: 0.9.10 +- category: main + dependencies: + libgcc-ng: '>=9.3.0' + xorg-kbproto: '' + xorg-libice: 1.0.* + xorg-libsm: 1.2.* + xorg-libx11: '>=1.7.0,<2.0a0' + xorg-xproto: '' + hash: + md5: 60d6eec5273f1c9af096c10c268912e3 + sha256: 25bfc4d86df3498b88aac2f02ecf65e739bf99a687805c31a635df6f2e60a163 + manager: conda + name: xorg-libxt + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libxt-1.2.1-h7f98852_2.tar.bz2 + version: 1.2.1 - category: main dependencies: python: '>=3.7' @@ -3406,30 +3471,30 @@ package: version: 2.12.1 - category: main dependencies: - fontconfig: '>=2.13.96,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' - 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category: main dependencies: click: '' @@ -3493,8 +3573,9 @@ package: - category: main dependencies: bzip2: '>=1.0.8,<2.0a0' - expat: '>=2.5.0,<3.0a0' - libcurl: '>=7.88.1,<8.0a0' + expat: '' + libcurl: '>=7.88.1,<9.0a0' + libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libstdcxx-ng: '>=12' libuv: '' @@ -3505,14 +3586,14 @@ package: zlib: '' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 02142080aee43c8ef90db543ffbc13dd - sha256: cbd17c0375a021b7de854e0841f3f1b28b1359bc52bdc0ba5aabaee0f65a0b7d + md5: 6edec767268ad8451d27bb65f38c7ea4 + sha256: 3bb9d7c35d5297d85516769eb0517c83f7fc2ed7ab944a8c028871bb375bed51 manager: conda name: cmake optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/cmake-3.26.0-h077f3f9_0.conda - version: 3.26.0 + url: https://conda.anaconda.org/conda-forge/linux-64/cmake-3.26.3-h077f3f9_0.conda + version: 3.26.3 - category: main dependencies: libgcc-ng: '>=12' @@ -3565,7 +3646,7 @@ package: dependencies: bzip2: '>=1.0.8,<2.0a0' libarchive: '>=3.5.2,<3.6.0a0' - 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category: main dependencies: cryptography: '' @@ -4670,19 +4770,18 @@ package: - category: main dependencies: distlib: <1,>=0.3.6 - filelock: <4,>=3.4.1 - importlib-metadata: '>=4.8.3' - platformdirs: <4,>=2.4 - python: '>=3.7' + filelock: <4,>=3.11 + platformdirs: <4,>=3.2 + python: '>=3.8' hash: - md5: cb9a711f7c9f3074fe522e5a34481e60 - sha256: 28540cdda9279d7daeb8f2deec6f1128869ba90742a966e488b692e8083c5349 + md5: 054007ab693cb77a029ea4f1f12f34a7 + sha256: acb9f18ef811cda29690d41e0e7c54f7088d35e6b5aa5db6403d13c9eb18336a manager: conda name: virtualenv optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.21.0-pyhd8ed1ab_0.conda - version: 20.21.0 + url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.22.0-pyhd8ed1ab_0.conda + version: 20.22.0 - category: main dependencies: conda-package-streaming: '>=0.7.0' @@ -4748,22 +4847,22 @@ package: version: 23.13.1 - category: main dependencies: - cairo: '>=1.16.0,<2.0.0a0' - gdk-pixbuf: '>=2.42.8,<3.0a0' - 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version: 1.26.62 + url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.116-pyhd8ed1ab_0.conda + version: 1.26.116 - category: main dependencies: boto3: '' python: '>=3.6' typing-extensions: '' hash: - md5: a0ead2e95ffa5942c419234c15463344 - sha256: 7e7bb339939a50d9e682c01938062d2d4e1157a7b034d7f91e44e11d98c0d05d + md5: 93e899cf501d962cfd1b251a45416825 + sha256: ef57856f4313eac453b53a119cedf121bd16fc98c64beaee8e3309959673daea manager: conda name: mypy_boto3_ec2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.91-pyhd8ed1ab_0.conda - version: 1.26.91 + url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.106-pyhd8ed1ab_0.conda + version: 1.26.106 - category: main dependencies: docutils: <0.19 @@ -5371,18 +5471,18 @@ package: aws-xray-sdk: '!=0.96,>=0.93' boto3: '>=1.9.201' botocore: '>=1.12.201' - cfn-lint: '>=0.4.0' + cfn-lint: '>=0.40.0' cryptography: '>=3.3.1' docker-py: '>=2.5.1' - flask: '' + flask: '!=2.2.0,!=2.2.1' flask_cors: '' graphql-core: '' idna: '>=2.5,<4' importlib_metadata: '' jinja2: '>=2.10.1' jsondiff: '>=1.1.2' - openapi-spec-validator: '' - pyparsing: '' + openapi-spec-validator: '>=0.2.8' + pyparsing: '>=3.0.7' python: '>=3.3' python-dateutil: '>=2.1,<3.0.0' python-jose: '>=3.1.0,<4.0.0' @@ -5392,17 +5492,17 @@ package: responses: '>=0.9.0' setuptools: '' sshpubkeys: '>=3.1.0' - werkzeug: <2.2.0,>=0.5 + werkzeug: '>=0.5,!=2.2.0,!=2.2.1' xmltodict: '' hash: - md5: 702e5d281f691be1bec2f23d1f24fee8 - sha256: 5f7094094ef361b135068b12facdf34c18d2b285c4bd87a935ab1c7e633990ee + md5: c4172149b03b032cd60cc79f1484a1dd + sha256: 5891a5ce23d274406bda81e202ddc303d30a3355c01c7d9ae461fc5313247e9d manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.5-pyhd8ed1ab_0.conda - version: 4.1.5 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.7-pyhd8ed1ab_2.conda + version: 4.1.7 - category: main dependencies: {} hash: @@ -5455,12 +5555,14 @@ package: platform: linux-64 url: https://files.pythonhosted.org/packages/9f/53/1ac75eab589149b1e02e38185ecebf09e1b805fc3fdeadbc16d1a2b7d208/paramiko_ng-2.8.10-py2.py3-none-any.whl version: 2.8.10 -- dependencies: +- category: main + dependencies: ruamel.yaml.clib: '>=0.2.6' hash: sha256: 742b35d3d665023981bd6d16b3d24248ce5df75fdb4e2924e93a05c1f8b61ca7 manager: pip name: ruamel.yaml + optional: false platform: linux-64 url: https://files.pythonhosted.org/packages/9e/cb/938214ac358fbef7058343b3765c79a1b7ed0c366f7f992ce7ff38335652/ruamel.yaml-0.17.21-py3-none-any.whl version: 0.17.21 @@ -5496,13 +5598,13 @@ package: pyyaml: '>=6.0,<7.0' ruamel.yaml: '>=0.17.21,<0.18.0' hash: - sha256: 638a6b8c3e631f85f235acf02d3bef35a0a6d7da2ec9fef17420d5dd2ce66678 + sha256: f4fb4dd5f7fac1f2206a25d0949024046fe8f855198e8edbd5206fa9d58ab05f manager: pip name: hammer-vlsi optional: false platform: linux-64 - url: https://files.pythonhosted.org/packages/53/39/18367e6fb4f20e9ae4fb3097f7b80704ff5cccf62980ea2871ba1d817a74/hammer_vlsi-1.1.0-py3-none-any.whl - version: 1.1.0 + url: https://files.pythonhosted.org/packages/0a/da/1897421311c6332655e2f73d02d8c914ecb724198a1988aacd8f4c61ae6e/hammer_vlsi-1.1.1-py3-none-any.whl + version: 1.1.1 - category: main dependencies: asttokens: '>=2,<3' From dfe34873f755c5e236933b46e268934eb4e96dbf Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 20 Apr 2023 16:39:05 -0700 Subject: [PATCH 122/184] Revert "bump testchipip" This reverts commit bb6f8be801537aa538bfc8928b823d8b934d93c4. --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 66ff09f6..aa9170af 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 66ff09f611b7b3af7d9413f216fe9890875b727c +Subproject commit aa9170afe133e74e1c66b0082dc943e272d9e6f0 From 57d7e55457d8a223fcf0941ab5948787c896dcb4 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 20 Apr 2023 18:20:26 -0700 Subject: [PATCH 123/184] oops --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index 213e37e5..5c1f2461 100644 --- a/common.mk +++ b/common.mk @@ -231,7 +231,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIR $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler # DOC include end: FirrtlCompiler -$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST) +$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST) $(base_dir)/scripts/split-module-files.py \ --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ --dut $(TOP) \ From 4d988a24e9500010eb8c8391831bc197d51660cf Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 21 Apr 2023 09:41:56 -0700 Subject: [PATCH 124/184] fix --- scripts/uniqify-module-names.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/scripts/uniqify-module-names.py b/scripts/uniqify-module-names.py index b573dfc6..a6255a8c 100755 --- a/scripts/uniqify-module-names.py +++ b/scripts/uniqify-module-names.py @@ -71,15 +71,11 @@ def dfs_update_modules(tree, common_fnames, visited, top_fnames): cur_file = cur_module + ".sv" new_file = None - # cur_file is in the common list, generate a new file - if cur_file in common_fnames: + # cur_file is in the common list, or is a ancestor of of them, generate a new file + if (cur_file in common_fnames) or len(childs_to_update) > 0: new_file = generate_copy(cur_file, MODEL_SFX) update_filelist(cur_file, os.path.basename(new_file)) - # has some child to update, but new_file wasn't generated - if (new_file is None) and len(childs_to_update) > 0: - new_file = os.path.join(args.gcpath, cur_file) - for submodule_name in childs_to_update: if (submodule_name + ".sv") in common_fnames: bash(f"sed -i s/\"{submodule_name}\"/\"{submodule_name}_{MODEL_SFX}\"/ {new_file}") From 3c043ee27f26a831f27cb9b8aa4db7426faeacd7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Apr 2023 14:37:29 -0700 Subject: [PATCH 125/184] Use $RISCV includes for tests --- tests/Makefile | 5 +++-- tests/encoding.h | 1 - tests/hello.c | 2 +- tests/mt-hello.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) delete mode 120000 tests/encoding.h diff --git a/tests/Makefile b/tests/Makefile index 28976a6a..b61bfb30 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -2,7 +2,8 @@ # RISCV Toolchain ################################# -PREFIX = riscv64-unknown-elf- +PREFIX_NO_MINUS = riscv64-unknown-elf +PREFIX = $(PREFIX_NO_MINUS)- GCC = $(PREFIX)gcc CXX = $(PREFIX)g++ @@ -21,7 +22,7 @@ ARCH = rv64imafdc ABI = lp64d ARCHFLAGS = -march=$(ARCH) -mabi=$(ABI) -CFLAGS = -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall +CFLAGS = -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall -I$(RISCV)/$(PREFIX_NO_MINUS)/include CFLAGS += $(ARCHFLAGS) LDFLAGS = -static diff --git a/tests/encoding.h b/tests/encoding.h deleted file mode 120000 index f398b163..00000000 --- a/tests/encoding.h +++ /dev/null @@ -1 +0,0 @@ -../toolchains/riscv-tools/riscv-tests/env/encoding.h \ No newline at end of file diff --git a/tests/hello.c b/tests/hello.c index dbfbfe56..7709f91a 100644 --- a/tests/hello.c +++ b/tests/hello.c @@ -1,5 +1,5 @@ #include -#include "encoding.h" +#include "riscv-pk/encoding.h" #include "marchid.h" int main(void) { diff --git a/tests/mt-hello.c b/tests/mt-hello.c index 5ab47a56..2ba0e32f 100644 --- a/tests/mt-hello.c +++ b/tests/mt-hello.c @@ -1,4 +1,4 @@ -#include "encoding.h" +#include "riscv-pk/encoding.h" #include #include "marchid.h" From c1667adf3d2220d3f1e19742586984a182721a26 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 27 Apr 2023 20:39:07 -0700 Subject: [PATCH 126/184] trial 1 --- common.mk | 20 ++-- scripts/split-module-files.py | 111 --------------------- scripts/uniqify-module-names.py | 170 +++++++++++++++++++++++++++----- 3 files changed, 153 insertions(+), 148 deletions(-) delete mode 100755 scripts/split-module-files.py diff --git a/common.mk b/common.mk index 5c1f2461..4aeb44aa 100644 --- a/common.mk +++ b/common.mk @@ -231,26 +231,22 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIR $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler # DOC include end: FirrtlCompiler -$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST) - $(base_dir)/scripts/split-module-files.py \ +$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_TOP_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST) + $(base_dir)/scripts/uniqify-module-names.py \ --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ + --top-hier-json $(MFC_TOP_HRCHY_JSON) \ + --in-all-filelist $(MFC_FILELIST) \ --dut $(TOP) \ + --model $(MODEL) \ + --target-dir $(GEN_COLLATERAL_DIR) \ --out-dut-filelist $(TOP_MODS_FILELIST) \ --out-model-filelist $(MODEL_MODS_FILELIST) \ - --in-all-filelist $(MFC_FILELIST) \ - --target-dir $(GEN_COLLATERAL_DIR) + --out-model-hier-json $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) \ + --gcpath $(GEN_COLLATERAL_DIR) $(SED) -e 's;^;$(GEN_COLLATERAL_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST) $(SED) -i 's/\.\///' $(TOP_MODS_FILELIST) $(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST) $(SED) -i 's/\.\///' $(BB_MODS_FILELIST) - $(base_dir)/scripts/uniqify-module-names.py \ - --top-filelist $(TOP_MODS_FILELIST) \ - --mod-filelist $(MODEL_MODS_FILELIST) \ - --gen-collateral-path $(GEN_COLLATERAL_DIR) \ - --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ - --out-model-hier-json $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) \ - --dut $(TOP) \ - --model $(MODEL) sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) &: $(BB_MODS_FILELIST) $(MFC_TOP_HRCHY_JSON) $(FINAL_ANNO_FILE) diff --git a/scripts/split-module-files.py b/scripts/split-module-files.py deleted file mode 100755 index 64fe5707..00000000 --- a/scripts/split-module-files.py +++ /dev/null @@ -1,111 +0,0 @@ -#!/usr/bin/env python3 - -import json -import argparse -from typing import List, Optional - -# Schema of json emitted by circt -""" -{ - "instance_name": "TestHarness", - "module_name": "TestHarness", - "instances": [ - { - "instance_name": "chiptop", - "module_name": "ChipTop", - "instances": [ - { - "instance_name": "system", - "module_name": "DigitalTop", - "instances": [ ] - }, ... - ] - }, - { - "instance_name": "simdram", - "module_name": "SimDRAM", - "instances": [] - }, - ] -} -""" - -def get_modules(js: dict) -> List[str]: - if 'instances' not in js: - return js['module_name'] - else: - mods = [] - for mod in js['instances']: - mods.extend(get_modules(mod)) - return [js['module_name']] + mods - -def find_mod_by_name(js: dict, name: str) -> Optional[List[dict]]: - if 'instances' not in js: - return None - else: - mods = [] - for mod in js['instances']: - if mod['module_name'] == name: - mods.append(mod) - other_mods = find_mod_by_name(mod, name) - if other_mods is not None: - mods.extend(other_mods) - return mods - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description='Convert CIRCT (firtool) hierarchy JSON into DUT and test harness filelists') - parser.add_argument('--model-hier-json', type=str, required=True, help='Path to hierarchy JSON emitted by firtool. Must include DUT as a module.') - parser.add_argument('--dut', type=str, required=True, help='Name of the DUT module.') - parser.add_argument('--out-dut-filelist', type=str, required=True, help='Path to output filelist including all modules under the DUT.') - parser.add_argument('--out-model-filelist', type=str, required=True, help='Path to output filelist including all modules under the top-most module but not modules under the DUT.') - parser.add_argument('--in-all-filelist', type=str, required=True, help='Path to input filelist that has all modules (relative paths).') - parser.add_argument('--target-dir', type=str, required=True, help='Path to where module sources are located (combined with --in-all-filelist gives the absolute path to module sources).') - args = parser.parse_args() - - with open(args.model_hier_json) as f: - j = json.load(f) - - dut_tops = find_mod_by_name(j, args.dut) - assert dut_tops is not None - assert len(dut_tops) == 1 - dut_top = dut_tops[0] - - dut_mods = set(get_modules(dut_top)) - model_mods = set(get_modules(j)) - dut_mods - both_mods = dut_mods.intersection(model_mods) - - assert len(both_mods) == 0 - - with open(args.out_dut_filelist, 'w') as df, \ - open(args.in_all_filelist) as fl: - # add paths that correspond to modules to output file - for path in fl: - writeOut = False - for dm in dut_mods: - if dm in path: - writeOut = True - break - - # prepend the target directory to get filelist with absolute paths - if writeOut: - if not args.target_dir in path: - df.write(f"{args.target_dir}/{path}") - else: - df.write(f"{path}") - - with open(args.out_model_filelist, 'w') as df, \ - open(args.in_all_filelist) as fl: - # add paths that correspond to modules to output file - for path in fl: - writeOut = False - for dm in model_mods: - if dm in path: - writeOut = True - break - - # prepend the target directory to get filelist with absolute paths - if writeOut: - if not args.target_dir in path: - df.write(f"{args.target_dir}/{path}") - else: - df.write(f"{path}") diff --git a/scripts/uniqify-module-names.py b/scripts/uniqify-module-names.py index a6255a8c..87b56b63 100755 --- a/scripts/uniqify-module-names.py +++ b/scripts/uniqify-module-names.py @@ -5,19 +5,21 @@ import argparse import shutil import os import datetime - +import sys parser = argparse.ArgumentParser(description="") -parser.add_argument("--top-filelist", type=str, required=True, help="Abs path to ..top.f") -parser.add_argument("--mod-filelist", type=str, required=True, help="Abs path to ..model.f") -parser.add_argument("--gen-collateral-path", dest="gcpath", type=str, required=True, help="Abs path to the gen-collateral directory") parser.add_argument("--model-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") -parser.add_argument("--out-model-hier-json", type=str, required=True, help="Path to updated hierarchy JSON emitted by this script.") +parser.add_argument("--top-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") +parser.add_argument('--in-all-filelist', type=str, required=True, help='Path to input filelist that has all modules (relative paths).') parser.add_argument("--dut", type=str, required=True, help="Name of the DUT module.") parser.add_argument("--model", type=str, required=True, help="Name of the Model module.") +parser.add_argument('--target-dir', type=str, required=True, help='Path to where module sources are located (combined with --in-all-filelist gives the absolute path to module sources).') +parser.add_argument('--out-dut-filelist', type=str, required=True, help='Path to output filelist including all modules under the DUT.') +parser.add_argument('--out-model-filelist', type=str, required=True, help='Path to output filelist including all modules under the MODEL.') +parser.add_argument("--out-model-hier-json", type=str, required=True, help="Path to updated hierarchy JSON emitted by this script.") +parser.add_argument("--gcpath", type=str, required=True, help="Path to gen-collateral") args = parser.parse_args() - MODEL_SFX=args.model + "_UNIQUIFIED" def bash(cmd): @@ -40,9 +42,6 @@ def get_filelist(filelist): print(f"Something is wrong about this line '{line}'") return fnames -def update_filelist(cur_file, new_file): - bash(f"echo \"{args.gcpath}/{new_file}\" >> {os.path.join(args.gcpath, args.mod_filelist)}") - def generate_copy(c, sfx): (cur_name, ext) = os.path.splitext(c) new_name = cur_name + "_" + sfx @@ -55,46 +54,167 @@ def generate_copy(c, sfx): bash(f"sed -i s/\"module {cur_name}\"/\"module {new_name}\"/ {new_file}") return new_file -def dfs_update_modules(tree, common_fnames, visited, top_fnames): +def dfs_update_modules(tree, common_fnames, visited, ext_dict): # List of direct submodules to update childs_to_update = list() for child in tree['instances']: # We don't have to change stuff that are under the dut - if (child['module_name'] == args.dut) or (child['module_name'] in visited): + if (child['module_name'] == args.dut): continue - if dfs_update_modules(child, common_fnames, visited, top_fnames): + if dfs_update_modules(child, common_fnames, visited, ext_dict): childs_to_update.append(child['module_name']) - if (child['module_name'] + ".sv") in common_fnames: + if (child['module_name']) in common_fnames: child['module_name'] = child['module_name'] + "_" + MODEL_SFX cur_module = tree['module_name'] - cur_file = cur_module + ".sv" new_file = None # cur_file is in the common list, or is a ancestor of of them, generate a new file - if (cur_file in common_fnames) or len(childs_to_update) > 0: - new_file = generate_copy(cur_file, MODEL_SFX) - update_filelist(cur_file, os.path.basename(new_file)) - - for submodule_name in childs_to_update: - if (submodule_name + ".sv") in common_fnames: - bash(f"sed -i s/\"{submodule_name}\"/\"{submodule_name}_{MODEL_SFX}\"/ {new_file}") + if (cur_module in common_fnames) or len(childs_to_update) > 0: + new_file = 1 visited.add(cur_module) return (new_file is not None) +def bfs_update(tree, common_fnames, ext_dict, filelist): + q = [(tree['instance_name'], tree['module_name'], tree['instances'], None)] + + updated_submodule = set() + + while len(q) != 0: + front = q[0] + q.pop(0) + (inst, mod, child, parent) = front + + try: + cur_file = mod + "." + ext_dict[mod] + except: + cur_file = mod + ".sv" + + mod_updated = False + + # if the module is common, make a copy & update its instance in its parent + if mod in common_fnames: + mod_updated = True + new_file = generate_copy(cur_file, MODEL_SFX) + filelist.append(new_file) + if parent is not None and ((parent, mod) not in updated_submodule): + print(mod, parent) + parent_file = os.path.join(args.gcpath, parent + "." + ext_dict[parent]) + bash(f"sed -i s/\"{mod}\"/\"{mod}_{MODEL_SFX}\"/ {parent_file}") + updated_submodule.add((parent, mod)) + else: + filelist.append(cur_file) + + # set the parent module name + new_mod = mod + if mod_updated: + new_mod = mod + "_" + MODEL_SFX + ext_dict[new_mod] = ext_dict[mod] + + # traverse its children + for c in child: + if c['module_name'] != args.dut: + q.append((c['instance_name'], c['module_name'], c['instances'], new_mod)) + +def bfs_collect_modules(tree, child_to_ignore = None): + q = [(tree['instance_name'], tree['module_name'], tree['instances'])] + + modules = list() + while len(q) != 0: + front = q[0] + q.pop(0) + + (inst, mod, child) = front + modules.append(mod) + for c in child: + if c['module_name'] != child_to_ignore: + print(c['module_name']) + q.append((c['instance_name'], c['module_name'], c['instances'])) + return modules + +def write_filelist(modules, out_file): + with open(out_file, "w") as df, \ + open(args.in_all_filelist) as fl: + # add paths that correspond to modules to output file + for path in fl: + writeOut = False + for dm in modules: + if dm in path: + writeOut = True + break + + # prepend the target directory to get filelist with absolute paths + if writeOut: + if not args.target_dir in path: + df.write(f"{args.target_dir}/{path}") + else: + df.write(f"{path}") + +def write_filelist_model(modules, out_file): + with open(out_file, "w") as df: + for m in modules: + if not args.target_dir in m: + df.write(f"{args.target_dir}/{m}\n") + else: + df.write(f"{m}\n") + +def get_file_ext(all_filelist): + ext_dict = dict() + with open(args.in_all_filelist) as fl: + for path in fl: + fname = os.path.basename(path) + (module, ext) = fname.strip().split(".") + ext_dict[module] = ext + return ext_dict + def main(): - top_fnames = set(get_filelist(args.top_filelist)) - mod_fnames = set(get_filelist(args.mod_filelist)) - common_fnames = top_fnames.intersection(mod_fnames) + with open(args.model_hier_json) as imhj: + imhj_data = json.load(imhj) + modules_under_model = set(bfs_collect_modules(imhj_data, child_to_ignore=args.dut)) + + for x in modules_under_model: + print(f"model only {x}") + + with open(args.top_hier_json) as imhj: + imhj_data = json.load(imhj) + modules_under_top = set(bfs_collect_modules(imhj_data)) + + for x in modules_under_top: + print(f"top only {x}") + + common_modules = modules_under_top.intersection(modules_under_model) + + print(f"modules under top {len(modules_under_top)}") + print(f"modules under model {len(modules_under_model)}") + print(f"modules under both {len(common_modules)}") + print(f"total modules {len(modules_under_top) + len(modules_under_model) - len(common_modules)}") + + write_filelist(modules_under_top, args.out_dut_filelist) + + ext_dict = get_file_ext(args.in_all_filelist) + print(f"total modules in filelist {len(ext_dict)}") + + for x in common_modules: + print(f"common {x}") + +# for x in common_fnames: +# print(f"common_fnames {x}") + with open(args.model_hier_json) as imhj: imhj_data = json.load(imhj) with open(args.out_model_hier_json, "w+") as out_file: visited = set() - dfs_update_modules(imhj_data, common_fnames, visited, top_fnames) + filelist = list() + bfs_update(imhj_data, common_modules, ext_dict, filelist) + dfs_update_modules(imhj_data, common_modules, visited, ext_dict) json.dump(imhj_data, out_file, indent=2) + updated_modules_under_model = set(bfs_collect_modules(imhj_data, child_to_ignore=args.dut)) + print(filelist) + write_filelist_model(set(filelist), args.out_model_filelist) + if __name__ == "__main__": main() From 85abce536a4ff7e93e8cfde545d1c3cdffb981d3 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 27 Apr 2023 20:42:34 -0700 Subject: [PATCH 127/184] cleanup --- scripts/uniqify-module-names.py | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/scripts/uniqify-module-names.py b/scripts/uniqify-module-names.py index 87b56b63..28d5f971 100755 --- a/scripts/uniqify-module-names.py +++ b/scripts/uniqify-module-names.py @@ -129,7 +129,6 @@ def bfs_collect_modules(tree, child_to_ignore = None): modules.append(mod) for c in child: if c['module_name'] != child_to_ignore: - print(c['module_name']) q.append((c['instance_name'], c['module_name'], c['instances'])) return modules @@ -173,34 +172,13 @@ def main(): imhj_data = json.load(imhj) modules_under_model = set(bfs_collect_modules(imhj_data, child_to_ignore=args.dut)) - for x in modules_under_model: - print(f"model only {x}") - with open(args.top_hier_json) as imhj: imhj_data = json.load(imhj) modules_under_top = set(bfs_collect_modules(imhj_data)) - for x in modules_under_top: - print(f"top only {x}") - common_modules = modules_under_top.intersection(modules_under_model) - - print(f"modules under top {len(modules_under_top)}") - print(f"modules under model {len(modules_under_model)}") - print(f"modules under both {len(common_modules)}") - print(f"total modules {len(modules_under_top) + len(modules_under_model) - len(common_modules)}") - write_filelist(modules_under_top, args.out_dut_filelist) - ext_dict = get_file_ext(args.in_all_filelist) - print(f"total modules in filelist {len(ext_dict)}") - - for x in common_modules: - print(f"common {x}") - -# for x in common_fnames: -# print(f"common_fnames {x}") - with open(args.model_hier_json) as imhj: imhj_data = json.load(imhj) @@ -213,7 +191,6 @@ def main(): json.dump(imhj_data, out_file, indent=2) updated_modules_under_model = set(bfs_collect_modules(imhj_data, child_to_ignore=args.dut)) - print(filelist) write_filelist_model(set(filelist), args.out_model_filelist) if __name__ == "__main__": From ab9ec1650e5fc0e24295e165e0625c31c791d2b5 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 28 Apr 2023 09:15:33 -0700 Subject: [PATCH 128/184] fixes --- common.mk | 2 +- ...dule-names.py => uniquify-module-names.py} | 31 ++++++++++--------- 2 files changed, 17 insertions(+), 16 deletions(-) rename scripts/{uniqify-module-names.py => uniquify-module-names.py} (91%) diff --git a/common.mk b/common.mk index 4aeb44aa..7afdf57b 100644 --- a/common.mk +++ b/common.mk @@ -232,7 +232,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIR # DOC include end: FirrtlCompiler $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_TOP_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST) - $(base_dir)/scripts/uniqify-module-names.py \ + $(base_dir)/scripts/uniquify-module-names.py \ --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ --top-hier-json $(MFC_TOP_HRCHY_JSON) \ --in-all-filelist $(MFC_FILELIST) \ diff --git a/scripts/uniqify-module-names.py b/scripts/uniquify-module-names.py similarity index 91% rename from scripts/uniqify-module-names.py rename to scripts/uniquify-module-names.py index 28d5f971..7eb03a7c 100755 --- a/scripts/uniqify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -97,14 +97,13 @@ def bfs_update(tree, common_fnames, ext_dict, filelist): if mod in common_fnames: mod_updated = True new_file = generate_copy(cur_file, MODEL_SFX) - filelist.append(new_file) + filelist.append((mod, new_file)) if parent is not None and ((parent, mod) not in updated_submodule): - print(mod, parent) parent_file = os.path.join(args.gcpath, parent + "." + ext_dict[parent]) - bash(f"sed -i s/\"{mod}\"/\"{mod}_{MODEL_SFX}\"/ {parent_file}") + bash(f"sed -i s/\"{mod} \"/\"{mod}_{MODEL_SFX} \"/ {parent_file}") updated_submodule.add((parent, mod)) else: - filelist.append(cur_file) + filelist.append((mod, cur_file)) # set the parent module name new_mod = mod @@ -150,20 +149,24 @@ def write_filelist(modules, out_file): else: df.write(f"{path}") -def write_filelist_model(modules, out_file): +def write_filelist_model(modules, out_file, ext_dict): with open(out_file, "w") as df: - for m in modules: - if not args.target_dir in m: - df.write(f"{args.target_dir}/{m}\n") - else: - df.write(f"{m}\n") + for (m, fname) in modules: + if m in ext_dict.keys(): + if not args.target_dir in fname: + df.write(f"{args.target_dir}/{fname}\n") + else: + df.write(f"{fname}\n") def get_file_ext(all_filelist): ext_dict = dict() - with open(args.in_all_filelist) as fl: + with open(all_filelist) as fl: for path in fl: fname = os.path.basename(path) - (module, ext) = fname.strip().split(".") + fname_strip = fname.strip().split(".") + ext = fname_strip[-1] + fname_strip.pop() + module = ".".join(fname_strip) ext_dict[module] = ext return ext_dict @@ -189,9 +192,7 @@ def main(): bfs_update(imhj_data, common_modules, ext_dict, filelist) dfs_update_modules(imhj_data, common_modules, visited, ext_dict) json.dump(imhj_data, out_file, indent=2) - - updated_modules_under_model = set(bfs_collect_modules(imhj_data, child_to_ignore=args.dut)) - write_filelist_model(set(filelist), args.out_model_filelist) + write_filelist_model(set(filelist), args.out_model_filelist, ext_dict) if __name__ == "__main__": main() From 27728a70efa3ab7a5acb4133939687d80ea46b8a Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 28 Apr 2023 12:27:54 -0700 Subject: [PATCH 129/184] fix for ext modules --- scripts/uniquify-module-names.py | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index 7eb03a7c..5b058651 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -95,13 +95,16 @@ def bfs_update(tree, common_fnames, ext_dict, filelist): # if the module is common, make a copy & update its instance in its parent if mod in common_fnames: - mod_updated = True - new_file = generate_copy(cur_file, MODEL_SFX) - filelist.append((mod, new_file)) - if parent is not None and ((parent, mod) not in updated_submodule): - parent_file = os.path.join(args.gcpath, parent + "." + ext_dict[parent]) - bash(f"sed -i s/\"{mod} \"/\"{mod}_{MODEL_SFX} \"/ {parent_file}") - updated_submodule.add((parent, mod)) + try: + new_file = generate_copy(cur_file, MODEL_SFX) + filelist.append((mod, new_file)) + if parent is not None and ((parent, mod) not in updated_submodule): + parent_file = os.path.join(args.gcpath, parent + "." + ext_dict[parent]) + bash(f"sed -i s/\"{mod} \"/\"{mod}_{MODEL_SFX} \"/ {parent_file}") + updated_submodule.add((parent, mod)) + mod_updated = True + except: + print(f"No corresponding file for {cur_file}") else: filelist.append((mod, cur_file)) From 30ec9806e03c4d0f72c05f7d5f5754a662f757e1 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 28 Apr 2023 13:30:34 -0700 Subject: [PATCH 130/184] final fix --- scripts/uniquify-module-names.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index 5b058651..641ef563 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -141,7 +141,11 @@ def write_filelist(modules, out_file): for path in fl: writeOut = False for dm in modules: - if dm in path: + bm_ext = os.path.basename(path).split(".") + bm_ext.pop() + bm = ".".join(bm_ext) + print(bm) + if dm == bm: writeOut = True break From 3f80507ce4a2f8ae659da2d27ab81d0a3be8f564 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Sat, 29 Apr 2023 18:21:48 -0700 Subject: [PATCH 131/184] rm split-bb-files.py --- common.mk | 10 +--- scripts/split-bb-files.py | 82 -------------------------------- scripts/uniquify-module-names.py | 18 ++++--- variables.mk | 4 -- vlsi/Makefile | 4 +- 5 files changed, 15 insertions(+), 103 deletions(-) delete mode 100755 scripts/split-bb-files.py diff --git a/common.mk b/common.mk index 7afdf57b..0868088b 100644 --- a/common.mk +++ b/common.mk @@ -249,14 +249,6 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL $(SED) -i 's/\.\///' $(BB_MODS_FILELIST) sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST) -$(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) &: $(BB_MODS_FILELIST) $(MFC_TOP_HRCHY_JSON) $(FINAL_ANNO_FILE) - $(base_dir)/scripts/split-bb-files.py \ - --in-bb-f $(BB_MODS_FILELIST) \ - --in-top-hrchy-json $(MFC_TOP_HRCHY_JSON) \ - --in-anno-json $(FINAL_ANNO_FILE) \ - --out-top-bb-f $(TOP_BB_MODS_FILELIST) \ - --out-model-bb-f $(MODEL_BB_MODS_FILELIST) - $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) $(base_dir)/scripts/split-mems-conf.py \ --in-smems-conf $(MFC_SMEMS_CONF) \ @@ -280,7 +272,7 @@ $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE # note: {MODEL,TOP}_BB_MODS_FILELIST is added as a req. so that the files get generated, # however it is really unneeded since ALL_MODS_FILELIST includes all BB files ######################################################################################## -$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) +$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(BB_MODS_FILELIST) sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@ echo "$(TOP_SMEMS_FILE)" >> $@ echo "$(MODEL_SMEMS_FILE)" >> $@ diff --git a/scripts/split-bb-files.py b/scripts/split-bb-files.py deleted file mode 100755 index 959a10a2..00000000 --- a/scripts/split-bb-files.py +++ /dev/null @@ -1,82 +0,0 @@ -#!/usr/bin/env python3 - -import json -import argparse -from collections import defaultdict - -# Schema of *.f emitted by circt -""" -//gen-collateral/SimUART.cc -//gen-collateral/AsyncQueueSource.sv -//gen-collateral/AsyncQueueSink.sv -//gen-collateral/AsyncQueueSource_1.sv -//gen-collateral/AsyncQueueSink_1.sv -//gen-collateral/AsyncQueueSource_2.sv -//gen-collateral/AsyncQueueSink_2.sv -//gen-collateral/AsyncResetSynchronizerShiftReg_w4_d3_i0.sv -""" - -def bfs_collect_submodules(tree): - output = set() - q = [(tree['instance_name'], tree['module_name'], tree['instances'])] - - while len(q) != 0: - front = q[0] - q.pop(0) - - (inst, mod, child) = front - output.add(mod) - for c in child: - q.append((c['instance_name'], c['module_name'], c['instances'])) - return output - -def write_lines_to_file(lines, file_path): - with open(file_path, "w") as fp: - for line in lines: - fp.write("%s\n" % line) - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description='Create *.model.bb.f and *.top.bb.f blackbox filelists') - parser.add_argument('--in-bb-f', type=str, required=True, help='All blackbox files filelist (includes both MODEL/TOP files)') - parser.add_argument('--in-top-hrchy-json', type=str, required=True, help='List containing hierarchy of top modules (top-module-hierarchy.json)') - parser.add_argument('--in-anno-json', type=str, required=True, help='Anno. file with blackbox annotations') - parser.add_argument('--out-top-bb-f', type=str, required=True, help='List of blackbox files for TOP') - parser.add_argument('--out-model-bb-f', type=str, required=True, help='List of blackbox files for MODEL') - args = parser.parse_args() - - # module_path -> list of bb paths (not fully resolved paths) - mod_bb_dict = defaultdict(list) - with open(args.in_anno_json, "r") as f: - anno_data = json.load(f) - for anno in anno_data: - if 'BlackBoxInlineAnno' in anno['class']: - mod_bb_dict[anno['target']].append(anno['name']) - if 'BlackBoxPathAnno' in anno['class']: - mod_bb_dict[anno['target']].append(anno['path']) - - with open(args.in_top_hrchy_json) as ihj: - ihj_data = json.load(ihj) - top_inner_modules = bfs_collect_submodules(ihj_data) - - with open(args.in_bb_f) as ibf: - lines = ibf.read().splitlines() - - tbfs = set() - for mod_path, bb_files in mod_bb_dict.items(): - leaf_mod = mod_path.split('.')[-1] - - # if matched, add the fully resolved path to the top bb filelist - if leaf_mod in top_inner_modules: - for line in lines: - for bb_file in bb_files: - if bb_file in line: - tbfs.add(line) - - # now tbfs should be complete (need to remove tbf files from original bb file for model bb) - mbfs = set() - for line in lines: - if not line in tbfs: - mbfs.add(line) - - write_lines_to_file(tbfs, args.out_top_bb_f) - write_lines_to_file(mbfs, args.out_model_bb_f) diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index 641ef563..768a061e 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -54,14 +54,14 @@ def generate_copy(c, sfx): bash(f"sed -i s/\"module {cur_name}\"/\"module {new_name}\"/ {new_file}") return new_file -def dfs_update_modules(tree, common_fnames, visited, ext_dict): +def dfs_update_modules(tree, common_fnames, visited): # List of direct submodules to update childs_to_update = list() for child in tree['instances']: # We don't have to change stuff that are under the dut if (child['module_name'] == args.dut): continue - if dfs_update_modules(child, common_fnames, visited, ext_dict): + if dfs_update_modules(child, common_fnames, visited): childs_to_update.append(child['module_name']) if (child['module_name']) in common_fnames: child['module_name'] = child['module_name'] + "_" + MODEL_SFX @@ -87,7 +87,7 @@ def bfs_update(tree, common_fnames, ext_dict, filelist): (inst, mod, child, parent) = front try: - cur_file = mod + "." + ext_dict[mod] + cur_file = mod + "." + ext_dict[mod][0] except: cur_file = mod + ".sv" @@ -99,7 +99,7 @@ def bfs_update(tree, common_fnames, ext_dict, filelist): new_file = generate_copy(cur_file, MODEL_SFX) filelist.append((mod, new_file)) if parent is not None and ((parent, mod) not in updated_submodule): - parent_file = os.path.join(args.gcpath, parent + "." + ext_dict[parent]) + parent_file = os.path.join(args.gcpath, parent + "." + ext_dict[parent][0]) bash(f"sed -i s/\"{mod} \"/\"{mod}_{MODEL_SFX} \"/ {parent_file}") updated_submodule.add((parent, mod)) mod_updated = True @@ -165,6 +165,10 @@ def write_filelist_model(modules, out_file, ext_dict): else: df.write(f"{fname}\n") + if len(ext_dict[m]) > 1: + assert(len(ext_dict[m]) == 2) + df.write(f"{args.target_dir}/{m}.{ext_dict[m][1]}\n") + def get_file_ext(all_filelist): ext_dict = dict() with open(all_filelist) as fl: @@ -174,7 +178,9 @@ def get_file_ext(all_filelist): ext = fname_strip[-1] fname_strip.pop() module = ".".join(fname_strip) - ext_dict[module] = ext + if module not in ext_dict.keys(): + ext_dict[module] = list() + ext_dict[module].append(ext) return ext_dict def main(): @@ -197,7 +203,7 @@ def main(): visited = set() filelist = list() bfs_update(imhj_data, common_modules, ext_dict, filelist) - dfs_update_modules(imhj_data, common_modules, visited, ext_dict) + dfs_update_modules(imhj_data, common_modules, visited) json.dump(imhj_data, out_file, indent=2) write_filelist_model(set(filelist), args.out_model_filelist, ext_dict) diff --git a/variables.mk b/variables.mk index 1f659ac7..443caa94 100644 --- a/variables.mk +++ b/variables.mk @@ -186,10 +186,6 @@ MODEL_MODS_FILELIST ?= $(build_dir)/$(long_name).model.f # list of all blackbox files (may be included in the top/model.f files) # this has the build_dir appended BB_MODS_FILELIST ?= $(build_dir)/$(long_name).bb.f -# top blackbox module files to include -TOP_BB_MODS_FILELIST ?= $(build_dir)/$(long_name).top.bb.f -# model blackbox module files to include (not including top blackbox modules) -MODEL_BB_MODS_FILELIST ?= $(build_dir)/$(long_name).model.bb.f # all module files to include (top, model, bb included) ALL_MODS_FILELIST ?= $(build_dir)/$(long_name).all.f diff --git a/vlsi/Makefile b/vlsi/Makefile index 8259e7a6..ad51c754 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -72,7 +72,7 @@ VLSI_RTL = $(build_dir)/syn.f ifneq ($(CUSTOM_VLOG), ) RTL_DEPS = $(CUSTOM_VLOG) else - RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) $(TOP_SMEMS_FILE) + RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_SMEMS_FILE) endif $(VLSI_RTL): $(RTL_DEPS) @@ -80,7 +80,7 @@ ifneq ($(CUSTOM_VLOG), ) > $(VLSI_RTL) $(foreach file,$^,echo $(file) >> $(VLSI_RTL)) else - cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL) + cat $(TOP_MODS_FILELIST) | sort -u > $(VLSI_RTL) echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL) endif From a5bf60c0f1cdb3376559b887ffcfdda2109e8f38 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Sat, 29 Apr 2023 21:32:00 -0700 Subject: [PATCH 132/184] oops --- vlsi/sim.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 13a7fcc3..291c93ad 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files) echo " top_module: $(VLSI_TOP)" >> $@ echo " tb_name: ''" >> $@ # don't specify -top echo " input_files:" >> $@ - for x in $$(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ + for x in $$(cat $(MODEL_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@ From 884cf3cf6128cbe910a03d8913d10f2448db83e1 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Sun, 30 Apr 2023 13:32:46 -0700 Subject: [PATCH 133/184] deal with bb --- scripts/uniquify-module-names.py | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index 768a061e..bd7ddcd9 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -134,7 +134,7 @@ def bfs_collect_modules(tree, child_to_ignore = None): q.append((c['instance_name'], c['module_name'], c['instances'])) return modules -def write_filelist(modules, out_file): +def write_filelist(modules, out_file, files_written): with open(out_file, "w") as df, \ open(args.in_all_filelist) as fl: # add paths that correspond to modules to output file @@ -144,19 +144,20 @@ def write_filelist(modules, out_file): bm_ext = os.path.basename(path).split(".") bm_ext.pop() bm = ".".join(bm_ext) - print(bm) - if dm == bm: + print(dm, bm, bm_ext) + if (dm == bm) or (dm == bm_ext[0]): writeOut = True break # prepend the target directory to get filelist with absolute paths if writeOut: + files_written.add(os.path.basename(path)) if not args.target_dir in path: df.write(f"{args.target_dir}/{path}") else: df.write(f"{path}") -def write_filelist_model(modules, out_file, ext_dict): +def write_filelist_model(modules, out_file, ext_dict, files_written): with open(out_file, "w") as df: for (m, fname) in modules: if m in ext_dict.keys(): @@ -164,10 +165,7 @@ def write_filelist_model(modules, out_file, ext_dict): df.write(f"{args.target_dir}/{fname}\n") else: df.write(f"{fname}\n") - - if len(ext_dict[m]) > 1: - assert(len(ext_dict[m]) == 2) - df.write(f"{args.target_dir}/{m}.{ext_dict[m][1]}\n") + files_written.add(os.path.basename(fname)) def get_file_ext(all_filelist): ext_dict = dict() @@ -188,12 +186,15 @@ def main(): imhj_data = json.load(imhj) modules_under_model = set(bfs_collect_modules(imhj_data, child_to_ignore=args.dut)) + + files_written = set() + with open(args.top_hier_json) as imhj: imhj_data = json.load(imhj) modules_under_top = set(bfs_collect_modules(imhj_data)) common_modules = modules_under_top.intersection(modules_under_model) - write_filelist(modules_under_top, args.out_dut_filelist) + write_filelist(modules_under_top, args.out_dut_filelist, files_written) ext_dict = get_file_ext(args.in_all_filelist) with open(args.model_hier_json) as imhj: @@ -205,7 +206,15 @@ def main(): bfs_update(imhj_data, common_modules, ext_dict, filelist) dfs_update_modules(imhj_data, common_modules, visited) json.dump(imhj_data, out_file, indent=2) - write_filelist_model(set(filelist), args.out_model_filelist, ext_dict) + write_filelist_model(set(filelist), args.out_model_filelist, ext_dict, files_written) + + with open(args.out_model_filelist, "a") as of, \ + open(args.in_all_filelist) as fl: + for path in fl: + fname = os.path.basename(path) + ext = fname.strip().split(".")[-1] + if (fname not in files_written) and (ext == "cc"): + of.write(f"{args.target_dir}/{fname}") if __name__ == "__main__": main() From a299dae1a5abc24bff77539355ff3b27c8e5fcd9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 20 Apr 2023 18:58:53 -0700 Subject: [PATCH 134/184] Initialize cospike memory from SimDRAM memory --- .../src/main/resources/csrc/cospike.cc | 172 ++++++++++-------- generators/testchipip | 2 +- 2 files changed, 98 insertions(+), 76 deletions(-) diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index 1b4cdb93..f531e61f 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -20,6 +20,12 @@ extern testchip_dtm_t* dtm; bool spike_loadarch_done = false; #endif +#if __has_include ("mm.h") +#define COSPIKE_SIMDRAM +#include "mm.h" +extern std::map backing_mem_data; +#endif + #define CLINT_BASE (0x2000000) #define CLINT_SIZE (0x1000) @@ -169,6 +175,22 @@ extern "C" void cospike_cosim(long long int cycle, nullptr ); +#ifdef COSPIKE_SIMDRAM + // match sim_t's backing memory with the SimDRAM memory + bus_t temp_mem_bus; + for (auto& pair : mems) temp_mem_bus.add_device(pair.first, pair.second); + + for (auto& pair : backing_mem_data) { + size_t base = pair.first; + size_t size = pair.second.size; + printf("Matching spike memory initial state for region %lx-%lx\n", base, base + size); + if (!temp_mem_bus.store(base, size, pair.second.data)) { + printf("Error, unable to match memory at address %lx\n", base); + abort(); + } + } +#endif + sim->configure_log(true, true); // Use our own reset vector for (int i = 0; i < info->nharts; i++) { @@ -281,10 +303,10 @@ extern "C" void cospike_cosim(long long int cycle, if (s_pc != iaddr) { printf("%d PC mismatch spike %llx != DUT %llx\n", cycle, s_pc, iaddr); if (unlikely(cospike_debug)) { - printf("spike mstatus is %lx\n", s->mstatus->read()); - printf("spike mcause is %lx\n", s->mcause->read()); - printf("spike mtval is %lx\n" , s->mtval->read()); - printf("spike mtinst is %lx\n", s->mtinst->read()); + printf("spike mstatus is %lx\n", s->mstatus->read()); + printf("spike mcause is %lx\n", s->mcause->read()); + printf("spike mtval is %lx\n" , s->mtval->read()); + printf("spike mtinst is %lx\n", s->mtinst->read()); } exit(1); } @@ -305,80 +327,80 @@ extern "C" void cospike_cosim(long long int cycle, printf("Probable magic mem %lx\n", w_data); magic_addrs.insert(w_data); } - } - // Try to remember magic_mem addrs, and ignore these in the future - if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { - printf("Probable magic mem %lx\n", w_data); - magic_addrs.insert(w_data); - } - } - - bool scalar_wb = false; - bool vector_wb = false; - uint32_t vector_cnt = 0; - - for (auto ®write : log) { - - //TODO: scaling to multi issue reads? - reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]); - - int rd = regwrite.first >> 4; - int type = regwrite.first & 0xf; - - // 0 => int - // 1 => fp - // 2 => vec - // 3 => vec hint - // 4 => csr - - bool ignore_read = (!mem_read.empty() && - ((magic_addrs.count(mem_read_addr) || - (tohost_addr && mem_read_addr == tohost_addr) || - (fromhost_addr && mem_read_addr == fromhost_addr) || - (CLINT_BASE <= mem_read_addr && - mem_read_addr < (CLINT_BASE + CLINT_SIZE))))); - - // check the type is compliant with writeback first - if ((type == 0 || type == 1)) - scalar_wb = true; - if (type == 2) { - vector_wb = true; - } - if (type == 3) continue; - - - if ((rd != 0 && type == 0) || type == 1) { - // Override reads from some CSRs - uint64_t csr_addr = (insn >> 20) & 0xfff; - bool csr_read = (insn & 0x7f) == 0x73; - if (csr_read) - printf("CSR read %lx\n", csr_addr); - if (csr_read && ((csr_addr == 0xf13) || // mimpid - (csr_addr == 0xf12) || // marchid - (csr_addr == 0xf11) || // mvendorid - (csr_addr == 0xb00) || // mcycle - (csr_addr == 0xb02) || // minstret - (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr - )) { - printf("CSR override\n"); - s->XPR.write(rd, wdata); - } else if (ignore_read) { - // Don't check reads from tohost, reads from magic memory, or reads - // from clint Technically this could be buggy because log_mem_read - // only reports vaddrs, but no software ever should access - // tohost/fromhost/clint with vaddrs anyways - printf("Read override %lx\n", mem_read_addr); - s->XPR.write(rd, wdata); - } else if (wdata != regwrite.second.v[0]) { - printf("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd, - regwrite.second.v[0], wdata); - exit(1); + // Try to remember magic_mem addrs, and ignore these in the future + if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { + printf("Probable magic mem %lx\n", w_data); + magic_addrs.insert(w_data); } } - if (scalar_wb ^ has_wdata) { - printf("Scalar behavior divergence between spike and DUT\n"); - exit(-1); + bool scalar_wb = false; + bool vector_wb = false; + uint32_t vector_cnt = 0; + + for (auto ®write : log) { + + //TODO: scaling to multi issue reads? + reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]); + + int rd = regwrite.first >> 4; + int type = regwrite.first & 0xf; + + // 0 => int + // 1 => fp + // 2 => vec + // 3 => vec hint + // 4 => csr + + bool ignore_read = (!mem_read.empty() && + ((magic_addrs.count(mem_read_addr) || + (tohost_addr && mem_read_addr == tohost_addr) || + (fromhost_addr && mem_read_addr == fromhost_addr) || + (CLINT_BASE <= mem_read_addr && mem_read_addr < (CLINT_BASE + CLINT_SIZE))))); + + // check the type is compliant with writeback first + if ((type == 0 || type == 1)) + scalar_wb = true; + if (type == 2) { + vector_wb = true; + } + if (type == 3) continue; + + + if ((rd != 0 && type == 0) || type == 1) { + // Override reads from some CSRs + uint64_t csr_addr = (insn >> 20) & 0xfff; + bool csr_read = (insn & 0x7f) == 0x73; + if (csr_read) + printf("CSR read %lx\n", csr_addr); + if (csr_read && ((csr_addr == 0xf13) || // mimpid + (csr_addr == 0xf12) || // marchid + (csr_addr == 0xf11) || // mvendorid + (csr_addr == 0xb00) || // mcycle + (csr_addr == 0xb02) || // minstret + (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr + )) { + printf("CSR override\n"); + s->XPR.write(rd, wdata); + } else if (ignore_read) { + // Don't check reads from tohost, reads from magic memory, or reads + // from clint Technically this could be buggy because log_mem_read + // only reports vaddrs, but no software ever should access + // tohost/fromhost/clint with vaddrs anyways + printf("Read override %lx\n", mem_read_addr); + s->XPR.write(rd, wdata); + } else if (wdata != regwrite.second.v[0]) { + printf("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd, + regwrite.second.v[0], wdata); + exit(1); + } + } + + // TODO FIX: Rocketchip TracedInstruction.wdata should be Valid(UInt) + // if (scalar_wb ^ has_wdata) { + // printf("Scalar wdata behavior divergence between spike and DUT\n"); + // exit(-1); + // } } } } diff --git a/generators/testchipip b/generators/testchipip index b192ac11..de6a4a19 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b192ac11d2e88579f9d1329578e88de5c5c1fde4 +Subproject commit de6a4a19b523020104ccb8f41a6cb23bdcd7f6fb From b91e24a30a44c3f80b62a8eff3489da361e1fe32 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 1 May 2023 10:51:15 -0700 Subject: [PATCH 135/184] Use pk/encoding.h for hello/mt-hello --- tests/encoding.h | 1 - tests/hello.c | 2 +- tests/mt-hello.c | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) delete mode 120000 tests/encoding.h diff --git a/tests/encoding.h b/tests/encoding.h deleted file mode 120000 index f398b163..00000000 --- a/tests/encoding.h +++ /dev/null @@ -1 +0,0 @@ -../toolchains/riscv-tools/riscv-tests/env/encoding.h \ No newline at end of file diff --git a/tests/hello.c b/tests/hello.c index dbfbfe56..626cd930 100644 --- a/tests/hello.c +++ b/tests/hello.c @@ -1,5 +1,5 @@ #include -#include "encoding.h" +#include #include "marchid.h" int main(void) { diff --git a/tests/mt-hello.c b/tests/mt-hello.c index 5ab47a56..f0f521c7 100644 --- a/tests/mt-hello.c +++ b/tests/mt-hello.c @@ -1,4 +1,4 @@ -#include "encoding.h" +#include #include #include "marchid.h" From 1cc5ea519200f7d4037d53ee1de0eb6e65997a28 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 3 May 2023 18:23:16 -0700 Subject: [PATCH 136/184] Fix no-uart configs (#1457) --- generators/chipyard/src/main/scala/Subsystem.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 6a07ff64..e98a51bc 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -65,6 +65,7 @@ trait CanHaveChosenInDTS { this: BaseSubsystem => t.uarts.foreach(u => Resource(chosen, "uart").bind(ResourceAlias(u.device.label))) } } + case _ => } } } From b05f36df793c0b1cef24fc27767007db658b92a5 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 3 May 2023 18:23:36 -0700 Subject: [PATCH 137/184] Fix support for no-bootROM systems (#1458) --- generators/chipyard/src/main/scala/System.scala | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index a6c4b6b3..5643e380 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -31,6 +31,14 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } + + // If there is no bootrom, the tile reset vector bundle will be tied to zero + if (bootROM.isEmpty) { + val fakeResetVectorSourceNode = BundleBridgeSource[UInt]() + InModuleBody { fakeResetVectorSourceNode.bundle := 0.U } + tileResetVectorNexusNode := fakeResetVectorSourceNode + } + override lazy val module = new ChipyardSystemModule(this) } From b8ccb7d4f6affe0bbc33ecb24b30a1b6b1b13b10 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 4 May 2023 17:15:38 -0700 Subject: [PATCH 138/184] Support not instantiating the TileClockGater/ResetSetter PRCI controllers (#1459) --- .../src/main/scala/clocking/HasChipyardPRCI.scala | 14 ++++++++------ .../src/main/scala/clocking/TileClockGater.scala | 8 ++++---- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index d2c4f2e5..d571bc95 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -20,7 +20,8 @@ import chipyard.{DefaultClockFrequencyKey} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, - enableTileClockGating: Boolean = true + enableTileClockGating: Boolean = true, + enableTileResetSetting: Boolean = true ) @@ -72,12 +73,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = ClockGroupResetSynchronizer() - val tileClockGater = prci_ctrl_domain { - TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating) - } - val tileResetSetter = prci_ctrl_domain { + val tileClockGater = if (prciParams.enableTileClockGating) { prci_ctrl_domain { + TileClockGater(prciParams.baseAddress + 0x00000, tlbus) + } } else { ClockGroupEphemeralNode() } + val tileResetSetter = if (prciParams.enableTileResetSetting) { prci_ctrl_domain { TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) - } + } } else { ClockGroupEphemeralNode() } + (aggregator := frequencySpecifier := clockGroupCombiner diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala index a77b02d5..23d525a6 100644 --- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala +++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala @@ -19,7 +19,7 @@ import freechips.rocketchip.subsystem._ * flag will generate the registers, preserving the same memory map and behavior, but will not * generate any gaters */ -class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit p: Parameters, valName: ValName) extends LazyModule +class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, valName: ValName) extends LazyModule { val device = new SimpleDevice(s"clock-gater", Nil) val clockNode = ClockGroupIdentityNode() @@ -31,7 +31,7 @@ class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit val regs = (0 until nSinks).map({i => val sinkName = sinks(i)._1 val reg = withReset(sources(i).reset) { Module(new AsyncResetRegVec(w=1, init=1)) } - if (sinkName.contains("tile") && enable) { + if (sinkName.contains("tile")) { println(s"${(address+i*4).toString(16)}: Tile $sinkName clock gate") sinks(i)._2.clock := ClockGate(sources(i).clock, reg.io.q.asBool) sinks(i)._2.reset := sources(i).reset @@ -47,8 +47,8 @@ class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit } object TileClockGater { - def apply(address: BigInt, tlbus: TLBusWrapper, enable: Boolean)(implicit p: Parameters, v: ValName) = { - val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes, enable)) + def apply(address: BigInt, tlbus: TLBusWrapper)(implicit p: Parameters, v: ValName) = { + val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes)) tlbus.toVariableWidthSlave(Some("clock-gater")) { gater.tlNode := TLBuffer() } gater.clockNode } From 60e80a772ef59af8db7c1ccd8502ce9fd69acdfb Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 4 May 2023 20:15:21 -0700 Subject: [PATCH 139/184] Cleanup + fixes, think it's stable now --- scripts/uniquify-module-names.py | 277 +++++++++++++++---------------- 1 file changed, 132 insertions(+), 145 deletions(-) diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index bd7ddcd9..12a0843e 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -4,24 +4,25 @@ import json import argparse import shutil import os -import datetime import sys + parser = argparse.ArgumentParser(description="") parser.add_argument("--model-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") parser.add_argument("--top-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") parser.add_argument('--in-all-filelist', type=str, required=True, help='Path to input filelist that has all modules (relative paths).') parser.add_argument("--dut", type=str, required=True, help="Name of the DUT module.") parser.add_argument("--model", type=str, required=True, help="Name of the Model module.") -parser.add_argument('--target-dir', type=str, required=True, help='Path to where module sources are located (combined with --in-all-filelist gives the absolute path to module sources).') parser.add_argument('--out-dut-filelist', type=str, required=True, help='Path to output filelist including all modules under the DUT.') parser.add_argument('--out-model-filelist', type=str, required=True, help='Path to output filelist including all modules under the MODEL.') parser.add_argument("--out-model-hier-json", type=str, required=True, help="Path to updated hierarchy JSON emitted by this script.") +parser.add_argument('--target-dir', type=str, required=True, help='Path to where module sources are located (combined with --in-all-filelist gives the absolute path to module sources).') parser.add_argument("--gcpath", type=str, required=True, help="Path to gen-collateral") args = parser.parse_args() MODEL_SFX=args.model + "_UNIQUIFIED" + def bash(cmd): fail = os.system(cmd) if fail: @@ -30,17 +31,74 @@ def bash(cmd): else: print(cmd) -def get_filelist(filelist): - fnames = [] - with open(filelist) as f: +def bfs_collect_modules(tree, child_to_ignore = None): + q = [(tree['instance_name'], tree['module_name'], tree['instances'])] + + modules = list() + while len(q) != 0: + front = q[0] + q.pop(0) + + (inst, mod, child) = front + modules.append(mod) + for c in child: + if c['module_name'] != child_to_ignore: + q.append((c['instance_name'], c['module_name'], c['instances'])) + return modules + +def get_modules_in_verilog_file(file): + module_names = list() + with open(file) as f: lines = f.readlines() for line in lines: - try: - fname = line.split("/")[-1].strip() - fnames.append(fname) - except: - print(f"Something is wrong about this line '{line}'") - return fnames + words = line.split() + if len(words) > 0 and words[0] == "module": + module_names.append(words[1].replace("(", "")) + return module_names + +def get_modules_in_filelist(verilog_module_filename, cc_filelist): + with open(args.in_all_filelist) as fl: + lines = fl.readlines() + for line in lines: + path = line.strip() + basepath = os.path.basename(path) + ext = basepath.split(".")[-1] + + if (ext == "v") or (ext == "sv"): + modules = get_modules_in_verilog_file(os.path.join(args.gcpath, basepath)) + for module in modules: + verilog_module_filename[module] = basepath + else: + cc_filelist.append(basepath) + return (verilog_module_filename, cc_filelist) + +def get_modules_under_hier(hier, child_to_ignore=None): + with open(hier) as hj: + hj_data = json.load(hj) + modules_under_hier = set(bfs_collect_modules(hj_data, child_to_ignore=child_to_ignore)) + return modules_under_hier + +def write_verilog_filelist(modules, verilog_module_filename, out_filelist): + written_files = set() + existing_modules = verilog_module_filename.keys() + + with open(out_filelist, "w") as df: + for module in modules: + if module in existing_modules: + verilog_filename = verilog_module_filename[module] + if verilog_filename not in written_files: + written_files.add(verilog_filename) + if args.target_dir in verilog_filename: + df.write(f"{verilog_filename}\n") + else: + df.write(f"{args.target_dir}/{verilog_filename}\n") + return written_files + +def write_cc_filelist(filelist, out_filelist): + with open(out_filelist, "a") as df: + for path in filelist: + file = os.path.basename(path) + df.write(f"{args.target_dir}/{file}\n") def generate_copy(c, sfx): (cur_name, ext) = os.path.splitext(c) @@ -54,6 +112,44 @@ def generate_copy(c, sfx): bash(f"sed -i s/\"module {cur_name}\"/\"module {new_name}\"/ {new_file}") return new_file +def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename): + q = [(tree['instance_name'], tree['module_name'], tree['instances'], None)] + updated_submodule = set() + existing_modules = verilog_module_filename.keys() + + while len(q) != 0: + front = q[0] + q.pop(0) + (inst, mod, child, parent) = front + + # external module + if mod not in existing_modules: + assert(len(child) == 0) + continue + + cur_file = verilog_module_filename[mod] + + # if the module is common, make a copy & update its instance in its parent + new_mod = mod + if mod in common_fnames: + try: + new_file = generate_copy(cur_file, MODEL_SFX) + if parent is not None and ((parent, mod) not in updated_submodule): + parent_file = os.path.join(args.gcpath, verilog_module_filename[parent]) + bash(f"sed -i s/\"{mod} \"/\"{mod}_{MODEL_SFX} \"/ {parent_file}") + updated_submodule.add((parent, mod)) + + # add the uniquified module to the verilog_modul_filename dict + new_mod = mod + "_" + MODEL_SFX + verilog_module_filename[new_mod] = new_file + except: + print(f"No corresponding file for {cur_file}") + + # traverse its children + for c in child: + if c['module_name'] != args.dut: + q.append((c['instance_name'], c['module_name'], c['instances'], new_mod)) + def dfs_update_modules(tree, common_fnames, visited): # List of direct submodules to update childs_to_update = list() @@ -76,145 +172,36 @@ def dfs_update_modules(tree, common_fnames, visited): visited.add(cur_module) return (new_file is not None) -def bfs_update(tree, common_fnames, ext_dict, filelist): - q = [(tree['instance_name'], tree['module_name'], tree['instances'], None)] - - updated_submodule = set() - - while len(q) != 0: - front = q[0] - q.pop(0) - (inst, mod, child, parent) = front - - try: - cur_file = mod + "." + ext_dict[mod][0] - except: - cur_file = mod + ".sv" - - mod_updated = False - - # if the module is common, make a copy & update its instance in its parent - if mod in common_fnames: - try: - new_file = generate_copy(cur_file, MODEL_SFX) - filelist.append((mod, new_file)) - if parent is not None and ((parent, mod) not in updated_submodule): - parent_file = os.path.join(args.gcpath, parent + "." + ext_dict[parent][0]) - bash(f"sed -i s/\"{mod} \"/\"{mod}_{MODEL_SFX} \"/ {parent_file}") - updated_submodule.add((parent, mod)) - mod_updated = True - except: - print(f"No corresponding file for {cur_file}") - else: - filelist.append((mod, cur_file)) - - # set the parent module name - new_mod = mod - if mod_updated: - new_mod = mod + "_" + MODEL_SFX - ext_dict[new_mod] = ext_dict[mod] - - # traverse its children - for c in child: - if c['module_name'] != args.dut: - q.append((c['instance_name'], c['module_name'], c['instances'], new_mod)) - -def bfs_collect_modules(tree, child_to_ignore = None): - q = [(tree['instance_name'], tree['module_name'], tree['instances'])] - - modules = list() - while len(q) != 0: - front = q[0] - q.pop(0) - - (inst, mod, child) = front - modules.append(mod) - for c in child: - if c['module_name'] != child_to_ignore: - q.append((c['instance_name'], c['module_name'], c['instances'])) - return modules - -def write_filelist(modules, out_file, files_written): - with open(out_file, "w") as df, \ - open(args.in_all_filelist) as fl: - # add paths that correspond to modules to output file - for path in fl: - writeOut = False - for dm in modules: - bm_ext = os.path.basename(path).split(".") - bm_ext.pop() - bm = ".".join(bm_ext) - print(dm, bm, bm_ext) - if (dm == bm) or (dm == bm_ext[0]): - writeOut = True - break - - # prepend the target directory to get filelist with absolute paths - if writeOut: - files_written.add(os.path.basename(path)) - if not args.target_dir in path: - df.write(f"{args.target_dir}/{path}") - else: - df.write(f"{path}") - -def write_filelist_model(modules, out_file, ext_dict, files_written): - with open(out_file, "w") as df: - for (m, fname) in modules: - if m in ext_dict.keys(): - if not args.target_dir in fname: - df.write(f"{args.target_dir}/{fname}\n") - else: - df.write(f"{fname}\n") - files_written.add(os.path.basename(fname)) - -def get_file_ext(all_filelist): - ext_dict = dict() - with open(all_filelist) as fl: - for path in fl: - fname = os.path.basename(path) - fname_strip = fname.strip().split(".") - ext = fname_strip[-1] - fname_strip.pop() - module = ".".join(fname_strip) - if module not in ext_dict.keys(): - ext_dict[module] = list() - ext_dict[module].append(ext) - return ext_dict - -def main(): - with open(args.model_hier_json) as imhj: - imhj_data = json.load(imhj) - modules_under_model = set(bfs_collect_modules(imhj_data, child_to_ignore=args.dut)) - - - files_written = set() - - with open(args.top_hier_json) as imhj: - imhj_data = json.load(imhj) - modules_under_top = set(bfs_collect_modules(imhj_data)) - - common_modules = modules_under_top.intersection(modules_under_model) - write_filelist(modules_under_top, args.out_dut_filelist, files_written) - ext_dict = get_file_ext(args.in_all_filelist) - +def uniquify_modules_under_model(modules_under_model, common_modules, verilog_module_filename): with open(args.model_hier_json) as imhj: imhj_data = json.load(imhj) + visited = set() + bfs_uniquify_modules(imhj_data, common_modules, verilog_module_filename) + dfs_update_modules (imhj_data, common_modules, visited) with open(args.out_model_hier_json, "w+") as out_file: - visited = set() - filelist = list() - bfs_update(imhj_data, common_modules, ext_dict, filelist) - dfs_update_modules(imhj_data, common_modules, visited) json.dump(imhj_data, out_file, indent=2) - write_filelist_model(set(filelist), args.out_model_filelist, ext_dict, files_written) - with open(args.out_model_filelist, "a") as of, \ - open(args.in_all_filelist) as fl: - for path in fl: - fname = os.path.basename(path) - ext = fname.strip().split(".")[-1] - if (fname not in files_written) and (ext == "cc"): - of.write(f"{args.target_dir}/{fname}") +def main(): + verilog_module_filename = dict() + cc_filelist = list() + get_modules_in_filelist(verilog_module_filename, cc_filelist) -if __name__ == "__main__": + modules_under_model = get_modules_under_hier(args.model_hier_json, args.dut) + modules_under_top = get_modules_under_hier(args.top_hier_json) + common_modules = modules_under_top.intersection(modules_under_model) + + # write top filelist + write_verilog_filelist(modules_under_top, verilog_module_filename, args.out_dut_filelist) + + # rename modules that are common + uniquify_modules_under_model(modules_under_model, common_modules, verilog_module_filename) + uniquified_modules_under_model = get_modules_under_hier(args.out_model_hier_json, args.dut) + + # write model filelist + write_verilog_filelist(uniquified_modules_under_model, verilog_module_filename, args.out_model_filelist) + write_cc_filelist (cc_filelist, args.out_model_filelist) + + +if __name__=="__main__": main() From fec43fc14725859ec144c63f7c9a64f1c95cc512 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 4 May 2023 21:51:00 -0700 Subject: [PATCH 140/184] corner case --- scripts/uniquify-module-names.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index 12a0843e..75fc8c85 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -53,7 +53,7 @@ def get_modules_in_verilog_file(file): for line in lines: words = line.split() if len(words) > 0 and words[0] == "module": - module_names.append(words[1].replace("(", "")) + module_names.append(words[1].replace("(", "").replace(")", "").replace(";", "")) return module_names def get_modules_in_filelist(verilog_module_filename, cc_filelist): From 257e7d7507163a20132dfb28cc88b2635c529638 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 5 May 2023 17:09:07 -0700 Subject: [PATCH 141/184] Check that HarnessClockInstantiator doesn't receive requests for similarly-named-clocks with different frequencies (#1460) --- .../chipyard/src/main/scala/HarnessClocks.scala | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessClocks.scala b/generators/chipyard/src/main/scala/HarnessClocks.scala index c256caba..f9665e12 100644 --- a/generators/chipyard/src/main/scala/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/HarnessClocks.scala @@ -21,9 +21,15 @@ trait HarnessClockInstantiator { // request a clock bundle at a particular frequency def requestClockBundle(name: String, freqRequested: Double): ClockBundle = { - val clockBundle = Wire(new ClockBundle(ClockBundleParameters())) - _clockMap(name) = (freqRequested, clockBundle) - clockBundle + if (_clockMap.contains(name)) { + require(freqRequested == _clockMap(name)._1, + s"Request clock freq = $freqRequested != previously requested ${_clockMap(name)._2} for requested clock $name") + _clockMap(name)._2 + } else { + val clockBundle = Wire(new ClockBundle(ClockBundleParameters())) + _clockMap(name) = (freqRequested, clockBundle) + clockBundle + } } // refClock is the clock generated by TestDriver that is From d61be5cb1ca896c2fa9e88dfa3990cf1972dfc12 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 6 May 2023 19:27:31 -0700 Subject: [PATCH 142/184] Remove unnecessary include from tests/Makefile --- tests/Makefile | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/Makefile b/tests/Makefile index b61bfb30..28976a6a 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -2,8 +2,7 @@ # RISCV Toolchain ################################# -PREFIX_NO_MINUS = riscv64-unknown-elf -PREFIX = $(PREFIX_NO_MINUS)- +PREFIX = riscv64-unknown-elf- GCC = $(PREFIX)gcc CXX = $(PREFIX)g++ @@ -22,7 +21,7 @@ ARCH = rv64imafdc ABI = lp64d ARCHFLAGS = -march=$(ARCH) -mabi=$(ABI) -CFLAGS = -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall -I$(RISCV)/$(PREFIX_NO_MINUS)/include +CFLAGS = -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall CFLAGS += $(ARCHFLAGS) LDFLAGS = -static From 49dd3860db90dec2b59e35d8c99a4bc7648a66ae Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 6 May 2023 19:31:15 -0700 Subject: [PATCH 143/184] Update CHANGELOG.md --- CHANGELOG.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 6867e1d2..8e7ed003 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -11,6 +11,7 @@ Various fixes for Linux boot, More Chip/bringup examples, Chisel 3.5.6 bump * PLL integration example + FlatChipTop/TestHarness by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1427 * Bump TestChipIp to improve default serial_tl behavior by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1435 * Bump testchipip to standardize TL serdesser bundle params by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1446 +* HarnessBinder asserts to catch bad clock generation by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1460 ### Changed * New Scala-based Config Finder by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1424 @@ -19,12 +20,15 @@ Various fixes for Linux boot, More Chip/bringup examples, Chisel 3.5.6 bump * bump testchipip by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1434 * ADD: improve Makefile in tests/, add explicit arch flags by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1439 * Various submodule bumps by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1448 +* Support not instantiating tile reset/clock contorl features by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1459 ### Fixed * Various improvements and fixes by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1420 * Ensure conda cleanup regex properly filters out non-numeric chars by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1425 * Fix ChipLikeQuadRocketConfig crossing by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1436 * Uniquify module names that are common to Top & Model by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1442 +* Support for no-bootROM systems by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1458 +* Support for no-UART systems by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1457 ## [1.9.0] - 2023-03-23 From 40d0a1f3bd780ce11761727a0dc54b736578f50d Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sun, 7 May 2023 11:47:14 -0700 Subject: [PATCH 144/184] low mem configs --- generators/firechip/src/main/scala/TargetConfigs.scala | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 7af98c57..d7f6008a 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -186,6 +186,14 @@ class FireSimRocketConfig extends Config( new chipyard.RocketConfig) // DOC include end: firesimconfig +class FireSimRocket1GiBDRAMConfig extends Config( + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++ + new FireSimRocketConfig) + +class FireSimRocketMMIOOnly1GiBDRAMConfig extends Config( + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++ + new FireSimRocketMMIOOnlyConfig) + class FireSimQuadRocketConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ From 20fb8d2556b0fe2aa4ea1e03630b5feb1a4af7f4 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 7 May 2023 11:51:17 -0700 Subject: [PATCH 145/184] Update README.md --- README.md | 3 --- sims/firesim | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/README.md b/README.md index a21b142e..91aa07ef 100644 --- a/README.md +++ b/README.md @@ -2,9 +2,6 @@ # Chipyard Framework [![Test](https://github.com/ucb-bar/chipyard/actions/workflows/chipyard-run-tests.yml/badge.svg)](https://github.com/ucb-bar/chipyard/actions) -| We're running the First FireSim and Chipyard User/Developer Workshop at ASPLOS 2023 on March 26, 2023! This workshop will feature a full-day of submitted talks from users and developers in the FireSim and Chipyard community. Learn more and **submit your work** on the [2023 Workshop Page](https://fires.im/workshop-2023/)! | -|-----| - ## Quick Links * **Stable Documentation**: https://chipyard.readthedocs.io/ diff --git a/sims/firesim b/sims/firesim index 8c301ad5..3ae68ec3 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 8c301ad57ba962bf61838308b09121fcda6e190c +Subproject commit 3ae68ec3076c010c633ded369fd3874ec2e5e557 From 4eb0f81c1695b5d183219ef0914f908909fa4632 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 7 May 2023 16:02:23 -0700 Subject: [PATCH 146/184] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index de6a4a19..b6676e51 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit de6a4a19b523020104ccb8f41a6cb23bdcd7f6fb +Subproject commit b6676e5122e9ffab10928cc00417e163dc69c952 From 2d76a4fea92a61c197bcfb99db9d5fdb1a5fa96b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 3 May 2023 13:19:37 -0700 Subject: [PATCH 147/184] Always initialize fpga-shells with init-submodules.sh FPGA shells is ultra fast to clone, and this makes the normal repo init script actually set up the repo properly for all possible use cases. --- scripts/init-submodules-no-riscv-tools-nolog.sh | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index b3426288..bd723595 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -107,8 +107,7 @@ cd "$RDIR" software/coremark \ software/firemarshal \ software/spec2017 \ - vlsi/hammer-mentor-plugins \ - fpga/fpga-shells + vlsi/hammer-mentor-plugins do "$1" "${name%/}" done From f01101da4b841c5d54dbd9517f3e5a07f786d139 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 3 May 2023 18:36:08 -0700 Subject: [PATCH 148/184] Remove init-fpga scripts and references, init-submodules now also inits-fpga --- .github/scripts/remote-do-rtl-build.sh | 2 -- docs/Prototyping/General.rst | 9 +-------- scripts/build-setup.sh | 1 - scripts/init-fpga.sh | 12 ------------ 4 files changed, 1 insertion(+), 23 deletions(-) delete mode 100755 scripts/init-fpga.sh diff --git a/.github/scripts/remote-do-rtl-build.sh b/.github/scripts/remote-do-rtl-build.sh index 445c1c31..06b47ba2 100755 --- a/.github/scripts/remote-do-rtl-build.sh +++ b/.github/scripts/remote-do-rtl-build.sh @@ -16,8 +16,6 @@ source $SCRIPT_DIR/defaults.sh cd $REMOTE_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh --force -./scripts/init-fpga.sh - # Constellation can run without espresso, but this improves # elaboration time drastically diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index 89c0b512..2b7a7332 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -1,18 +1,11 @@ General Setup and Usage ============================== -Sources and Submodule Setup +Sources --------------------------- All FPGA prototyping-related collateral and sources are located in the ``fpga`` top-level Chipyard directory. This includes the ``fpga-shells`` submodule and the ``src`` directory that hold both Scala, TCL and other collateral. -However, the ``fpga-shells`` submodule repository is not initialized by default. -To initialize the ``fpga-shells`` submodule repository, run the included initialization script from the Chipyard top-level directory: - -.. code-block:: shell - - # in the chipyard top level folder - ./scripts/init-fpga.sh Generating a Bitstream ---------------------- diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index 262b3a19..a09f4359 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -138,7 +138,6 @@ fi # initialize all submodules (without the toolchain submodules) if run_step "2"; then $CYDIR/scripts/init-submodules-no-riscv-tools.sh $FORCE_FLAG - $CYDIR/scripts/init-fpga.sh $FORCE_FLAG fi # build extra toolchain collateral (i.e. spike, pk, riscv-tests, libgloss) diff --git a/scripts/init-fpga.sh b/scripts/init-fpga.sh deleted file mode 100755 index 0182bd4b..00000000 --- a/scripts/init-fpga.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/usr/bin/env bash - -# exit script if any command fails -set -e -set -o pipefail - -# Enable submodule update for FPGA tools. -git config --unset submodule.fpga/fpga-shells.update || : -# Initialize local FPGA tools. -git submodule update --init --recursive fpga/fpga-shells -# Disable submodule update for FPGA tools. -git config submodule.fpga/fpga-shells.update none From 2636965df330ae41e8ab340843ce5a3bc579d539 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 7 May 2023 16:07:16 -0700 Subject: [PATCH 149/184] Bump spike --- toolchains/riscv-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 80603341..fcbdbe79 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 80603341f6ac62be5abb6b7f1d09eb62bd7f2ff4 +Subproject commit fcbdbe7946079650d0e656fa3d353e3f652d471f From 5f076b184da256405e6aee1f80af14a4ca00d44a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 17:11:43 -0700 Subject: [PATCH 150/184] Flip serial_tl_clock to be generated off-chip --- .../main/scala/arty100t/HarnessBinders.scala | 3 ++- .../src/main/scala/HarnessBinders.scala | 19 +++++++++++-------- .../src/main/scala/config/ChipConfigs.scala | 5 ++--- .../main/scala/example/FlatTestHarness.scala | 3 ++- generators/testchipip | 2 +- 5 files changed, 18 insertions(+), 14 deletions(-) diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index d9a2df45..ed904183 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -25,7 +25,8 @@ class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarness ports.map({ port => val ath = th.asInstanceOf[Arty100THarness] val freq = p(PeripheryBusKey).dtsFrequency.get - val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + val bits = port.bits + port.clock := th.buildtopClock withClockAndReset(th.buildtopClock, th.buildtopReset) { val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) val uart_to_serial = Module(new UARTToSerial( diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 3f167aa3..4d2adcba 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -155,7 +155,8 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({ // DOC include start: HarnessClockInstantiatorEx withClockAndReset(th.buildtopClock, th.buildtopReset) { val memOverSerialTLClockBundle = th.harnessClockInstantiator.requestClockBundle("mem_over_serial_tl_clock", memFreq) - val serial_bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + val serial_bits = port.bits + port.clock := th.buildtopClock val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM( system.serdesser.get, serial_bits, @@ -302,11 +303,11 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) - withClockAndReset(th.buildtopClock, th.buildtopReset) { - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) - SerialAdapter.tieoff(ram.module.io.tsi_ser) - } + val bits = port.bits + port.clock := false.B.asClock + port.bits.out.ready := false.B + port.bits.in.valid := false.B + port.bits.in.bits := DontCare }) } }) @@ -315,7 +316,8 @@ class WithSimSerial extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + val bits = port.bits + port.clock := th.buildtopClock withClockAndReset(th.buildtopClock, th.buildtopReset) { val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool) @@ -330,7 +332,8 @@ class WithUARTSerial extends OverrideHarnessBinder({ implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val freq = p(PeripheryBusKey).dtsFrequency.get - val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + val bits = port.bits + port.clock := th.buildtopClock withClockAndReset(th.buildtopClock, th.buildtopReset) { val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) val uart_to_serial = Module(new UARTToSerial(freq, UARTParams(0))) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index e0ccd2cc..3643c66e 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -31,9 +31,8 @@ class ChipLikeQuadRocketConfig extends Config( //================================== new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++ // Use a PLL-based clock selector/divider generator structure - // Create two clock groups, uncore and fbus, in addition to the tile clock groups - new chipyard.clocking.WithClockGroupsCombinedByName("uncore", "implicit", "sbus", "mbus", "cbus", "system_bus") ++ - new chipyard.clocking.WithClockGroupsCombinedByName("fbus", "fbus", "pbus") ++ + // Create the uncore clock group + new chipyard.clocking.WithClockGroupsCombinedByName("uncore", "implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus") ++ // Set up the crossings new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between SBUS and FBUS diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index c428a5e9..50b76dff 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -49,7 +49,8 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { val memOverSerialTLClockBundle = Wire(new ClockBundle(ClockBundleParameters())) memOverSerialTLClockBundle.clock := clock memOverSerialTLClockBundle.reset := reset - val serial_bits = SerialAdapter.asyncQueue(dut.serial_tl_pad, clock, reset) + val serial_bits = dut.serial_tl_pad.bits + dut.serial_tl_pad.clock := clock val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM( lazyDut.system.serdesser.get, serial_bits, diff --git a/generators/testchipip b/generators/testchipip index b6676e51..2bbf3a2f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b6676e5122e9ffab10928cc00417e163dc69c952 +Subproject commit 2bbf3a2fe4a7b079bc591584b8eee12234433104 From 95666677674be38f32390628154eba83b9af4f08 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 18:31:47 -0700 Subject: [PATCH 151/184] Remove bus-to-bus crossings --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 6 ------ 1 file changed, 6 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 3643c66e..56280649 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -34,11 +34,5 @@ class ChipLikeQuadRocketConfig extends Config( // Create the uncore clock group new chipyard.clocking.WithClockGroupsCombinedByName("uncore", "implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus") ++ - // Set up the crossings - new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between SBUS and FBUS - new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS - new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS - new chipyard.config.AbstractConfig) From 4f5bbdca97dfdda9506984ce94577d8fb1edced8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 23:16:56 -0700 Subject: [PATCH 152/184] Flip serial_tl.clock for firechip BridgeBinders --- generators/firechip/src/main/scala/BridgeBinders.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 4d768da9..b543254d 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -72,7 +72,8 @@ class WithSerialBridge extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { port => implicit val p = GetSystemParameters(system) - val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + val bits = port.bits + port.clock := th.buildtopClock val ram = withClockAndReset(th.buildtopClock, th.buildtopReset) { SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) } @@ -125,8 +126,8 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({ axiClockBundle.clock := axiClock axiClockBundle.reset := ResetCatchAndSync(axiClock, th.buildtopReset.asBool) - val serial_bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) - + val serial_bits = port.bits + port.clock := th.buildtopClock val harnessMultiClockAXIRAM = withClockAndReset(th.buildtopClock, th.buildtopReset) { SerialAdapter.connectHarnessMultiClockAXIRAM( system.serdesser.get, From d42b195b9121505ea7d6c3727136791e7087a679 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 20 Apr 2023 00:00:42 -0700 Subject: [PATCH 153/184] Add notes to docs indicating SoftCore bringup with VCU118 is legacy --- docs/Advanced-Concepts/Chip-Communication.rst | 10 +++++++--- docs/Prototyping/VCU118.rst | 10 ++++++++-- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index f86a118a..1dc5ff45 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -206,8 +206,12 @@ This type of simulation setup is done in the following multi-clock configuration :start-after: DOC include start: MulticlockAXIOverSerialConfig :end-before: DOC include end: MulticlockAXIOverSerialConfig -Bringup Setup of the Example Test Chip after Tapeout -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Softcore-driven Bringup Setup of the Example Test Chip after Tapeout +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. warning:: + Bringing up test chips with a FPGA softcore as described here is discouraged. + An alternative approach using the FPGA to "bridge" between a x86 host and the test chip is the preferred approach. Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link. For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC). @@ -222,4 +226,4 @@ The following image shows this flow: .. image:: ../_static/images/chip-bringup.png In fact, this exact type of bringup setup is what the following section discusses: -:ref:`Prototyping/VCU118:Introduction to the Bringup Design`. +:ref:_legacy-vcu118-bringup. diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index c2c84dcb..96c67f48 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -47,8 +47,14 @@ After the harness is created, the ``BundleBridgeSource``'s must be connected to This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). For more information on harness binders and io binders, refer to :ref:`Customization/IOBinders:IOBinders and HarnessBinders`. -Introduction to the Bringup Design ----------------------------------- +(Legacy) Introduction to the Legacy Bringup Design +-------------------------------------------------- + +.. warning:: + The bringup VCU118 design described here is designed for old versions of Chipyard SoCs, pre-1.9.1. + The key difference is that these designs rely on a clock generated on-chip to synchronize the slow serialized-TileLink interface. + After Chipyard 1.9.1, the FPGA host is expected to pass the clock to the chip, instead of the other way around. + A new bringup solution will be developed for post-1.9.1 Chipyard designs. An example of a more complicated design used for Chipyard test chips can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. This example extends the default test harness and creates new ``Overlays`` to connect to a DUT (connected to the FMC port). From 3196d44f224d7dd3df951e5467c7e3ffcca2253d Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Thu, 20 Apr 2023 13:55:23 -0700 Subject: [PATCH 154/184] FIX: fix wording in doc We don't require the host computer to be x86 (can be RISC-V!) --- docs/Advanced-Concepts/Chip-Communication.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 1dc5ff45..f43ad628 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -211,7 +211,7 @@ Softcore-driven Bringup Setup of the Example Test Chip after Tapeout .. warning:: Bringing up test chips with a FPGA softcore as described here is discouraged. - An alternative approach using the FPGA to "bridge" between a x86 host and the test chip is the preferred approach. + An alternative approach using the FPGA to "bridge" between a host computer and the test chip is the preferred approach. Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link. For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC). From ac281daa78a64a4ba8be1c309e30a457263e8289 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 7 May 2023 23:16:35 -0700 Subject: [PATCH 155/184] Move TestHarness to chipyard.harness, make chipyard/harness directory --- docs/Advanced-Concepts/Harness-Clocks.rst | 4 ++-- docs/Customization/IOBinders.rst | 2 +- docs/VLSI/ASAP7-Tutorial.rst | 6 +++--- docs/VLSI/Sky130-Commercial-Tutorial.rst | 6 +++--- docs/VLSI/Sky130-OpenROAD-Tutorial.rst | 10 +++++----- fpga/src/main/scala/arty/TestHarness.scala | 3 +-- fpga/src/main/scala/arty100t/Harness.scala | 4 ++-- fpga/src/main/scala/vc707/Configs.scala | 3 ++- fpga/src/main/scala/vc707/TestHarness.scala | 4 ++-- fpga/src/main/scala/vcu118/Configs.scala | 3 ++- fpga/src/main/scala/vcu118/HarnessBinders.scala | 4 ++-- fpga/src/main/scala/vcu118/TestHarness.scala | 2 +- .../src/main/scala/vcu118/bringup/HarnessBinders.scala | 3 +-- .../src/main/scala/clocking/HasChipyardPRCI.scala | 2 +- .../chipyard/src/main/scala/config/ChipConfigs.scala | 4 ++-- .../scala/config/fragments/ClockingFragments.scala | 2 +- .../src/main/scala/example/CustomChipTop.scala | 1 + .../src/main/scala/example/FlatTestHarness.scala | 2 +- .../src/main/scala/{ => harness}/HarnessBinders.scala | 0 .../src/main/scala/{ => harness}/HarnessClocks.scala | 5 ++--- .../src/main/scala/{ => harness}/TestHarness.scala | 3 ++- generators/firechip/src/main/scala/BridgeBinders.scala | 1 - variables.mk | 2 +- 23 files changed, 38 insertions(+), 38 deletions(-) rename generators/chipyard/src/main/scala/{ => harness}/HarnessBinders.scala (100%) rename generators/chipyard/src/main/scala/{ => harness}/HarnessClocks.scala (97%) rename generators/chipyard/src/main/scala/{ => harness}/TestHarness.scala (97%) diff --git a/docs/Advanced-Concepts/Harness-Clocks.rst b/docs/Advanced-Concepts/Harness-Clocks.rst index ef224974..68ab4a4f 100644 --- a/docs/Advanced-Concepts/Harness-Clocks.rst +++ b/docs/Advanced-Concepts/Harness-Clocks.rst @@ -18,12 +18,12 @@ for a new clock domain. This is useful for simulating systems in which modules in the harness have independent clock domains from the DUT. -Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/TestHarness.scala``. +Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/harness/TestHarness.scla``. This class is accessed in harness components by referencing the Rocket Chip parameters key ``p(HarnessClockInstantiatorKey)``. Then you can request a clock and syncronized reset at a particular frequency by invoking the ``requestClockBundle`` function. Take the following example: -.. literalinclude:: ../../generators/chipyard/src/main/scala/HarnessBinders.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/harness/HarnessBinders.scala :language: scala :start-after: DOC include start: HarnessClockInstantiatorEx :end-before: DOC include end: HarnessClockInstantiatorEx diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index 1ae95512..d3626a03 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -31,7 +31,7 @@ Like ``IOBinders``, ``HarnessBinders`` are defined using macros (``OverrideHarne For exmaple, the ``WithUARTAdapter`` will connect the UART SW display adapter to the ports generated by the ``WithUARTIOCells`` described earlier, if those ports are present. -.. literalinclude:: ../../generators/chipyard/src/main/scala/HarnessBinders.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/harness/HarnessBinders.scala :language: scala :start-after: DOC include start: WithUARTAdapter :end-before: DOC include end: WithUARTAdapter diff --git a/docs/VLSI/ASAP7-Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst index 2da52d24..890d991c 100644 --- a/docs/VLSI/ASAP7-Tutorial.rst +++ b/docs/VLSI/ASAP7-Tutorial.rst @@ -115,7 +115,7 @@ Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped .. code-block:: shell - ./view_gds.py build/chipyard.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds + ./view_gds.py build/chipyard.harness.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names. @@ -126,9 +126,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc CONFIG=TinyRocketConfig - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc make lvs CONFIG=TinyRocketConfig - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__. Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors. diff --git a/docs/VLSI/Sky130-Commercial-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst index 4bc8449e..300a22d7 100644 --- a/docs/VLSI/Sky130-Commercial-Tutorial.rst +++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst @@ -121,7 +121,7 @@ It is recommended that you edit these variables directly in the Makefile rather The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources and (2) the mapping of memory instances in the design to SRAM macros; -all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory. +all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory. Note that the files in ``generated-src`` vary for each tool/technology flow. This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows (due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate @@ -168,9 +168,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc tutorial=sky130-commercial - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-commercial - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the `Sky130 Hammer plugin README `__. diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst index 882429d7..6777bb79 100644 --- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -149,7 +149,7 @@ It is recommended that you edit these variables directly in the Makefile rather The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources and (2) the mapping of memory instances in the design to SRAM macros; -all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory. +all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory. Note that the files in ``generated-src`` vary for each tool/technology flow. This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows (due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate @@ -197,7 +197,7 @@ Hammer generates a convenient script to launch these sessions .. code-block:: shell - cd ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir + cd ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated-scripts/open_chip Note that the conda OpenROAD package was compiled with the GUI disabled, so in order to view the layout, @@ -212,7 +212,7 @@ These databases can be restored using the same ``open_chip`` script for debuggin .. code-block:: shell - cd build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir + cd build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated_scripts/open_chip -h " Usage: ./generated-scripts/open_chip [-t] [openroad_db_name] @@ -245,9 +245,9 @@ To run DRC & LVS in Magic & Netgen, respectively: .. code-block:: shell make drc tutorial=sky130-openroad - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-openroad - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Note that in ``sky130-openroad.yml`` we have set the following YAML keys: diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 5e280469..d368ec55 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -7,8 +7,7 @@ import org.chipsalliance.cde.config.{Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import chipyard.{BuildTop, HasHarnessSignalReferences} -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.harness.{ApplyHarnessBinders, BuildTop, HasHarnessSignalReferences} import chipyard.iobinders.{HasIOBinders} class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index 88ea88af..dd76589a 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -13,8 +13,8 @@ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} import sifive.blocks.devices.uart._ -import chipyard._ -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.{ChipTop, CanHaveMasterTLMemPort, ExtTLMem} +import chipyard.harness._ import chipyard.iobinders.{HasIOBinders} class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell with HasHarnessSignalReferences diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index fa08a184..c0298610 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -17,7 +17,8 @@ import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey} +import chipyard.{BuildSystem, ExtTLMem} +import chipyard.harness.{DefaultClockFrequencyKey} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 94c0ba8e..8e0bd5bf 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -16,9 +16,9 @@ import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO} -import chipyard.{HasHarnessSignalReferences, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey} +import chipyard.{ChipTop, ExtTLMem, CanHaveMasterTLMemPort} import chipyard.iobinders.{HasIOBinders} -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.harness.{ApplyHarnessBinders, HasHarnessSignalReferences, BuildTop, DefaultClockFrequencyKey} class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer => diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index c4f4684e..ea6df6c3 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -17,7 +17,8 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey} +import chipyard.{BuildSystem, ExtTLMem} +import chipyard.harness.{DefaultClockFrequencyKey} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index d60af21a..50fbfeb4 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -9,8 +9,8 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} -import chipyard.harness.{OverrideHarnessBinder} +import chipyard.{CanHaveMasterTLMemPort} +import chipyard.harness.{HasHarnessSignalReferences, OverrideHarnessBinder} /*** UART ***/ class WithUART extends OverrideHarnessBinder({ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index e46745a8..9e7529dd 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -17,7 +17,7 @@ import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO} import chipyard._ import chipyard.iobinders.{HasIOBinders} -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.harness._ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index 27689ca8..7008092a 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -13,8 +13,7 @@ import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} -import chipyard.{HasHarnessSignalReferences} -import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} +import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder, HasHarnessSignalReferences} /*** UART ***/ class WithBringupUART extends ComposeHarnessBinder({ diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index d571bc95..1522648a 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.{TLTileResetCtrl} -import chipyard.{DefaultClockFrequencyKey} +import chipyard.harness.{DefaultClockFrequencyKey} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 56280649..e51ac525 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -8,8 +8,8 @@ class ChipLikeQuadRocketConfig extends Config( //================================== // Set up TestHarness //================================== - new chipyard.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness - // NOTE: This only simulates properly in VCS + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness + // NOTE: This only simulates properly in VCS //================================== // Set up tiles diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 7000c81c..6080c36f 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams} import chipyard._ import chipyard.clocking._ - +import chipyard.harness.{DefaultClockFrequencyKey} // The default RocketChip BaseSubsystem drives its diplomatic clock graph // with the implicit clocks of Subsystem. Don't do that, instead we extend diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala index 19ec945b..f2ebfc33 100644 --- a/generators/chipyard/src/main/scala/example/CustomChipTop.scala +++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala @@ -7,6 +7,7 @@ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy.{InModuleBody} import barstools.iocell.chisel._ import chipyard._ +import chipyard.harness.{BuildTop} // A "custom" IOCell with additional I/O // The IO don't do anything here in this example diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 50b76dff..6151f456 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem.{CacheBlockBytes} import freechips.rocketchip.devices.debug.{SimJTAG} import freechips.rocketchip.jtag.{JTAGIO} import testchipip.{SerialTLKey, SerialAdapter, UARTAdapter, SimDRAM} -import chipyard.{BuildTop} +import chipyard.harness.{BuildTop} // A "flat" TestHarness that doesn't use IOBinders // use with caution. diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala similarity index 100% rename from generators/chipyard/src/main/scala/HarnessBinders.scala rename to generators/chipyard/src/main/scala/harness/HarnessBinders.scala diff --git a/generators/chipyard/src/main/scala/HarnessClocks.scala b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala similarity index 97% rename from generators/chipyard/src/main/scala/HarnessClocks.scala rename to generators/chipyard/src/main/scala/harness/HarnessClocks.scala index f9665e12..513ca38c 100644 --- a/generators/chipyard/src/main/scala/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala @@ -1,4 +1,4 @@ -package chipyard +package chipyard.harness import chisel3._ @@ -8,10 +8,9 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.util.{ResetCatchAndSync} import freechips.rocketchip.prci._ -import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} +import chipyard.harness.{ApplyHarnessBinders, HarnessBinders, HarnessClockInstantiatorKey} import chipyard.iobinders.HasIOBinders import chipyard.clocking.{SimplePllConfiguration, ClockDividerN} -import chipyard.HarnessClockInstantiatorKey // HarnessClockInstantiators are classes which generate clocks that drive diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/harness/TestHarness.scala similarity index 97% rename from generators/chipyard/src/main/scala/TestHarness.scala rename to generators/chipyard/src/main/scala/harness/TestHarness.scala index a8b18d4f..22bcc167 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/harness/TestHarness.scala @@ -1,4 +1,4 @@ -package chipyard +package chipyard.harness import chisel3._ @@ -11,6 +11,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkP import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} import chipyard.iobinders.HasIOBinders import chipyard.clocking.{SimplePllConfiguration, ClockDividerN} +import chipyard.{ChipTop} // ------------------------------- // Chipyard Test Harness diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index b543254d..cd98c7fe 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -30,7 +30,6 @@ import cva6.CVA6Tile import boom.common.{BoomTile} import barstools.iocell.chisel._ import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey} -import chipyard.{HasHarnessSignalReferences} import chipyard.harness._ object MainMemoryConsts { diff --git a/variables.mk b/variables.mk index 9caaf676..89e66cd9 100644 --- a/variables.mk +++ b/variables.mk @@ -70,7 +70,7 @@ ifeq ($(SUB_PROJECT),chipyard) SBT_PROJECT ?= chipyard MODEL ?= TestHarness VLOG_MODEL ?= $(MODEL) - MODEL_PACKAGE ?= $(SBT_PROJECT) + MODEL_PACKAGE ?= chipyard.harness CONFIG ?= RocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) From 95da9cefb521fa38c2af072865dc660dae0ac0ca Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Mon, 8 May 2023 13:41:51 -0700 Subject: [PATCH 156/184] 4GB DRAM configs --- .../firechip/src/main/scala/TargetConfigs.scala | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d7f6008a..fd2eba86 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -194,6 +194,17 @@ class FireSimRocketMMIOOnly1GiBDRAMConfig extends Config( new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++ new FireSimRocketMMIOOnlyConfig) + +class FireSimRocket4GiBDRAMConfig extends Config( + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ + new FireSimRocketConfig) + +class FireSimRocketMMIOOnly4GiBDRAMConfig extends Config( + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ + new FireSimRocketMMIOOnlyConfig) + + + class FireSimQuadRocketConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ From ad98363addd9ce0db843bc58649df4e9837c0c63 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 8 May 2023 18:17:20 -0700 Subject: [PATCH 157/184] Update docs/Advanced-Concepts/Harness-Clocks.rst Co-authored-by: Abraham Gonzalez --- docs/Advanced-Concepts/Harness-Clocks.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Advanced-Concepts/Harness-Clocks.rst b/docs/Advanced-Concepts/Harness-Clocks.rst index 68ab4a4f..e7501cec 100644 --- a/docs/Advanced-Concepts/Harness-Clocks.rst +++ b/docs/Advanced-Concepts/Harness-Clocks.rst @@ -18,7 +18,7 @@ for a new clock domain. This is useful for simulating systems in which modules in the harness have independent clock domains from the DUT. -Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/harness/TestHarness.scla``. +Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/harness/TestHarness.scala``. This class is accessed in harness components by referencing the Rocket Chip parameters key ``p(HarnessClockInstantiatorKey)``. Then you can request a clock and syncronized reset at a particular frequency by invoking the ``requestClockBundle`` function. Take the following example: From eced8e63d9171d5b03c50ac1503ba54fa18ef002 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 8 May 2023 15:39:16 -0700 Subject: [PATCH 158/184] Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness --- docs/Advanced-Concepts/Chip-Communication.rst | 12 ++++++------ docs/Advanced-Concepts/Resources.rst | 12 ++++++------ .../Configs-Parameters-Mixins.rst | 14 ++++++-------- docs/Generators/TestChipIP.rst | 8 ++++---- .../main/scala/arty100t/HarnessBinders.scala | 14 +++++++------- .../src/main/scala/config/AbstractConfig.scala | 2 +- .../src/main/scala/config/BoomConfigs.scala | 4 ++-- .../src/main/scala/config/CVA6Configs.scala | 2 +- .../scala/config/PeripheralDeviceConfigs.scala | 2 +- .../src/main/scala/config/SpikeConfigs.scala | 4 ++-- .../main/scala/example/FlatTestHarness.scala | 6 +++--- .../main/scala/harness/HarnessBinders.scala | 18 +++++++++--------- .../src/main/scala/BridgeBinders.scala | 14 +++++++------- generators/testchipip | 2 +- sims/firesim | 2 +- sims/verilator/Makefile | 2 +- 16 files changed, 58 insertions(+), 60 deletions(-) diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index f43ad628..3e067965 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -47,12 +47,12 @@ Using the Tethered Serial Interface (TSI) By default, Chipyard uses the Tethered Serial Interface (TSI) to communicate with the DUT. TSI protocol is an implementation of HTIF that is used to send commands to the RISC-V DUT. These TSI commands are simple R/W commands that are able to access the DUT's memory space. -During simulation, the host sends TSI commands to a simulation stub in the test harness called ``SimSerial`` -(C++ class) that resides in a ``SimSerial`` Verilog module (both are located in the ``generators/testchipip`` +During simulation, the host sends TSI commands to a simulation stub in the test harness called ``SimTSI`` +(C++ class) that resides in a ``SimTSI`` Verilog module (both are located in the ``generators/testchipip`` project). -This ``SimSerial`` Verilog module then sends the TSI command recieved by the simulation stub +This ``SimTSI`` Verilog module then sends the TSI command recieved by the simulation stub to an adapter that converts the TSI command into a TileLink request. -This conversion is done by the ``SerialAdapter`` module (located in the ``generators/testchipip`` project). +This conversion is done by the ``TSIToTileLink`` module (located in the ``generators/testchipip`` project). After the transaction is converted to TileLink, the ``TLSerdesser`` (located in ``generators/testchipip``) serializes the transaction and sends it to the chip (this ``TLSerdesser`` is sometimes also referred to as a digital serial-link or SerDes). Once the serialized transaction is received on the chip, it is deserialized and masters a TileLink bus on the chip @@ -76,7 +76,7 @@ simulation stub called ``SimDTM`` (C++ class) that resides in a ``SimDTM`` Veril sends the DMI command recieved by the simulation stub into the DUT which then converts the DMI command into a TileLink request. This conversion is done by the DTM named ``DebugModule`` in the ``generators/rocket-chip`` project. When the DTM receives the program to load, it starts to write the binary byte-wise into memory. -This is considerably slower than the TSI protocol communication pipeline (i.e. ``SimSerial``/``SerialAdapter``/TileLink) +This is considerably slower than the TSI protocol communication pipeline (i.e. ``SimTSI``/``TSIToTileLink``/TileLink) which directly writes the program binary to memory. Starting the TSI or DMI Simulation @@ -216,7 +216,7 @@ Softcore-driven Bringup Setup of the Example Test Chip after Tapeout Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link. For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC). This RISC-V soft-core would serve as the host of the test that will run on the DUT. -This is done by the RISC-V soft-core running FESVR, sending TSI commands to a ``SerialAdapter`` / ``TLSerdesser`` programmed on the FPGA. +This is done by the RISC-V soft-core running FESVR, sending TSI commands to a ``TSIToTileLink`` / ``TLSerdesser`` programmed on the FPGA. Once the commands are converted to serialized TileLink, then they can be sent over some medium to the DUT (like an FMC cable or a set of wires connecting FPGA outputs to the DUT board). Similar to simulation, if the chip requests offchip memory, it can then send the transaction back over the serial-link. diff --git a/docs/Advanced-Concepts/Resources.rst b/docs/Advanced-Concepts/Resources.rst index 6af72836..fbfaad60 100644 --- a/docs/Advanced-Concepts/Resources.rst +++ b/docs/Advanced-Concepts/Resources.rst @@ -2,24 +2,24 @@ Accessing Scala Resources =============================== A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``addResource`` function given by FIRRTL. -An example of its use can be seen in `generators/testchipip/src/main/scala/SerialAdapter.scala `_. +An example of its use can be seen in `generators/testchipip/src/main/scala/SimTSI.scala `_. Here is the example inlined: .. code-block:: scala - class SimSerial(w: Int) extends BlackBox with HasBlackBoxResource { + class SimTSI extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) - val serial = Flipped(new SerialIO(w)) + val tsi = Flipped(new TSIIO) val exit = Output(Bool()) }) - addResource("/testchipip/vsrc/SimSerial.v") - addResource("/testchipip/csrc/SimSerial.cc") + addResource("/testchipip/vsrc/SimTSI.v") + addResource("/testchipip/csrc/SimTSI.cc") } -In this example, the ``SimSerial`` files will be copied from a specific folder (in this case the ``path/to/testchipip/src/main/resources/testchipip/...``) to the build folder. +In this example, the ``SimTSI`` files will be copied from a specific folder (in this case the ``path/to/testchipip/src/main/resources/testchipip/...``) to the build folder. The ``addResource`` path retrieves resources from the ``src/main/resources`` directory. So to get an item at ``src/main/resources/fileA.v`` you can use ``addResource("/fileA.v")``. However, one caveat of this approach is that to retrieve the file during the FIRRTL compile, you must have that project in the FIRRTL compiler's classpath. diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index f55d15be..818d7b69 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -83,8 +83,8 @@ This example shows the Chipyard default top that composes multiple traits togeth :end-before: DOC include end: DigitalTop -There are two "cakes" or mixins here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module -implementation (ex. ``CanHavePeripherySerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines +There are two "cakes" or mixins here. One for the lazy module (ex. ``CanHavePeripheryTLSerial``) and one for the lazy module +implementation (ex. ``CanHavePeripheryTLSerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines all the logical connections between generators and exchanges configuration information among them, while the lazy module implementation performs the actual Chisel RTL elaboration. @@ -93,19 +93,17 @@ In the ``DigitalTop`` example class, the "outer" ``DigitalTop`` instantiates the of the module until all logical connections are determined and all configuration information is exchanged. The ``System`` outer base class, as well as the ``CanHavePeriphery`` outer traits contain code to perform high-level logical -connections. For example, the ``CanHavePeripherySerial`` outer trait contains code -to optionally lazily instantiate the ``SerialAdapter``, and connect the ``SerialAdapter``'s +connections. For example, the ``CanHavePeripheryTLSerial`` outer trait contains code +to optionally lazily instantiate the ``TLSerdesser``, and connect the ``TLSerdesser`` 's TileLink node to the Front bus. The ``ModuleImp`` classes and traits perform elaboration of real RTL. -For example, the ``CanHavePeripherySerialModuleImp`` trait optionally physically connects -the ``SerialAdapter`` module, and instantiates queues. In the test harness, the SoC is elaborated with ``val dut = p(BuildTop)(p)``. After elaboration, the system submodule of ``ChipTop`` will be a ``DigitalTop`` module, which contains a -``SerialAdapter`` module (among others), if the config specified for that block to be instantiated. +``TLSerdesser`` module (among others), if the config specified for that block to be instantiated. From a high level, classes which extend ``LazyModule`` *must* reference their module implementation through ``lazy val module``, and they @@ -116,7 +114,7 @@ other normal modules OR lazy modules (for nested Diplomacy graphs, for example). The naming convention for an additive mixin or trait is ``CanHave``. -This is shown in the ``Top`` class where things such as ``CanHavePeripherySerial`` connect a RTL component to a bus and expose signals to the top-level. +This is shown in the ``Top`` class where things such as ``CanHavePeripheryTLSerial`` connect a RTL component to a bus and expose signals to the top-level. Additional References --------------------------- diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 9d08a895..2c382d4f 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -2,16 +2,16 @@ Test Chip IP ============ Chipyard includes a Test Chip IP library which provides various hardware -widgets that may be useful when designing SoCs. This includes a :ref:`Generators/TestChipIP:Serial Adapter`, +widgets that may be useful when designing SoCs. This includes a :ref:`Generators/TestChipIP:SimTSI`, :ref:`Generators/TestChipIP:Block Device Controller`, :ref:`Generators/TestChipIP:TileLink SERDES`, :ref:`Generators/TestChipIP:TileLink Switcher`, :ref:`Generators/TestChipIP:TileLink Ring Network`, and :ref:`Generators/TestChipIP:UART Adapter`. -Serial Adapter +SimTSI -------------- -The serial adapter is used by tethered test chips to communicate with the host +The SimTSI and TSIToTileLink are used by tethered test chips to communicate with the host processor. An instance of RISC-V frontend server running on the host CPU -can send commands to the serial adapter to read and write data from the memory +can send commands to the TSIToTileLink to read and write data from the memory system. The frontend server uses this functionality to load the test program into memory and to poll for completion of the program. More information on this can be found in :ref:`Customization/Boot-Process:Chipyard Boot Process`. diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index ed904183..c403b604 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -28,22 +28,22 @@ class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarness val bits = port.bits port.clock := th.buildtopClock withClockAndReset(th.buildtopClock, th.buildtopReset) { - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) + val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset) val uart_to_serial = Module(new UARTToSerial( freq, UARTParams(0, initBaudRate=uartBaudRate))) val serial_width_adapter = Module(new SerialWidthAdapter( - narrowW = 8, wideW = SerialAdapter.SERIAL_TSI_WIDTH)) + narrowW = 8, wideW = TSI.WIDTH)) serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial) - ram.module.io.tsi_ser.flipConnect(serial_width_adapter.io.wide) + ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide) ath.io_uart_bb.bundle <> uart_to_serial.io.uart ath.other_leds(1) := uart_to_serial.io.dropped - ath.other_leds(9) := ram.module.io.adapter_state(0) - ath.other_leds(10) := ram.module.io.adapter_state(1) - ath.other_leds(11) := ram.module.io.adapter_state(2) - ath.other_leds(12) := ram.module.io.adapter_state(3) + ath.other_leds(9) := ram.module.io.tsi2tl_state(0) + ath.other_leds(10) := ram.module.io.tsi2tl_state(1) + ath.other_leds(11) := ram.module.io.tsi2tl_state(2) + ath.other_leds(12) := ram.module.io.tsi2tl_state(3) } }) } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index ef02f468..3cce1e00 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -14,7 +14,7 @@ class AbstractConfig extends Config( // The HarnessBinders control generation of hardware in the TestHarness new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled - new chipyard.harness.WithSimSerial ++ // add external serial-adapter and RAM + new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 5544e4c3..092da3c3 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -55,7 +55,7 @@ class MediumBoomCosimConfig extends Config( new chipyard.config.AbstractConfig) class dmiMediumBoomConfig extends Config( - new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new boom.common.WithNMediumBooms(1) ++ new chipyard.config.AbstractConfig) @@ -63,7 +63,7 @@ class dmiMediumBoomConfig extends Config( class dmiMediumBoomCosimConfig extends Config( new chipyard.harness.WithCospike ++ // attach spike-cosim new chipyard.config.WithTraceIO ++ // enable the traceio - new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anythint to serial-tl new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new boom.common.WithNMediumBooms(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/CVA6Configs.scala b/generators/chipyard/src/main/scala/config/CVA6Configs.scala index c0d6adb1..7b4406c4 100644 --- a/generators/chipyard/src/main/scala/config/CVA6Configs.scala +++ b/generators/chipyard/src/main/scala/config/CVA6Configs.scala @@ -13,7 +13,7 @@ class CVA6Config extends Config( new chipyard.config.AbstractConfig) class dmiCVA6Config extends Config( - new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.harness.WithSerialTLTiedOff ++ // Tie off the serial-tilelink port new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new cva6.WithNCVA6Cores(1) ++ // single CVA6 core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index 3bb2390d..029dd2bd 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -58,7 +58,7 @@ class LBWIFRocketConfig extends Config( // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index 34413b36..8caed688 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -11,7 +11,7 @@ class SpikeConfig extends Config( new chipyard.config.AbstractConfig) class dmiSpikeConfig extends Config( - new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tilelink new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new SpikeConfig) @@ -35,7 +35,7 @@ class SpikeUltraFastConfig extends Config( new chipyard.config.AbstractConfig) class dmiSpikeUltraFastConfig extends Config( - new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tilelink new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new SpikeUltraFastConfig) diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 6151f456..55b414cf 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.util.{PlusArg} import freechips.rocketchip.subsystem.{CacheBlockBytes} import freechips.rocketchip.devices.debug.{SimJTAG} import freechips.rocketchip.jtag.{JTAGIO} -import testchipip.{SerialTLKey, SerialAdapter, UARTAdapter, SimDRAM} +import testchipip.{SerialTLKey, UARTAdapter, SimDRAM, TSIHarness, SimTSI} import chipyard.harness.{BuildTop} // A "flat" TestHarness that doesn't use IOBinders @@ -51,12 +51,12 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { memOverSerialTLClockBundle.reset := reset val serial_bits = dut.serial_tl_pad.bits dut.serial_tl_pad.clock := clock - val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM( + val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM( lazyDut.system.serdesser.get, serial_bits, memOverSerialTLClockBundle, reset) - io.success := SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, clock, reset) + io.success := SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), clock, reset) // connect SimDRAM from the AXI port coming from the harness multi clock axi ram (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) => diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 4d2adcba..e4e8391b 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -157,13 +157,13 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({ val memOverSerialTLClockBundle = th.harnessClockInstantiator.requestClockBundle("mem_over_serial_tl_clock", memFreq) val serial_bits = port.bits port.clock := th.buildtopClock - val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM( + val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM( system.serdesser.get, serial_bits, memOverSerialTLClockBundle, th.buildtopReset) // DOC include end: HarnessClockInstantiatorEx - val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool) + val success = SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), th.buildtopClock, th.buildtopReset.asBool) when (success) { th.success := true.B } // connect SimDRAM from the AXI port coming from the harness multi clock axi ram @@ -299,7 +299,7 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ }) -class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ +class WithSerialTLTiedOff extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => @@ -312,15 +312,15 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ } }) -class WithSimSerial extends OverrideHarnessBinder({ +class WithSimTSIOverSerialTL extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val bits = port.bits port.clock := th.buildtopClock withClockAndReset(th.buildtopClock, th.buildtopReset) { - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) - val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool) + val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset) + val success = SimTSI.connect(Some(ram.module.io.tsi), th.buildtopClock, th.buildtopReset.asBool) when (success) { th.success := true.B } } }) @@ -335,11 +335,11 @@ class WithUARTSerial extends OverrideHarnessBinder({ val bits = port.bits port.clock := th.buildtopClock withClockAndReset(th.buildtopClock, th.buildtopReset) { - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) + val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset) val uart_to_serial = Module(new UARTToSerial(freq, UARTParams(0))) val serial_width_adapter = Module(new SerialWidthAdapter( - 8, SerialAdapter.SERIAL_TSI_WIDTH)) - ram.module.io.tsi_ser.flipConnect(serial_width_adapter.io.wide) + 8, TSI.WIDTH)) + ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide) UARTAdapter.connect(Seq(uart_to_serial.io.uart), uart_to_serial.div) serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial) th.success := false.B diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index cd98c7fe..579c2d50 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -67,16 +67,16 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { case IOCellKey => FireSimIOCellParams() }) -class WithSerialBridge extends OverrideHarnessBinder({ +class WithTSIBridgeAndHarnessRAMOverSerialTL extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { port => implicit val p = GetSystemParameters(system) val bits = port.bits port.clock := th.buildtopClock val ram = withClockAndReset(th.buildtopClock, th.buildtopReset) { - SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) + TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset) } - SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName), th.buildtopReset.asBool) + TSIBridge(th.buildtopClock, ram.module.io.tsi, p(ExtMem).map(_ => MainMemoryConsts.globalName), th.buildtopReset.asBool) } Nil } @@ -128,13 +128,13 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({ val serial_bits = port.bits port.clock := th.buildtopClock val harnessMultiClockAXIRAM = withClockAndReset(th.buildtopClock, th.buildtopReset) { - SerialAdapter.connectHarnessMultiClockAXIRAM( + TSIHarness.connectMultiClockAXIRAM( system.serdesser.get, serial_bits, axiClockBundle, th.buildtopReset) } - SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool) + TSIBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool) // connect SimAxiMem (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) => @@ -232,7 +232,7 @@ class WithFireSimFAME5 extends ComposeIOBinder({ // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( - new WithSerialBridge ++ + new WithTSIBridgeAndHarnessRAMOverSerialTL ++ new WithNICBridge ++ new WithUARTBridge ++ new WithBlockDeviceBridge ++ @@ -245,7 +245,7 @@ class WithDefaultFireSimBridges extends Config( // Shorthand to register all of the provided mmio-only bridges above class WithDefaultMMIOOnlyFireSimBridges extends Config( - new WithSerialBridge ++ + new WithTSIBridgeAndHarnessRAMOverSerialTL ++ new WithUARTBridge ++ new WithBlockDeviceBridge ++ new WithFASEDBridge ++ diff --git a/generators/testchipip b/generators/testchipip index 2bbf3a2f..363b6835 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 2bbf3a2fe4a7b079bc591584b8eee12234433104 +Subproject commit 363b683552e66e1e8f6552f25a4ee24b532e7faf diff --git a/sims/firesim b/sims/firesim index 3ae68ec3..5f9bf2b4 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 3ae68ec3076c010c633ded369fd3874ec2e5e557 +Subproject commit 5f9bf2b42b9dedadaee857b6524f9222136280d4 diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 96f37237..e1291bbe 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -52,7 +52,7 @@ SIM_FILE_REQS += \ # the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build) SIM_FILE_REQS += \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimTSI.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ From e832667ccec09a3ff887a8942729577a3bca965b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 May 2023 13:31:00 -0700 Subject: [PATCH 159/184] Bump Verilator --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 3ae68ec3..0c1a7a63 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 3ae68ec3076c010c633ded369fd3874ec2e5e557 +Subproject commit 0c1a7a63396fa213d22ff218e00acc0594e303a8 From dbbf7c90b4c25d9e1d0ffeeef18f94fb850da2d5 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 May 2023 13:58:40 -0700 Subject: [PATCH 160/184] Separate out conda-lock generation into new script --- conda-reqs/chipyard.yaml | 2 +- ...irements-esp-tools-linux-64.conda-lock.yml | 515 +++++++++-------- ...ements-riscv-tools-linux-64.conda-lock.yml | 542 +++++++++--------- scripts/build-setup.sh | 3 +- scripts/generate-conda-lockfile.sh | 31 + 5 files changed, 577 insertions(+), 516 deletions(-) create mode 100755 scripts/generate-conda-lockfile.sh diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml index 25e5f1a5..2dd4f7bf 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard.yaml @@ -131,7 +131,7 @@ dependencies: - pytest-mock - moto - mypy - - s3fs + - s3fs==0.4.2 - aiohttp - pip: - sure diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml index 7a0c7cd8..5039e151 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml @@ -9,7 +9,7 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml +# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/esp-tools.yaml -f /scratch/abejgonza/cy/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -21,12 +21,14 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 3794abe8e222921d310bbd60f30fea775b80f7533f7a57d57c11bb3640a3643a + linux-64: 6553d7c92f7543a655a57c1e9b739574f229af6a2caec82046f8cce24d91d271 platforms: - linux-64 sources: - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/esp-tools.yaml + - /scratch/abejgonza/cy/conda-reqs/chipyard.yaml + - /scratch/abejgonza/cy/conda-reqs/esp-tools.yaml package: - category: main dependencies: {} @@ -42,13 +44,13 @@ package: - category: main dependencies: {} hash: - md5: a581b4a89191b6c1d6a16488a9cffbfc - sha256: 695e67ae4bc22f9e0be5f54b1948a8f2b678f4da920fa2082a249dd5a88f440e + md5: f6ce7955b53ae1ca83144adb3be9c600 + sha256: 546e4eb1cbd822a66b363ec3fbdcc4fcc53853bcab57674cb46b8f3209b856f2 manager: conda name: _sysroot_linux-64_curr_repodata_hack optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h5bd9786_13.tar.bz2 + url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_13.conda version: '3' - category: main dependencies: {} @@ -64,14 +66,14 @@ package: - category: main dependencies: {} hash: - md5: ff9f73d45c4a07d6f424495288a26080 - sha256: 8f6c81b0637771ae0ea73dc03a6d30bec3326ba3927f2a7b91931aa2d59b1789 + md5: f5c65075fc34438d5b456c7f3f5ab695 + sha256: 0cf1bb3d0bfc5519b60af2c360fa4888fb838e1476b1e0f65b9dbc48b45c7345 manager: conda name: ca-certificates optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2022.12.7-ha878542_0.conda - version: 2022.12.7 + url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2023.5.7-hbcca054_0.conda + version: 2023.5.7 - category: main dependencies: {} hash: @@ -883,13 +885,13 @@ package: ca-certificates: '' libgcc-ng: '>=12' hash: - md5: 2d833be81a21128e317325a01326d36f - sha256: d378afcec34b86fef4da3ebd622b3e614cb3f71e54b6a5a10adb1d23745ecc72 + md5: 8f24d371ed9efb3f0b0de383fb81d51c + sha256: 24bf6cf8f741c28a8d10f51c917f378694d4a98a38ab4372629932cd6c94e9e8 manager: conda name: openssl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.1.0-h0b41bf4_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.1.0-hd590300_3.conda version: 3.1.0 - category: main dependencies: @@ -1358,14 +1360,14 @@ package: libgcc-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 2e5f9a37d487e1019fd4d8113adb2f9f - sha256: 6008a0b914bd1a3510a3dba38eada93aa0349ebca3a21e5fa276833c8205bf49 + md5: 1d002bf709048f8021c32abfd0e0d395 + sha256: bb2a8ddb26e74f2cedc36825fc6f95d45f19e1912a1a6c75847952d92fc16215 manager: conda name: libsqlite optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libsqlite-3.40.0-h753d276_0.tar.bz2 - version: 3.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libsqlite-3.41.2-h2797004_1.conda + version: 3.41.2 - category: main dependencies: libgcc-ng: '>=12' @@ -1709,13 +1711,13 @@ package: dependencies: gcc_impl_linux-64: 12.2.0.* hash: - md5: c241b4f6676222c2feefc9dc4b9d1728 - sha256: f4b4184cc3e0864abadfc5b06ae869b479e736ff1dc46723967256d11b5bc7c4 + md5: ec93d13e0fe8514f65842120dbae1b16 + sha256: 5478f5b7672b6c2d5b644aaa9fe18fbb1468ca6ea9cea1b0f0a2254459438e24 manager: conda name: gcc optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_12.conda + url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_13.conda version: 12.2.0 - category: main dependencies: @@ -1806,14 +1808,14 @@ package: libzlib: '>=1.2.13,<1.3.0a0' pcre2: '>=10.40,<10.41.0a0' hash: - md5: 984fc0159591041a411d96718e7073d0 - sha256: afac276054c6fc2959347e7e1da211554f5cc4efbdda6d1f29b6d98919eae833 + md5: db1d4a1dfc04f3eab50d97551850759a + sha256: e0d54ffe98b7471cfc95f043bf3921412843c05ba5f1f10ceeac5edb328ac928 manager: conda name: libglib optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.76.1-ha491796_0.conda - version: 2.76.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.76.2-hebfc3b9_0.conda + version: 2.76.2 - category: main dependencies: libblas: 3.9.0 16_linux64_openblas @@ -1846,18 +1848,18 @@ package: dependencies: libgcc-ng: '>=12' libstdcxx-ng: '>=12' - libxml2: '>=2.10.3,<2.11.0a0' + libxml2: '>=2.10.4,<2.11.0a0' libzlib: '>=1.2.13,<1.3.0a0' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 716f4c806c384ee7bf1647814516c241 - sha256: 95a7e646c035b2515c69af0c47acf1840557160123f8ee6441d8b0f254098342 + md5: 3d942f062d7656168bb42b3439bdfede + sha256: c52c239b583a1b2d03bdc641afd8cbab0499b0a46ea55b40e1dbed112283a772 manager: conda name: libllvm16 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libllvm16-16.0.1-hadd5161_0.conda - version: 16.0.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libllvm16-16.0.3-hbf9e925_1.conda + version: 16.0.3 - category: main dependencies: lerc: '>=4.0.0,<5.0a0' @@ -1957,19 +1959,19 @@ package: - category: main dependencies: libgcc-ng: '>=12' - libsqlite: 3.40.0 h753d276_0 + libsqlite: 3.41.2 h2797004_1 libzlib: '>=1.2.13,<1.3.0a0' ncurses: '>=6.3,<7.0a0' - readline: '>=8.1.2,<9.0a0' + readline: '>=8.2,<9.0a0' hash: - md5: bb11803129cbbb53ed56f9506ff74145 - sha256: baf0e77938e5215653aa6609ff154cb94aeb0a08083ff8dec2d3ba8dd62263e9 + md5: c8771266cc289756099c04e597209862 + sha256: 2674e5b0888799ad055bdbc79e2257d67f52b0c11f4c174d4deff4b69874cf45 manager: conda name: sqlite optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/sqlite-3.40.0-h4ff8645_0.tar.bz2 - version: 3.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/sqlite-3.41.2-h2c6b66d_1.conda + version: 3.41.2 - category: main dependencies: libgcc-ng: '>=9.4.0' @@ -2028,16 +2030,16 @@ package: version: 1.4.4 - category: main dependencies: - python: '>=3.6' + python: '>=3.7' hash: - md5: 99b19895abe40280358488acb9589532 - sha256: 2b273efc522834e4c8563da7998b9b683eed467660fe8a5a3c24d58aaa85a9cb + md5: 0b3460f5bf4ae27dfd72fdcccc9667a9 + sha256: 18aad01518cb08e4eff18e507e14ebf6c522d89ef53ca267c48080933c4435f7 manager: conda name: argcomplete optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.5-pyhd8ed1ab_0.conda - version: 3.0.5 + url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.8-pyhd8ed1ab_0.conda + version: 3.0.8 - category: main dependencies: libgcc-ng: '>=12' @@ -2054,16 +2056,28 @@ package: version: 2.38.0 - category: main dependencies: - python: '>=3.5' + python: '>=3.7' hash: - md5: 8b76db7818a4e401ed4486c4c1635cd9 - sha256: 3a58d4a4933fa8735471c782d35326ab78e0bcfce84756408515f82a94e4dec4 + md5: 3edfead7cedd1ab4400a6c588f3e75f8 + sha256: 063639cd568f5c7a557b0fb1cc27f098598c0d8ff869088bfeb82934674f8821 manager: conda name: attrs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/attrs-22.2.0-pyh71513ae_0.conda - version: 22.2.0 + url: https://conda.anaconda.org/conda-forge/noarch/attrs-23.1.0-pyh71513ae_1.conda + version: 23.1.0 +- category: main + dependencies: + python: '>=3.7' + hash: + md5: 2fb79ec81bad9492b6d59a06b3b647a4 + sha256: b6f32491536823e47cf6eb4717dd341385600a2b901235028dedc629a77aeb82 + manager: conda + name: blinker + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/blinker-1.6.2-pyhd8ed1ab_0.conda + version: 1.6.2 - category: main dependencies: brotli-bin: 1.0.9 h166bdaf_8 @@ -2095,14 +2109,14 @@ package: dependencies: python: '>=3.7' hash: - md5: fb9addc3db06e56abe03e0e9f21a63e6 - sha256: 5e22af4776700200fab2c1df41a2188ab9cfe90a50c4f388592bb978562c88ec + md5: 5d1b71c942b8421285934dad1d891ebc + sha256: f839a6e04d94069f90dd85337ea9108f058dc76771bb469a413f32bb1ba0b256 manager: conda name: certifi optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/certifi-2022.12.7-pyhd8ed1ab_0.conda - version: 2022.12.7 + url: https://conda.anaconda.org/conda-forge/noarch/certifi-2023.5.7-pyhd8ed1ab_0.conda + version: 2023.5.7 - category: main dependencies: python: '>=3.6.1' @@ -2129,16 +2143,16 @@ package: version: 2.1.1 - category: main dependencies: - __unix: '' - python: '>=3.8' + python: '>=3.9,<3.10.0a0' + python_abi: 3.9.* *_cp39 hash: - md5: 20e4087407c7cb04a40817114b333dbf - sha256: 23676470b591b100393bb0f6c46fe10624dcbefc696a6a9f42932ed8816ef0ea + md5: 3613ff4128b3e565d048106196206929 + sha256: 21c425ecc4e6f4ec97aab1285b22ad629c75d2efb62f89cd6d9618ab6a2e606c manager: conda name: click optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/click-8.1.3-unix_pyhd8ed1ab_2.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/click-8.1.3-py39hf3d152e_1.tar.bz2 version: 8.1.3 - category: main dependencies: @@ -2302,14 +2316,14 @@ package: dependencies: python: '>=3.8' hash: - md5: a993e42df87a292d8fd7396a2e2a8d75 - sha256: c2a5db01537aae91a54dbd163b85421de2b623c75803af4e38ea01ba000317d1 + md5: 20edd290b319aa0eff3e9055375756dc + sha256: cbb5c77c0217cda9bf4f4240158de11822a099a6eaa05ba626e822819a54f46d manager: conda name: fsspec optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.4.0-pyh1a96a4e_0.conda - version: 2023.4.0 + url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.5.0-pyh1a96a4e_0.conda + version: 2023.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -2363,13 +2377,13 @@ package: gcc: 12.2.0.* gxx_impl_linux-64: 12.2.0.* hash: - md5: 56e0d282569b6cd349035a1bb5efae47 - sha256: b428f0af395194cb327fb212167efc3a837866d11b9f1a8bbad7e953c595c6cb + md5: de605ff437f3fdc010f1b529642339f1 + sha256: 58bc0a7ff843c4ac2fd53b1370d266d635b59cf8d1d6f165cc26cf1f5324c9f8 manager: conda name: gxx optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_12.conda + url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_13.conda version: 12.2.0 - category: main dependencies: @@ -2527,31 +2541,31 @@ package: - category: main dependencies: libgcc-ng: '>=12' - libllvm16: '>=16.0.1,<16.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' hash: - md5: 2c00ecf8081a8f23043b055a68d7ba90 - sha256: 5f3eb78832674b8038dd65c80d09837a01f3300bf516370fc16650f33b8b87ed + md5: 205aca93c1bc4a0bc663dd787c224025 + sha256: 66e0e925088acbc1306c814ca8441e61dd2f2a2ff93ff752b914939b87864d24 manager: conda name: libclang-cpp16 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libclang-cpp16-16.0.1-default_h62803fd_0.conda - version: 16.0.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libclang-cpp16-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: libgcc-ng: '>=12' - libllvm16: '>=16.0.1,<16.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' hash: - 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version: 1.24.2 + url: https://conda.anaconda.org/conda-forge/linux-64/numpy-1.24.3-py39h6183b62_0.conda + version: 1.24.3 - category: main dependencies: libgcc-ng: '>=12' @@ -2802,15 +2816,16 @@ package: version: 1.9.6 - category: main dependencies: - python: '>=3.8' + python: '>=3.9,<3.10.0a0' + python_abi: 3.9.* *_cp39 hash: - md5: 7d301a0d25f424d96175f810935f0da9 - sha256: c25e1757e4e90638bb1e778aba3ee5f3c01fae9752e3c3929f9be7d367f6c7f3 + md5: d86903c57fe229d9dd8878a6dd9d149f + sha256: abf2d34464c6255d35703e3c9477475e3e6e353ca8675990596d2477cdbc5b52 manager: conda name: pluggy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pluggy-1.0.0-pyhd8ed1ab_5.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/pluggy-1.0.0-py39hf3d152e_4.tar.bz2 version: 1.0.0 - category: main dependencies: @@ -2941,16 +2956,16 @@ package: version: 0.19.3 - category: main dependencies: - __unix: '' - python: '>=3.8' + python: '>=3.9,<3.10.0a0' + python_abi: 3.9.* *_cp39 hash: - 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category: main dependencies: click: '' @@ -3723,14 +3750,14 @@ package: python: '>=3.8' zipp: '>=0.5' hash: - md5: ab2f9216e346f43599af3f7839931da1 - sha256: 1854da61b10c601bae3497e0d457b1bb029715d4bcabb5594199519de7c72f5a + md5: f91a5d5175fb7ff2a91952ec7da59cb9 + sha256: 33d49065756a73fbb92277c756fa00a41891408528eb90ae05ff3367a401ae6e manager: conda name: importlib-metadata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.5.0-pyha770c72_0.conda - version: 6.5.0 + url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.6.0-pyha770c72_0.conda + version: 6.6.0 - category: main dependencies: python: '>=3.7' @@ -3911,14 +3938,14 @@ package: setuptools: '' wheel: '' hash: - md5: 9ccbacfd1cbfa0be00cc345fe5ad8816 - sha256: 781992f04a8c765b1ad29b54fc9f76c12b0864f9defd2869eeb5edff15b51546 + md5: 7288da0d36821349cf1126e8670292df + sha256: 4fe1f47f6eac5b2635a622b6f985640bf835843c1d8d7ccbbae0f7d27cadec92 manager: conda name: pip optional: false platform: linux-64 - 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url: https://conda.anaconda.org/conda-forge/noarch/tomlkit-0.11.7-pyha770c72_0.conda - version: 0.11.7 + url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.17.24-py39hd1e30aa_0.conda + version: 0.17.24 - category: main dependencies: colorama: '' @@ -4011,14 +4025,14 @@ package: python: '>=3.6' types-urllib3: <1.27 hash: - md5: 856c0ae2398368dba2555354564d5228 - sha256: caacc1f5c91c39754611cd74cdc3b34a87efa5963d38c937fc927960586c18dd + md5: 1ab2e9a47f24fac257f88956828f1956 + sha256: 19d2affb4d3fab4d1d60eb3748b2d80b9ff2983c9b196e74aae7a0dc03fe74d8 manager: conda name: types-requests optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-requests-2.28.11.17-pyhd8ed1ab_0.conda - version: 2.28.11.17 + url: https://conda.anaconda.org/conda-forge/noarch/types-requests-2.30.0.0-pyhd8ed1ab_0.conda + version: 2.30.0.0 - category: main dependencies: typing_extensions: 4.5.0 pyha770c72_0 @@ -4043,27 +4057,27 @@ package: xorg-libx11: '>=1.8.4,<2.0a0' xorg-libxt: '' hash: - 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category: main dependencies: libgcc-ng: '>=9.3.0' @@ -4088,14 +4102,14 @@ package: python: '>=3.9,<3.10.0a0' python_abi: 3.9.* *_cp39 hash: - md5: fc75e67104cc1bdd6aa2a3b970b19f7f - sha256: 0fb71fdb26db6e49ad92a09ffd26c99145dc02eeb8e15e48fde4437b6237ea58 + md5: 38cd0735b2002777c765fa5b7f4217b5 + sha256: d9e48f222156d21817588a853efa63e84d5f2c5dedfb00df73a53857ef12ec26 manager: conda name: yarl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/yarl-1.8.2-py39hb9d737c_0.conda - version: 1.8.2 + url: https://conda.anaconda.org/conda-forge/linux-64/yarl-1.9.1-py39hd1e30aa_0.conda + version: 1.9.1 - category: main dependencies: python: '>=3.6' @@ -4143,20 +4157,20 @@ package: version: 0.7.0 - category: main dependencies: - clang-format-16: 16.0.1 default_h62803fd_0 - libclang-cpp16: '>=16.0.1,<16.1.0a0' + clang-format-16: 16.0.3 default_h83cc7fd_0 + libclang-cpp16: '>=16.0.3,<16.1.0a0' libgcc-ng: '>=12' - libllvm16: '>=16.0.1,<16.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' hash: - 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category: main dependencies: libgcc-ng: '>=12' @@ -4412,14 +4427,14 @@ package: pip: '' python: '>=3.7,<4.0' hash: - md5: fb6a4bb2c52647f4422e8a47d706ef1c - sha256: 092ddd70025bbe90042fb77bc21aa467b6181f486e7137d2c47b72f824688ea9 + md5: 8462b4f53fa7d7dc057a26d589ec71de + sha256: dc2928817ff89e3628f82f3cedd4369c84d7079d04493b33dc67e4288d1de35d manager: conda name: types-awscrt optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.16.15-pyhd8ed1ab_0.conda - version: 0.16.15 + url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.16.17-pyhd8ed1ab_0.conda + version: 0.16.17 - category: main dependencies: cffi: '' @@ -4496,31 +4511,31 @@ package: types-awscrt: '' typing_extensions: '' hash: - md5: a2b0b88e5b4bcfdab4c03acd24667046 - sha256: 161c95587e95cedcf2587b1e666827d29c02383e4bbfdc338dfe0f8183af3747 + md5: 01961f718d29cabd188e863a61d8fd81 + sha256: 1fc8f40eb33d7e38590d88d847fb39329628c31269c8a2e5aaab7d51cc5b501f manager: conda name: botocore-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.115-pyhd8ed1ab_0.conda - version: 1.29.115 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.129-pyhd8ed1ab_0.conda + version: 1.29.129 - category: main dependencies: - clang-format: 16.0.1 default_h62803fd_0 - libclang-cpp16: '>=16.0.1,<16.1.0a0' - libclang13: '>=16.0.1' + clang-format: 16.0.3 default_h83cc7fd_0 + libclang-cpp16: '>=16.0.3,<16.1.0a0' + libclang13: '>=16.0.3' libgcc-ng: '>=12' - libllvm16: '>=16.0.1,<16.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' hash: - md5: 6fa41767486e911517c03bb069b9f5fa - sha256: a0acf37ed406a66e72577d40b52185488644a9a1ce56a99823c3318f9900260b + md5: ceedc73b354682b0d63d61d654ebcd33 + sha256: b5ea9bef3e3316c34bfbde0a3a50cb53a2bf2db89221c9b145d37fc1e5c89576 manager: conda name: clang-tools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-tools-16.0.1-default_h62803fd_0.conda - version: 16.0.1 + url: https://conda.anaconda.org/conda-forge/linux-64/clang-tools-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: python: '>=3.7' @@ -4553,14 +4568,14 @@ package: python: '>=3.6' ukkonen: '' hash: - md5: b8d16e273396a0115199a83769a39246 - sha256: 45cbad9e8329b33d348c536ef0c49fb1811261201072e3d536199c106562d607 + md5: a4085ab0562d5081a9333435837b538a + sha256: 4027103c59220a68b41aed056d2ce89d46e4971033d259293ca07198a8a81fdc manager: conda name: identify optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.22-pyhd8ed1ab_0.conda - version: 2.5.22 + url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.24-pyhd8ed1ab_0.conda + version: 2.5.24 - category: main dependencies: importlib_metadata: '' @@ -4799,14 +4814,14 @@ package: platformdirs: <4,>=3.2 python: '>=3.8' hash: - md5: 054007ab693cb77a029ea4f1f12f34a7 - sha256: acb9f18ef811cda29690d41e0e7c54f7088d35e6b5aa5db6403d13c9eb18336a + md5: a920e114c4c2ced2280e266da65ab5e6 + sha256: 13d667887ea08b6d1fe2eb09d2d737f9af7343735d3bfa5ffaa3f67eec8eaff7 manager: conda name: virtualenv optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.22.0-pyhd8ed1ab_0.conda - version: 20.22.0 + url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.23.0-pyhd8ed1ab_0.conda + version: 20.23.0 - category: main dependencies: conda-package-streaming: '>=0.7.0' @@ -4913,14 +4928,14 @@ package: pyyaml: '>=5.1' virtualenv: '>=20.10.0' hash: - md5: c4aab94cab4ddeb340e36d4c670a5f24 - sha256: 4331584fffa05cf3096799c95495ce97563699dc7c4da341e9b1ced96e4f5526 + md5: c3ad8d291556452edb6c301c91f330ed + sha256: db90abf2c06c8bace41c491e2af445d06178fa8c9111e0e2ae4738866cb929ef manager: conda name: pre-commit optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.2.2-pyha770c72_0.conda - version: 3.2.2 + url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.3.1-pyha770c72_0.conda + version: 3.3.1 - category: main dependencies: __unix: '' @@ -4959,14 +4974,14 @@ package: python-dateutil: '>=2.1,<3.0.0' urllib3: '>=1.25.4,<1.27' hash: - md5: fb3a321c00c20e538fa694ea3aa56bb3 - sha256: 6cd079ddf88e9fe825e60ce4f01cacbbd5e0571f792b9c4628b77eb073bcdbf7 + md5: b6cdb2c025e2a44462c7f0f4ee1502a8 + sha256: 1a92aaf1e978b1a219726fd9747cd43d43aed2d3aee9932be0d8b79a66e5ea83 manager: conda name: botocore optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.116-pyhd8ed1ab_0.conda - version: 1.29.116 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.130-pyhd8ed1ab_0.conda + version: 1.29.130 - category: main dependencies: cairo: '>=1.16.0,<2.0a0' @@ -4980,8 +4995,8 @@ package: libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libgd: '>=2.3.3,<2.4.0a0' - libglib: '>=2.76.1,<3.0a0' - librsvg: '>=2.54.4,<3.0a0' + libglib: '>=2.76.2,<3.0a0' + librsvg: '>=2.56.0,<3.0a0' libstdcxx-ng: '>=12' libtool: '' libwebp-base: '>=1.3.0,<2.0a0' @@ -4989,30 +5004,30 @@ package: pango: '>=1.50.14,<2.0a0' zlib: '' hash: - md5: 09c3cfc5ec50aef65f67c5f1bde535c6 - sha256: 9da43e1550de05f9e56d0b1d452d9567d9156e3fbcba0e0291ff458300bb70b4 + md5: 597e2d0e1c6bc2e4457714ff479fe142 + sha256: 4bfb42de2d28406666ef6729169cae3f49c216c5ebd9f34afa40223755e2aaf8 manager: conda name: graphviz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/graphviz-8.0.3-h2e5815a_0.conda - version: 8.0.3 + url: https://conda.anaconda.org/conda-forge/linux-64/graphviz-8.0.5-h28d9a01_0.conda + version: 8.0.5 - category: main dependencies: certifi: '>=2017.4.17' charset-normalizer: '>=2,<4' idna: '>=2.5,<4' - python: '>=3.7,<4.0' + python: '>=3.7' urllib3: '>=1.21.1,<1.27' hash: - md5: 3bfbd6ead1d7299ed46dab3a7bf0bc8c - sha256: 9a7c3410970217fa035cca7f72c175989e1c8b22f855b852b9d5fde07c3550dd + md5: 5fa992d972fbccfc069161805122cb8d + sha256: bd06a6603104050fc9c4fd9bf3de7b28bbb6b9ce4b33130519d8611488213f67 manager: conda name: requests optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/requests-2.28.2-pyhd8ed1ab_1.conda - version: 2.28.2 + url: https://conda.anaconda.org/conda-forge/noarch/requests-2.29.0-pyhd8ed1ab_0.conda + version: 2.29.0 - category: main dependencies: aiohttp: '>=3.3.1' @@ -5104,14 +5119,14 @@ package: urllib3: '>=1.26.0' websocket-client: '>=0.32.0' hash: - md5: 8b0d1b5227ce39053aa69c3ff18417ec - sha256: 45e16e6f7e4105c71c1494ca523b01e676349a25ee1f8114a6c10bbdd8549d50 + md5: 543336c6aa9516cfb29c51d5c162b177 + sha256: 5e01e15e20ee573c99b530633a0d5c71fd515e4ac6d2f5f5f57baece8b915cc3 manager: conda name: docker-py optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/docker-py-6.0.0-pyhd8ed1ab_0.tar.bz2 - version: 6.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/docker-py-6.1.0-pyhd8ed1ab_0.conda + version: 6.1.0 - category: main dependencies: appdirs: '' @@ -5175,14 +5190,14 @@ package: botocore: '>=1.12.36,<2.0a.0' python: '>=3.7' hash: - md5: 900e74d8547fbea3af028937df28ed77 - sha256: 0e459ed32b00e96b62c2ab7e2dba0135c73fd980120fe1a7bd49901f2d50760f + md5: b19a857ac845097e9c823c9f4d35f80e + sha256: 99512bf4f4e297cc7565c94eee8ccc908411f836b341668e2b5d064273e21762 manager: conda name: s3transfer optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/s3transfer-0.6.0-pyhd8ed1ab_0.tar.bz2 - version: 0.6.0 + url: https://conda.anaconda.org/conda-forge/noarch/s3transfer-0.6.1-pyhd8ed1ab_0.conda + version: 0.6.1 - category: main dependencies: alabaster: '>=0.7,<0.8' @@ -5214,7 +5229,7 @@ package: version: 5.1.1 - category: main dependencies: - botocore: 1.29.116 + botocore: 1.29.130 colorama: '>=0.2.5,<0.4.5' docutils: '>=0.10,<0.17' python: '>=3.9,<3.10.0a0' @@ -5223,29 +5238,29 @@ package: rsa: '>=3.1.2,<4.8' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: 7ff7995ef5ae66e3f40ecf8715f94af9 - sha256: 075259e8d6df02f58a7d4b0a981ea0713936de293758f77d874dfaead449ad55 + md5: d29b9589db984f0409b1dbf4e7823fe4 + sha256: 1a5b51fbb3152115acb26b65f3811aa022a0ae9103031bc88953feff463679d4 manager: conda name: awscli optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.116-py39hf3d152e_0.conda - version: 1.27.116 + url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.130-py39hf3d152e_0.conda + version: 1.27.130 - category: main dependencies: - botocore: '>=1.29.116,<1.30.0' + botocore: '>=1.29.130,<1.30.0' jmespath: '>=0.7.1,<2.0.0' python: '>=3.7' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: 858c31f9e605c623871cb7521e37c926 - sha256: c834aa58f41881ebf642da868008dfbe64b4868d4dcf8b91c57b52fcadccec3b + md5: b41eaaaf0f77cce83052e5cfa841251c + sha256: 29588b211401de9dc34318bbb00eeb946e6961afb74f1097ec1ed24948300116 manager: conda name: boto3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.116-pyhd8ed1ab_0.conda - version: 1.26.116 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.130-pyhd8ed1ab_0.conda + version: 1.26.130 - category: main dependencies: cachecontrol: 0.12.11 pyhd8ed1ab_1 @@ -5371,14 +5386,14 @@ package: python: '' typing_extensions: '' hash: - md5: cfd95e43a27c0af1a206f7557d7f132e - sha256: 02570a9062717ec9b3293199ab8e8983c92f2320f5f8066ef541929a1166d9f1 + md5: da03042814034e36f0938058b7b218fb + sha256: d18385d39e4af117b99cbd931cb68cbd33582949a837ae4e6453964ecc64d80a manager: conda name: boto3-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.117-pyhd8ed1ab_0.conda - version: 1.26.117 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.130-pyhd8ed1ab_0.conda + version: 1.26.130 - category: main dependencies: cachecontrol-with-filecache: '>=0.12.9' @@ -5419,28 +5434,28 @@ package: python: '>=3.6' typing-extensions: '' hash: - md5: cfc72b1b83d1b8503b1071455534ebac - sha256: 1df5aa62e1fc8d498a37f30723d15a1626dc9b686603e79b4b44ba6c95f8f659 + md5: adb30ee4ef9f506b62f732c8a78d250b + sha256: 281ba68f92f05626bf37df32156abbf62e6ed963ab40b2205277a066391cc06f manager: conda name: mypy-boto3-s3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.116-pyhd8ed1ab_0.conda - version: 1.26.116 + url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.127-pyhd8ed1ab_0.conda + version: 1.26.127 - category: main dependencies: boto3: '' python: '>=3.6' typing-extensions: '' hash: - md5: 93e899cf501d962cfd1b251a45416825 - sha256: ef57856f4313eac453b53a119cedf121bd16fc98c64beaee8e3309959673daea + md5: 35a0dc87b7ff0abd9e3012bea164f439 + sha256: 706be4a8f070af47d29e18315c3053977315c1c58479ecfebb2443d3a72edf87 manager: conda name: mypy_boto3_ec2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.106-pyhd8ed1ab_0.conda - version: 1.26.106 + url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.129-pyhd8ed1ab_0.conda + version: 1.26.129 - category: main dependencies: boto3: '' @@ -5519,14 +5534,14 @@ package: werkzeug: '>=0.5,!=2.2.0,!=2.2.1' xmltodict: '' hash: - md5: c4172149b03b032cd60cc79f1484a1dd - sha256: 5891a5ce23d274406bda81e202ddc303d30a3355c01c7d9ae461fc5313247e9d + md5: 89dfb6776dcc992a100cafd0c612b7fb + sha256: f5de61e07e99798c0f73947fae9f947a4eb7aeff7adc04e78b9a9a3ef2ddc780 manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.7-pyhd8ed1ab_2.conda - version: 4.1.7 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.9-pyhd8ed1ab_0.conda + version: 4.1.9 - category: main dependencies: {} hash: diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index 1fbce68b..46143863 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -9,7 +9,7 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml +# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml -f /scratch/abejgonza/cy/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -21,12 +21,14 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 3d155013008436d15b7f1d8d02c2aa15cfa96a5619d70b0a018c7ff253303935 + linux-64: 498b97706da9689cdb3c746adf985ab110ff8b43831da408f8042336b15563bc platforms: - linux-64 sources: - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml + - /scratch/abejgonza/cy/conda-reqs/chipyard.yaml + - /scratch/abejgonza/cy/conda-reqs/riscv-tools.yaml package: - category: main dependencies: {} @@ -42,13 +44,13 @@ package: - category: main dependencies: {} hash: - md5: a581b4a89191b6c1d6a16488a9cffbfc - sha256: 695e67ae4bc22f9e0be5f54b1948a8f2b678f4da920fa2082a249dd5a88f440e + md5: f6ce7955b53ae1ca83144adb3be9c600 + sha256: 546e4eb1cbd822a66b363ec3fbdcc4fcc53853bcab57674cb46b8f3209b856f2 manager: conda name: _sysroot_linux-64_curr_repodata_hack optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h5bd9786_13.tar.bz2 + url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_13.conda version: '3' - category: main dependencies: {} @@ -64,14 +66,14 @@ package: - category: main dependencies: {} hash: - md5: ff9f73d45c4a07d6f424495288a26080 - sha256: 8f6c81b0637771ae0ea73dc03a6d30bec3326ba3927f2a7b91931aa2d59b1789 + md5: f5c65075fc34438d5b456c7f3f5ab695 + sha256: 0cf1bb3d0bfc5519b60af2c360fa4888fb838e1476b1e0f65b9dbc48b45c7345 manager: conda name: ca-certificates optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2022.12.7-ha878542_0.conda - version: 2022.12.7 + url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2023.5.7-hbcca054_0.conda + version: 2023.5.7 - category: main dependencies: {} hash: @@ -883,13 +885,13 @@ package: ca-certificates: '' libgcc-ng: '>=12' hash: - md5: 2d833be81a21128e317325a01326d36f - sha256: d378afcec34b86fef4da3ebd622b3e614cb3f71e54b6a5a10adb1d23745ecc72 + md5: 8f24d371ed9efb3f0b0de383fb81d51c + sha256: 24bf6cf8f741c28a8d10f51c917f378694d4a98a38ab4372629932cd6c94e9e8 manager: conda name: openssl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.1.0-h0b41bf4_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.1.0-hd590300_3.conda version: 3.1.0 - category: main dependencies: @@ -1358,14 +1360,14 @@ package: libgcc-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 2e5f9a37d487e1019fd4d8113adb2f9f - sha256: 6008a0b914bd1a3510a3dba38eada93aa0349ebca3a21e5fa276833c8205bf49 + md5: 1d002bf709048f8021c32abfd0e0d395 + sha256: bb2a8ddb26e74f2cedc36825fc6f95d45f19e1912a1a6c75847952d92fc16215 manager: conda name: libsqlite optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libsqlite-3.40.0-h753d276_0.tar.bz2 - version: 3.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libsqlite-3.41.2-h2797004_1.conda + version: 3.41.2 - category: main dependencies: libgcc-ng: '>=12' @@ -1709,13 +1711,13 @@ package: dependencies: gcc_impl_linux-64: 12.2.0.* hash: - md5: c241b4f6676222c2feefc9dc4b9d1728 - sha256: f4b4184cc3e0864abadfc5b06ae869b479e736ff1dc46723967256d11b5bc7c4 + md5: ec93d13e0fe8514f65842120dbae1b16 + sha256: 5478f5b7672b6c2d5b644aaa9fe18fbb1468ca6ea9cea1b0f0a2254459438e24 manager: conda name: gcc optional: false platform: linux-64 - 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url: https://conda.anaconda.org/conda-forge/linux-64/sqlite-3.40.0-h4ff8645_0.tar.bz2 - version: 3.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/sqlite-3.41.2-h2c6b66d_1.conda + version: 3.41.2 - category: main dependencies: libgcc-ng: '>=9.4.0' @@ -2028,16 +2030,16 @@ package: version: 1.4.4 - category: main dependencies: - python: '>=3.6' + python: '>=3.7' hash: - md5: 99b19895abe40280358488acb9589532 - sha256: 2b273efc522834e4c8563da7998b9b683eed467660fe8a5a3c24d58aaa85a9cb + md5: 0b3460f5bf4ae27dfd72fdcccc9667a9 + sha256: 18aad01518cb08e4eff18e507e14ebf6c522d89ef53ca267c48080933c4435f7 manager: conda name: argcomplete optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.5-pyhd8ed1ab_0.conda - version: 3.0.5 + url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.8-pyhd8ed1ab_0.conda + version: 3.0.8 - category: main dependencies: libgcc-ng: '>=12' @@ -2054,16 +2056,28 @@ package: version: 2.38.0 - category: main dependencies: - python: '>=3.5' + python: '>=3.7' hash: - md5: 8b76db7818a4e401ed4486c4c1635cd9 - sha256: 3a58d4a4933fa8735471c782d35326ab78e0bcfce84756408515f82a94e4dec4 + md5: 3edfead7cedd1ab4400a6c588f3e75f8 + sha256: 063639cd568f5c7a557b0fb1cc27f098598c0d8ff869088bfeb82934674f8821 manager: conda name: attrs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/attrs-22.2.0-pyh71513ae_0.conda - version: 22.2.0 + url: https://conda.anaconda.org/conda-forge/noarch/attrs-23.1.0-pyh71513ae_1.conda + version: 23.1.0 +- category: main + dependencies: + python: '>=3.7' + hash: + md5: 2fb79ec81bad9492b6d59a06b3b647a4 + sha256: b6f32491536823e47cf6eb4717dd341385600a2b901235028dedc629a77aeb82 + manager: conda + name: blinker + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/blinker-1.6.2-pyhd8ed1ab_0.conda + version: 1.6.2 - category: main dependencies: brotli-bin: 1.0.9 h166bdaf_8 @@ -2095,14 +2109,14 @@ package: dependencies: python: '>=3.7' hash: - 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version: 1.24.2 + url: https://conda.anaconda.org/conda-forge/linux-64/numpy-1.24.3-py310ha4c1d20_0.conda + version: 1.24.3 - category: main dependencies: libgcc-ng: '>=12' @@ -2785,15 +2799,16 @@ package: version: 1.9.6 - category: main dependencies: - python: '>=3.8' + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 hash: - md5: 7d301a0d25f424d96175f810935f0da9 - sha256: c25e1757e4e90638bb1e778aba3ee5f3c01fae9752e3c3929f9be7d367f6c7f3 + md5: 02e428ab589e3cefe070352c905cefec + sha256: 28967130059ac29a1298de5f4555c0ec6344ea56e32642c44f40c19d83f38162 manager: conda name: pluggy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pluggy-1.0.0-pyhd8ed1ab_5.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/pluggy-1.0.0-py310hff52083_4.tar.bz2 version: 1.0.0 - category: main dependencies: @@ -2924,16 +2939,16 @@ package: version: 0.19.3 - category: main dependencies: - __unix: '' - python: '>=3.8' + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 hash: - 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category: main dependencies: python: '' @@ -3179,6 +3194,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/tomli-2.0.1-pyhd8ed1ab_0.tar.bz2 version: 2.0.1 +- category: main + dependencies: + python: '>=3.7' + hash: + md5: 75838e8556166263a82038b51d01d5f1 + sha256: 3002e87338a98ba501fbf53981f8267b2def2548265a3622d403d06747872ccd + manager: conda + name: tomlkit + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/tomlkit-0.11.8-pyha770c72_0.conda + version: 0.11.8 - category: main dependencies: python: '>=3.5' @@ -3233,14 +3260,14 @@ package: dependencies: python: '>=3.6' hash: - md5: 1c44c106ac42fde5774d31e37220f4df - sha256: b9df570c65f14a002a3972bf9e9ed0c0ef8ff6a29087ba8d6be6493bfd1ea8ef + md5: 8b7a7a28f8a274b98f0387c13c56c94c + sha256: e07d313a9c7aa2dfe425ca5a3bdc65cd015a8819cda8e576edb3b3a47535da1a manager: conda name: types-urllib3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-urllib3-1.26.25.10-pyhd8ed1ab_0.conda - version: 1.26.25.10 + url: https://conda.anaconda.org/conda-forge/noarch/types-urllib3-1.26.25.12-pyhd8ed1ab_0.conda + version: 1.26.25.12 - category: main dependencies: python: '>=3' @@ -3530,19 +3557,19 @@ package: version: 15.0.7 - category: main dependencies: - libclang-cpp16: '>=16.0.1,<16.1.0a0' + libclang-cpp16: '>=16.0.3,<16.1.0a0' libgcc-ng: '>=12' - libllvm16: '>=16.0.1,<16.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' hash: - md5: cc2343dad8afb0b3d9cc368da2d58e22 - sha256: a3ae4c803ff00cdf74984c02ac8279e39861bb4aad16854c18a81792936714ac + md5: 14a18f87f492a905cee3d833eae4e86b + sha256: 0896316dbdcd3dca118c61127b2d79cc0c0bdb08f869cff9f35fe2c5a4673555 manager: conda name: clang-format-16 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-16-16.0.1-default_h62803fd_0.conda - version: 16.0.1 + url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-16-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: click: '' @@ -3725,14 +3752,14 @@ package: python: '>=3.8' zipp: '>=0.5' hash: - md5: ab2f9216e346f43599af3f7839931da1 - sha256: 1854da61b10c601bae3497e0d457b1bb029715d4bcabb5594199519de7c72f5a + md5: f91a5d5175fb7ff2a91952ec7da59cb9 + sha256: 33d49065756a73fbb92277c756fa00a41891408528eb90ae05ff3367a401ae6e manager: conda name: importlib-metadata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.5.0-pyha770c72_0.conda - version: 6.5.0 + url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.6.0-pyha770c72_0.conda + version: 6.6.0 - category: main dependencies: more-itertools: '' @@ -3900,14 +3927,14 @@ package: setuptools: '' wheel: '' hash: - md5: 9ccbacfd1cbfa0be00cc345fe5ad8816 - sha256: 781992f04a8c765b1ad29b54fc9f76c12b0864f9defd2869eeb5edff15b51546 + md5: 7288da0d36821349cf1126e8670292df + sha256: 4fe1f47f6eac5b2635a622b6f985640bf835843c1d8d7ccbbae0f7d27cadec92 manager: conda name: pip optional: false platform: linux-64 - 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category: main dependencies: libgcc-ng: '>=9.3.0' @@ -4077,14 +4091,14 @@ package: python: '>=3.10,<3.11.0a0' python_abi: 3.10.* *_cp310 hash: - md5: a88cda17074955bdb5e93b8e3be59e7d - sha256: eb7fd99bf87e0d150ee6946479172688ded1c4fb51382ad27be5da217cd8815b + md5: e8ede9a6fedf3e0e640e810749b4cb6e + sha256: d56b21d563c673023561a4e83e9f5731441ce2bce80ca5cfe55cfa8bfa5d5eb1 manager: conda name: yarl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/yarl-1.8.2-py310h5764c6d_0.conda - version: 1.8.2 + url: https://conda.anaconda.org/conda-forge/linux-64/yarl-1.9.1-py310h2372a71_0.conda + version: 1.9.1 - category: main dependencies: python: '>=3.6' @@ -4132,20 +4146,20 @@ package: version: 0.7.0 - category: main dependencies: - clang-format-16: 16.0.1 default_h62803fd_0 - libclang-cpp16: '>=16.0.1,<16.1.0a0' + clang-format-16: 16.0.3 default_h83cc7fd_0 + libclang-cpp16: '>=16.0.3,<16.1.0a0' libgcc-ng: '>=12' - libllvm16: '>=16.0.1,<16.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' hash: - 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url: https://conda.anaconda.org/conda-forge/noarch/flask-2.2.3-pyhd8ed1ab_0.conda - version: 2.2.3 + url: https://conda.anaconda.org/conda-forge/noarch/flask-2.3.2-pyhd8ed1ab_0.conda + version: 2.3.2 - category: main dependencies: curl: '' - expat: '>=2.5.0,<3.0a0' gettext: '' + libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libiconv: '>=1.17,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' @@ -4205,14 +4220,14 @@ package: pcre2: '>=10.40,<10.41.0a0' perl: 5.* hash: - md5: 06b9b63f77ee1dea0d3a0c97f839385a - sha256: 3734da309ef157024b69fb01947fa71a04dfd8ca798eba962e8575da9ebfac9a + md5: 0cb5ff348eb4c201b3b920eff851675d + sha256: 528c9fdaf799b38611276d6f676da6018da2aaf93fb5b0328c00923909e99432 manager: conda name: git optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/git-2.40.0-pl5321h3ca6407_1.conda - version: 2.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/git-2.40.1-pl5321h86e50cf_0.conda + version: 2.40.1 - category: main dependencies: gitdb: '>=4.0.1,<5' @@ -4247,16 +4262,16 @@ package: version: 6.0.0 - category: main dependencies: - importlib-metadata: '>=6.5.0,<6.5.1.0a0' + importlib-metadata: '>=6.6.0,<6.6.1.0a0' hash: - md5: 24bfc0314deeea53d54c71de2b436ed6 - sha256: 11c866dd631856dfa043ced5d85b892798a93bd5cd617bce2368a83b90b5c93d + md5: 3cbc9615f10a3d471532b83e4250b971 + sha256: 5de35d3c019d8a36e0a0deeb04a62689837bd68234a0a73a3355b860b442eca4 manager: conda name: importlib_metadata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-6.5.0-hd8ed1ab_0.conda - version: 6.5.0 + url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-6.6.0-hd8ed1ab_0.conda + version: 6.6.0 - category: main dependencies: attrs: '>=17.4.0' @@ -4325,14 +4340,14 @@ package: python_abi: 3.10.* *_cp310 pytz: '>=2020.1' hash: - md5: 38dd747dcb3403c0958c4f510ed4316e - sha256: 1757d0991592083172a63fc79a576dd16e94cb4a353da4d00ac7280806e5dd30 + md5: 25fc16ee9a1df69e91c8213530f2cc8c + sha256: 4af68421353f552c6d321bfc8b76040eaa89fa35c0a7854be8acaddf154be63e manager: conda name: pandas optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pandas-2.0.0-py310h9b08913_0.conda - version: 2.0.0 + url: https://conda.anaconda.org/conda-forge/linux-64/pandas-2.0.1-py310h7cbd5c2_1.conda + version: 2.0.1 - category: main dependencies: pip: '' @@ -4351,14 +4366,14 @@ package: python: '>=3.7' typing-extensions: '>=4.5' hash: - md5: f10c2cf447ca96f12a326b83c75b8e33 - sha256: 51816d5471cc42059cc7a8616c8899b6fda7347999359c3979fefd0035ab274c + md5: 6c36f1c42dd0069b7f23acc74f19be46 + sha256: e6d247b9a645ac6a2e4909cbe9cfad5cf9ba1a2f4352fee7aac3acb640371a54 manager: conda name: platformdirs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/platformdirs-3.2.0-pyhd8ed1ab_0.conda - version: 3.2.0 + url: https://conda.anaconda.org/conda-forge/noarch/platformdirs-3.5.0-pyhd8ed1ab_0.conda + version: 3.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -4415,14 +4430,14 @@ package: pip: '' python: '>=3.7,<4.0' hash: - md5: fb6a4bb2c52647f4422e8a47d706ef1c - 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category: main dependencies: - clang-format: 16.0.1 default_h62803fd_0 - libclang-cpp16: '>=16.0.1,<16.1.0a0' - libclang13: '>=16.0.1' + clang-format: 16.0.3 default_h83cc7fd_0 + libclang-cpp16: '>=16.0.3,<16.1.0a0' + libclang13: '>=16.0.3' libgcc-ng: '>=12' - libllvm16: '>=16.0.1,<16.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' hash: - md5: 6fa41767486e911517c03bb069b9f5fa - sha256: a0acf37ed406a66e72577d40b52185488644a9a1ce56a99823c3318f9900260b + md5: ceedc73b354682b0d63d61d654ebcd33 + sha256: b5ea9bef3e3316c34bfbde0a3a50cb53a2bf2db89221c9b145d37fc1e5c89576 manager: conda name: clang-tools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-tools-16.0.1-default_h62803fd_0.conda - version: 16.0.1 + url: https://conda.anaconda.org/conda-forge/linux-64/clang-tools-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: python: '>=3.7' @@ -4556,14 +4571,14 @@ package: python: '>=3.6' ukkonen: '' hash: - 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version: 20.22.0 + url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.23.0-pyhd8ed1ab_0.conda + version: 20.23.0 - category: main dependencies: conda-package-streaming: '>=0.7.0' @@ -4888,14 +4903,14 @@ package: pyyaml: '>=5.1' virtualenv: '>=20.10.0' hash: - md5: c4aab94cab4ddeb340e36d4c670a5f24 - sha256: 4331584fffa05cf3096799c95495ce97563699dc7c4da341e9b1ced96e4f5526 + md5: c3ad8d291556452edb6c301c91f330ed + sha256: db90abf2c06c8bace41c491e2af445d06178fa8c9111e0e2ae4738866cb929ef manager: conda name: pre-commit optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.2.2-pyha770c72_0.conda - version: 3.2.2 + url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.3.1-pyha770c72_0.conda + version: 3.3.1 - category: main dependencies: __unix: '' @@ -4934,14 +4949,14 @@ package: python-dateutil: '>=2.1,<3.0.0' urllib3: '>=1.25.4,<1.27' hash: - md5: c23737efb6d9e44fa00795cded4f5ed9 - sha256: 38e65d48b017160bbcc455159616e1025ca48a8e54304d5f9448d304837021e2 + md5: b6cdb2c025e2a44462c7f0f4ee1502a8 + sha256: 1a92aaf1e978b1a219726fd9747cd43d43aed2d3aee9932be0d8b79a66e5ea83 manager: conda name: botocore optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.76-pyhd8ed1ab_0.conda - version: 1.29.76 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.130-pyhd8ed1ab_0.conda + version: 1.29.130 - category: main dependencies: cairo: '>=1.16.0,<2.0a0' @@ -4955,8 +4970,8 @@ package: libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libgd: '>=2.3.3,<2.4.0a0' - libglib: '>=2.76.1,<3.0a0' - librsvg: '>=2.54.4,<3.0a0' + libglib: '>=2.76.2,<3.0a0' + librsvg: '>=2.56.0,<3.0a0' libstdcxx-ng: '>=12' libtool: '' libwebp-base: '>=1.3.0,<2.0a0' @@ -4964,30 +4979,30 @@ package: pango: '>=1.50.14,<2.0a0' zlib: '' hash: - md5: 09c3cfc5ec50aef65f67c5f1bde535c6 - sha256: 9da43e1550de05f9e56d0b1d452d9567d9156e3fbcba0e0291ff458300bb70b4 + md5: 597e2d0e1c6bc2e4457714ff479fe142 + sha256: 4bfb42de2d28406666ef6729169cae3f49c216c5ebd9f34afa40223755e2aaf8 manager: conda name: graphviz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/graphviz-8.0.3-h2e5815a_0.conda - version: 8.0.3 + url: https://conda.anaconda.org/conda-forge/linux-64/graphviz-8.0.5-h28d9a01_0.conda + version: 8.0.5 - category: main dependencies: certifi: '>=2017.4.17' charset-normalizer: '>=2,<4' idna: '>=2.5,<4' - python: '>=3.7,<4.0' + python: '>=3.7' urllib3: '>=1.21.1,<1.27' hash: - md5: 3bfbd6ead1d7299ed46dab3a7bf0bc8c - sha256: 9a7c3410970217fa035cca7f72c175989e1c8b22f855b852b9d5fde07c3550dd + md5: 5fa992d972fbccfc069161805122cb8d + sha256: bd06a6603104050fc9c4fd9bf3de7b28bbb6b9ce4b33130519d8611488213f67 manager: conda name: requests optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/requests-2.28.2-pyhd8ed1ab_1.conda - version: 2.28.2 + url: https://conda.anaconda.org/conda-forge/noarch/requests-2.29.0-pyhd8ed1ab_0.conda + version: 2.29.0 - category: main dependencies: aiohttp: '>=3.3.1' @@ -5079,14 +5094,14 @@ package: urllib3: '>=1.26.0' websocket-client: '>=0.32.0' hash: - md5: 8b0d1b5227ce39053aa69c3ff18417ec - sha256: 45e16e6f7e4105c71c1494ca523b01e676349a25ee1f8114a6c10bbdd8549d50 + md5: 543336c6aa9516cfb29c51d5c162b177 + sha256: 5e01e15e20ee573c99b530633a0d5c71fd515e4ac6d2f5f5f57baece8b915cc3 manager: conda name: docker-py optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/docker-py-6.0.0-pyhd8ed1ab_0.tar.bz2 - version: 6.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/docker-py-6.1.0-pyhd8ed1ab_0.conda + version: 6.1.0 - category: main dependencies: appdirs: '' @@ -5150,14 +5165,14 @@ package: botocore: '>=1.12.36,<2.0a.0' python: '>=3.7' hash: - md5: 900e74d8547fbea3af028937df28ed77 - sha256: 0e459ed32b00e96b62c2ab7e2dba0135c73fd980120fe1a7bd49901f2d50760f + md5: b19a857ac845097e9c823c9f4d35f80e + sha256: 99512bf4f4e297cc7565c94eee8ccc908411f836b341668e2b5d064273e21762 manager: conda name: s3transfer optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/s3transfer-0.6.0-pyhd8ed1ab_0.tar.bz2 - version: 0.6.0 + url: https://conda.anaconda.org/conda-forge/noarch/s3transfer-0.6.1-pyhd8ed1ab_0.conda + version: 0.6.1 - category: main dependencies: alabaster: '>=0.7,<0.8' @@ -5189,7 +5204,7 @@ package: version: 5.1.1 - category: main dependencies: - botocore: 1.29.76 + botocore: 1.29.130 colorama: '>=0.2.5,<0.4.5' docutils: '>=0.10,<0.17' python: '>=3.10,<3.11.0a0' @@ -5198,29 +5213,29 @@ package: rsa: '>=3.1.2,<4.8' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: 8c10a8f0d1fdf0bcaf3e7ddba412dab1 - sha256: 80b95da17548e8ba8e2b3aa292829bc0c0e8edf37f25019b2a1ce97b94bb66f7 + md5: 73d250b9c5952035e0583db4a5b91895 + sha256: af8a05666cfc0376c503d9ec9bbec05205d699226c12d598a719325c249fb688 manager: conda name: awscli optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.76-py310hff52083_0.conda - version: 1.27.76 + url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.130-py310hff52083_0.conda + version: 1.27.130 - category: main dependencies: - botocore: '>=1.29.76,<1.30.0' + botocore: '>=1.29.130,<1.30.0' jmespath: '>=0.7.1,<2.0.0' python: '>=3.7' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: 5246a3712ba575428ab1e4cf8c5e289d - sha256: bd52736dcdcf9a46d7fd93baea1140b0185af3880bdfef78b9d62fdf586b65fc + md5: b41eaaaf0f77cce83052e5cfa841251c + sha256: 29588b211401de9dc34318bbb00eeb946e6961afb74f1097ec1ed24948300116 manager: conda name: boto3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.76-pyhd8ed1ab_0.conda - version: 1.26.76 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.130-pyhd8ed1ab_0.conda + version: 1.26.130 - category: main dependencies: cachecontrol: 0.12.11 pyhd8ed1ab_1 @@ -5281,21 +5296,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/msal_extensions-1.0.0-pyhd8ed1ab_0.tar.bz2 version: 1.0.0 -- category: main - dependencies: - aiobotocore: '>=2.5.0,<2.5.1' - aiohttp: '' - fsspec: 2023.4.0 - python: '>=3.8' - hash: - md5: 4a0d69ed950a71844181abc227bc0bfc - sha256: cf9a0c2dabbd465b6ec4d1387babea78a39886d71444efc63061f62e79af8ec2 - manager: conda - name: s3fs - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/s3fs-2023.4.0-pyhd8ed1ab_0.conda - version: 2023.4.0 - category: main dependencies: livereload: '>=2.3.0' @@ -5361,14 +5361,14 @@ package: python: '' typing_extensions: '' hash: - md5: cfd95e43a27c0af1a206f7557d7f132e - sha256: 02570a9062717ec9b3293199ab8e8983c92f2320f5f8066ef541929a1166d9f1 + md5: da03042814034e36f0938058b7b218fb + sha256: d18385d39e4af117b99cbd931cb68cbd33582949a837ae4e6453964ecc64d80a manager: conda name: boto3-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.117-pyhd8ed1ab_0.conda - version: 1.26.117 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.130-pyhd8ed1ab_0.conda + version: 1.26.130 - category: main dependencies: cachecontrol-with-filecache: '>=0.12.9' @@ -5409,28 +5409,42 @@ package: python: '>=3.6' typing-extensions: '' hash: - md5: cfc72b1b83d1b8503b1071455534ebac - sha256: 1df5aa62e1fc8d498a37f30723d15a1626dc9b686603e79b4b44ba6c95f8f659 + md5: adb30ee4ef9f506b62f732c8a78d250b + sha256: 281ba68f92f05626bf37df32156abbf62e6ed963ab40b2205277a066391cc06f manager: conda name: mypy-boto3-s3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.116-pyhd8ed1ab_0.conda - version: 1.26.116 + url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.127-pyhd8ed1ab_0.conda + version: 1.26.127 - category: main dependencies: boto3: '' python: '>=3.6' typing-extensions: '' hash: - md5: 93e899cf501d962cfd1b251a45416825 - sha256: ef57856f4313eac453b53a119cedf121bd16fc98c64beaee8e3309959673daea + md5: 35a0dc87b7ff0abd9e3012bea164f439 + sha256: 706be4a8f070af47d29e18315c3053977315c1c58479ecfebb2443d3a72edf87 manager: conda name: mypy_boto3_ec2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.106-pyhd8ed1ab_0.conda - version: 1.26.106 + url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.129-pyhd8ed1ab_0.conda + version: 1.26.129 +- category: main + dependencies: + boto3: '' + fsspec: '>=0.6.0' + python: '>=3.5' + hash: + md5: ead328eb12f01d88706126ba061e7a69 + sha256: 7a4cb574ff7edf773e5e4c396733dcb08ffcfd6e4f8b27e5b84b35fd4666ef5b + manager: conda + name: s3fs + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/s3fs-0.4.2-py_0.tar.bz2 + version: 0.4.2 - category: main dependencies: docutils: <0.19 @@ -5495,14 +5509,14 @@ package: werkzeug: '>=0.5,!=2.2.0,!=2.2.1' xmltodict: '' hash: - md5: c4172149b03b032cd60cc79f1484a1dd - sha256: 5891a5ce23d274406bda81e202ddc303d30a3355c01c7d9ae461fc5313247e9d + md5: 89dfb6776dcc992a100cafd0c612b7fb + sha256: f5de61e07e99798c0f73947fae9f947a4eb7aeff7adc04e78b9a9a3ef2ddc780 manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.7-pyhd8ed1ab_2.conda - version: 4.1.7 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.9-pyhd8ed1ab_0.conda + version: 4.1.9 - category: main dependencies: {} hash: diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index a09f4359..ccb3e8c5 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -114,11 +114,12 @@ if run_step "1"; then # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154 CONDA_REQS=$CYDIR/conda-reqs CONDA_LOCK_REQS=$CONDA_REQS/conda-lock-reqs + # must match with the file generated by generate-conda-lockfile.sh LOCKFILE=$CONDA_LOCK_REQS/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml if [ "$USE_UNPINNED_DEPS" = true ]; then # auto-gen the lockfile - conda-lock -f $CONDA_REQS/chipyard.yaml -f $CONDA_REQS/$TOOLCHAIN_TYPE.yaml --lockfile $LOCKFILE + $CYDIR/scripts/generate-conda-lockfile.sh $TOOLCHAIN_TYPE fi # use conda-lock to create env diff --git a/scripts/generate-conda-lockfile.sh b/scripts/generate-conda-lockfile.sh new file mode 100755 index 00000000..7a5d72fa --- /dev/null +++ b/scripts/generate-conda-lockfile.sh @@ -0,0 +1,31 @@ +#!/usr/bin/env bash + +set -ex + +CUR_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) + +TOOLCHAIN_TYPE="riscv-tools" + +# getopts does not support long options, and is inflexible +while [ "$1" != "" ]; +do + case $1 in + riscv-tools | esp-tools) + TOOLCHAIN_TYPE=$1 ;; + * ) + error "invalid option $1" + usage 1 ;; + esac + shift +done + +REQS_DIR="$CUR_DIR/../conda-reqs" +if [ ! -d "$REQS_DIR" ]; then + echo "$REQS_DIR does not exist, make sure you're calling this script from chipyard/" + exit 1 +fi + +# note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154 +LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml + +conda-lock -f "$REQS_DIR/chipyard.yaml" -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" -p linux-64 --lockfile $LOCKFILE From 1f687af9975fe854d7831f607b922490f4d8454b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 May 2023 14:12:09 -0700 Subject: [PATCH 161/184] Generate all lockfiles at once --- scripts/build-setup.sh | 4 ++-- scripts/generate-conda-lockfile.sh | 31 ----------------------------- scripts/generate-conda-lockfiles.sh | 18 +++++++++++++++++ 3 files changed, 20 insertions(+), 33 deletions(-) delete mode 100755 scripts/generate-conda-lockfile.sh create mode 100755 scripts/generate-conda-lockfiles.sh diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index ccb3e8c5..02e1fd81 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -118,8 +118,8 @@ if run_step "1"; then LOCKFILE=$CONDA_LOCK_REQS/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml if [ "$USE_UNPINNED_DEPS" = true ]; then - # auto-gen the lockfile - $CYDIR/scripts/generate-conda-lockfile.sh $TOOLCHAIN_TYPE + # auto-gen the lockfiles + $CYDIR/scripts/generate-conda-lockfiles.sh fi # use conda-lock to create env diff --git a/scripts/generate-conda-lockfile.sh b/scripts/generate-conda-lockfile.sh deleted file mode 100755 index 7a5d72fa..00000000 --- a/scripts/generate-conda-lockfile.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env bash - -set -ex - -CUR_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) - -TOOLCHAIN_TYPE="riscv-tools" - -# getopts does not support long options, and is inflexible -while [ "$1" != "" ]; -do - case $1 in - riscv-tools | esp-tools) - TOOLCHAIN_TYPE=$1 ;; - * ) - error "invalid option $1" - usage 1 ;; - esac - shift -done - -REQS_DIR="$CUR_DIR/../conda-reqs" -if [ ! -d "$REQS_DIR" ]; then - echo "$REQS_DIR does not exist, make sure you're calling this script from chipyard/" - exit 1 -fi - -# note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154 -LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml - -conda-lock -f "$REQS_DIR/chipyard.yaml" -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" -p linux-64 --lockfile $LOCKFILE diff --git a/scripts/generate-conda-lockfiles.sh b/scripts/generate-conda-lockfiles.sh new file mode 100755 index 00000000..f2e81106 --- /dev/null +++ b/scripts/generate-conda-lockfiles.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash + +set -ex + +CUR_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) + +REQS_DIR="$CUR_DIR/../conda-reqs" +if [ ! -d "$REQS_DIR" ]; then + echo "$REQS_DIR does not exist, make sure you're calling this script from chipyard/" + exit 1 +fi + +for TOOLCHAIN_TYPE in riscv-tools esp-tools; do + # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154 + LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml + + conda-lock -f "$REQS_DIR/chipyard.yaml" -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" -p linux-64 --lockfile $LOCKFILE +done From d8bbc71821786ca129000e18d44aaa07ec15e668 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 9 May 2023 17:20:12 -0700 Subject: [PATCH 162/184] Always generate objdump for run-binary-debug targets --- common.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/common.mk b/common.mk index cf2236ff..a8e2e9a8 100644 --- a/common.mk +++ b/common.mk @@ -309,6 +309,9 @@ run-binary-fast: $(SIM_PREREQ) check-binary | $(output_dir) # run simulator with as much debug info as possible run-binary-debug: $(SIM_DEBUG_PREREQ) check-binary | $(output_dir) +ifneq (none,$(BINARY)) + riscv64-unknown-elf-objdump -D $(BINARY) > $(sim_out_name).dump +endif (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast From ff3b66e2f2a0658e5e4fed8c89017c63174eb2f2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 9 May 2023 17:38:46 -0700 Subject: [PATCH 163/184] Makefile should error if BINARY is set incorrectly --- common.mk | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/common.mk b/common.mk index a8e2e9a8..2dce97ec 100644 --- a/common.mk +++ b/common.mk @@ -292,6 +292,11 @@ check-binary: ifeq (,$(BINARY)) $(error BINARY variable is not set. Set it to the simulation binary) endif +ifneq (none,$(BINARY)) +ifeq ("$(wildcard $(BINARY))","") + $(error BINARY=$(BINARY) not found) +endif +endif # allow you to override sim prereq ifeq (,$(BREAK_SIM_PREREQ)) From 94f83e319a830678646225ac186dc24c2d281f7b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 9 May 2023 17:39:48 -0700 Subject: [PATCH 164/184] Fix bugs in spike-cosim --- .../src/main/resources/csrc/cospike.cc | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index f531e61f..6cf8910b 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -284,9 +284,9 @@ extern "C" void cospike_cosim(long long int cycle, printf("%d exception %lx\n", cycle, cause); if (valid) { printf("%d Cosim: %lx", cycle, iaddr); - if (has_wdata) { - printf(" s: %lx", wdata); - } + // if (has_wdata) { + // printf(" s: %lx", wdata); + // } printf("\n"); } if (valid || raise_interrupt || raise_exception) { @@ -299,7 +299,7 @@ extern "C" void cospike_cosim(long long int cycle, } } - if (valid) { + if (valid && !raise_exception) { if (s_pc != iaddr) { printf("%d PC mismatch spike %llx != DUT %llx\n", cycle, s_pc, iaddr); if (unlikely(cospike_debug)) { @@ -373,12 +373,13 @@ extern "C" void cospike_cosim(long long int cycle, bool csr_read = (insn & 0x7f) == 0x73; if (csr_read) printf("CSR read %lx\n", csr_addr); - if (csr_read && ((csr_addr == 0xf13) || // mimpid - (csr_addr == 0xf12) || // marchid - (csr_addr == 0xf11) || // mvendorid - (csr_addr == 0xb00) || // mcycle - (csr_addr == 0xb02) || // minstret - (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr + if (csr_read && ((csr_addr == 0xf13) || // mimpid + (csr_addr == 0xf12) || // marchid + (csr_addr == 0xf11) || // mvendorid + (csr_addr == 0xb00) || // mcycle + (csr_addr == 0xb02) || // minstret + (csr_addr >= 0x7a0 && csr_addr <= 0x7aa) || // debug trigger registers + (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr )) { printf("CSR override\n"); s->XPR.write(rd, wdata); From 8be6d4260674fcae8e900ed5d9ecfcd279583923 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 9 May 2023 20:15:38 -0700 Subject: [PATCH 165/184] Bump DRAMSim2 to avoid verbose log files --- tools/DRAMSim2 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/DRAMSim2 b/tools/DRAMSim2 index 49ec2f32..44322e2f 160000 --- a/tools/DRAMSim2 +++ b/tools/DRAMSim2 @@ -1 +1 @@ -Subproject commit 49ec2f32eea6687a36acdb8d1d636d992d9e8daa +Subproject commit 44322e2f935d7dac83b7adf8dd270b41a54c6acb From abe8a7fb8b29f06f970feaa2019b98db7ee0109a Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Wed, 10 May 2023 11:31:05 -0700 Subject: [PATCH 166/184] remove extra newlines --- generators/firechip/src/main/scala/TargetConfigs.scala | 3 --- 1 file changed, 3 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index fd2eba86..621a152c 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -194,7 +194,6 @@ class FireSimRocketMMIOOnly1GiBDRAMConfig extends Config( new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++ new FireSimRocketMMIOOnlyConfig) - class FireSimRocket4GiBDRAMConfig extends Config( new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ new FireSimRocketConfig) @@ -203,8 +202,6 @@ class FireSimRocketMMIOOnly4GiBDRAMConfig extends Config( new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ new FireSimRocketMMIOOnlyConfig) - - class FireSimQuadRocketConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ From c148f1daf1620bc7329713bb230d6ec8a4fa12ed Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 8 May 2023 14:36:36 -0700 Subject: [PATCH 167/184] Make BootAddrReg optional --- generators/chipyard/src/main/scala/DigitalTop.scala | 2 +- generators/chipyard/src/main/scala/config/AbstractConfig.scala | 2 ++ generators/testchipip | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index d20bade9..6711eac7 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin - with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register + with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 3cce1e00..ceee4c0f 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -46,6 +46,8 @@ class AbstractConfig extends Config( // This should get replaced with a PLL-like config instead new chipyard.clocking.WithDividerOnlyClockGenerator ++ + new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address + new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity diff --git a/generators/testchipip b/generators/testchipip index 363b6835..ebf61569 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 363b683552e66e1e8f6552f25a4ee24b532e7faf +Subproject commit ebf61569c5a65ff46ac3ee77fcc3a8404441ab9d From ab6479641e06d2f1590b967c08fb220b77b9659d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 10 May 2023 15:16:16 -0700 Subject: [PATCH 168/184] Fix verilator vcd/fsdt file extension --- sims/verilator/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 9e22821d..11b80331 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -96,8 +96,7 @@ USE_FST ?= 0 TRACING_OPTS := $(if $(filter $(USE_FST),0),\ --trace,--trace-fst --trace-threads 1) # TODO: consider renaming +vcdfile in TestDriver.v to +waveformfile (or similar) -WAVEFORM_FLAG := +vcdfile=$(sim_out_name).$(if $(filter $(USE_FST),0),\ - vcd,fst) +WAVEFORM_FLAG := +vcdfile=$(sim_out_name).$(if $(filter $(USE_FST),0),vcd,fst) #---------------------------------------------------------------------------------------- # verilation configuration/optimization From a0569208a52dcb04180b3d2481ba252f41d538bd Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 10 May 2023 15:49:59 -0700 Subject: [PATCH 169/184] Fix VCS waveforms --- sims/vcs/vcs.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/vcs/vcs.mk b/sims/vcs/vcs.mk index 31784ad9..f816f102 100644 --- a/sims/vcs/vcs.mk +++ b/sims/vcs/vcs.mk @@ -57,5 +57,5 @@ VCS_PREPROC_DEFINES = \ +define+VCS ifndef USE_VPD -PREPROC_DEFINES += +define+FSDB +VCS_PREPROC_DEFINES += +define+FSDB endif From 71fe1ad8585ec0b5031c4acce093e2cd0e80e00f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 10 May 2023 14:30:58 -0700 Subject: [PATCH 170/184] Switch RTL sims to absolute clock-generators --- .../chipyard/src/main/scala/IOBinders.scala | 1 - .../main/scala/clocking/ClockBinders.scala | 84 +++++++++---------- .../clocking/DividerOnlyClockGenerator.scala | 54 ------------ .../main/scala/config/AbstractConfig.scala | 7 +- .../main/scala/config/TracegenConfigs.scala | 3 +- .../main/scala/harness/HarnessClocks.scala | 38 --------- .../src/main/scala/harness/TestHarness.scala | 2 +- 7 files changed, 46 insertions(+), 143 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 1e234144..8dd0020e 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -25,7 +25,6 @@ import barstools.iocell.chisel._ import testchipip._ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.{CanHaveMasterTLMemPort} -import chipyard.clocking.{HasChipyardPRCI, DividerOnlyClockGenerator} import scala.reflect.{ClassTag} diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 5a02277c..c91f5cb4 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -13,53 +13,11 @@ class ClockWithFreq(val freqMHz: Double) extends Bundle { val clock = Clock() } -// This uses synthesizable clock divisors to approximate frequency rations -// between the requested clocks. This is currently the defualt clock generator "model", -// as it can be used in VCS/Xcelium/Verilator/FireSim -class WithDividerOnlyClockGenerator extends OverrideLazyIOBinder({ - (system: HasChipyardPRCI) => { - // Connect the implicit clock - implicit val p = GetSystemParameters(system) - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - InModuleBody { - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - } - - // Connect all other requested clocks - val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) - val dividerOnlyClockGen = LazyModule(new DividerOnlyClockGenerator("buildTopClockGenerator")) - - (system.allClockGroupsNode - := dividerOnlyClockGen.node - := referenceClockSource) - - InModuleBody { - val clock_wire = Wire(Input(new ClockWithFreq(dividerOnlyClockGen.module.referenceFreq))) - val reset_wire = Wire(Input(AsyncReset())) - val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) - val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) - - referenceClockSource.out.unzip._1.map { o => - o.clock := clock_wire.clock - o.reset := reset_wire - } - - (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) - } - } -}) - // This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate // the requested clocks. This also adds TileLink ClockDivider and ClockSelector // blocks, which allow memory-mapped control of clock division, and clock muxing // between the FakePLL and the slow off-chip clock -// Note: This will not simulate properly with verilator or firesim +// Note: This will not simulate properly with firesim class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { // Connect the implicit clock @@ -100,7 +58,7 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ pllCtrlSink := pllCtrl.ctrlNode InModuleBody { - val clock_wire = Wire(Input(new ClockWithFreq(80))) + val clock_wire = Wire(Input(new ClockWithFreq(100))) val reset_wire = Wire(Input(AsyncReset())) val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) @@ -125,3 +83,41 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ } } }) + +// This passes all clocks through to the TestHarness +class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ + (system: HasChipyardPRCI) => { + // Connect the implicit clock + implicit val p = GetSystemParameters(system) + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) + system.connectImplicitClockSinkNode(implicitClockSinkNode) + InModuleBody { + val implicit_clock = implicitClockSinkNode.in.head._1.clock + val implicit_reset = implicitClockSinkNode.in.head._1.reset + system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { + l.clock := implicit_clock + l.reset := implicit_reset + }} + } + + // This aggregate node should do nothing + val clockGroupAggNode = ClockGroupAggregateNode("fake") + val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + system.allClockGroupsNode :*= clockGroupAggNode := clockGroupsSourceNode + + InModuleBody { + val reset_io = IO(Input(AsyncReset())) + val clock_ios = clockGroupAggNode.out.map { case (bundle, edge) => + val freqs = edge.sink.members.map(_.take.map(_.freqMHz)).flatten + require(freqs.distinct.size == 1) + val clock_io = IO(Input(new ClockWithFreq(freqs.head))).suggestName(s"clock_${edge.sink.name}") + bundle.member.data.foreach { b => + b.clock := clock_io.clock + b.reset := reset_io + } + clock_io + } + ((clock_ios :+ reset_io), Nil) + } + } +}) diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala index 121cca24..0458c621 100644 --- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala +++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala @@ -92,57 +92,3 @@ class SimplePllConfiguration( def referenceSinkParams(): ClockSinkParameters = sinkDividerMap.find(_._2 == 1).get._1 } -case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValName) - extends MixedNexusNode(ClockImp, ClockGroupImp)( - dFn = { _ => ClockGroupSourceParameters() }, - uFn = { u => - require(u.size == 1) - require(!u.head.members.contains(None), - "All output clocks in group must set their take parameters. Use a ClockGroupDealiaser") - ClockSinkParameters( - name = Some(s"${pllName}_reference_input"), - take = Some(ClockParameters(new SimplePllConfiguration(pllName, u.head.members).referenceFreqMHz))) } - ) - -/** - * Generates a digital-divider-only PLL model that verilator can simulate. - * Inspects all take-specified frequencies in the output ClockGroup, calculates a - * fast reference clock (roughly LCM(requested frequencies)) which is passed up the - * diplomatic graph, and then generates dividers for each unique requested - * frequency. - * - * Output resets are not synchronized to generated clocks and should be - * synchronized by the user in a manner they see fit. - * - */ - -class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule { - val node = DividerOnlyClockGeneratorNode(pllName) - - lazy val module = new Impl - class Impl extends LazyRawModuleImp(this) { - require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator") - val (refClock, ClockEdgeParameters(_, refSinkParam, _, _)) = node.in.head - val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head - - val referenceFreq = refSinkParam.take.get.freqMHz - val pllConfig = new SimplePllConfiguration(pllName, outSinkParams.members) - pllConfig.emitSummaries() - - val dividedClocks = mutable.HashMap[Int, Clock]() - def instantiateDivider(div: Int): Clock = { - val divider = Module(new ClockDividerN(div)) - divider.suggestName(s"ClockDivideBy${div}") - divider.io.clk_in := refClock.clock - dividedClocks(div) = divider.io.clk_out - divider.io.clk_out - } - - for (((sinkBName, sinkB), sinkP) <- outClocks.member.elements.zip(outSinkParams.members)) { - val div = pllConfig.sinkDividerMap(sinkP) - sinkB.clock := dividedClocks.getOrElse(div, instantiateDivider(div)) - // Reset handling and synchronization is expected to be handled by a downstream node - sinkB.reset := refClock.reset - } - } -} diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index ceee4c0f..02ab9b5a 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -23,6 +23,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present new chipyard.harness.WithCustomBootPinPlusArg ++ new chipyard.harness.WithClockAndResetFromHarness ++ + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through @@ -41,10 +42,8 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithExtInterruptIOCells ++ new chipyard.iobinders.WithCustomBootPin ++ - // Default behavior is to use a divider-only clock-generator - // This works in VCS, Verilator, and FireSim/ - // This should get replaced with a PLL-like config instead - new chipyard.clocking.WithDividerOnlyClockGenerator ++ + // By default, punch out IOs to the Harness + new chipyard.clocking.WithPassthroughClockGenerator ++ new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index b92b2f46..3c2b9a0c 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -4,12 +4,13 @@ import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.rocket.{DCacheParams} class AbstractTraceGenConfig extends Config( + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ new chipyard.harness.WithBlackBoxSimMem ++ new chipyard.harness.WithTraceGenSuccess ++ new chipyard.harness.WithClockAndResetFromHarness ++ new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ - new chipyard.clocking.WithDividerOnlyClockGenerator ++ + new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ diff --git a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala index 513ca38c..22c7417e 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala @@ -36,44 +36,6 @@ trait HarnessClockInstantiator { def instantiateHarnessClocks(refClock: ClockBundle): Unit } -// The DividerOnlyHarnessClockInstantiator uses synthesizable clock divisors -// to approximate frequency ratios between the requested clocks -class DividerOnlyHarnessClockInstantiator extends HarnessClockInstantiator { - // connect all clock wires specified to a divider only PLL - def instantiateHarnessClocks(refClock: ClockBundle): Unit = { - val sinks = _clockMap.map({ case (name, (freq, bundle)) => - ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name)) - }).toSeq - - val pllConfig = new SimplePllConfiguration("harnessDividerOnlyClockGenerator", sinks) - pllConfig.emitSummaries() - - val dividedClocks = LinkedHashMap[Int, Clock]() - def instantiateDivider(div: Int): Clock = { - val divider = Module(new ClockDividerN(div)) - divider.suggestName(s"ClockDivideBy${div}") - divider.io.clk_in := refClock.clock - dividedClocks(div) = divider.io.clk_out - divider.io.clk_out - } - - // connect wires to clock source - for (sinkParams <- sinks) { - // bypass the reference freq. (don't create a divider + reset sync) - val (divClock, divReset) = if (sinkParams.take.get.freqMHz != pllConfig.referenceFreqMHz) { - val div = pllConfig.sinkDividerMap(sinkParams) - val divClock = dividedClocks.getOrElse(div, instantiateDivider(div)) - (divClock, ResetCatchAndSync(divClock, refClock.reset.asBool)) - } else { - (refClock.clock, refClock.reset) - } - - _clockMap(sinkParams.name.get)._2.clock := divClock - _clockMap(sinkParams.name.get)._2.reset := divReset - } - } -} - // The AbsoluteFreqHarnessClockInstantiator uses a Verilog blackbox to // provide the precise requested frequency. // This ClockInstantiator cannot be synthesized, run in Verilator, or run in FireSim diff --git a/generators/chipyard/src/main/scala/harness/TestHarness.scala b/generators/chipyard/src/main/scala/harness/TestHarness.scala index 22bcc167..cb8cfe47 100644 --- a/generators/chipyard/src/main/scala/harness/TestHarness.scala +++ b/generators/chipyard/src/main/scala/harness/TestHarness.scala @@ -19,7 +19,7 @@ import chipyard.{ChipTop} case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) => new ChipTop()(p)) case object DefaultClockFrequencyKey extends Field[Double](100.0) // MHz -case object HarnessClockInstantiatorKey extends Field[() => HarnessClockInstantiator](() => new DividerOnlyHarnessClockInstantiator) +case object HarnessClockInstantiatorKey extends Field[() => HarnessClockInstantiator]() trait HasHarnessSignalReferences { implicit val p: Parameters From 5c8ea080eed8e710d8043704df60173067821558 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 10 May 2023 16:52:42 -0700 Subject: [PATCH 171/184] Switch to our own ClockSourceAtFreq that is verilator-compatible --- .../main/scala/harness/HarnessClocks.scala | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala index 22c7417e..585062a5 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala @@ -1,7 +1,8 @@ package chipyard.harness import chisel3._ - +import chisel3.util._ +import chisel3.experimental.DoubleParam import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} import freechips.rocketchip.diplomacy.{LazyModule} import org.chipsalliance.cde.config.{Field, Parameters, Config} @@ -36,6 +37,26 @@ trait HarnessClockInstantiator { def instantiateHarnessClocks(refClock: ClockBundle): Unit } +class ClockSourceAtFreqMHz(val freqMHz: Double) extends BlackBox(Map( + "PERIOD" -> DoubleParam(freqMHz) +)) with HasBlackBoxInline { + val io = IO(new ClockSourceIO) + + setInline("ClockSourceAtFreqMHz.v", + s""" + |module ClockSourceAtFreqMHz #(parameter PERIOD="") ( + | input power, + | input gate, + | output clk); + | + | reg clk_i = 1'b0; + | always #(PERIOD/2.0) clk_i = ~clk_i & (power & ~gate); + | assign clk = clk_i; + |endmodule + |""".stripMargin) +} + + // The AbsoluteFreqHarnessClockInstantiator uses a Verilog blackbox to // provide the precise requested frequency. // This ClockInstantiator cannot be synthesized, run in Verilator, or run in FireSim @@ -48,7 +69,7 @@ class AbsoluteFreqHarnessClockInstantiator extends HarnessClockInstantiator { // connect wires to clock source for (sinkParams <- sinks) { - val source = Module(new ClockSourceAtFreq(sinkParams.take.get.freqMHz)) + val source = Module(new ClockSourceAtFreqMHz(sinkParams.take.get.freqMHz)) source.io.power := true.B source.io.gate := false.B From bcd273986fde0e979cd8c551d64df33587b56199 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 10 May 2023 21:18:52 -0700 Subject: [PATCH 172/184] Fix ClockSourceAtFreqMHz period calc --- generators/chipyard/src/main/scala/harness/HarnessClocks.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala index 585062a5..d505c66b 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala @@ -38,7 +38,7 @@ trait HarnessClockInstantiator { } class ClockSourceAtFreqMHz(val freqMHz: Double) extends BlackBox(Map( - "PERIOD" -> DoubleParam(freqMHz) + "PERIOD" -> DoubleParam(1000/freqMHz) )) with HasBlackBoxInline { val io = IO(new ClockSourceIO) From 1916d3e4fc5e794af6b293dfe1eca91314b6f09d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 10 May 2023 21:30:59 -0700 Subject: [PATCH 173/184] Add timeunit to ClockSourceAtFreqMHz --- generators/chipyard/src/main/scala/harness/HarnessClocks.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala index d505c66b..9f0d41b5 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala @@ -48,7 +48,7 @@ class ClockSourceAtFreqMHz(val freqMHz: Double) extends BlackBox(Map( | input power, | input gate, | output clk); - | + | timeunit 1ns/1ps; | reg clk_i = 1'b0; | always #(PERIOD/2.0) clk_i = ~clk_i & (power & ~gate); | assign clk = clk_i; From ffc4d1f66218a78869ef3eb34de90b43f879c530 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 10 May 2023 21:37:19 -0700 Subject: [PATCH 174/184] Use getClass.getSimpleName for ClockSourceAtFreqMHz blackbox inline --- .../chipyard/src/main/scala/harness/HarnessClocks.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala index 9f0d41b5..beded345 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala @@ -41,10 +41,11 @@ class ClockSourceAtFreqMHz(val freqMHz: Double) extends BlackBox(Map( "PERIOD" -> DoubleParam(1000/freqMHz) )) with HasBlackBoxInline { val io = IO(new ClockSourceIO) + val moduleName = this.getClass.getSimpleName - setInline("ClockSourceAtFreqMHz.v", + setInline(s"$moduleName.v", s""" - |module ClockSourceAtFreqMHz #(parameter PERIOD="") ( + |module $moduleName #(parameter PERIOD="") ( | input power, | input gate, | output clk); From 624785376a584dc293e1d717e2ea38f72b209b42 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 10 May 2023 23:34:29 -0700 Subject: [PATCH 175/184] Fix PassThroughClockGenerator to handle multiclock properly --- .../main/scala/clocking/ClockBinders.scala | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index c91f5cb4..5a53051e 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -103,20 +103,20 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ // This aggregate node should do nothing val clockGroupAggNode = ClockGroupAggregateNode("fake") val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - system.allClockGroupsNode :*= clockGroupAggNode := clockGroupsSourceNode + system.allClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode InModuleBody { val reset_io = IO(Input(AsyncReset())) - val clock_ios = clockGroupAggNode.out.map { case (bundle, edge) => - val freqs = edge.sink.members.map(_.take.map(_.freqMHz)).flatten - require(freqs.distinct.size == 1) - val clock_io = IO(Input(new ClockWithFreq(freqs.head))).suggestName(s"clock_${edge.sink.name}") - bundle.member.data.foreach { b => - b.clock := clock_io.clock - b.reset := reset_io - } + require(clockGroupAggNode.out.size == 1) + val (bundle, edge) = clockGroupAggNode.out(0) + + val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) => + val freq = m.take.get.freqMHz + val clock_io = IO(Input(new ClockWithFreq(freq))).suggestName(s"clock_${m.name.get}") + b.clock := clock_io.clock + b.reset := reset_io clock_io - } + }.toSeq ((clock_ios :+ reset_io), Nil) } } From f4bf1b0a2836fa631c7deb19f0747d23b29b738b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 11 May 2023 00:52:57 -0700 Subject: [PATCH 176/184] Fix multiclockrocketconfig --- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 965a81fc..ea00f8b2 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -86,7 +86,7 @@ class MbusScratchpadRocketConfig extends Config( // DOC include end: mbusscratchpadrocket class MulticlockRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Frequency specifications new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 From 4dd017d181524d54acd9b8e5e6e6f98b8325d0af Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 11 May 2023 00:53:52 -0700 Subject: [PATCH 177/184] Fix WithClockAndResetFromHarness to actually request harness clocks --- .../chipyard/src/main/scala/harness/HarnessBinders.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index e4e8391b..d78318f8 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -393,8 +393,8 @@ class WithClockAndResetFromHarness extends OverrideHarnessBinder({ implicit val p = GetSystemParameters(system) ports.map ({ case c: ClockWithFreq => { - th.setRefClockFreq(c.freqMHz) - c.clock := th.buildtopClock + val clock = th.harnessClockInstantiator.requestClockBundle(s"clock_${c.freqMHz}MHz", c.freqMHz * (1000 * 1000)) + c.clock := clock.clock } case r: AsyncReset => r := th.buildtopReset.asAsyncReset }) From 1a6b34696eb74524485d7aee33fa2a3c50c9c199 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 11 May 2023 10:43:16 -0700 Subject: [PATCH 178/184] Set a more realistic 500 MHz uncore clock: --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 02ab9b5a..6d243d5f 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -56,8 +56,8 @@ class AbstractConfig extends Config( new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) - new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus - new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus + new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus + new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ // Default 2 memory channels new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port From a9bc11accbb71d3907c10d033228c6001a03ea43 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 11 May 2023 10:45:31 -0700 Subject: [PATCH 179/184] Update comments on harnessbinders in AbstractConfig --- .../main/scala/config/AbstractConfig.scala | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 6d243d5f..4b179fd0 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -12,18 +12,18 @@ import org.chipsalliance.cde.config.{Config} class AbstractConfig extends Config( // The HarnessBinders control generation of hardware in the TestHarness - new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present - new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled - new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM - new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled - new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present - new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled - new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled - new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present - new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present - new chipyard.harness.WithCustomBootPinPlusArg ++ - new chipyard.harness.WithClockAndResetFromHarness ++ - new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ + new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present + new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled + new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM + new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled + new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present + new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled + new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled + new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present + new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present + new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present + new chipyard.harness.WithClockAndResetFromHarness ++ // all Clock/Reset I/O in ChipTop should be driven by harnessClockInstantiator + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through From 64ad77bbcf829cfd6b4f8bea23eaea5b460762c9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 11 May 2023 13:03:47 -0700 Subject: [PATCH 180/184] Make FPGA flows use the harnessClockInstantiator --- fpga/src/main/scala/arty/Configs.scala | 2 +- fpga/src/main/scala/arty/TestHarness.scala | 6 ++++++ fpga/src/main/scala/arty100t/Configs.scala | 1 + fpga/src/main/scala/arty100t/Harness.scala | 6 ++++++ fpga/src/main/scala/vc707/Configs.scala | 1 + fpga/src/main/scala/vc707/TestHarness.scala | 6 ++++++ fpga/src/main/scala/vcu118/Configs.scala | 1 + fpga/src/main/scala/vcu118/TestHarness.scala | 6 ++++++ .../src/main/scala/harness/HarnessClocks.scala | 15 +++++++++++++++ 9 files changed, 43 insertions(+), 1 deletion(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 10af0223..ad8b9a32 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -21,7 +21,7 @@ class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ new WithDebugResetPassthrough ++ - + new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.config.WithDTSTimebase(32768) ++ new testchipip.WithNoSerialTL ) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index d368ec55..6f7c5ea5 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -3,6 +3,7 @@ package chipyard.fpga.arty import chisel3._ import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import org.chipsalliance.cde.config.{Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} @@ -36,4 +37,9 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell lazyDut match { case d: HasIOBinders => ApplyHarnessBinders(this, d.lazySystem, d.portMap) } + + val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + implicitHarnessClockBundle.clock := buildtopClock + implicitHarnessClockBundle.reset := buildtopReset + harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle) } diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index 673b8b58..16683141 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -22,6 +22,7 @@ class WithNoDesignKey extends Config((site, here, up) => { }) class WithArty100TTweaks extends Config( + new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new WithArty100TUARTTSI ++ new WithArty100TDDRTL ++ new WithNoDesignKey ++ diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index dd76589a..d4e7ebc9 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -5,6 +5,7 @@ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset} +import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.shell._ @@ -87,6 +88,11 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell chiptop match { case d: HasIOBinders => ApplyHarnessBinders(this, d.lazySystem, d.portMap) } + + val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + implicitHarnessClockBundle.clock := buildtopClock + implicitHarnessClockBundle.reset := buildtopReset + harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle) } } diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index c0298610..70bd7073 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -40,6 +40,7 @@ class WithSystemModifications extends Config((site, here, up) => { class WithVC707Tweaks extends Config ( // harness binders + new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new WithVC707UARTHarnessBinder ++ new WithVC707SPISDCardHarnessBinder ++ new WithVC707DDRMemHarnessBinder ++ diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 8e0bd5bf..553cf06e 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -6,6 +6,7 @@ import chisel3.experimental.{IO} import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode} +import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay} import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} @@ -132,4 +133,9 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul // check the top-level reference clock is equal to the default // non-exhaustive since you need all ChipTop clocks to equal the default require(getRefClockFreq == p(DefaultClockFrequencyKey)) + + val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + implicitHarnessClockBundle.clock := buildtopClock + implicitHarnessClockBundle.reset := buildtopReset + harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle) } diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index ea6df6c3..0d82e107 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -42,6 +42,7 @@ class WithSystemModifications extends Config((site, here, up) => { // DOC include start: AbstractVCU118 and Rocket class WithVCU118Tweaks extends Config( // harness binders + new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new WithUART ++ new WithSPISDCard ++ new WithDDRMem ++ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 9e7529dd..5ca3d4a0 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -6,6 +6,7 @@ import chisel3.experimental.{IO} import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode} +import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} @@ -134,4 +135,9 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod // check the top-level reference clock is equal to the default // non-exhaustive since you need all ChipTop clocks to equal the default require(getRefClockFreq == p(DefaultClockFrequencyKey)) + + val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + implicitHarnessClockBundle.clock := buildtopClock + implicitHarnessClockBundle.reset := buildtopReset + harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle) } diff --git a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala index beded345..4fb7ea9e 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala @@ -83,3 +83,18 @@ class AbsoluteFreqHarnessClockInstantiator extends HarnessClockInstantiator { class WithAbsoluteFreqHarnessClockInstantiator extends Config((site, here, up) => { case HarnessClockInstantiatorKey => () => new AbsoluteFreqHarnessClockInstantiator }) + +class AllClocksFromHarnessClockInstantiator extends HarnessClockInstantiator { + def instantiateHarnessClocks(refClock: ClockBundle): Unit = { + val freqs = _clockMap.map(_._2._1) + freqs.tail.foreach(t => require(t == freqs.head, s"Mismatching clocks $t != ${freqs.head}")) + for ((_, (_, bundle)) <- _clockMap) { + bundle.clock := refClock.clock + bundle.reset := refClock.reset + } + } +} + +class WithAllClocksFromHarnessClockInstantiator extends Config((site, here, up) => { + case HarnessClockInstantiatorKey => () => new AllClocksFromHarnessClockInstantiator +}) From d673c61b8bfdb310b27f19187896452eea3059ce Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 11 May 2023 17:19:17 -0700 Subject: [PATCH 181/184] Switch SpikeTile CI to SpikeConfig --- .github/scripts/defaults.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 176d20d5..d2362dbd 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -47,7 +47,7 @@ mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig" mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig" mapping["chipyard-dmiboom"]=" CONFIG=dmiMediumBoomCosimConfig" -mapping["chipyard-spike"]=" CONFIG=SpikeFastUARTConfig EXTRA_SIM_FLAGS='+spike-ipc=10'" +mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'" mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" mapping["chipyard-cva6"]=" CONFIG=CVA6Config" From 059f88a80dbb46ffe685ee6654a325e43c94a927 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 17 May 2023 11:20:46 -0700 Subject: [PATCH 182/184] Add embench build support --- .gitmodules | 3 +++ software/embench/build.sh | 23 +++++++++++++++++++++++ software/embench/embench-iot | 1 + 3 files changed, 27 insertions(+) create mode 100755 software/embench/build.sh create mode 160000 software/embench/embench-iot diff --git a/.gitmodules b/.gitmodules index f5055865..5a3eb6fc 100644 --- a/.gitmodules +++ b/.gitmodules @@ -121,3 +121,6 @@ [submodule "tools/cde"] path = tools/cde url = https://github.com/chipsalliance/cde.git +[submodule "software/embench/embench-iot"] + path = software/embench/embench-iot + url = https://github.com/embench/embench-iot.git diff --git a/software/embench/build.sh b/software/embench/build.sh new file mode 100755 index 00000000..2d22166c --- /dev/null +++ b/software/embench/build.sh @@ -0,0 +1,23 @@ +#!/usr/bin/env bash + +set -e + +echo "Building embench-iot for riscv64" +BUILDDIR=$(pwd)/build +mkdir -p $BUILDDIR + +cd embench-iot +# use the riscv32 target, but use riscv64 compiler +./build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cc riscv64-unknown-elf-gcc --cflags="-c -O2 -ffunction-sections -mabi=lp64d -specs=htif_nano.specs" --ldflags="-Wl,-gc-sections -specs=htif_nano.specs" --user-libs="-lm" --clean -v + +echo "Copying binaries to $BUILDDIR" +bmarks=("aha-mont64" "crc32" "cubic" "edn" "huffbench" + "matmult-int" "minver" "nbody" "nettle-aes" + "nettle-sha256" "nsichneu" "picojpeg" + "qrduino" "sglib-combined" "slre" "st" + "statemate" "ud" "wikisort") +for bmark in "${bmarks[@]}" +do + cp bd/src/$bmark/$bmark $BUILDDIR/ +done + diff --git a/software/embench/embench-iot b/software/embench/embench-iot new file mode 160000 index 00000000..d9b30cdf --- /dev/null +++ b/software/embench/embench-iot @@ -0,0 +1 @@ +Subproject commit d9b30cdf805133bef9db5f7ecf84ae1ce8124291 From c2ca66ac4d2f534f522fcae47aff95a7422b4287 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 17 May 2023 15:21:11 -0700 Subject: [PATCH 183/184] Support ssip interrupts in spike-cosim --- generators/chipyard/src/main/resources/csrc/cospike.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index 6cf8910b..dd60d078 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -266,12 +266,15 @@ extern "C" void cospike_cosim(long long int cycle, #endif uint64_t s_pc = s->pc; uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF; + bool ssip_interrupt = interrupt_cause == 0x1; bool msip_interrupt = interrupt_cause == 0x3; bool debug_interrupt = interrupt_cause == 0xe; if (raise_interrupt) { printf("%d interrupt %lx\n", cycle, cause); - if (msip_interrupt) { + if (ssip_interrupt) { + // do nothing + } else if (msip_interrupt) { s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP); } else if (debug_interrupt) { return; From abf2af16b4ef6a7d9fffeff0d50d1601489a5ae1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 17 May 2023 16:06:24 -0700 Subject: [PATCH 184/184] Cospike should always include zicntr --- generators/chipyard/src/main/resources/csrc/cospike.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index dd60d078..b30806ce 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -63,7 +63,8 @@ extern "C" void cospike_set_sysinfo(char* isa, int pmpregions, ) { if (!info) { info = new system_info_t; - info->isa = std::string(isa); + // technically the targets aren't zicntr compliant, but they implement the zicntr registers + info->isa = std::string(isa) + "_zicntr"; info->pmpregions = pmpregions; info->mem0_base = mem0_base; info->mem0_size = mem0_size;