From dd358f45ab7e3e85aab41cbef04710a056a89b3e Mon Sep 17 00:00:00 2001
From: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Date: Mon, 19 Oct 2020 11:29:25 -0700
Subject: [PATCH] UART Working... Bumped to newer fpga-shells

---
 fpga/Makefile                                 |  2 +-
 fpga/fpga-shells                              |  2 +-
 .../main/scala/vcu118/bringup/Configs.scala   | 24 ++++++++++++-------
 .../scala/vcu118/bringup/CustomOverlays.scala |  3 +--
 .../scala/vcu118/bringup/TestHarness.scala    |  3 +++
 generators/sifive-blocks                      |  2 +-
 6 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/fpga/Makefile b/fpga/Makefile
index e6bc426a..b984431c 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -29,7 +29,7 @@ TB                := none # unused
 TOP               := ChipTop
 
 # setup the board to use
-BOARD ?= arty
+BOARD ?= vcu118
 
 .PHONY: default
 default: $(mcs)
diff --git a/fpga/fpga-shells b/fpga/fpga-shells
index e8e7f8a3..89a5efec 160000
--- a/fpga/fpga-shells
+++ b/fpga/fpga-shells
@@ -1 +1 @@
-Subproject commit e8e7f8a321ebde213ebc79db06422278d9aa477f
+Subproject commit 89a5efec011ebc21b9455923501df70783161cb8
diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala
index f0dd91cc..8db731ed 100644
--- a/fpga/src/main/scala/vcu118/bringup/Configs.scala
+++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala
@@ -1,6 +1,7 @@
 package chipyard.fpga.vcu118.bringup
 
 import math.min
+import sys.process._
 
 import freechips.rocketchip.config._
 import freechips.rocketchip.subsystem._
@@ -54,6 +55,7 @@ class WithBringupPeripherals extends Config((site, here, up) => {
 })
 
 class SmallModifications extends Config((site, here, up) => {
+  case DebugModuleKey => None // disable debug module
   case SystemBusKey => up(SystemBusKey).copy(
     errorDevice = Some(DevNullParams(
       Seq(AddressSet(0x3000, 0xfff)),
@@ -61,18 +63,24 @@ class SmallModifications extends Config((site, here, up) => {
       maxTransfer=128,
       region = RegionType.TRACKED)))
   case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency =
-    Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt),
+    Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt))
+  case ControlBusKey => up(ControlBusKey, site).copy(
     errorDevice = None)
   case DTSTimebase => BigInt(1000000)
-  case JtagDTMKey => new JtagDTMConfig(
-    idcodeVersion = 2,      // 1 was legacy (FE310-G000, Acai).
-    idcodePartNum = 0x000,  // Decided to simplify.
-    idcodeManufId = 0x489,  // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses.
-    debugIdleCycles = 5)    // Reasonable guess for synchronization
 })
 
+class WithBootROM extends Config((site, here, up) => {
+  case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
+    // invoke makefile for sdboot
+    val freqMHz = site(DUTFrequencyKey).toInt * 1000000
+    val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin"
+    require (make.! == 0, "Failed to build bootrom")
+    p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
+  }
+})
 
 class FakeBringupConfig extends Config(
+  new SmallModifications ++
   new WithBringupUART ++
   new WithBringupSPI ++
   new WithBringupI2C ++
@@ -80,14 +88,14 @@ class FakeBringupConfig extends Config(
   new WithBringupDDR ++
   new WithUARTIOPassthrough ++
   new WithSPIIOPassthrough ++
-  //new WithMMCSPIDTS ++
   new WithI2CIOPassthrough ++
   new WithGPIOIOPassthrough ++
   new WithTLIOPassthrough ++
   new WithBringupPeripherals ++
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new chipyard.config.WithNoSubsystemDrivenClocks ++
   new chipyard.config.WithPeripheryBusFrequencyAsDefault ++
-  new chipyard.config.WithBootROM ++
+  new WithBootROM ++ // use local bootrom
   new chipyard.config.WithL2TLBs(1024) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
   new freechips.rocketchip.subsystem.WithNoMMIOPort ++
diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
index 2c438a34..fdbbb919 100644
--- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
@@ -138,8 +138,7 @@ class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name:
     packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, io) => {
       shell.xdc.addPackagePin(io, pin)
       shell.xdc.addIOStandard(io, iostd)
-      // TODO: no drive strength found
-      //if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") }
+      if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") }
     } }
   } }
 }
diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
index 28e42e3c..28c3ae14 100644
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -181,6 +181,9 @@ class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) exte
   val dutReset = harnessReset
   val success = false.B
 
+  childClock := harnessClock
+  childReset := harnessReset
+
   // harness binders are non-lazy
   _outer.topDesign match { case d: HasTestHarnessFunctions =>
     d.harnessFunctions.foreach(_(this))
diff --git a/generators/sifive-blocks b/generators/sifive-blocks
index ed9f63f9..c160544e 160000
--- a/generators/sifive-blocks
+++ b/generators/sifive-blocks
@@ -1 +1 @@
-Subproject commit ed9f63f9f5b9209c9e5ef2adfd063d6669691d79
+Subproject commit c160544e74db4f33d51f23c8a41c07a1ec16b7b7