add more to docs | 1st spelling pass | more links | proper formatting

docs/Generators/BOOM.rst

@@ -1,10 +1,11 @@
 Berkeley Out-of-Order Machine (BOOM)
 ==============================================
 
-The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. 
+The `Berkeley Out-of-Order Machine (BOOM) <https://boom-core.org/>`__ is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language.
+It serves as a drop-in replacement to the Rocket core given by Rocket Chip.
+BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 outoforder processors.
+Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”).
+Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit.
+However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”).
 
-BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 outoforder processors. Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”).
-
-Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”).
-
-Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages <https://docs.boom-core.org/en/latest/index.html>__`.
+Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages <https://docs.boom-core.org/>__`.

docs/Generators/Hwacha.rst

@@ -0,0 +1,8 @@
+Hwacha
+====================================
+
+The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption.
+Inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures Scale and Maven, we are bringing back elegant, performant, and energy-efficient aspects of vector processing to modern data-parallel architectures.
+We propose a new vector-fetch architectural paradigm, which focuses on the following aspects for higher performance, better energy efficiency, and lower complexity.
+
+For more information, please visit the `Hwacha website <http://hwacha.org/>`__.

docs/Generators/Rocket.rst

@@ -1,3 +1,12 @@
 Rocket
 ====================================
-TODO: Basic rocket introduction
+
+`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar core generator that is supported by `SiFive <https://www.sifive.com/>`__.
+It supports the open source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
+It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.
+Branch prediction is configurable and provided by a branch target buffer (BTB), branch history table (BHT), and a return address stack (RAS).
+For floating-point,  Rocket  makes  use  of  Berkeley’s  Chisel  implementations  of  floating-point  units.
+Rocket also supports the RISC-V machine, supervisor, and user privilege levels.
+A number of parameters are exposed, including the optional support of some ISA extensions (M, A, F, D), the number of floating-point pipeline stages, and the cache and TLB sizes.
+
+For more information, please refer to the `GitHub repository <https://github.com/freechipsproject/rocket-chip>`__, `technical report <https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html>`__ or to `this Chisel Community Conference video <https://youtu.be/Eko86PGEoDY>`__.

docs/Generators/index.rst

@@ -1,8 +1,11 @@
 Generators
 ============================
-Generator can be thought of as generalized RTL designs, written using a mix of meta-programming and standard RTL.
-This type of meta-programming is enabled by the Chisel hardware description framework embedded in Scala. 
-A standard RTL design is esentially a degenerate form of a generator. However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. The following pages introduce the generators integrated with the ReBAR framework.
+
+Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL.
+This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Chisel`).
+A standard RTL design is essentially just a single instance of a design coming from a generator.
+However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways.
+The following pages introduce the generators integrated with the REBAR framework.
 
 .. toctree::
    :maxdepth: 2
@@ -10,4 +13,5 @@ A standard RTL design is esentially a degenerate form of a generator. However, b
 
    Rocket
    BOOM
+   Hwacha