From 0a4466da1ed291684859ba4765e45d498b469859 Mon Sep 17 00:00:00 2001 From: Kevin Anderson Date: Fri, 17 Mar 2023 20:37:04 -0700 Subject: [PATCH 1/4] Add name to IOCell definition --- .../barstools/iocell/chisel/IOCell.scala | 35 +++++++++++++++---- 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/src/main/scala/barstools/iocell/chisel/IOCell.scala b/src/main/scala/barstools/iocell/chisel/IOCell.scala index 6d444936..993f8b39 100644 --- a/src/main/scala/barstools/iocell/chisel/IOCell.scala +++ b/src/main/scala/barstools/iocell/chisel/IOCell.scala @@ -59,7 +59,9 @@ class DigitalInIOCellBundle extends Bundle { val ie = Input(Bool()) } -trait IOCell extends BaseModule +trait IOCell extends BaseModule { + var i_name : String +} trait AnalogIOCell extends IOCell { val io: AnalogIOCellBundle @@ -87,15 +89,19 @@ abstract class GenericIOCell extends BlackBox with HasBlackBoxResource { class GenericAnalogIOCell extends GenericIOCell with AnalogIOCell { val io = IO(new AnalogIOCellBundle) + var i_name = "NoNameAssigned" } class GenericDigitalGPIOCell extends GenericIOCell with DigitalGPIOCell { val io = IO(new DigitalGPIOCellBundle) + var i_name = "NoNameAssigned" } class GenericDigitalInIOCell extends GenericIOCell with DigitalInIOCell { val io = IO(new DigitalInIOCellBundle) + var i_name = "NoNameAssigned" } class GenericDigitalOutIOCell extends GenericIOCell with DigitalOutIOCell { val io = IO(new DigitalOutIOCellBundle) + var i_name = "NoNameAssigned" } trait IOCellTypeParams { @@ -112,8 +118,12 @@ case class GenericIOCellParams() extends IOCellTypeParams { def output() = Module(new GenericDigitalOutIOCell) } -object IOCell { +trait IOCellName { + var i_name : String +} +object IOCell extends IOCellName{ + var i_name = "NoNameAssigned" /** From within a RawModule or MultiIOModule context, generate new module IOs from a given * signal and return the new IO and a Seq containing all generated IO cells. * @param coreSignal The signal onto which to add IO cells @@ -156,10 +166,14 @@ object IOCell { )(coreSignal: T, padSignal: T ): Seq[IOCell] = { + print("Suggested names: " + name + " ") DataMirror.directionOf(coreSignal) match { case ActualDirection.Input => { val iocell = typeParams.input() - name.foreach(n => iocell.suggestName(n)) + name.foreach(n => { + iocell.suggestName(n) + iocell.i_name = n + }) coreSignal := castFromBool(iocell.io.i) iocell.io.ie := true.B iocell.io.pad := castToBool(padSignal) @@ -167,7 +181,10 @@ object IOCell { } case ActualDirection.Output => { val iocell = typeParams.output() - name.foreach(n => iocell.suggestName(n)) + name.foreach(n => { + iocell.suggestName(n) + iocell.i_name = n + }) iocell.io.o := castToBool(coreSignal) iocell.io.oe := true.B padSignal := castFromBool(iocell.io.pad) @@ -215,7 +232,10 @@ object IOCell { // Note that we are relying on chisel deterministically naming this in the index order (which it does) // This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals // An alternative solution would be to suggestName(n + "_" + i) - name.foreach(n => iocell.suggestName(n)) + name.foreach(n => { + iocell.suggestName(n) + iocell.i_name = n + }) iocell.io.pad := sig iocell.io.ie := true.B iocell @@ -230,7 +250,10 @@ object IOCell { // Note that we are relying on chisel deterministically naming this in the index order (which it does) // This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals // An alternative solution would be to suggestName(n + "_" + i) - name.foreach(n => iocell.suggestName(n)) + name.foreach(n => { + iocell.suggestName(n) + iocell.i_name = n + }) iocell.io.o := sig iocell.io.oe := true.B iocell From 0df6e34813cbf511a9fdff68a0daf895ad50b6a2 Mon Sep 17 00:00:00 2001 From: Kevin Anderson Date: Fri, 17 Mar 2023 20:48:35 -0700 Subject: [PATCH 2/4] formatting fix --- src/main/scala/barstools/iocell/chisel/IOCell.scala | 12 +++++++----- .../tapeout/transforms/stage/TapeoutStage.scala | 2 +- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/main/scala/barstools/iocell/chisel/IOCell.scala b/src/main/scala/barstools/iocell/chisel/IOCell.scala index 993f8b39..65e1c73d 100644 --- a/src/main/scala/barstools/iocell/chisel/IOCell.scala +++ b/src/main/scala/barstools/iocell/chisel/IOCell.scala @@ -60,7 +60,7 @@ class DigitalInIOCellBundle extends Bundle { } trait IOCell extends BaseModule { - var i_name : String + var i_name: String } trait AnalogIOCell extends IOCell { @@ -119,11 +119,11 @@ case class GenericIOCellParams() extends IOCellTypeParams { } trait IOCellName { - var i_name : String + var i_name: String } -object IOCell extends IOCellName{ - var i_name = "NoNameAssigned" +object IOCell extends IOCellName { + /** From within a RawModule or MultiIOModule context, generate new module IOs from a given * signal and return the new IO and a Seq containing all generated IO cells. * @param coreSignal The signal onto which to add IO cells @@ -144,6 +144,8 @@ object IOCell extends IOCellName{ (padSignal, iocells) } + var i_name = "NoNameAssigned" + /** Connect two identical signals together by adding IO cells between them and return a Seq * containing all generated IO cells. * @param coreSignal The core-side (internal) signal onto which to connect/add IO cells @@ -253,7 +255,7 @@ object IOCell extends IOCellName{ name.foreach(n => { iocell.suggestName(n) iocell.i_name = n - }) + }) iocell.io.o := sig iocell.io.oe := true.B iocell diff --git a/src/main/scala/barstools/tapeout/transforms/stage/TapeoutStage.scala b/src/main/scala/barstools/tapeout/transforms/stage/TapeoutStage.scala index 14b57e3e..cdae1bfd 100644 --- a/src/main/scala/barstools/tapeout/transforms/stage/TapeoutStage.scala +++ b/src/main/scala/barstools/tapeout/transforms/stage/TapeoutStage.scala @@ -33,7 +33,7 @@ trait TapeoutCli { parser.note("Tapeout specific options") Seq( - OutAnnoAnnotation, + OutAnnoAnnotation ).foreach(_.addOptions(parser)) } From cc4f8419378272d2c309aa29da197d9cadfce629 Mon Sep 17 00:00:00 2001 From: Kevin Anderson Date: Sat, 18 Mar 2023 13:04:39 -0700 Subject: [PATCH 3/4] Code improvement; define IOCell name as Option and place in trait to reduce code modifications --- .../barstools/iocell/chisel/IOCell.scala | 35 +++++++++---------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/src/main/scala/barstools/iocell/chisel/IOCell.scala b/src/main/scala/barstools/iocell/chisel/IOCell.scala index 65e1c73d..5bbfb119 100644 --- a/src/main/scala/barstools/iocell/chisel/IOCell.scala +++ b/src/main/scala/barstools/iocell/chisel/IOCell.scala @@ -60,7 +60,17 @@ class DigitalInIOCellBundle extends Bundle { } trait IOCell extends BaseModule { - var i_name: String + var iocell_name : Option[String] = None + + /** Set IOCell name + * @param s Proposed name for the IOCell + * + * @return An inherited IOCell with given the proposed name + */ + def suggestName(s: String) : this.type = { + iocell_name = Some(s) + super.suggestName(s) + } } trait AnalogIOCell extends IOCell { @@ -89,19 +99,15 @@ abstract class GenericIOCell extends BlackBox with HasBlackBoxResource { class GenericAnalogIOCell extends GenericIOCell with AnalogIOCell { val io = IO(new AnalogIOCellBundle) - var i_name = "NoNameAssigned" } class GenericDigitalGPIOCell extends GenericIOCell with DigitalGPIOCell { val io = IO(new DigitalGPIOCellBundle) - var i_name = "NoNameAssigned" } class GenericDigitalInIOCell extends GenericIOCell with DigitalInIOCell { val io = IO(new DigitalInIOCellBundle) - var i_name = "NoNameAssigned" } class GenericDigitalOutIOCell extends GenericIOCell with DigitalOutIOCell { val io = IO(new DigitalOutIOCellBundle) - var i_name = "NoNameAssigned" } trait IOCellTypeParams { @@ -118,11 +124,9 @@ case class GenericIOCellParams() extends IOCellTypeParams { def output() = Module(new GenericDigitalOutIOCell) } -trait IOCellName { - var i_name: String -} -object IOCell extends IOCellName { + +object IOCell { /** From within a RawModule or MultiIOModule context, generate new module IOs from a given * signal and return the new IO and a Seq containing all generated IO cells. @@ -144,8 +148,6 @@ object IOCell extends IOCellName { (padSignal, iocells) } - var i_name = "NoNameAssigned" - /** Connect two identical signals together by adding IO cells between them and return a Seq * containing all generated IO cells. * @param coreSignal The core-side (internal) signal onto which to connect/add IO cells @@ -168,13 +170,11 @@ object IOCell extends IOCellName { )(coreSignal: T, padSignal: T ): Seq[IOCell] = { - print("Suggested names: " + name + " ") DataMirror.directionOf(coreSignal) match { case ActualDirection.Input => { val iocell = typeParams.input() name.foreach(n => { - iocell.suggestName(n) - iocell.i_name = n + iocell.suggestName(n) }) coreSignal := castFromBool(iocell.io.i) iocell.io.ie := true.B @@ -184,8 +184,7 @@ object IOCell extends IOCellName { case ActualDirection.Output => { val iocell = typeParams.output() name.foreach(n => { - iocell.suggestName(n) - iocell.i_name = n + iocell.suggestName(n) }) iocell.io.o := castToBool(coreSignal) iocell.io.oe := true.B @@ -236,7 +235,6 @@ object IOCell extends IOCellName { // An alternative solution would be to suggestName(n + "_" + i) name.foreach(n => { iocell.suggestName(n) - iocell.i_name = n }) iocell.io.pad := sig iocell.io.ie := true.B @@ -254,8 +252,7 @@ object IOCell extends IOCellName { // An alternative solution would be to suggestName(n + "_" + i) name.foreach(n => { iocell.suggestName(n) - iocell.i_name = n - }) + }) iocell.io.o := sig iocell.io.oe := true.B iocell From 96155c845c2a545bf1aa9d7dfd3b463f8b7efb44 Mon Sep 17 00:00:00 2001 From: Kevin Anderson Date: Sat, 18 Mar 2023 13:09:38 -0700 Subject: [PATCH 4/4] format IOCell.scala --- .../barstools/iocell/chisel/IOCell.scala | 22 +++++++++---------- 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/src/main/scala/barstools/iocell/chisel/IOCell.scala b/src/main/scala/barstools/iocell/chisel/IOCell.scala index 5bbfb119..b90e43ac 100644 --- a/src/main/scala/barstools/iocell/chisel/IOCell.scala +++ b/src/main/scala/barstools/iocell/chisel/IOCell.scala @@ -60,14 +60,14 @@ class DigitalInIOCellBundle extends Bundle { } trait IOCell extends BaseModule { - var iocell_name : Option[String] = None + var iocell_name: Option[String] = None - /** Set IOCell name - * @param s Proposed name for the IOCell - * - * @return An inherited IOCell with given the proposed name - */ - def suggestName(s: String) : this.type = { + /** Set IOCell name + * @param s Proposed name for the IOCell + * + * @return An inherited IOCell with given the proposed name + */ + def suggestName(s: String): this.type = { iocell_name = Some(s) super.suggestName(s) } @@ -124,8 +124,6 @@ case class GenericIOCellParams() extends IOCellTypeParams { def output() = Module(new GenericDigitalOutIOCell) } - - object IOCell { /** From within a RawModule or MultiIOModule context, generate new module IOs from a given @@ -174,7 +172,7 @@ object IOCell { case ActualDirection.Input => { val iocell = typeParams.input() name.foreach(n => { - iocell.suggestName(n) + iocell.suggestName(n) }) coreSignal := castFromBool(iocell.io.i) iocell.io.ie := true.B @@ -184,7 +182,7 @@ object IOCell { case ActualDirection.Output => { val iocell = typeParams.output() name.foreach(n => { - iocell.suggestName(n) + iocell.suggestName(n) }) iocell.io.o := castToBool(coreSignal) iocell.io.oe := true.B @@ -252,7 +250,7 @@ object IOCell { // An alternative solution would be to suggestName(n + "_" + i) name.foreach(n => { iocell.suggestName(n) - }) + }) iocell.io.o := sig iocell.io.oe := true.B iocell