From deab3b11b66119db896aa0c5ae763f56433d836b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 12 Oct 2023 15:37:03 -0700 Subject: [PATCH] Fix UARTAdapter div bits --- generators/chipyard/src/main/scala/harness/HarnessBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 32c31840..0446b783 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -42,7 +42,7 @@ class WithGPIOTiedOff extends HarnessBinder({ // DOC include start: WithUARTAdapter class WithUARTAdapter extends HarnessBinder({ case (th: HasHarnessInstantiators, port: UARTPort) => { - val div = (th.getHarnessBinderClockFreqMHz * 1000000 / port.io.c.initBaudRate.toDouble).toInt + val div = (th.getHarnessBinderClockFreqMHz.toDouble * 1000000 / port.io.c.initBaudRate.toDouble).toInt val uart_sim = Module(new UARTAdapter(port.uartNo, div, false)).suggestName(s"uart_sim_uartno${port.uartNo}") uart_sim.io.uart.txd := port.io.txd port.io.rxd := uart_sim.io.uart.rxd