From 2def0dfea79401b5c55a89ff0dcdf60f5be53fdd Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 7 Mar 2019 14:18:24 -0800 Subject: [PATCH 001/120] change dir structure --- .gitmodules | 6 +++--- Makefrag | 14 +++++++------- build.sbt | 10 +++++----- rocket-chip => generators/rocket-chip | 0 testchipip => generators/testchipip | 0 {verisim => sims/verisim}/.gitignore | 0 {verisim => sims/verisim}/Makefile | 2 +- {verisim => sims/verisim}/Makefrag-verilator | 0 {vsim => sims/vsim}/.gitignore | 0 {vsim => sims/vsim}/Makefile | 2 +- barstools => tools/barstools | 0 11 files changed, 17 insertions(+), 17 deletions(-) rename rocket-chip => generators/rocket-chip (100%) rename testchipip => generators/testchipip (100%) rename {verisim => sims/verisim}/.gitignore (100%) rename {verisim => sims/verisim}/Makefile (99%) rename {verisim => sims/verisim}/Makefrag-verilator (100%) rename {vsim => sims/vsim}/.gitignore (100%) rename {vsim => sims/vsim}/Makefile (98%) rename barstools => tools/barstools (100%) diff --git a/.gitmodules b/.gitmodules index fb609717..1efe8129 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,9 +1,9 @@ [submodule "rocket-chip"] - path = rocket-chip + path = generators/rocket-chip url = https://github.com/ucb-bar/rocket-chip.git [submodule "testchipip"] - path = testchipip + path = generators/testchipip url = https://github.com/ucb-bar/testchipip.git [submodule "barstools"] - path = barstools + path = tools/barstools url = https://github.com/ucb-bar/barstools.git diff --git a/Makefrag b/Makefrag index 7cc4df34..3d90d8c9 100644 --- a/Makefrag +++ b/Makefrag @@ -1,5 +1,5 @@ -ROCKETCHIP_DIR=$(base_dir)/rocket-chip -TESTCHIP_DIR = $(base_dir)/testchipip +ROCKETCHIP_DIR=$(base_dir)/generators/rocket-chip +TESTCHIP_DIR = $(base_dir)/generators/testchipip SCALA_VERSION=2.12.4 SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) @@ -9,7 +9,7 @@ SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null) PACKAGES=rocket-chip testchipip -SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) +SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes" @@ -39,16 +39,16 @@ REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) # This should match whatever the commonSettings version is in build.sbt BARSTOOLS_VER=1.0 -TAPEOUT_JAR=$(base_dir)/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar -MACROCOMPILER_JAR=$(base_dir)/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar +TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar +MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR) MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR) -$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/barstools/tapeout/src/main/scala) +$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala) cd $(base_dir) && $(SBT) "tapeout/assembly" -$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/barstools/mdf/scalalib/src/main/scala) +$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/tools/barstools/mdf/scalalib/src/main/scala) cd $(base_dir) && $(SBT) "barstools-macros/assembly" .PHONY: jars diff --git a/build.sbt b/build.sbt index 553ca61b..2d217ba4 100644 --- a/build.sbt +++ b/build.sbt @@ -19,9 +19,9 @@ lazy val commonSettings = Seq( Resolver.sonatypeRepo("releases"), Resolver.mavenLocal)) -lazy val rocketchip = RootProject(file("rocket-chip")) +lazy val rocketchip = RootProject(file("generators/rocket-chip")) -lazy val testchipip = project.settings(commonSettings) +lazy val testchipip = (project in file("generators/testchipip")).settings(commonSettings) .dependsOn(rocketchip) // Checks for -DROCKET_USE_MAVEN. @@ -39,12 +39,12 @@ def conditionalDependsOn(prj: Project): Project = { lazy val example = conditionalDependsOn(project in file(".")) .settings(commonSettings) -lazy val tapeout = conditionalDependsOn(project in file("./barstools/tapeout/")) +lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) .settings(commonSettings) -lazy val mdf = (project in file("./barstools/mdf/scalalib/")) +lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) -lazy val `barstools-macros` = conditionalDependsOn(project in file("./barstools/macros/")) +lazy val `barstools-macros` = conditionalDependsOn(project in file("./tools/barstools/macros/")) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) .dependsOn(mdf) diff --git a/rocket-chip b/generators/rocket-chip similarity index 100% rename from rocket-chip rename to generators/rocket-chip diff --git a/testchipip b/generators/testchipip similarity index 100% rename from testchipip rename to generators/testchipip diff --git a/verisim/.gitignore b/sims/verisim/.gitignore similarity index 100% rename from verisim/.gitignore rename to sims/verisim/.gitignore diff --git a/verisim/Makefile b/sims/verisim/Makefile similarity index 99% rename from verisim/Makefile rename to sims/verisim/Makefile index dc3a219e..9cab741c 100644 --- a/verisim/Makefile +++ b/sims/verisim/Makefile @@ -1,4 +1,4 @@ -base_dir=$(abspath ..) +base_dir=$(abspath ../..) sim_dir=$(abspath .) PROJECT ?= example diff --git a/verisim/Makefrag-verilator b/sims/verisim/Makefrag-verilator similarity index 100% rename from verisim/Makefrag-verilator rename to sims/verisim/Makefrag-verilator diff --git a/vsim/.gitignore b/sims/vsim/.gitignore similarity index 100% rename from vsim/.gitignore rename to sims/vsim/.gitignore diff --git a/vsim/Makefile b/sims/vsim/Makefile similarity index 98% rename from vsim/Makefile rename to sims/vsim/Makefile index bd8afc29..c0ed1bc1 100644 --- a/vsim/Makefile +++ b/sims/vsim/Makefile @@ -1,4 +1,4 @@ -base_dir=$(abspath ..) +base_dir=$(abspath ../..) sim_dir=$(abspath .) PROJECT ?= example diff --git a/barstools b/tools/barstools similarity index 100% rename from barstools rename to tools/barstools From 2e7791a57d9e1e1c637b1fb88aae32d32e8d95e8 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 7 Mar 2019 16:06:04 -0800 Subject: [PATCH 002/120] add chisel and firrtl submodules --- .gitmodules | 6 ++++++ tools/chisel3 | 1 + tools/firrtl | 1 + 3 files changed, 8 insertions(+) create mode 160000 tools/chisel3 create mode 160000 tools/firrtl diff --git a/.gitmodules b/.gitmodules index 1efe8129..7b062654 100644 --- a/.gitmodules +++ b/.gitmodules @@ -7,3 +7,9 @@ [submodule "barstools"] path = tools/barstools url = https://github.com/ucb-bar/barstools.git +[submodule "tools/chisel3"] + path = tools/chisel3 + url = https://github.com/freechipsproject/chisel3.git +[submodule "tools/firrtl"] + path = tools/firrtl + url = https://github.com/freechipsproject/firrtl diff --git a/tools/chisel3 b/tools/chisel3 new file mode 160000 index 00000000..9a0ce227 --- /dev/null +++ b/tools/chisel3 @@ -0,0 +1 @@ +Subproject commit 9a0ce2272c9d5d0a8bdc90e84269749ce054664d diff --git a/tools/firrtl b/tools/firrtl new file mode 160000 index 00000000..2272044c --- /dev/null +++ b/tools/firrtl @@ -0,0 +1 @@ +Subproject commit 2272044c6ab46b5148c39c124e66e1a8e9073a24 From 4d62a2b215a5f00098a8c4cf3383868bb1507b7d Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 8 Mar 2019 09:51:55 -0800 Subject: [PATCH 003/120] docs placeholder --- docs/index.rst | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 docs/index.rst diff --git a/docs/index.rst b/docs/index.rst new file mode 100644 index 00000000..d8f3db37 --- /dev/null +++ b/docs/index.rst @@ -0,0 +1,61 @@ +.. ReBAR documentation master file, created by + sphinx-quickstart on Thu Apr 26 23:51:51 2018. + You can adapt this file completely to your liking, but it should at least + contain the root `toctree` directive. + +Welcome to ReBAR's documentation! +=================================== + +ReBAR is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. New to ReBAR? Jump to the :ref:`rebar-basics` page for more info. + +.. toctree:: + :maxdepth: 3 + :caption: Getting Started: + :numbered: + + ReBAR-Basics + Initial-Setup/index + Creating-Configuration-Tutorial/index + Adding-An-Accelerator-Tutorial/index + Running-Simulations-Tutorial/index + Building-Chips-Tutorial/index + +.. toctree:: + :maxdepth: 3 + :caption: Generators: + + Generators/Rocketchip/index + Generators/BOOM/index + Generators/Hwacha/index + + +.. toctree:: + :maxdepth: 3 + :caption: Simulation: + + Simulation/Open-Source-Simulators/index + Simulation/Commercial-Simulators/index + Simulation/FPGA-Based-Simulation/index + + + +.. toctree:: + :maxdepth: 3 + :caption: Production: + + Production/VLSI-Physical-Design/index + + +.. toctree:: + :maxdepth: 3 + :caption: Software: + + Software/Toolchains/index + + +Indices and tables +================== + +* :ref:`genindex` +* :ref:`modindex` +* :ref:`search` From 6ccb3defc147f8bf604b981c5eefb5b4c7f9ae22 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 8 Mar 2019 11:08:11 -0800 Subject: [PATCH 004/120] add toolchains --- .gitmodules | 6 ++++++ README.md | 4 ++++ build.sh | 19 +++++++++++++++++++ scripts/build-toolchains.sh | 37 +++++++++++++++++++++++++++++++++++++ toolchains/esp-tools | 1 + toolchains/riscv-tools | 1 + 6 files changed, 68 insertions(+) create mode 100644 build.sh create mode 100755 scripts/build-toolchains.sh create mode 160000 toolchains/esp-tools create mode 160000 toolchains/riscv-tools diff --git a/.gitmodules b/.gitmodules index 7b062654..72203f96 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,3 +13,9 @@ [submodule "tools/firrtl"] path = tools/firrtl url = https://github.com/freechipsproject/firrtl +[submodule "riscv-tools"] + path = toolchains/riscv-tools + url = https://github.com/riscv/riscv-tools.git +[submodule "esp-tools"] + path = toolchains/esp-tools + url = https://github.com/ucb-bar/esp-tools.git diff --git a/README.md b/README.md index 53d1ab70..8f07c855 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,9 @@ # RISC-V Project Template +**THIS BRANCH IS UNDER DEVELOPMENT** +**IT CURRENTLY HAS MANY SUBMODULES** +**PLEASE RUN ./build.sh TO UPDATE SUBMODULES, UNLESS YOU WANT TO SPEND A LONG TIME WAITING FOR SUBMODULE TO CLONE** + This is a starter template for your custom RISC-V project. It will allow you to leverage the Chisel HDL and RocketChip SoC generator to produce a RISC-V SoC with MMIO-mapped peripherals, DMA, and custom accelerators. diff --git a/build.sh b/build.sh new file mode 100644 index 00000000..27005cbb --- /dev/null +++ b/build.sh @@ -0,0 +1,19 @@ +#!/usr/bin/env bash + +# exit script if any command fails +set -e +set -o pipefail + +unamestr=$(uname) +RDIR=$(pwd) + +# ignore riscv-tools for submodule init recursive +# you must do this globally (otherwise riscv-tools deep +# in the submodule tree will get pulled anyway +git config --global submodule.riscv-tools.update none +git config --global submodule.esp-tools.update none +git config --global submodule.experimental-blocks.update none +git submodule update --init --recursive #--jobs 8 +# unignore riscv-tools,catapult-shell2 globally +git config --global --unset submodule.riscv-tools.update +git config --global --unset submodule.experimental-blocks.update diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh new file mode 100755 index 00000000..ddf9b462 --- /dev/null +++ b/scripts/build-toolchains.sh @@ -0,0 +1,37 @@ +#!/usr/bin/env bash + +# exit script if any command fails +set -e +set -o pipefail + +unamestr=$(uname) +RDIR=$(pwd) + +if [ $# -ne 0 ]; then + TOOLCHAIN=$1 + if [ $1 == "riscv" ]; then + TOOLCHAIN="riscv-tools" + elif [ $1 == "hwacha" ]; then + TOOLCHAIN="esp-tools" + fi +else + TOOLCHAIN="riscv-tools" +fi + +INSTALL_DIR="$TOOLCHAIN-install" +mkdir -p "$(pwd)/$INSTALL_DIR" + +RISCV="$(pwd)/$INSTALL_DIR" + +# install risc-v tools +export RISCV="$RISCV" +git submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 +cd "toolchains/$TOOLCHAIN" +export MAKEFLAGS="-j16" +./build.sh +cd $RDIR + +echo "export RISCV=$RISCV" > env.sh +echo "export PATH=$RISCV/bin:$RDIR/$DTCversion:\$PATH" >> env.sh +echo "export LD_LIBRARY_PATH=$RISCV/lib" >> env.sh +echo "Toolchain Build Complete!" diff --git a/toolchains/esp-tools b/toolchains/esp-tools new file mode 160000 index 00000000..f2e562c0 --- /dev/null +++ b/toolchains/esp-tools @@ -0,0 +1 @@ +Subproject commit f2e562c0f9089746c6beb15f04b00fbb48f2e9ae diff --git a/toolchains/riscv-tools b/toolchains/riscv-tools new file mode 160000 index 00000000..962bc098 --- /dev/null +++ b/toolchains/riscv-tools @@ -0,0 +1 @@ +Subproject commit 962bc09873071aa7816d5f805c6e5797a3b5bcf7 From 49ab106b9ed6ee35dbaf77ef118cedcb290e503c Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 8 Mar 2019 11:48:52 -0800 Subject: [PATCH 005/120] docs placeholder --- docs/Makefile | 20 ++++++ docs/conf.py | 180 +++++++++++++++++++++++++++++++++++++++++++++++++ docs/index.rst | 5 +- 3 files changed, 203 insertions(+), 2 deletions(-) create mode 100644 docs/Makefile create mode 100644 docs/conf.py diff --git a/docs/Makefile b/docs/Makefile new file mode 100644 index 00000000..14ce8965 --- /dev/null +++ b/docs/Makefile @@ -0,0 +1,20 @@ +# Minimal makefile for Sphinx documentation +# + +# You can set these variables from the command line. +SPHINXOPTS = +SPHINXBUILD = python -msphinx +SPHINXPROJ = ReBAR +SOURCEDIR = . +BUILDDIR = _build + +# Put it first so that "make" without argument is like "make help". +help: + @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + +.PHONY: help Makefile + +# Catch-all target: route all unknown targets to Sphinx using the new +# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). +%: Makefile + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) \ No newline at end of file diff --git a/docs/conf.py b/docs/conf.py new file mode 100644 index 00000000..6864fc63 --- /dev/null +++ b/docs/conf.py @@ -0,0 +1,180 @@ +# -*- coding: utf-8 -*- +# +# ReBAR documentation build configuration file, created by +# sphinx-quickstart on Fri Mar 8 11:46:38 2019. +# +# This file is execfile()d with the current directory set to its +# containing dir. +# +# Note that not all possible configuration values are present in this +# autogenerated file. +# +# All configuration values have a default; values that are commented out +# serve to show the default. + +# If extensions (or modules to document with autodoc) are in another directory, +# add these directories to sys.path here. If the directory is relative to the +# documentation root, use os.path.abspath to make it absolute, like shown here. +# +# import os +# import sys +# sys.path.insert(0, os.path.abspath('.')) + + +# -- General configuration ------------------------------------------------ + +# If your documentation needs a minimal Sphinx version, state it here. +# +# needs_sphinx = '1.0' + +# Add any Sphinx extension module names here, as strings. They can be +# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom +# ones. +extensions = ['sphinx.ext.autodoc', + 'sphinx.ext.intersphinx', + 'sphinx.ext.todo', + 'sphinx.ext.mathjax', + 'sphinx.ext.ifconfig', + 'sphinx.ext.viewcode', + 'sphinx.ext.githubpages'] + +# Add any paths that contain templates here, relative to this directory. +templates_path = ['_templates'] + +# The suffix(es) of source filenames. +# You can specify multiple suffix as a list of string: +# +# source_suffix = ['.rst', '.md'] +source_suffix = '.rst' + +# The master toctree document. +master_doc = 'index' + +# General information about the project. +project = u'ReBAR' +copyright = u'2019, Berkeley Architecture Research' +author = u'Berkeley Architecture Research' + +# The version info for the project you're documenting, acts as replacement for +# |version| and |release|, also used in various other places throughout the +# built documents. +# +# The short X.Y version. +version = u'0.1' +# The full version, including alpha/beta/rc tags. +release = u'0.1' + +# The language for content autogenerated by Sphinx. Refer to documentation +# for a list of supported languages. +# +# This is also used if you do content translation via gettext catalogs. +# Usually you set "language" from the command line for these cases. +language = None + +# List of patterns, relative to source directory, that match files and +# directories to ignore when looking for source files. +# This patterns also effect to html_static_path and html_extra_path +exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store'] + +# The name of the Pygments (syntax highlighting) style to use. +pygments_style = 'sphinx' + +# If true, `todo` and `todoList` produce output, else they produce nothing. +todo_include_todos = True + + +# -- Options for HTML output ---------------------------------------------- + +# The theme to use for HTML and HTML Help pages. See the documentation for +# a list of builtin themes. +# +html_theme = 'alabaster' + +# Theme options are theme-specific and customize the look and feel of a theme +# further. For a list of options available for each theme, see the +# documentation. +# +# html_theme_options = {} + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +html_static_path = ['_static'] + +# Custom sidebar templates, must be a dictionary that maps document names +# to template names. +# +# This is required for the alabaster theme +# refs: http://alabaster.readthedocs.io/en/latest/installation.html#sidebars +html_sidebars = { + '**': [ + 'about.html', + 'navigation.html', + 'relations.html', # needs 'show_related': True theme option to display + 'searchbox.html', + 'donate.html', + ] +} + + +# -- Options for HTMLHelp output ------------------------------------------ + +# Output file base name for HTML help builder. +htmlhelp_basename = 'ReBARdoc' + + +# -- Options for LaTeX output --------------------------------------------- + +latex_elements = { + # The paper size ('letterpaper' or 'a4paper'). + # + # 'papersize': 'letterpaper', + + # The font size ('10pt', '11pt' or '12pt'). + # + # 'pointsize': '10pt', + + # Additional stuff for the LaTeX preamble. + # + # 'preamble': '', + + # Latex figure (float) alignment + # + # 'figure_align': 'htbp', +} + +# Grouping the document tree into LaTeX files. List of tuples +# (source start file, target name, title, +# author, documentclass [howto, manual, or own class]). +latex_documents = [ + (master_doc, 'ReBAR.tex', u'ReBAR Documentation', + u'Berkeley Architecture Research', 'manual'), +] + + +# -- Options for manual page output --------------------------------------- + +# One entry per manual page. List of tuples +# (source start file, name, description, authors, manual section). +man_pages = [ + (master_doc, 'rebar', u'ReBAR Documentation', + [author], 1) +] + + +# -- Options for Texinfo output ------------------------------------------- + +# Grouping the document tree into Texinfo files. List of tuples +# (source start file, target name, title, author, +# dir menu entry, description, category) +texinfo_documents = [ + (master_doc, 'ReBAR', u'ReBAR Documentation', + author, 'ReBAR', 'One line description of project.', + 'Miscellaneous'), +] + + + + +# Example configuration for intersphinx: refer to the Python standard library. +intersphinx_mapping = {'https://docs.python.org/': None} diff --git a/docs/index.rst b/docs/index.rst index d8f3db37..4afa90d9 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,10 +1,10 @@ .. ReBAR documentation master file, created by - sphinx-quickstart on Thu Apr 26 23:51:51 2018. + sphinx-quickstart on Fri Mar 8 11:46:38 2019. You can adapt this file completely to your liking, but it should at least contain the root `toctree` directive. Welcome to ReBAR's documentation! -=================================== +================================= ReBAR is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. New to ReBAR? Jump to the :ref:`rebar-basics` page for more info. @@ -53,6 +53,7 @@ ReBAR is a a framework for designing and evaluating full-system hardware using a Software/Toolchains/index + Indices and tables ================== From 82273107c1836b87df3695ecb7dc93faa816b338 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Mar 2019 16:23:35 -0800 Subject: [PATCH 006/120] makefile changes/split | add scripts --- .ctags | 13 ++ .ctagsignore | 1 + .gitignore | 9 +- Makefrag | 105 +++++++++------ Makefrag-Variables | 79 ++++++++++++ scripts/gen-tags.sh | 17 +++ sims/verisim/Makefile | 92 +++++++------- ...{Makefrag-verilator => Makefrag-Verilator} | 19 ++- sims/vsim/Makefile | 120 ++++++++++-------- 9 files changed, 317 insertions(+), 138 deletions(-) create mode 100644 .ctags create mode 100644 .ctagsignore create mode 100644 Makefrag-Variables create mode 100755 scripts/gen-tags.sh rename sims/verisim/{Makefrag-verilator => Makefrag-Verilator} (54%) diff --git a/.ctags b/.ctags new file mode 100644 index 00000000..b7d31250 --- /dev/null +++ b/.ctags @@ -0,0 +1,13 @@ +--langdef=scala +--langmap=scala:.scala + +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*class[ \t]+([a-zA-Z0-9_]+)/\4/c,classes/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*object[ \t]+([a-zA-Z0-9_]+)/\4/o,objects/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*((abstract|final|sealed|implicit|lazy)[ \t ]*)*case class[ \t ]+([a-zA-Z0-9_]+)/\6/C,case classes/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*case object[ \t]+([a-zA-Z0-9_]+)/\4/O,case objects/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*trait[ \t]+([a-zA-Z0-9_]+)/\4/t,traits/ +--regex-scala=/^[ \t]*type[ \t]+([a-zA-Z0-9_]+)/\1/T,types/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*(\[[a-z]*\])*|protected)[ \t]*)*def[ \t]+([a-zA-Z0-9_]+)/\4/m,methods/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*val[ \t]+([a-zA-Z0-9_]+)/\3/V,values/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*var[ \t]+([a-zA-Z0-9_]+)/\3/v,variables/ +--regex-scala=/^[ \t]*package[ \t]+([a-zA-Z0-9_.]+)/\1/p,packages/ diff --git a/.ctagsignore b/.ctagsignore new file mode 100644 index 00000000..c910d58a --- /dev/null +++ b/.ctagsignore @@ -0,0 +1 @@ +*/target diff --git a/.gitignore b/.gitignore index f0fb9a39..2efa7a6a 100644 --- a/.gitignore +++ b/.gitignore @@ -3,10 +3,11 @@ bootrom target *.jar *.stamp -/vsim -/verisim/generated-src* -/verisim/simulator-* -/verisim/verilator +/sims/vsim +/sims/verisim simv* *.vcd +*.swp +.idea .DS_Store +tags diff --git a/Makefrag b/Makefrag index 3d90d8c9..591069bf 100644 --- a/Makefrag +++ b/Makefrag @@ -1,50 +1,38 @@ -ROCKETCHIP_DIR=$(base_dir)/generators/rocket-chip -TESTCHIP_DIR = $(base_dir)/generators/testchipip - -SCALA_VERSION=2.12.4 -SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) - -SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION) +######################################################################################### +# set default shell for make +######################################################################################### +SHELL=/bin/bash +######################################################################################### +# variables to get all *.scala files +######################################################################################### lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null) PACKAGES=rocket-chip testchipip SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) +######################################################################################### +# rocket and testchipip classes +######################################################################################### ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes" + +######################################################################################### +# jar creation variables and rules +######################################################################################### FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar +# this should match whatever the commonSettings version is in build.sbt +BARSTOOLS_VER=1.0 +TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar +MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar + $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala) $(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala mkdir -p $(dir $@) cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@ touch $@ -build_dir=$(sim_dir)/generated-src - -CHISEL_ARGS ?= - -long_name=$(PROJECT).$(MODEL).$(CONFIG) - -FIRRTL_FILE ?=$(build_dir)/$(long_name).fir -ANNO_FILE ?=$(build_dir)/$(long_name).anno.json -VERILOG_FILE ?=$(build_dir)/$(long_name).top.v -HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v -SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v -SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf -sim_dotf ?= $(build_dir)/sim_files.f - -REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) - -# This should match whatever the commonSettings version is in build.sbt -BARSTOOLS_VER=1.0 -TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar -MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar - -TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR) -MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR) - $(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala) cd $(base_dir) && $(SBT) "tapeout/assembly" @@ -54,13 +42,32 @@ $(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macr .PHONY: jars jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) +######################################################################################### +# tapeout and macrocompiler commands +######################################################################################### +TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR) +MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR) + +######################################################################################### +# create simulation args file rule +######################################################################################### $(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" +######################################################################################### +# create firrtl file rule and variables +######################################################################################### +CHISEL_ARGS ?= + $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) mkdir -p $(build_dir) cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" +######################################################################################### +# create verilog files rules and variables +######################################################################################### +REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) + $(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir) @@ -71,6 +78,30 @@ $(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR) $(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops +######################################################################################### +# run assembly/benchmarks rules +######################################################################################### +$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% + mkdir -p $(output_dir) + ln -sf $< $@ + +$(output_dir)/%.run: $(output_dir)/% $(sim) + $(sim) +max-cycles=$(timeout_cycles) $< && touch $@ + +$(output_dir)/%.out: $(output_dir)/% $(sim) + $(sim) +verbose +max-cycles=$(timeout_cycles) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + +######################################################################################### +# include build/project specific makefrags made from the generator +######################################################################################### +ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) +-include $(build_dir)/$(long_name).d +endif + +######################################################################################### +# default regression tests variables and rules +# TODO: Remove in favor of each project having its own regression tests? +######################################################################################### regression-tests = \ rv64ud-v-fcvt \ rv64ud-p-fdiv \ @@ -98,12 +129,14 @@ regression-tests = \ rv64um-v-mulh \ rv64si-p-dirty -output_dir=$(sim_dir)/output - -$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% - mkdir -p $(output_dir) - ln -sf $< $@ +.PHONY: run-regression-tests run-regression-tests-fast run-regression-tests-debug +run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) +run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) +run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) +######################################################################################### +# general jar cleanup rule +######################################################################################### .PHONY: clean-scala clean-scala: rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) diff --git a/Makefrag-Variables b/Makefrag-Variables new file mode 100644 index 00000000..18793d3d --- /dev/null +++ b/Makefrag-Variables @@ -0,0 +1,79 @@ +######################################################################################### +# makefile variables shared across multiple makefiles +######################################################################################### + +######################################################################################### +# default variables to invoke the generator +# descriptions: +# PROJECT = the scala package to find the MODEL in +# MODEL = the top level module of the project +# CONFIG = the configuration class to give the parameters for the project +# CFG_PROJECT = the scala package to find the CONFIG class +# TB = TODO +# TOP = TODO +######################################################################################### +PROJECT ?= example +MODEL ?= TestHarness +CONFIG ?= DefaultExampleConfig +CFG_PROJECT ?= $(PROJECT) +TB ?= TestDriver +TOP ?= ExampleTop + +######################################################################################### +# path to rocket-chip and testchipip +######################################################################################### +ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip +TESTCHIP_DIR = $(base_dir)/generators/testchipip + +######################################################################################### +# names of various files needed to compile and run things +######################################################################################### +long_name = $(PROJECT).$(MODEL).$(CONFIG) + +FIRRTL_FILE ?= $(build_dir)/$(long_name).fir +ANNO_FILE ?= $(build_dir)/$(long_name).anno.json +VERILOG_FILE ?= $(build_dir)/$(long_name).top.v +HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v +SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v +SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf +sim_dotf ?= $(build_dir)/sim_files.f + +######################################################################################### +# default sbt launch command +######################################################################################### +SCALA_VERSION=2.12.4 +SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) + +SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION) + +######################################################################################### +# output directory for tests +######################################################################################### +output_dir=$(sim_dir)/output + +######################################################################################### +# build output directory for compilation +######################################################################################### +build_dir=$(sim_dir)/generated-src + +######################################################################################### +# vsrcs needed to run projects +######################################################################################### +rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc + +######################################################################################### +# sources needed to run simulators +######################################################################################### +sim_blackboxes = \ + $(build_dir)/firrtl_black_box_resource_files.f + +sim_vsrcs = \ + $(VERILOG_FILE) \ + $(HARNESS_FILE) \ + $(SMEMS_FILE) + +######################################################################################### +# assembly/benchmark variables +######################################################################################### +timeout_cycles = 10000000 +bmark_timeout_cycles = 100000000 diff --git a/scripts/gen-tags.sh b/scripts/gen-tags.sh new file mode 100755 index 00000000..52df9aa7 --- /dev/null +++ b/scripts/gen-tags.sh @@ -0,0 +1,17 @@ +#!/usr/bin/env bash + +# run this script in the main rebar directory to generate ctags for all relevant repos +# note: this requires exuberant-ctags +# tested with: Exuberant Ctags 5.8 +# instructions: +# cd /path/to/rebar/ +# ./scripts/gen-tags.sh +# +# input: +# * nothing +# +# output: +# * tags file in the directory that this was called in + +# ctags wrapper +ctags -R --exclude=@.ctagsignore --links=no diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 9cab741c..f75fb5f1 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -1,41 +1,43 @@ +######################################################################################### +# verilator makefile +######################################################################################### + +######################################################################################### +# general path variables +######################################################################################### base_dir=$(abspath ../..) sim_dir=$(abspath .) -PROJECT ?= example -MODEL ?= TestHarness -CONFIG ?= DefaultExampleConfig -CFG_PROJECT ?= $(PROJECT) -TB ?= TestDriver -TOP ?= ExampleTop +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/Makefrag-Variables +######################################################################################### +# name of simulator (used to generate *.f arguments file) +######################################################################################### sim_name = verilator -sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG) -sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug +######################################################################################### +# vcs simulator types and rules +######################################################################################### +sim_prefix = simulator +sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG) +sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug +.PHONY: default debug default: $(sim) - debug: $(sim_debug) -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread - +######################################################################################### +# import other necessary rules and variables +######################################################################################### include $(base_dir)/Makefrag -include $(sim_dir)/Makefrag-verilator -ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) --include $(build_dir)/$(long_name).d -endif - -sim_blackboxes = \ - $(build_dir)/firrtl_black_box_resource_files.f - -rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc - -sim_vsrcs = \ - $(VERILOG_FILE) \ - $(HARNESS_FILE) \ - $(SMEMS_FILE) +include $(sim_dir)/Makefrag-Verilator +######################################################################################### +# verilator build paths and file names +######################################################################################### model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug @@ -45,6 +47,11 @@ model_header_debug = $(model_dir_debug)/V$(MODEL).h model_mk = $(model_dir)/V$(MODEL).mk model_mk_debug = $(model_dir_debug)/V$(MODEL).mk +######################################################################################### +# build makefile fragment that builds the verilator sim rules +######################################################################################### +LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread + $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) @@ -53,10 +60,6 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" touch $@ -$(sim): $(model_mk) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk - - $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug @@ -65,25 +68,26 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" touch $@ +######################################################################################### +# invoke make to make verilator sim rules +######################################################################################### +$(sim): $(model_mk) + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk + $(sim_debug): $(model_mk_debug) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk -$(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@ - -$(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) +max-cycles=1000000 $< && touch $@ - +######################################################################################### +# create a vcs vpd rule +######################################################################################### $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - $(sim_debug) -v$@.vcd +max-cycles=1000000 $< - -run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) - -run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) - -run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) + $(sim_debug) -v$@.vcd +max-cycles=$(timeout_cycles) $< +######################################################################################### +# general cleanup rule +######################################################################################### +.PHONY: clean clean: clean-scala - rm -rf generated-src ./simulator-* + rm -rf $(build_dir) $(sim_prefix)-* diff --git a/sims/verisim/Makefrag-verilator b/sims/verisim/Makefrag-Verilator similarity index 54% rename from sims/verisim/Makefrag-verilator rename to sims/verisim/Makefrag-Verilator index f8ea0b4c..3af9b335 100644 --- a/sims/verisim/Makefrag-verilator +++ b/sims/verisim/Makefrag-Verilator @@ -1,7 +1,17 @@ -# Build and install our own Verilator, to work around versionining issues. -VERILATOR_VERSION=3.920 +######################################################################################### +# verilator installation makefrag +######################################################################################### + +######################################################################################### +# verilator version, binary, and path +######################################################################################### +VERILATOR_VERSION=4.008 VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) + +######################################################################################### +# build and install our own verilator to work around versioning issues +######################################################################################### $(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata touch $@ @@ -24,8 +34,11 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz: mkdir -p $(dir $@) wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ -# Run Verilator to produce a fast binary to emulate this circuit. +######################################################################################### +# verilator binary and flags +######################################################################################### VERILATOR := $(INSTALLED_VERILATOR) --cc --exe +CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS VERILATOR_FLAGS := --top-module $(MODEL) \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index c0ed1bc1..451b4602 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -1,84 +1,102 @@ +######################################################################################### +# vcs makefile +######################################################################################### + +######################################################################################### +# general path variables +######################################################################################### base_dir=$(abspath ../..) sim_dir=$(abspath .) -PROJECT ?= example -MODEL ?= TestHarness -CONFIG ?= DefaultExampleConfig -CFG_PROJECT ?= $(PROJECT) -TB ?= TestDriver -TOP ?= ExampleTop +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/Makefrag-Variables +######################################################################################### +# name of simulator (used to generate *.f arguments file) +######################################################################################### sim_name = vcs -simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG) -simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug +######################################################################################### +# vcs simulator types and rules +######################################################################################### +sim_prefix = simv +sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG) +sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug -default: $(simv) - -debug: $(simv_debug) +.PHONY: default debug +default: $(sim) +debug: $(sim_debug) +######################################################################################### +# import other necessary rules and variables +######################################################################################### include $(base_dir)/Makefrag -ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) --include $(build_dir)/$(long_name).d -endif - -sim_blackboxes = \ - $(build_dir)/firrtl_black_box_resource_files.f - -rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc - -sim_vsrcs = \ - $(VERILOG_FILE) \ - $(HARNESS_FILE) \ - $(SMEMS_FILE) +######################################################################################### +# vcs binary and arguments +######################################################################################### VCS = vcs -full64 -VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \ - +rad +v2k +vcs+lic+wait \ - +vc+list -CC "-I$(VCS_HOME)/include" \ +VCS_CC_OPTS = \ + -CC "-I$(VCS_HOME)/include" \ -CC "-I$(RISCV)/include" \ -CC "-std=c++11" \ -CC "-Wl,-rpath,$(RISCV)/lib" \ - -f $(sim_blackboxes) -f $(sim_dotf) \ - $(RISCV)/lib/libfesvr.so \ + $(RISCV)/lib/libfesvr.so + +VCS_NONCC_OPTS = \ + +lint=all,noVCDE,noONGS,noUI \ + -error=PCWM-L \ + -timescale=1ns/10ps \ + -quiet \ + +rad \ + +v2k \ + +vcs+lic+wait \ + +vc+list \ + -f $(sim_blackboxes) \ + -f $(sim_dotf) \ -sverilog \ - +incdir+$(generated_dir) \ - +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \ + +incdir+$(build_dir) \ + +define+CLOCK_PERIOD=1.0 \ + $(sim_vsrcs) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE_MEM_INIT \ +define+RANDOMIZE_REG_INIT \ +define+RANDOMIZE_GARBAGE_ASSIGN \ +define+RANDOMIZE_INVALID_ASSIGN \ - +libext+.v \ + +libext+.v +VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) + +######################################################################################### +# helper rule to just make verilog files +######################################################################################### +.PHONY: verilog verilog: $(sim_vsrcs) -$(simv): $(sim_vsrcs) $(sim_dotf) +######################################################################################### +# vcs simulator rules +######################################################################################### +$(sim): $(sim_vsrcs) $(sim_dotf) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(simv_debug) : $(sim_vsrcs) $(sim_dotf) +$(sim_debug) : $(sim_vsrcs) $(sim_dotf) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp -$(output_dir)/%.out: $(output_dir)/% $(simv) - $(simv) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@ - -$(output_dir)/%.run: $(output_dir)/% $(simv) - $(simv) +max-cycles=1000000 $< && touch $@ - -$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug) - $(simv_debug) +vcdplusfile=$@ +max-cycles=1000000 $< - -run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) - -run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) - -run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) - -clean: - rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h +######################################################################################### +# create a vcs vpd rule +######################################################################################### +$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) + $(sim_debug) +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $< +######################################################################################### +# general cleanup rule +######################################################################################### .PHONY: clean +clean: clean-scala + rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h From 2c246af1108ad46d25ab10d385ebf90d6cdec702 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Mar 2019 16:47:27 -0800 Subject: [PATCH 007/120] rename makefiles | move verilog rule to common.mk --- Makefrag => common.mk | 6 ++++ sims/verisim/Makefile | 6 ++-- sims/verisim/Makefrag-Verilator | 47 ------------------------------ sims/vsim/Makefile | 10 ++----- Makefrag-Variables => variables.mk | 6 ++-- 5 files changed, 14 insertions(+), 61 deletions(-) rename Makefrag => common.mk (96%) delete mode 100644 sims/verisim/Makefrag-Verilator rename Makefrag-Variables => variables.mk (93%) diff --git a/Makefrag b/common.mk similarity index 96% rename from Makefrag rename to common.mk index 591069bf..dd1cbd8e 100644 --- a/Makefrag +++ b/common.mk @@ -78,6 +78,12 @@ $(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR) $(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops +######################################################################################### +# helper rule to just make verilog files +######################################################################################### +.PHONY: verilog +verilog: $(sim_vsrcs) + ######################################################################################### # run assembly/benchmarks rules ######################################################################################### diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index f75fb5f1..8049bab9 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -11,7 +11,7 @@ sim_dir=$(abspath .) ######################################################################################### # include shared variables ######################################################################################### -include $(base_dir)/Makefrag-Variables +include $(base_dir)/variables.mk ######################################################################################### # name of simulator (used to generate *.f arguments file) @@ -32,8 +32,8 @@ debug: $(sim_debug) ######################################################################################### # import other necessary rules and variables ######################################################################################### -include $(base_dir)/Makefrag -include $(sim_dir)/Makefrag-Verilator +include $(base_dir)/common.mk +include $(sim_dir)/verilator.mk ######################################################################################### # verilator build paths and file names diff --git a/sims/verisim/Makefrag-Verilator b/sims/verisim/Makefrag-Verilator deleted file mode 100644 index 3af9b335..00000000 --- a/sims/verisim/Makefrag-Verilator +++ /dev/null @@ -1,47 +0,0 @@ -######################################################################################### -# verilator installation makefrag -######################################################################################### - -######################################################################################### -# verilator version, binary, and path -######################################################################################### -VERILATOR_VERSION=4.008 -VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) -INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) - -######################################################################################### -# build and install our own verilator to work around versioning issues -######################################################################################### -$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator - $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata - touch $@ - -$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile - $(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin - touch $@ - -$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure - mkdir -p $(dir $@) - cd $(dir $@) && ./configure --prefix=$(abspath verilator/install) - -$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz - rm -rf $(dir $@) - mkdir -p $(dir $@) - cat $^ | tar -xz --strip-components=1 -C $(dir $@) - touch $@ - -verilator/verilator-$(VERILATOR_VERSION).tar.gz: - mkdir -p $(dir $@) - wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ - -######################################################################################### -# verilator binary and flags -######################################################################################### -VERILATOR := $(INSTALLED_VERILATOR) --cc --exe -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS -VERILATOR_FLAGS := --top-module $(MODEL) \ - +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ - --output-split 20000 \ - -Wno-STMTDLY --x-assign unique \ - -O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR" diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 451b4602..022e8079 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -11,7 +11,7 @@ sim_dir=$(abspath .) ######################################################################################### # include shared variables ######################################################################################### -include $(base_dir)/Makefrag-Variables +include $(base_dir)/variables.mk ######################################################################################### # name of simulator (used to generate *.f arguments file) @@ -32,7 +32,7 @@ debug: $(sim_debug) ######################################################################################### # import other necessary rules and variables ######################################################################################### -include $(base_dir)/Makefrag +include $(base_dir)/common.mk ######################################################################################### # vcs binary and arguments @@ -71,12 +71,6 @@ VCS_NONCC_OPTS = \ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) -######################################################################################### -# helper rule to just make verilog files -######################################################################################### -.PHONY: verilog -verilog: $(sim_vsrcs) - ######################################################################################### # vcs simulator rules ######################################################################################### diff --git a/Makefrag-Variables b/variables.mk similarity index 93% rename from Makefrag-Variables rename to variables.mk index 18793d3d..f44286c5 100644 --- a/Makefrag-Variables +++ b/variables.mk @@ -6,11 +6,11 @@ # default variables to invoke the generator # descriptions: # PROJECT = the scala package to find the MODEL in -# MODEL = the top level module of the project +# MODEL = the top level module of the project (normally the harness) # CONFIG = the configuration class to give the parameters for the project # CFG_PROJECT = the scala package to find the CONFIG class -# TB = TODO -# TOP = TODO +# TB = wrapper over the TestHarness needed to simulate in VCS +# TOP = top level module of the project (normally the module instantiated by the harness) ######################################################################################### PROJECT ?= example MODEL ?= TestHarness From 4fd1bfbd567e137d09ca85106f614d9044c1d53e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Mar 2019 17:00:21 -0800 Subject: [PATCH 008/120] delete .ctags (have the user put this in their home) --- .ctags | 13 ------------- 1 file changed, 13 deletions(-) delete mode 100644 .ctags diff --git a/.ctags b/.ctags deleted file mode 100644 index b7d31250..00000000 --- a/.ctags +++ /dev/null @@ -1,13 +0,0 @@ ---langdef=scala ---langmap=scala:.scala - ---regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*class[ \t]+([a-zA-Z0-9_]+)/\4/c,classes/ ---regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*object[ \t]+([a-zA-Z0-9_]+)/\4/o,objects/ ---regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*((abstract|final|sealed|implicit|lazy)[ \t ]*)*case class[ \t ]+([a-zA-Z0-9_]+)/\6/C,case classes/ ---regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*case object[ \t]+([a-zA-Z0-9_]+)/\4/O,case objects/ ---regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*trait[ \t]+([a-zA-Z0-9_]+)/\4/t,traits/ ---regex-scala=/^[ \t]*type[ \t]+([a-zA-Z0-9_]+)/\1/T,types/ ---regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*(\[[a-z]*\])*|protected)[ \t]*)*def[ \t]+([a-zA-Z0-9_]+)/\4/m,methods/ ---regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*val[ \t]+([a-zA-Z0-9_]+)/\3/V,values/ ---regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*var[ \t]+([a-zA-Z0-9_]+)/\3/v,variables/ ---regex-scala=/^[ \t]*package[ \t]+([a-zA-Z0-9_.]+)/\1/p,packages/ From c3648695638a7416290892a5e96add15419394f3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Mar 2019 18:11:10 -0800 Subject: [PATCH 009/120] default to .gitignoring all files in verisim/vsim | read verilator.mk --- .gitignore | 3 --- sims/verisim/.gitignore | 3 ++- sims/verisim/verilator.mk | 47 +++++++++++++++++++++++++++++++++++++++ sims/vsim/.gitignore | 3 ++- 4 files changed, 51 insertions(+), 5 deletions(-) create mode 100644 sims/verisim/verilator.mk diff --git a/.gitignore b/.gitignore index 2efa7a6a..3866cf2f 100644 --- a/.gitignore +++ b/.gitignore @@ -3,9 +3,6 @@ bootrom target *.jar *.stamp -/sims/vsim -/sims/verisim -simv* *.vcd *.swp .idea diff --git a/sims/verisim/.gitignore b/sims/verisim/.gitignore index e442175e..afbfb95f 100644 --- a/sims/verisim/.gitignore +++ b/sims/verisim/.gitignore @@ -1,3 +1,4 @@ +* !.gitignore !Makefile -!Makefrag-verilator +!verilator.mk diff --git a/sims/verisim/verilator.mk b/sims/verisim/verilator.mk new file mode 100644 index 00000000..3af9b335 --- /dev/null +++ b/sims/verisim/verilator.mk @@ -0,0 +1,47 @@ +######################################################################################### +# verilator installation makefrag +######################################################################################### + +######################################################################################### +# verilator version, binary, and path +######################################################################################### +VERILATOR_VERSION=4.008 +VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) +INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) + +######################################################################################### +# build and install our own verilator to work around versioning issues +######################################################################################### +$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator + $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata + touch $@ + +$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile + $(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin + touch $@ + +$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure + mkdir -p $(dir $@) + cd $(dir $@) && ./configure --prefix=$(abspath verilator/install) + +$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz + rm -rf $(dir $@) + mkdir -p $(dir $@) + cat $^ | tar -xz --strip-components=1 -C $(dir $@) + touch $@ + +verilator/verilator-$(VERILATOR_VERSION).tar.gz: + mkdir -p $(dir $@) + wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ + +######################################################################################### +# verilator binary and flags +######################################################################################### +VERILATOR := $(INSTALLED_VERILATOR) --cc --exe +CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS +VERILATOR_FLAGS := --top-module $(MODEL) \ + +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ + +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ + --output-split 20000 \ + -Wno-STMTDLY --x-assign unique \ + -O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR" diff --git a/sims/vsim/.gitignore b/sims/vsim/.gitignore index 803a3908..a0991ff4 100644 --- a/sims/vsim/.gitignore +++ b/sims/vsim/.gitignore @@ -1,2 +1,3 @@ -!Makefile +* !.gitignore +!Makefile From e33f2fcedf889e10332317dfe2b6d531e9bb08bd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 12 Mar 2019 15:39:19 -0700 Subject: [PATCH 010/120] find now follows symlinks --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index dd1cbd8e..1ff52172 100644 --- a/common.mk +++ b/common.mk @@ -6,7 +6,7 @@ SHELL=/bin/bash ######################################################################################### # variables to get all *.scala files ######################################################################################### -lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null) +lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null) PACKAGES=rocket-chip testchipip SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) From 319d2fedf745f52211ae71a306d22a3ee6348f56 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sat, 16 Mar 2019 00:15:02 -0700 Subject: [PATCH 011/120] more docs --- .../Adding-An-Accelerator-Tutorial.rst | 362 ++++++++++++++++++ docs/ReBAR-Basics/rebar-generator-mixins.rst | 135 +++++++ docs/Simulation/Commercial-Simulators.rst | 33 ++ docs/Simulation/FPGA-Based-Simulators.rst | 13 + docs/Simulation/Open-Source-Simulators.rst | 33 ++ 5 files changed, 576 insertions(+) create mode 100644 docs/ReBAR-Basics/Adding-An-Accelerator-Tutorial.rst create mode 100644 docs/ReBAR-Basics/rebar-generator-mixins.rst create mode 100644 docs/Simulation/Commercial-Simulators.rst create mode 100644 docs/Simulation/FPGA-Based-Simulators.rst create mode 100644 docs/Simulation/Open-Source-Simulators.rst diff --git a/docs/ReBAR-Basics/Adding-An-Accelerator-Tutorial.rst b/docs/ReBAR-Basics/Adding-An-Accelerator-Tutorial.rst new file mode 100644 index 00000000..1df6b0d5 --- /dev/null +++ b/docs/ReBAR-Basics/Adding-An-Accelerator-Tutorial.rst @@ -0,0 +1,362 @@ + + +Adding An Accelerator/Device +=============================== + +Accelerators or custom IO devices can be added to your SoC in several ways: ++ MMIO Peripheral (a.k.a TileLink-Attached Accelerator) ++ Tightly-Coupled RoCC Accelerator + +These approaches differ in the method of the communication between the processor and the custom block. + +With the TileLink-Attached approach, the processor communicates with MMIO peripherals through memory-mapped registers. + +In contrast, the processor communicates with a RoCC accelerators through a custom protocol and custom non-standard ISA instructions reserved in the RISC-V ISA encoding space. Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU. +RoCC coprocessor instructions have the following form. + +:: + customX rd, rs1, rs2, funct + +The X will be a number 0-3, and determines the opcode of the instruction, +which controls which accelerator an instruction will be routed to. +The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination +register and two source registers. The ``funct`` field is a 7-bit integer that +the accelerator can use to distinguish different instructions from each other. + +Note that communication through a RoCC interfaces requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with approriate driver support. + + +Integrating into the Generator Build System +------------------------------------------- + +While developing, you want to include Chisel code in a submodule so that it +can be shared by different projects. To add a submodule to the project +template, make sure that your project is organized as follows. + + yourproject/ + build.sbt + src/main/scala/ + YourFile.scala + +Put this in a git repository and make it accessible. Then add it as a submodule +to under the following directory hierarchy: ``rebar/generators/yourproject``. + +:: + git submodule add https://git-repository.com/yourproject.git + +Then add `yourproject` to the ReBAR top-level build.sbt file. + +:: + lazy val yourproject = project.settings(commonSettings).dependsOn(rocketchip) + + +You can then import the classes defined in the submodule in a new project if +you add it as a dependency. For instance, if you want to use this code in +the `example` project, change the final line in build.sbt to the following. + +:: + lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) + + +Finally, add `yourproject` to the `PACKAGES` variable in the `Makefrag`. This will allow make to detect +that your source files have changed when building the verilog/firrtl files. + + + +MMIO Peripheral +------------------ + +The easiest way to create a TileLink peripheral is to use the +TLRegisterRouter, which abstracts away the details of handling the TileLink +protocol and provides a convenient interface for specifying memory-mapped +registers. To create a RegisterRouter-based peripheral, you will need to +specify a parameter case class for the configuration settings, a bundle trait +with the extra top-level ports, and a module implementation containing the +actual RTL. + +:: + case class PWMParams(address: BigInt, beatBytes: Int) + + trait PWMTLBundle extends Bundle { + val pwmout = Output(Bool()) + } + + trait PWMTLModule { + val io: PWMTLBundle + implicit val p: Parameters + def params: PWMParams + + val w = params.beatBytes * 8 + val period = Reg(UInt(w.W)) + val duty = Reg(UInt(w.W)) + val enable = RegInit(false.B) + + // ... Use the registers to drive io.pwmout ... + + regmap( + 0x00 -> Seq( + RegField(w, period)), + 0x04 -> Seq( + RegField(w, duty)), + 0x08 -> Seq( + RegField(1, enable))) + } + + +Once you have these classes, you can construct the final peripheral by +extending the TLRegisterRouter and passing the proper arguments. The first +set of arguments determines where the register router will be placed in the +global address map and what information will be put in its device tree entry. +The second set of arguments is the IO bundle constructor, which we create +by extending TLRegBundle with our bundle trait. The final set of arguments +is the module constructor, which we create by extends TLRegModule with our +module trait. + +:: + class PWMTL(c: PWMParams)(implicit p: Parameters) + extends TLRegisterRouter( + c.address, "pwm", Seq("ucbbar,pwm"), + beatBytes = c.beatBytes)( + new TLRegBundle(c, _) with PWMTLBundle)( + new TLRegModule(c, _, _) with PWMTLModule) + + +The full module code with comments can be found in src/main/scala/example/PWM.scala. + +After creating the module, we need to hook it up to our SoC. Rocketchip +accomplishes this using the [cake pattern](http://www.cakesolutions.net/teamblogs/2011/12/19/cake-pattern-in-depth). +This basically involves placing code inside traits. In the RocketChip cake, +there are two kinds of traits: a LazyModule trait and a module implementation +trait. + +The LazyModule trait runs setup code that must execute before all the hardware +gets elaborated. For a simple memory-mapped peripheral, this just involves +connecting the peripheral's TileLink node to the MMIO crossbar. + +:: + trait HasPeripheryPWM extends HasSystemNetworks { + implicit val p: Parameters + + private val address = 0x2000 + + val pwm = LazyModule(new PWMTL( + PWMParams(address, peripheryBusConfig.beatBytes))(p)) + + pwm.node := TLFragmenter( + peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) + } + + +Note that the PWMTL class we created from the register router is itself a +LazyModule. Register routers have a TileLike node simply named "node", which +we can hook up to the RocketChip peripheryBus. This will automatically add +address map and device tree entries for the peripheral. + +The module implementation trait is where we instantiate our PWM module and +connect it to the rest of the SoC. Since this module has an extra `pwmout` +output, we declare that in this trait, using Chisel's multi-IO +functionality. We then connect the PWMTL's pwmout to the pwmout we declared. + +:: + trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp { + implicit val p: Parameters + val outer: HasPeripheryPWM + + val pwmout = IO(Output(Bool())) + + pwmout := outer.pwm.module.io.pwmout + } + + +Now we want to mix our traits into the system as a whole. This code is from +src/main/scala/example/Top.scala. + +:: + class ExampleTopWithPWM(q: Parameters) extends ExampleTop(q) + with PeripheryPWM { + override lazy val module = Module( + new ExampleTopWithPWMModule(p, this)) + } + + class ExampleTopWithPWMModule(l: ExampleTopWithPWM) + extends ExampleTopModule(l) with HasPeripheryPWMModuleImp + + +Just as we need separate traits for LazyModule and module implementation, we +need two classes to build the system. The ExampleTop classes already have the +basic peripherals included for us, so we will just extend those. + +The ExampleTop class includes the pre-elaboration code and also a lazy val to +produce the module implementation (hence LazyModule). The ExampleTopModule +class is the actual RTL that gets synthesized. + +Finally, we need to add a configuration class in +src/main/scala/example/Configs.scala that tells the TestHarness to instantiate +ExampleTopWithPWM instead of the default ExampleTop. + +:: + class WithPWM extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => + Module(LazyModule(new ExampleTopWithPWM()(p)).module) + }) + + class PWMConfig extends Config(new WithPWM ++ new BaseExampleConfig) + + +Now we can test that the PWM is working. The test program is in tests/pwm.c + +:: + #define PWM_PERIOD 0x2000 + #define PWM_DUTY 0x2008 + #define PWM_ENABLE 0x2010 + + static inline void write_reg(unsigned long addr, unsigned long data) + { + volatile unsigned long *ptr = (volatile unsigned long *) addr; + *ptr = data; + } + + static inline unsigned long read_reg(unsigned long addr) + { + volatile unsigned long *ptr = (volatile unsigned long *) addr; + return *ptr; + } + + int main(void) + { + write_reg(PWM_PERIOD, 20); + write_reg(PWM_DUTY, 5); + write_reg(PWM_ENABLE, 1); + } + + +This just writes out to the registers we defined earlier. The base of the +module's MMIO region is at 0x2000. This will be printed out in the address +map portion when you generated the verilog code. + +Compiling this program with make produces a `pwm.riscv` executable. + +Now with all of that done, we can go ahead and run our simulation. + +:: + cd verisim + make CONFIG=PWMConfig + ./simulator-example-PWMConfig ../tests/pwm.riscv + + + + +Adding a RoCC Accelerator +---------------------------- + +RoCC accelerators are lazy modules that extend the LazyRoCC class. +Their implementation should extends the LazyRoCCModule class. + +:: + class CustomAccelerator(opcodes: OpcodeSet) + (implicit p: Parameters) extends LazyRoCC(opcodes) { + override lazy val module = new CustomAcceleratorModule(this) + } + + class CustomAcceleratorModule(outer: CustomAccelerator) + extends LazyRoCCModuleImp(outer) { + val cmd = Queue(io.cmd) + // The parts of the command are as follows + // inst - the parts of the instruction itself + // opcode + // rd - destination register number + // rs1 - first source register number + // rs2 - second source register number + // funct + // xd - is the destination register being used? + // xs1 - is the first source register being used? + // xs2 - is the second source register being used? + // rs1 - the value of source register 1 + // rs2 - the value of source register 2 + ... + } + + +The ``opcodes`` parameter for ``LazyRoCC`` is +the set of custom opcodes that will map to this accelerator. More on this +in the next subsection. + +The ``LazyRoCC`` class contains two TLOutputNode instances, ``atlNode`` and ``tlNode``. +The former connects into a tile-local arbiter along with the backside of the +L1 instruction cache. The latter connects directly to the L1-L2 crossbar. +The corresponding Tilelink ports in the module implementation's IO bundle +are ``atl`` and ``tl``, respectively. + +The other interfaces available to the accelerator are ``mem``, which provides +access to the L1 cache; ``ptw`` which provides access to the page-table walker; +the ``busy`` signal, which indicates when the accelerator is still handling an +instruction; and the ``interrupt`` signal, which can be used to interrupt the CPU. + +Look at the examples in rocket-chip/src/main/scala/tile/LazyRocc.scala for +detailed information on the different IOs. + +### Adding RoCC accelerator to Config + +RoCC accelerators can be added to a core by overriding the ``BuildRoCC`` parameter +in the configuration. This takes a sequence of functions producing ``LazyRoCC`` +objects, one for each accelerator you wish to add. + +For instance, if we wanted to add the previously defined accelerator and +route custom0 and custom1 instructions to it, we could do the following. + +:: + class WithCustomAccelerator extends Config((site, here, up) => { + case BuildRoCC => Seq((p: Parameters) => LazyModule( + new CustomAccelerator(OpcodeSet.custom0 | OpcodeSet.custom1)(p))) + }) + + class CustomAcceleratorConfig extends Config( + new WithCustomAccelerator ++ new DefaultExampleConfig) + + + + +Adding a DMA port +------------------- + +IO devices or accelerators (like a disk or network +driver), we may want to have the device write directly to the coherent +memory system instead. To add a device like that, you would do the following. + +:: + class DMADevice(implicit p: Parameters) extends LazyModule { + val node = TLClientNode(TLClientParameters( + name = "dma-device", sourceId = IdRange(0, 1))) + + lazy val module = new DMADeviceModule(this) + } + + class DMADeviceModule(outer: DMADevice) extends LazyModuleImp(outer) { + val io = IO(new Bundle { + val mem = outer.node.bundleOut + val ext = new ExtBundle + }) + + // ... rest of the code ... + } + + trait HasPeripheryDMA extends HasSystemNetworks { + implicit val p: Parameters + + val dma = LazyModule(new DMADevice) + + fsb.node := dma.node + } + + trait HasPeripheryDMAModuleImp extends LazyMultiIOModuleImp { + val ext = IO(new ExtBundle) + ext <> outer.dma.module.io.ext + } + + +The ``ExtBundle`` contains the signals we connect off-chip that we get data from. +The DMADevice also has a Tilelink client port that we connect into the L1-L2 +crossbar through the front-side buffer (fsb). The sourceId variable given in +the TLClientNode instantiation determines the range of ids that can be used +in acquire messages from this device. Since we specified [0, 1) as our range, +only the ID 0 can be used. diff --git a/docs/ReBAR-Basics/rebar-generator-mixins.rst b/docs/ReBAR-Basics/rebar-generator-mixins.rst new file mode 100644 index 00000000..e950ffda --- /dev/null +++ b/docs/ReBAR-Basics/rebar-generator-mixins.rst @@ -0,0 +1,135 @@ + + +SoC Generator Config Mix-ins: +============================== + +Rocket Chip +----------------------- + ++ System-on-Chip + - HasTiles + - HasClockDomainCrossing + - HasResetVectorWire + - HasNoiseMakerIO + + ++ Basic Core + - HasRocketTiles + - HasRocketCoreParameters + - HasCoreIO + + ++ Branch Prediction + - HasBtbParameters + + ++ Additional Compute + - HasFPUCtrlSigs + - HasFPUParameters + - HasLazyRoCC + - HasFpuOpt + + ++ Memory System + - HasRegMap + - HasCoreMemOp + - HasHellaCache + - HasL1ICacheParameters + - HasICacheFrontendModule + - HasAXI4ControlRegMap + - HasTLControlRegMap + - HasTLBusParams + - HasTLXbarPhy + + ++ Interrupts + - HasInterruptSources + - HasExtInterrupts + - HasAsyncExtInterrupts + - HasSyncExtInterrupts + + ++ Periphery + - HasPeripheryDebug + - HasPeripheryBootROM + - HasBuiltInDeviceParams + + +BOOM +----------------------- ++ Basic Core + - HasBoomTiles + - HasBoomCoreParameters + - HasBoomCoreIO + - HasBoomUOP + - HasRegisterFileIO + + ++ Branch Prediction + - HasGShareParameters + - HasBoomBTBParameters + + ++ Memory System + - HasL1ICacheBankedParameters + - HasBoomICacheFrontend + - HasBoomHellaCache + + +SiFive Blocks +----------------------- + ++ Peripherals + - HasPeripheryGPIO + - HasPeripheryI2C + - HasPeripheryMockAON + - HasPeripheryPWM + - HasPeripherySPI + - HasSPIProtocol + - HasSPIEndian + - HasSPILength + - HasSPICSMode + - HasPeripherySPIFlash + - HasPeripheryUART + + +testchipip +----------------------- + ++ Peripherals + - HasPeripheryBlockDevice + - HasPeripherySerial + - HasNoDebug + + +Icenet +----------------------- + ++ Periphery Network Interface Controller + - HasPeripheryIceNIC + + +AWL +----------------------- + ++ IO + - HasEncoding8b10b + - HasTLBidirectionalPacketizer + - HasTLController + - HasGenericTransceiverSubsystem + ++ Debug/Testing + - HasBertDebug + - HasPatternMemDebug + - HasBitStufferDebug4Modes + - HasBitReversalDebug + + + + + + + + + + diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Commercial-Simulators.rst new file mode 100644 index 00000000..e107d703 --- /dev/null +++ b/docs/Simulation/Commercial-Simulators.rst @@ -0,0 +1,33 @@ +Commericial Simulators +============================== +The ReBAR framework currently supports only the VCS commerical simulator + +VCS +----------------------- +VCS is a commercial RTL simulator developed by Synopsys. It requires commerical licenses. +The ReBAR framework can compile and execute simulations using VCS. VCS simulation will generally compile +faster than Verilator simulations. + +To run a simulation using VCS, perform the following steps: + +Make sure that the VCS simulator is on your `PATH`. + +To compile the example design, run make in the ``sims/vsim`` directory. +This will elaborate the DefaultExampleConfig in the example project. + +An executable called simulator-example-DefaultExampleConfig will be produced. +This executable is a simulator that has been compiled based on the design that was built. +You can then use this executable to run any compatible RV64 code. For instance, +to run one of the riscv-tools assembly tests. + +:: + ./simulator-example-DefaultExampleConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + +If you later create your own project, you can use environment variables to +build an alternate configuration. + +:: + make PROJECT=yourproject CONFIG=YourConfig + ./simulator-yourproject-YourConfig ... + +If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. This will generate a vpd file (this is a proprietry waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. If you have Synopsys licenses, we recommend using the DVE waveform viewers diff --git a/docs/Simulation/FPGA-Based-Simulators.rst b/docs/Simulation/FPGA-Based-Simulators.rst new file mode 100644 index 00000000..fbacafa4 --- /dev/null +++ b/docs/Simulation/FPGA-Based-Simulators.rst @@ -0,0 +1,13 @@ +FPGA-Based Simulators +============================== + +FireSim +----------------------- +FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). +FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. FireSim also provide additional device models to allow full-system simulation, including memory models and network models. + +FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. In order to simulate your ReBAR design using FireSim, you should follow the following steps: + +Follow the initial EC2 setup instructions as detailed in the FireSim documentatino . Then clone your full ReBAR repository onto your Amazon EC2 FireSim manager instance. + +Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for running a simulation diff --git a/docs/Simulation/Open-Source-Simulators.rst b/docs/Simulation/Open-Source-Simulators.rst new file mode 100644 index 00000000..2b8e1f4e --- /dev/null +++ b/docs/Simulation/Open-Source-Simulators.rst @@ -0,0 +1,33 @@ +Open Source Simulators +============================== + +Verilator +----------------------- +Verilator is an open-source LGPL-Licensed simulator maintained by `Veripool `__ +The ReBAR framework can download, build, and execute simulations using Verilator. + +To run a simulation using verilator, perform the following steps: + +To compile the example design, run make in the ``sims/verisim`` directory. +This will elaborate the DefaultExampleConfig in the example project. + +An executable called simulator-example-DefaultExampleConfig will be produced. +This executable is a simulator that has been compiled based on the design that was built. +You can then use this executable to run any compatible RV64 code. For instance, +to run one of the riscv-tools assembly tests. + +:: + ./simulator-example-DefaultExampleConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + +If you later create your own project, you can use environment variables to +build an alternate configuration. + +:: + make PROJECT=yourproject CONFIG=YourConfig + ./simulator-yourproject-YourConfig ... + + +If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. An open-source vcd-capable waveform viewer is `GTKWave __ + + + From ffee1f1e983de6b548f357932f6df081d521aeac Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Mon, 18 Mar 2019 07:31:27 -0700 Subject: [PATCH 012/120] Bump barstools and re-add infer-rw for better SRAM mapping --- common.mk | 2 +- tools/barstools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index 1ff52172..2f99a048 100644 --- a/common.mk +++ b/common.mk @@ -66,7 +66,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) ######################################################################################### # create verilog files rules and variables ######################################################################################### -REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) +REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) $(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir) diff --git a/tools/barstools b/tools/barstools index 9d505d60..0b9d74ad 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 9d505d6063f07f7750686f67d2cda49b17f6d898 +Subproject commit 0b9d74ada7e3271e82d665b09b3b9ff087c70f91 From 31e30b2ec7dfb4ab472911a791c1ad4b32966b8f Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 7 Mar 2019 14:18:24 -0800 Subject: [PATCH 013/120] change dir structure --- Makefrag | 110 ++++++++++++++++++++++++++++++ sims/verisim/Makefile | 91 ++++++++++++------------- sims/verisim/Makefrag-verilator | 34 ++++++++++ sims/vsim/Makefile | 115 ++++++++++++++------------------ 4 files changed, 236 insertions(+), 114 deletions(-) create mode 100644 Makefrag create mode 100644 sims/verisim/Makefrag-verilator diff --git a/Makefrag b/Makefrag new file mode 100644 index 00000000..3d90d8c9 --- /dev/null +++ b/Makefrag @@ -0,0 +1,110 @@ +ROCKETCHIP_DIR=$(base_dir)/generators/rocket-chip +TESTCHIP_DIR = $(base_dir)/generators/testchipip + +SCALA_VERSION=2.12.4 +SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) + +SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION) + +lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null) + +PACKAGES=rocket-chip testchipip +SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) + +ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" +TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes" +FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar + +$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala) + $(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala + mkdir -p $(dir $@) + cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@ + touch $@ + +build_dir=$(sim_dir)/generated-src + +CHISEL_ARGS ?= + +long_name=$(PROJECT).$(MODEL).$(CONFIG) + +FIRRTL_FILE ?=$(build_dir)/$(long_name).fir +ANNO_FILE ?=$(build_dir)/$(long_name).anno.json +VERILOG_FILE ?=$(build_dir)/$(long_name).top.v +HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v +SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v +SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf +sim_dotf ?= $(build_dir)/sim_files.f + +REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) + +# This should match whatever the commonSettings version is in build.sbt +BARSTOOLS_VER=1.0 +TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar +MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar + +TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR) +MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR) + +$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala) + cd $(base_dir) && $(SBT) "tapeout/assembly" + +$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/tools/barstools/mdf/scalalib/src/main/scala) + cd $(base_dir) && $(SBT) "barstools-macros/assembly" + +.PHONY: jars +jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) + +$(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR) + cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" + +$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) + mkdir -p $(build_dir) + cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" + +$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) + $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir) + +$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) + $(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir) + +# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs +$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR) + $(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops + +regression-tests = \ + rv64ud-v-fcvt \ + rv64ud-p-fdiv \ + rv64ud-v-fadd \ + rv64uf-v-fadd \ + rv64um-v-mul \ + rv64mi-p-breakpoint \ + rv64uc-v-rvc \ + rv64ud-v-structural \ + rv64si-p-wfi \ + rv64um-v-divw \ + rv64ua-v-lrsc \ + rv64ui-v-fence_i \ + rv64ud-v-fcvt_w \ + rv64uf-v-fmin \ + rv64ui-v-sb \ + rv64ua-v-amomax_d \ + rv64ud-v-move \ + rv64ud-v-fclass \ + rv64ua-v-amoand_d \ + rv64ua-v-amoxor_d \ + rv64si-p-sbreak \ + rv64ud-v-fmadd \ + rv64uf-v-ldst \ + rv64um-v-mulh \ + rv64si-p-dirty + +output_dir=$(sim_dir)/output + +$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% + mkdir -p $(output_dir) + ln -sf $< $@ + +.PHONY: clean-scala +clean-scala: + rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) + diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 8049bab9..74950993 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -1,43 +1,38 @@ -######################################################################################### -# verilator makefile -######################################################################################### - -######################################################################################### -# general path variables -######################################################################################### base_dir=$(abspath ../..) sim_dir=$(abspath .) -######################################################################################### -# include shared variables -######################################################################################### -include $(base_dir)/variables.mk +PROJECT ?= example +MODEL ?= TestHarness +CONFIG ?= DefaultExampleConfig +CFG_PROJECT ?= $(PROJECT) +TB ?= TestDriver +TOP ?= ExampleTop -######################################################################################### -# name of simulator (used to generate *.f arguments file) -######################################################################################### sim_name = verilator -######################################################################################### -# vcs simulator types and rules -######################################################################################### -sim_prefix = simulator -sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG) -sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug +sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG) +sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug -.PHONY: default debug default: $(sim) + debug: $(sim_debug) -######################################################################################### -# import other necessary rules and variables -######################################################################################### -include $(base_dir)/common.mk -include $(sim_dir)/verilator.mk +CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS +LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread + +include $(base_dir)/Makefrag +include $(sim_dir)/Makefrag-verilator + +sim_blackboxes = \ + $(build_dir)/firrtl_black_box_resource_files.f + +rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc + +sim_vsrcs = \ + $(VERILOG_FILE) \ + $(HARNESS_FILE) \ + $(SMEMS_FILE) -######################################################################################### -# verilator build paths and file names -######################################################################################### model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug @@ -47,11 +42,6 @@ model_header_debug = $(model_dir_debug)/V$(MODEL).h model_mk = $(model_dir)/V$(MODEL).mk model_mk_debug = $(model_dir_debug)/V$(MODEL).mk -######################################################################################### -# build makefile fragment that builds the verilator sim rules -######################################################################################### -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread - $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) @@ -60,6 +50,10 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" touch $@ +$(sim): $(model_mk) + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk + + $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug @@ -68,26 +62,25 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" touch $@ -######################################################################################### -# invoke make to make verilator sim rules -######################################################################################### -$(sim): $(model_mk) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk - $(sim_debug): $(model_mk_debug) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk -######################################################################################### -# create a vcs vpd rule -######################################################################################### +$(output_dir)/%.out: $(output_dir)/% $(sim) + $(sim) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + +$(output_dir)/%.run: $(output_dir)/% $(sim) + $(sim) +max-cycles=1000000 $< && touch $@ + $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - $(sim_debug) -v$@.vcd +max-cycles=$(timeout_cycles) $< + $(sim_debug) -v$@.vcd +max-cycles=1000000 $< + +run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) + +run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) + +run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) -######################################################################################### -# general cleanup rule -######################################################################################### -.PHONY: clean clean: clean-scala - rm -rf $(build_dir) $(sim_prefix)-* + rm -rf generated-src ./simulator-* diff --git a/sims/verisim/Makefrag-verilator b/sims/verisim/Makefrag-verilator new file mode 100644 index 00000000..f8ea0b4c --- /dev/null +++ b/sims/verisim/Makefrag-verilator @@ -0,0 +1,34 @@ +# Build and install our own Verilator, to work around versionining issues. +VERILATOR_VERSION=3.920 +VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) +INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) +$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator + $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata + touch $@ + +$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile + $(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin + touch $@ + +$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure + mkdir -p $(dir $@) + cd $(dir $@) && ./configure --prefix=$(abspath verilator/install) + +$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz + rm -rf $(dir $@) + mkdir -p $(dir $@) + cat $^ | tar -xz --strip-components=1 -C $(dir $@) + touch $@ + +verilator/verilator-$(VERILATOR_VERSION).tar.gz: + mkdir -p $(dir $@) + wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ + +# Run Verilator to produce a fast binary to emulate this circuit. +VERILATOR := $(INSTALLED_VERILATOR) --cc --exe +VERILATOR_FLAGS := --top-module $(MODEL) \ + +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ + +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ + --output-split 20000 \ + -Wno-STMTDLY --x-assign unique \ + -O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR" diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 022e8079..41c73b58 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -1,96 +1,81 @@ -######################################################################################### -# vcs makefile -######################################################################################### - -######################################################################################### -# general path variables -######################################################################################### base_dir=$(abspath ../..) sim_dir=$(abspath .) -######################################################################################### -# include shared variables -######################################################################################### -include $(base_dir)/variables.mk +PROJECT ?= example +MODEL ?= TestHarness +CONFIG ?= DefaultExampleConfig +CFG_PROJECT ?= $(PROJECT) +TB ?= TestDriver +TOP ?= ExampleTop -######################################################################################### -# name of simulator (used to generate *.f arguments file) -######################################################################################### sim_name = vcs -######################################################################################### -# vcs simulator types and rules -######################################################################################### -sim_prefix = simv -sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG) -sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug +simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG) +simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug -.PHONY: default debug -default: $(sim) -debug: $(sim_debug) +default: $(simv) -######################################################################################### -# import other necessary rules and variables -######################################################################################### -include $(base_dir)/common.mk +debug: $(simv_debug) + +include $(base_dir)/Makefrag + +sim_blackboxes = \ + $(build_dir)/firrtl_black_box_resource_files.f + +rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc + +sim_vsrcs = \ + $(VERILOG_FILE) \ + $(HARNESS_FILE) \ + $(SMEMS_FILE) -######################################################################################### -# vcs binary and arguments -######################################################################################### VCS = vcs -full64 -VCS_CC_OPTS = \ - -CC "-I$(VCS_HOME)/include" \ +VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \ + +rad +v2k +vcs+lic+wait \ + +vc+list -CC "-I$(VCS_HOME)/include" \ -CC "-I$(RISCV)/include" \ -CC "-std=c++11" \ -CC "-Wl,-rpath,$(RISCV)/lib" \ - $(RISCV)/lib/libfesvr.so - -VCS_NONCC_OPTS = \ - +lint=all,noVCDE,noONGS,noUI \ - -error=PCWM-L \ - -timescale=1ns/10ps \ - -quiet \ - +rad \ - +v2k \ - +vcs+lic+wait \ - +vc+list \ - -f $(sim_blackboxes) \ - -f $(sim_dotf) \ + -f $(sim_blackboxes) -f $(sim_dotf) \ + $(RISCV)/lib/libfesvr.so \ -sverilog \ - +incdir+$(build_dir) \ - +define+CLOCK_PERIOD=1.0 \ - $(sim_vsrcs) \ + +incdir+$(generated_dir) \ + +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE_MEM_INIT \ +define+RANDOMIZE_REG_INIT \ +define+RANDOMIZE_GARBAGE_ASSIGN \ +define+RANDOMIZE_INVALID_ASSIGN \ - +libext+.v + +libext+.v \ -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) +verilog: $(sim_vsrcs) -######################################################################################### -# vcs simulator rules -######################################################################################### -$(sim): $(sim_vsrcs) $(sim_dotf) +$(simv): $(sim_vsrcs) $(sim_dotf) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug) : $(sim_vsrcs) $(sim_dotf) +$(simv_debug) : $(sim_vsrcs) $(sim_dotf) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp -######################################################################################### -# create a vcs vpd rule -######################################################################################### -$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - $(sim_debug) +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $< +$(output_dir)/%.out: $(output_dir)/% $(simv) + $(simv) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + +$(output_dir)/%.run: $(output_dir)/% $(simv) + $(simv) +max-cycles=1000000 $< && touch $@ + +$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug) + $(simv_debug) +vcdplusfile=$@ +max-cycles=1000000 $< + +run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) + +run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) + +run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) + +clean: + rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h -######################################################################################### -# general cleanup rule -######################################################################################### .PHONY: clean -clean: clean-scala - rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h From eb44ae13d4eee84ece7db470bfca5f69c4eab2e4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Mar 2019 16:23:35 -0800 Subject: [PATCH 014/120] makefile changes/split | add scripts --- .ctags | 13 ++ Makefrag | 98 +++++++++------ Makefrag-Variables | 79 ++++++++++++ sims/verisim/Makefile | 89 +++++++------ ...{Makefrag-verilator => Makefrag-Verilator} | 19 ++- sims/vsim/Makefile | 117 +++++++++++------- 6 files changed, 287 insertions(+), 128 deletions(-) create mode 100644 .ctags create mode 100644 Makefrag-Variables rename sims/verisim/{Makefrag-verilator => Makefrag-Verilator} (54%) diff --git a/.ctags b/.ctags new file mode 100644 index 00000000..b7d31250 --- /dev/null +++ b/.ctags @@ -0,0 +1,13 @@ +--langdef=scala +--langmap=scala:.scala + +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*class[ \t]+([a-zA-Z0-9_]+)/\4/c,classes/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*object[ \t]+([a-zA-Z0-9_]+)/\4/o,objects/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*((abstract|final|sealed|implicit|lazy)[ \t ]*)*case class[ \t ]+([a-zA-Z0-9_]+)/\6/C,case classes/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*case object[ \t]+([a-zA-Z0-9_]+)/\4/O,case objects/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*trait[ \t]+([a-zA-Z0-9_]+)/\4/t,traits/ +--regex-scala=/^[ \t]*type[ \t]+([a-zA-Z0-9_]+)/\1/T,types/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*(\[[a-z]*\])*|protected)[ \t]*)*def[ \t]+([a-zA-Z0-9_]+)/\4/m,methods/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*val[ \t]+([a-zA-Z0-9_]+)/\3/V,values/ +--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*var[ \t]+([a-zA-Z0-9_]+)/\3/v,variables/ +--regex-scala=/^[ \t]*package[ \t]+([a-zA-Z0-9_.]+)/\1/p,packages/ diff --git a/Makefrag b/Makefrag index 3d90d8c9..d5f009ec 100644 --- a/Makefrag +++ b/Makefrag @@ -1,50 +1,38 @@ -ROCKETCHIP_DIR=$(base_dir)/generators/rocket-chip -TESTCHIP_DIR = $(base_dir)/generators/testchipip - -SCALA_VERSION=2.12.4 -SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) - -SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION) +######################################################################################### +# set default shell for make +######################################################################################### +SHELL=/bin/bash +######################################################################################### +# variables to get all *.scala files +######################################################################################### lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null) PACKAGES=rocket-chip testchipip SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) +######################################################################################### +# rocket and testchipip classes +######################################################################################### ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes" + +######################################################################################### +# jar creation variables and rules +######################################################################################### FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar +# this should match whatever the commonSettings version is in build.sbt +BARSTOOLS_VER=1.0 +TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar +MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar + $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala) $(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala mkdir -p $(dir $@) cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@ touch $@ -build_dir=$(sim_dir)/generated-src - -CHISEL_ARGS ?= - -long_name=$(PROJECT).$(MODEL).$(CONFIG) - -FIRRTL_FILE ?=$(build_dir)/$(long_name).fir -ANNO_FILE ?=$(build_dir)/$(long_name).anno.json -VERILOG_FILE ?=$(build_dir)/$(long_name).top.v -HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v -SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v -SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf -sim_dotf ?= $(build_dir)/sim_files.f - -REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) - -# This should match whatever the commonSettings version is in build.sbt -BARSTOOLS_VER=1.0 -TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar -MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar - -TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR) -MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR) - $(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala) cd $(base_dir) && $(SBT) "tapeout/assembly" @@ -54,13 +42,32 @@ $(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macr .PHONY: jars jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) +######################################################################################### +# tapeout and macrocompiler commands +######################################################################################### +TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR) +MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR) + +######################################################################################### +# create simulation args file rule +######################################################################################### $(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" +######################################################################################### +# create firrtl file rule and variables +######################################################################################### +CHISEL_ARGS ?= + $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) mkdir -p $(build_dir) cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" +######################################################################################### +# create verilog files rules and variables +######################################################################################### +REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) + $(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir) @@ -71,6 +78,23 @@ $(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR) $(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops +######################################################################################### +# run assembly/benchmarks rules +######################################################################################### +$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% + mkdir -p $(output_dir) + ln -sf $< $@ + +$(output_dir)/%.run: $(output_dir)/% $(sim) + $(sim) +max-cycles=$(timeout_cycles) $< && touch $@ + +$(output_dir)/%.out: $(output_dir)/% $(sim) + $(sim) +verbose +max-cycles=$(timeout_cycles) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + +######################################################################################### +# default regression tests variables and rules +# TODO: Remove in favor of each project having its own regression tests? +######################################################################################### regression-tests = \ rv64ud-v-fcvt \ rv64ud-p-fdiv \ @@ -98,12 +122,14 @@ regression-tests = \ rv64um-v-mulh \ rv64si-p-dirty -output_dir=$(sim_dir)/output - -$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% - mkdir -p $(output_dir) - ln -sf $< $@ +.PHONY: run-regression-tests run-regression-tests-fast run-regression-tests-debug +run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) +run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) +run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) +######################################################################################### +# general jar cleanup rule +######################################################################################### .PHONY: clean-scala clean-scala: rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) diff --git a/Makefrag-Variables b/Makefrag-Variables new file mode 100644 index 00000000..18793d3d --- /dev/null +++ b/Makefrag-Variables @@ -0,0 +1,79 @@ +######################################################################################### +# makefile variables shared across multiple makefiles +######################################################################################### + +######################################################################################### +# default variables to invoke the generator +# descriptions: +# PROJECT = the scala package to find the MODEL in +# MODEL = the top level module of the project +# CONFIG = the configuration class to give the parameters for the project +# CFG_PROJECT = the scala package to find the CONFIG class +# TB = TODO +# TOP = TODO +######################################################################################### +PROJECT ?= example +MODEL ?= TestHarness +CONFIG ?= DefaultExampleConfig +CFG_PROJECT ?= $(PROJECT) +TB ?= TestDriver +TOP ?= ExampleTop + +######################################################################################### +# path to rocket-chip and testchipip +######################################################################################### +ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip +TESTCHIP_DIR = $(base_dir)/generators/testchipip + +######################################################################################### +# names of various files needed to compile and run things +######################################################################################### +long_name = $(PROJECT).$(MODEL).$(CONFIG) + +FIRRTL_FILE ?= $(build_dir)/$(long_name).fir +ANNO_FILE ?= $(build_dir)/$(long_name).anno.json +VERILOG_FILE ?= $(build_dir)/$(long_name).top.v +HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v +SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v +SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf +sim_dotf ?= $(build_dir)/sim_files.f + +######################################################################################### +# default sbt launch command +######################################################################################### +SCALA_VERSION=2.12.4 +SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) + +SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION) + +######################################################################################### +# output directory for tests +######################################################################################### +output_dir=$(sim_dir)/output + +######################################################################################### +# build output directory for compilation +######################################################################################### +build_dir=$(sim_dir)/generated-src + +######################################################################################### +# vsrcs needed to run projects +######################################################################################### +rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc + +######################################################################################### +# sources needed to run simulators +######################################################################################### +sim_blackboxes = \ + $(build_dir)/firrtl_black_box_resource_files.f + +sim_vsrcs = \ + $(VERILOG_FILE) \ + $(HARNESS_FILE) \ + $(SMEMS_FILE) + +######################################################################################### +# assembly/benchmark variables +######################################################################################### +timeout_cycles = 10000000 +bmark_timeout_cycles = 100000000 diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 74950993..f75fb5f1 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -1,38 +1,43 @@ +######################################################################################### +# verilator makefile +######################################################################################### + +######################################################################################### +# general path variables +######################################################################################### base_dir=$(abspath ../..) sim_dir=$(abspath .) -PROJECT ?= example -MODEL ?= TestHarness -CONFIG ?= DefaultExampleConfig -CFG_PROJECT ?= $(PROJECT) -TB ?= TestDriver -TOP ?= ExampleTop +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/Makefrag-Variables +######################################################################################### +# name of simulator (used to generate *.f arguments file) +######################################################################################### sim_name = verilator -sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG) -sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug +######################################################################################### +# vcs simulator types and rules +######################################################################################### +sim_prefix = simulator +sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG) +sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug +.PHONY: default debug default: $(sim) - debug: $(sim_debug) -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread - +######################################################################################### +# import other necessary rules and variables +######################################################################################### include $(base_dir)/Makefrag -include $(sim_dir)/Makefrag-verilator - -sim_blackboxes = \ - $(build_dir)/firrtl_black_box_resource_files.f - -rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc - -sim_vsrcs = \ - $(VERILOG_FILE) \ - $(HARNESS_FILE) \ - $(SMEMS_FILE) +include $(sim_dir)/Makefrag-Verilator +######################################################################################### +# verilator build paths and file names +######################################################################################### model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug @@ -42,6 +47,11 @@ model_header_debug = $(model_dir_debug)/V$(MODEL).h model_mk = $(model_dir)/V$(MODEL).mk model_mk_debug = $(model_dir_debug)/V$(MODEL).mk +######################################################################################### +# build makefile fragment that builds the verilator sim rules +######################################################################################### +LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread + $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) @@ -50,10 +60,6 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" touch $@ -$(sim): $(model_mk) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk - - $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug @@ -62,25 +68,26 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" touch $@ +######################################################################################### +# invoke make to make verilator sim rules +######################################################################################### +$(sim): $(model_mk) + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk + $(sim_debug): $(model_mk_debug) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk -$(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@ - -$(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) +max-cycles=1000000 $< && touch $@ - +######################################################################################### +# create a vcs vpd rule +######################################################################################### $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - $(sim_debug) -v$@.vcd +max-cycles=1000000 $< - -run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) - -run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) - -run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) + $(sim_debug) -v$@.vcd +max-cycles=$(timeout_cycles) $< +######################################################################################### +# general cleanup rule +######################################################################################### +.PHONY: clean clean: clean-scala - rm -rf generated-src ./simulator-* + rm -rf $(build_dir) $(sim_prefix)-* diff --git a/sims/verisim/Makefrag-verilator b/sims/verisim/Makefrag-Verilator similarity index 54% rename from sims/verisim/Makefrag-verilator rename to sims/verisim/Makefrag-Verilator index f8ea0b4c..3af9b335 100644 --- a/sims/verisim/Makefrag-verilator +++ b/sims/verisim/Makefrag-Verilator @@ -1,7 +1,17 @@ -# Build and install our own Verilator, to work around versionining issues. -VERILATOR_VERSION=3.920 +######################################################################################### +# verilator installation makefrag +######################################################################################### + +######################################################################################### +# verilator version, binary, and path +######################################################################################### +VERILATOR_VERSION=4.008 VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) + +######################################################################################### +# build and install our own verilator to work around versioning issues +######################################################################################### $(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata touch $@ @@ -24,8 +34,11 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz: mkdir -p $(dir $@) wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ -# Run Verilator to produce a fast binary to emulate this circuit. +######################################################################################### +# verilator binary and flags +######################################################################################### VERILATOR := $(INSTALLED_VERILATOR) --cc --exe +CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS VERILATOR_FLAGS := --top-module $(MODEL) \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 41c73b58..451b4602 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -1,81 +1,102 @@ +######################################################################################### +# vcs makefile +######################################################################################### + +######################################################################################### +# general path variables +######################################################################################### base_dir=$(abspath ../..) sim_dir=$(abspath .) -PROJECT ?= example -MODEL ?= TestHarness -CONFIG ?= DefaultExampleConfig -CFG_PROJECT ?= $(PROJECT) -TB ?= TestDriver -TOP ?= ExampleTop +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/Makefrag-Variables +######################################################################################### +# name of simulator (used to generate *.f arguments file) +######################################################################################### sim_name = vcs -simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG) -simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug +######################################################################################### +# vcs simulator types and rules +######################################################################################### +sim_prefix = simv +sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG) +sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug -default: $(simv) - -debug: $(simv_debug) +.PHONY: default debug +default: $(sim) +debug: $(sim_debug) +######################################################################################### +# import other necessary rules and variables +######################################################################################### include $(base_dir)/Makefrag -sim_blackboxes = \ - $(build_dir)/firrtl_black_box_resource_files.f - -rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc - -sim_vsrcs = \ - $(VERILOG_FILE) \ - $(HARNESS_FILE) \ - $(SMEMS_FILE) - +######################################################################################### +# vcs binary and arguments +######################################################################################### VCS = vcs -full64 -VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \ - +rad +v2k +vcs+lic+wait \ - +vc+list -CC "-I$(VCS_HOME)/include" \ +VCS_CC_OPTS = \ + -CC "-I$(VCS_HOME)/include" \ -CC "-I$(RISCV)/include" \ -CC "-std=c++11" \ -CC "-Wl,-rpath,$(RISCV)/lib" \ - -f $(sim_blackboxes) -f $(sim_dotf) \ - $(RISCV)/lib/libfesvr.so \ + $(RISCV)/lib/libfesvr.so + +VCS_NONCC_OPTS = \ + +lint=all,noVCDE,noONGS,noUI \ + -error=PCWM-L \ + -timescale=1ns/10ps \ + -quiet \ + +rad \ + +v2k \ + +vcs+lic+wait \ + +vc+list \ + -f $(sim_blackboxes) \ + -f $(sim_dotf) \ -sverilog \ - +incdir+$(generated_dir) \ - +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \ + +incdir+$(build_dir) \ + +define+CLOCK_PERIOD=1.0 \ + $(sim_vsrcs) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE_MEM_INIT \ +define+RANDOMIZE_REG_INIT \ +define+RANDOMIZE_GARBAGE_ASSIGN \ +define+RANDOMIZE_INVALID_ASSIGN \ - +libext+.v \ + +libext+.v +VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) + +######################################################################################### +# helper rule to just make verilog files +######################################################################################### +.PHONY: verilog verilog: $(sim_vsrcs) -$(simv): $(sim_vsrcs) $(sim_dotf) +######################################################################################### +# vcs simulator rules +######################################################################################### +$(sim): $(sim_vsrcs) $(sim_dotf) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(simv_debug) : $(sim_vsrcs) $(sim_dotf) +$(sim_debug) : $(sim_vsrcs) $(sim_dotf) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp -$(output_dir)/%.out: $(output_dir)/% $(simv) - $(simv) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@ - -$(output_dir)/%.run: $(output_dir)/% $(simv) - $(simv) +max-cycles=1000000 $< && touch $@ - -$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug) - $(simv_debug) +vcdplusfile=$@ +max-cycles=1000000 $< - -run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) - -run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) - -run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) - -clean: - rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h +######################################################################################### +# create a vcs vpd rule +######################################################################################### +$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) + $(sim_debug) +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $< +######################################################################################### +# general cleanup rule +######################################################################################### .PHONY: clean +clean: clean-scala + rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h From 8b899c519d327e7391b0e52e1bf9b91f42348b53 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Mar 2019 16:47:27 -0800 Subject: [PATCH 015/120] rename makefiles | move verilog rule to common.mk --- Makefrag | 136 -------------------------------- Makefrag-Variables | 79 ------------------- sims/verisim/Makefile | 6 +- sims/verisim/Makefrag-Verilator | 47 ----------- sims/vsim/Makefile | 10 +-- 5 files changed, 5 insertions(+), 273 deletions(-) delete mode 100644 Makefrag delete mode 100644 Makefrag-Variables delete mode 100644 sims/verisim/Makefrag-Verilator diff --git a/Makefrag b/Makefrag deleted file mode 100644 index d5f009ec..00000000 --- a/Makefrag +++ /dev/null @@ -1,136 +0,0 @@ -######################################################################################### -# set default shell for make -######################################################################################### -SHELL=/bin/bash - -######################################################################################### -# variables to get all *.scala files -######################################################################################### -lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null) - -PACKAGES=rocket-chip testchipip -SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) - -######################################################################################### -# rocket and testchipip classes -######################################################################################### -ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" -TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes" - -######################################################################################### -# jar creation variables and rules -######################################################################################### -FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar - -# this should match whatever the commonSettings version is in build.sbt -BARSTOOLS_VER=1.0 -TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar -MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar - -$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala) - $(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala - mkdir -p $(dir $@) - cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@ - touch $@ - -$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala) - cd $(base_dir) && $(SBT) "tapeout/assembly" - -$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/tools/barstools/mdf/scalalib/src/main/scala) - cd $(base_dir) && $(SBT) "barstools-macros/assembly" - -.PHONY: jars -jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) - -######################################################################################### -# tapeout and macrocompiler commands -######################################################################################### -TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR) -MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR) - -######################################################################################### -# create simulation args file rule -######################################################################################### -$(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR) - cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" - -######################################################################################### -# create firrtl file rule and variables -######################################################################################### -CHISEL_ARGS ?= - -$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) - mkdir -p $(build_dir) - cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" - -######################################################################################### -# create verilog files rules and variables -######################################################################################### -REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) - -$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) - $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir) - -$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) - $(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir) - -# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs -$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR) - $(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops - -######################################################################################### -# run assembly/benchmarks rules -######################################################################################### -$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% - mkdir -p $(output_dir) - ln -sf $< $@ - -$(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) +max-cycles=$(timeout_cycles) $< && touch $@ - -$(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) +verbose +max-cycles=$(timeout_cycles) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ - -######################################################################################### -# default regression tests variables and rules -# TODO: Remove in favor of each project having its own regression tests? -######################################################################################### -regression-tests = \ - rv64ud-v-fcvt \ - rv64ud-p-fdiv \ - rv64ud-v-fadd \ - rv64uf-v-fadd \ - rv64um-v-mul \ - rv64mi-p-breakpoint \ - rv64uc-v-rvc \ - rv64ud-v-structural \ - rv64si-p-wfi \ - rv64um-v-divw \ - rv64ua-v-lrsc \ - rv64ui-v-fence_i \ - rv64ud-v-fcvt_w \ - rv64uf-v-fmin \ - rv64ui-v-sb \ - rv64ua-v-amomax_d \ - rv64ud-v-move \ - rv64ud-v-fclass \ - rv64ua-v-amoand_d \ - rv64ua-v-amoxor_d \ - rv64si-p-sbreak \ - rv64ud-v-fmadd \ - rv64uf-v-ldst \ - rv64um-v-mulh \ - rv64si-p-dirty - -.PHONY: run-regression-tests run-regression-tests-fast run-regression-tests-debug -run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) -run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) -run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) - -######################################################################################### -# general jar cleanup rule -######################################################################################### -.PHONY: clean-scala -clean-scala: - rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) - diff --git a/Makefrag-Variables b/Makefrag-Variables deleted file mode 100644 index 18793d3d..00000000 --- a/Makefrag-Variables +++ /dev/null @@ -1,79 +0,0 @@ -######################################################################################### -# makefile variables shared across multiple makefiles -######################################################################################### - -######################################################################################### -# default variables to invoke the generator -# descriptions: -# PROJECT = the scala package to find the MODEL in -# MODEL = the top level module of the project -# CONFIG = the configuration class to give the parameters for the project -# CFG_PROJECT = the scala package to find the CONFIG class -# TB = TODO -# TOP = TODO -######################################################################################### -PROJECT ?= example -MODEL ?= TestHarness -CONFIG ?= DefaultExampleConfig -CFG_PROJECT ?= $(PROJECT) -TB ?= TestDriver -TOP ?= ExampleTop - -######################################################################################### -# path to rocket-chip and testchipip -######################################################################################### -ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip -TESTCHIP_DIR = $(base_dir)/generators/testchipip - -######################################################################################### -# names of various files needed to compile and run things -######################################################################################### -long_name = $(PROJECT).$(MODEL).$(CONFIG) - -FIRRTL_FILE ?= $(build_dir)/$(long_name).fir -ANNO_FILE ?= $(build_dir)/$(long_name).anno.json -VERILOG_FILE ?= $(build_dir)/$(long_name).top.v -HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v -SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v -SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf -sim_dotf ?= $(build_dir)/sim_files.f - -######################################################################################### -# default sbt launch command -######################################################################################### -SCALA_VERSION=2.12.4 -SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) - -SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION) - -######################################################################################### -# output directory for tests -######################################################################################### -output_dir=$(sim_dir)/output - -######################################################################################### -# build output directory for compilation -######################################################################################### -build_dir=$(sim_dir)/generated-src - -######################################################################################### -# vsrcs needed to run projects -######################################################################################### -rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc - -######################################################################################### -# sources needed to run simulators -######################################################################################### -sim_blackboxes = \ - $(build_dir)/firrtl_black_box_resource_files.f - -sim_vsrcs = \ - $(VERILOG_FILE) \ - $(HARNESS_FILE) \ - $(SMEMS_FILE) - -######################################################################################### -# assembly/benchmark variables -######################################################################################### -timeout_cycles = 10000000 -bmark_timeout_cycles = 100000000 diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index f75fb5f1..8049bab9 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -11,7 +11,7 @@ sim_dir=$(abspath .) ######################################################################################### # include shared variables ######################################################################################### -include $(base_dir)/Makefrag-Variables +include $(base_dir)/variables.mk ######################################################################################### # name of simulator (used to generate *.f arguments file) @@ -32,8 +32,8 @@ debug: $(sim_debug) ######################################################################################### # import other necessary rules and variables ######################################################################################### -include $(base_dir)/Makefrag -include $(sim_dir)/Makefrag-Verilator +include $(base_dir)/common.mk +include $(sim_dir)/verilator.mk ######################################################################################### # verilator build paths and file names diff --git a/sims/verisim/Makefrag-Verilator b/sims/verisim/Makefrag-Verilator deleted file mode 100644 index 3af9b335..00000000 --- a/sims/verisim/Makefrag-Verilator +++ /dev/null @@ -1,47 +0,0 @@ -######################################################################################### -# verilator installation makefrag -######################################################################################### - -######################################################################################### -# verilator version, binary, and path -######################################################################################### -VERILATOR_VERSION=4.008 -VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) -INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) - -######################################################################################### -# build and install our own verilator to work around versioning issues -######################################################################################### -$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator - $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata - touch $@ - -$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile - $(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin - touch $@ - -$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure - mkdir -p $(dir $@) - cd $(dir $@) && ./configure --prefix=$(abspath verilator/install) - -$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz - rm -rf $(dir $@) - mkdir -p $(dir $@) - cat $^ | tar -xz --strip-components=1 -C $(dir $@) - touch $@ - -verilator/verilator-$(VERILATOR_VERSION).tar.gz: - mkdir -p $(dir $@) - wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ - -######################################################################################### -# verilator binary and flags -######################################################################################### -VERILATOR := $(INSTALLED_VERILATOR) --cc --exe -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS -VERILATOR_FLAGS := --top-module $(MODEL) \ - +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ - --output-split 20000 \ - -Wno-STMTDLY --x-assign unique \ - -O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR" diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 451b4602..022e8079 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -11,7 +11,7 @@ sim_dir=$(abspath .) ######################################################################################### # include shared variables ######################################################################################### -include $(base_dir)/Makefrag-Variables +include $(base_dir)/variables.mk ######################################################################################### # name of simulator (used to generate *.f arguments file) @@ -32,7 +32,7 @@ debug: $(sim_debug) ######################################################################################### # import other necessary rules and variables ######################################################################################### -include $(base_dir)/Makefrag +include $(base_dir)/common.mk ######################################################################################### # vcs binary and arguments @@ -71,12 +71,6 @@ VCS_NONCC_OPTS = \ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) -######################################################################################### -# helper rule to just make verilog files -######################################################################################### -.PHONY: verilog -verilog: $(sim_vsrcs) - ######################################################################################### # vcs simulator rules ######################################################################################### From d80acd8cf837331664146fb4c41f91d1905cb342 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Mar 2019 17:13:08 -0800 Subject: [PATCH 016/120] added boom and torture | added csmith --- .gitmodules | 6 + build.sbt | 3 + common.mk | 2 +- generators/boom | 1 + scripts/csmith/install-csmith.sh | 6 + scripts/csmith/run-csmith.sh | 188 ++++ scripts/csmith/sources/crt.S | 237 +++++ scripts/csmith/sources/encoding.h | 1471 +++++++++++++++++++++++++++++ scripts/csmith/sources/link.ld | 66 ++ scripts/csmith/sources/syscalls.c | 471 +++++++++ scripts/csmith/sources/util.h | 90 ++ tools/torture | 1 + 12 files changed, 2541 insertions(+), 1 deletion(-) create mode 160000 generators/boom create mode 100755 scripts/csmith/install-csmith.sh create mode 100755 scripts/csmith/run-csmith.sh create mode 100644 scripts/csmith/sources/crt.S create mode 100644 scripts/csmith/sources/encoding.h create mode 100644 scripts/csmith/sources/link.ld create mode 100644 scripts/csmith/sources/syscalls.c create mode 100644 scripts/csmith/sources/util.h create mode 160000 tools/torture diff --git a/.gitmodules b/.gitmodules index 72203f96..3d3a7a73 100644 --- a/.gitmodules +++ b/.gitmodules @@ -19,3 +19,9 @@ [submodule "esp-tools"] path = toolchains/esp-tools url = https://github.com/ucb-bar/esp-tools.git +[submodule "tools/torture"] + path = tools/torture + url = git@github.com:ucb-bar/riscv-torture.git +[submodule "generators/boom"] + path = generators/boom + url = git@github.com:riscv-boom/riscv-boom.git diff --git a/build.sbt b/build.sbt index 2d217ba4..a251d86d 100644 --- a/build.sbt +++ b/build.sbt @@ -24,6 +24,9 @@ lazy val rocketchip = RootProject(file("generators/rocket-chip")) lazy val testchipip = (project in file("generators/testchipip")).settings(commonSettings) .dependsOn(rocketchip) +lazy val boom = (project in file("generators/boom")).settings(commonSettings) + .dependsOn(rocketchip) + // Checks for -DROCKET_USE_MAVEN. // If it's there, use a maven dependency. // Else, depend on subprojects in git submodules. diff --git a/common.mk b/common.mk index 2f99a048..43097731 100644 --- a/common.mk +++ b/common.mk @@ -8,7 +8,7 @@ SHELL=/bin/bash ######################################################################################### lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null) -PACKAGES=rocket-chip testchipip +PACKAGES=rocket-chip testchipip boom SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) ######################################################################################### diff --git a/generators/boom b/generators/boom new file mode 160000 index 00000000..c7489137 --- /dev/null +++ b/generators/boom @@ -0,0 +1 @@ +Subproject commit c7489137d420b5095a78ab6c64ded56a4581397a diff --git a/scripts/csmith/install-csmith.sh b/scripts/csmith/install-csmith.sh new file mode 100755 index 00000000..5b7576a7 --- /dev/null +++ b/scripts/csmith/install-csmith.sh @@ -0,0 +1,6 @@ +git clone https://github.com/csmith-project/csmith.git +cd csmith +mkdir build +cd build +../configure --prefix=$RISCV +make install diff --git a/scripts/csmith/run-csmith.sh b/scripts/csmith/run-csmith.sh new file mode 100755 index 00000000..e668fa89 --- /dev/null +++ b/scripts/csmith/run-csmith.sh @@ -0,0 +1,188 @@ +# Script to run the csmith random test generator multiple times + +TEST_NAME=test +SIM=$1 +RUN_AMT=-1 +P_INST=1 +SEED=-1 +WDEBUG_EXT=false +NDEBUG=false + +# Make output directory +OUTPUT_DIR=output +SRC_DIR=sources +mkdir -p output + +usage(){ + echo "run-csmith.sh --sim SIM_BINARY [--run RUN_AMT] [--parallel PARALLEL_INSTANCES] [--seed SEED] [--withdebugext] [--nodebug]" + echo " --sim -s SIM_BINARY is the simulator to test spike against" + echo " --run -r RUN_AMT is the amount of times to run the csmith tests" + echo " defaults to infinity" + echo " --parallel -p PARALLEL_INSTANCES is the amount of instances to spawn in parallel" + echo " defaults to one instance" + echo " --seed -e SEED runs a single test with the seed specified" + echo " ignores all other parameters" + echo " --withdebugext -d run debug version of simulator (used for when" + echo " main sim is not debug version)" + echo " (just appends -debug to sim name)" + echo " --nodebug -n just error when there is a sim mismatch (no vpd)" +} + +# Exit everything on one ctrl+c +trap kill_group SIGINT +kill_group(){ + echo "" + echo "[ALL] Killing instances." + kill 0 +} + +# Run the csmith test once +# +# Args: +# $1 instance that this test is running on +# $2 seed to run the test with +run_once () { + BASE_NAME=$OUTPUT_DIR/$TEST_NAME-$1-$2 + + echo "[$1] Running csmith test with seed=$2" + csmith --seed $2 > $BASE_NAME.c + + # Build both a RISCV binary and normal binary + + # Test x86-64 first + gcc -I$RISCV/include/csmith-2.4.0 -w $BASE_NAME.c -o $BASE_NAME.bin + timeout 1s ./$BASE_NAME.bin | awk '{print tolower($0)}' > $BASE_NAME.host.out + RV=$? + if [ $RV -ne 0 ]; then + echo "[$1] x86-64 binary timed out. Discard and start over." + rm $BASE_NAME.bin $BASE_NAME.host.out $BASE_NAME.c + return 0 + fi + + # Test RISCV spike version + riscv64-unknown-elf-gcc -w -I./$SRC_DIR -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -o $BASE_NAME.riscv $BASE_NAME.c $SRC_DIR/syscalls.c $SRC_DIR/crt.S -static -nostdlib -nostartfiles -lm -lgcc -T $SRC_DIR/link.ld -I$RISCV/include/csmith-2.4.0 + timeout --foreground 10s spike $BASE_NAME.riscv 1> $BASE_NAME.spike.out 2> $BASE_NAME.spike.log + RV=$? + if [ $RV -ne 0 ]; then + echo "[$1] Spike timed out. Discard and start over." + rm $BASE_NAME.bin $BASE_NAME.host.out $BASE_NAME.c $BASE_NAME.riscv $BASE_NAME.spike.out $BASE_NAME.spike.log + return 0 + fi + + # Compare x86-64 and Spike + cmp -s $BASE_NAME.spike.out $BASE_NAME.host.out + RV=$? + if [ $RV -ne 0 ]; then + echo "[$1] Spike produces wrong result compared to x86-64 binary. Discard and start over." + rm $BASE_NAME.bin $BASE_NAME.host.out $BASE_NAME.c $BASE_NAME.riscv $BASE_NAME.spike.out $BASE_NAME.spike.log + return 0 + fi + + # Compare simulator output versus spike + timeout 15m $SIM $BASE_NAME.riscv 1> $BASE_NAME.sim.out + RV=$? + if [ $RV == 124 ]; then + echo "[$1] Simulator timed out. Discard and start over." + rm $BASE_NAME.bin $BASE_NAME.host.out $BASE_NAME.c $BASE_NAME.riscv $BASE_NAME.spike.out $BASE_NAME.spike.log $BASE_NAME.sim.out + return 0 + fi + + cmp -s $BASE_NAME.sim.out $BASE_NAME.spike.out + RV=$? + if [ $RV -ne 0 ]; then + echo "[$1] Simulator produced wrong result." + if [ $NDEBUG == false ]; then + if [ $WDEBUG_EXT == true ]; then + ${SIM}-debug $BASE_NAME.riscv +verbose +vcdplusfile=$BASE_NAME.vpd 1> $BASE_NAME.sim.out 2> $BASE_NAME.sim.log + else + $SIM $BASE_NAME.riscv +verbose +vcdplusfile=$BASE_NAME.vpd 1> $BASE_NAME.sim.out 2> $BASE_NAME.sim.log + fi + echo "[$1] Vpd of error file: $BASE_NAME.vpd" + echo "[$1] Simulator output file: $BASE_NAME.sim.out" + echo "[$1] Simulator log file: $BASE_NAME.sim.log" + fi + kill_group + else + echo "[$1] Simulator and spike agree." + rm $BASE_NAME.bin $BASE_NAME.host.out $BASE_NAME.c $BASE_NAME.riscv $BASE_NAME.spike.out $BASE_NAME.spike.log $BASE_NAME.sim.out + return 0 + fi +} + +# Run the test for a certain amount of times +# Also setup a random seed +# +# Args: +# $1 instance that this is running on +run() { + if [ $SEED == -1 ]; then + if [ $RUN_AMT == -1 ]; then + while true; + do + SEED=$(od -N 4 -t uL -An /dev/urandom | tr -d " ") + run_once $1 $SEED + done + else + for j in `seq 1 $RUN_AMT`; + do + SEED=$(od -N 4 -t uL -An /dev/urandom | tr -d " ") + run_once $1 $SEED + done + fi + else + run_once $1 $SEED + fi +} + +# Parse arguments +while [ "$1" != "" ]; +do + case $1 in + -s | --sim ) shift + SIM=$1 + ;; + -r | --run ) shift + RUN_AMT=$1 + ;; + -p | --parallel ) shift + P_INST=$1 + ;; + -e | --seed ) shift + SEED=$1 + ;; + --withdebugext | -d ) shift + WDEBUG_EXT=true + ;; + --nodebug | -n ) shift + NDEBUG=true + ;; + -h | --help ) usage + exit 0 + esac + shift +done + +# Start of script +if [ -z "$SIM" ]; then + echo "Forgot simulator binary." + usage + exit 1 +fi + +if [ $SEED == -1 ]; then + if [ $RUN_AMT == -1 ]; then + echo "Spawning $P_INST instance(s), running csmith infinite times" + else + echo "Spawning $P_INST instance(s), running csmith $RUN_AMT times" + fi + + for i in `seq 1 $P_INST`; + do + run $i & + done + wait +else + RUN_AMT=1 + run 1 + wait +fi diff --git a/scripts/csmith/sources/crt.S b/scripts/csmith/sources/crt.S new file mode 100644 index 00000000..d75e81e0 --- /dev/null +++ b/scripts/csmith/sources/crt.S @@ -0,0 +1,237 @@ +# See LICENSE for license details. + +#include "encoding.h" + +#if __riscv_xlen == 64 +# define LREG ld +# define SREG sd +# define REGBYTES 8 +#else +# define LREG lw +# define SREG sw +# define REGBYTES 4 +#endif + + .section ".text.init" + .globl _start +_start: + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10,0 + li x11,0 + li x12,0 + li x13,0 + li x14,0 + li x15,0 + li x16,0 + li x17,0 + li x18,0 + li x19,0 + li x20,0 + li x21,0 + li x22,0 + li x23,0 + li x24,0 + li x25,0 + li x26,0 + li x27,0 + li x28,0 + li x29,0 + li x30,0 + li x31,0 + + # enable FPU and accelerator if present + li t0, MSTATUS_FS | MSTATUS_XS + csrs mstatus, t0 + + # make sure XLEN agrees with compilation choice + li t0, 1 + slli t0, t0, 31 +#if __riscv_xlen == 64 + bgez t0, 1f +#else + bltz t0, 1f +#endif +2: + li a0, 1 + sw a0, tohost, t0 + j 2b +1: + +#ifdef __riscv_flen + # initialize FPU if we have one + la t0, 1f + csrw mtvec, t0 + + fssr x0 + fmv.s.x f0, x0 + fmv.s.x f1, x0 + fmv.s.x f2, x0 + fmv.s.x f3, x0 + fmv.s.x f4, x0 + fmv.s.x f5, x0 + fmv.s.x f6, x0 + fmv.s.x f7, x0 + fmv.s.x f8, x0 + fmv.s.x f9, x0 + fmv.s.x f10,x0 + fmv.s.x f11,x0 + fmv.s.x f12,x0 + fmv.s.x f13,x0 + fmv.s.x f14,x0 + fmv.s.x f15,x0 + fmv.s.x f16,x0 + fmv.s.x f17,x0 + fmv.s.x f18,x0 + fmv.s.x f19,x0 + fmv.s.x f20,x0 + fmv.s.x f21,x0 + fmv.s.x f22,x0 + fmv.s.x f23,x0 + fmv.s.x f24,x0 + fmv.s.x f25,x0 + fmv.s.x f26,x0 + fmv.s.x f27,x0 + fmv.s.x f28,x0 + fmv.s.x f29,x0 + fmv.s.x f30,x0 + fmv.s.x f31,x0 +1: +#endif + + # initialize trap vector + la t0, trap_entry + csrw mtvec, t0 + + # initialize global pointer +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + la tp, _end + 63 + and tp, tp, -64 + + # get core id + csrr a0, mhartid + # for now, assume only 1 core + li a1, 1 +1:bgeu a0, a1, 1b + + # give each core 128KB of stack + TLS +#define STKSHIFT 17 + sll a2, a0, STKSHIFT + add tp, tp, a2 + add sp, a0, 1 + sll sp, sp, STKSHIFT + add sp, sp, tp + + j _init + + .align 2 +trap_entry: + addi sp, sp, -272 + + SREG x1, 1*REGBYTES(sp) + SREG x2, 2*REGBYTES(sp) + SREG x3, 3*REGBYTES(sp) + SREG x4, 4*REGBYTES(sp) + SREG x5, 5*REGBYTES(sp) + SREG x6, 6*REGBYTES(sp) + SREG x7, 7*REGBYTES(sp) + SREG x8, 8*REGBYTES(sp) + SREG x9, 9*REGBYTES(sp) + SREG x10, 10*REGBYTES(sp) + SREG x11, 11*REGBYTES(sp) + SREG x12, 12*REGBYTES(sp) + SREG x13, 13*REGBYTES(sp) + SREG x14, 14*REGBYTES(sp) + SREG x15, 15*REGBYTES(sp) + SREG x16, 16*REGBYTES(sp) + SREG x17, 17*REGBYTES(sp) + SREG x18, 18*REGBYTES(sp) + SREG x19, 19*REGBYTES(sp) + SREG x20, 20*REGBYTES(sp) + SREG x21, 21*REGBYTES(sp) + SREG x22, 22*REGBYTES(sp) + SREG x23, 23*REGBYTES(sp) + SREG x24, 24*REGBYTES(sp) + SREG x25, 25*REGBYTES(sp) + SREG x26, 26*REGBYTES(sp) + SREG x27, 27*REGBYTES(sp) + SREG x28, 28*REGBYTES(sp) + SREG x29, 29*REGBYTES(sp) + SREG x30, 30*REGBYTES(sp) + SREG x31, 31*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + jal handle_trap + csrw mepc, a0 + + # Remain in M-mode after eret + li t0, MSTATUS_MPP + csrs mstatus, t0 + + LREG x1, 1*REGBYTES(sp) + LREG x2, 2*REGBYTES(sp) + LREG x3, 3*REGBYTES(sp) + LREG x4, 4*REGBYTES(sp) + LREG x5, 5*REGBYTES(sp) + LREG x6, 6*REGBYTES(sp) + LREG x7, 7*REGBYTES(sp) + LREG x8, 8*REGBYTES(sp) + LREG x9, 9*REGBYTES(sp) + LREG x10, 10*REGBYTES(sp) + LREG x11, 11*REGBYTES(sp) + LREG x12, 12*REGBYTES(sp) + LREG x13, 13*REGBYTES(sp) + LREG x14, 14*REGBYTES(sp) + LREG x15, 15*REGBYTES(sp) + LREG x16, 16*REGBYTES(sp) + LREG x17, 17*REGBYTES(sp) + LREG x18, 18*REGBYTES(sp) + LREG x19, 19*REGBYTES(sp) + LREG x20, 20*REGBYTES(sp) + LREG x21, 21*REGBYTES(sp) + LREG x22, 22*REGBYTES(sp) + LREG x23, 23*REGBYTES(sp) + LREG x24, 24*REGBYTES(sp) + LREG x25, 25*REGBYTES(sp) + LREG x26, 26*REGBYTES(sp) + LREG x27, 27*REGBYTES(sp) + LREG x28, 28*REGBYTES(sp) + LREG x29, 29*REGBYTES(sp) + LREG x30, 30*REGBYTES(sp) + LREG x31, 31*REGBYTES(sp) + + addi sp, sp, 272 + mret + +.section ".tdata.begin" +.globl _tdata_begin +_tdata_begin: + +.section ".tdata.end" +.globl _tdata_end +_tdata_end: + +.section ".tbss.end" +.globl _tbss_end +_tbss_end: + +.section ".tohost","aw",@progbits +.align 6 +.globl tohost +tohost: .dword 0 +.align 6 +.globl fromhost +fromhost: .dword 0 diff --git a/scripts/csmith/sources/encoding.h b/scripts/csmith/sources/encoding.h new file mode 100644 index 00000000..c109ce18 --- /dev/null +++ b/scripts/csmith/sources/encoding.h @@ -0,0 +1,1471 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/scripts/csmith/sources/link.ld b/scripts/csmith/sources/link.ld new file mode 100644 index 00000000..4f8892ee --- /dev/null +++ b/scripts/csmith/sources/link.ld @@ -0,0 +1,66 @@ +/*======================================================================*/ +/* Proxy kernel linker script */ +/*======================================================================*/ +/* This is the linker script used when building the proxy kernel. */ + +/*----------------------------------------------------------------------*/ +/* Setup */ +/*----------------------------------------------------------------------*/ + +/* The OUTPUT_ARCH command specifies the machine architecture where the + argument is one of the names used in the BFD library. More + specifically one of the entires in bfd/cpu-mips.c */ + +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ + +SECTIONS +{ + + /* text: test code section */ + . = 0x80000000; + .text.init : { *(.text.init) } + + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + + .text : { *(.text) } + + /* data segment */ + .data : { *(.data) } + + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + + /* bss segment */ + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { *(.bss) } + + /* thread-local data segment */ + .tdata : + { + _tls_data = .; + *(.tdata.begin) + *(.tdata) + *(.tdata.end) + } + .tbss : + { + *(.tbss) + *(.tbss.end) + } + + /* End of uninitalized data segement */ + _end = .; +} + diff --git a/scripts/csmith/sources/syscalls.c b/scripts/csmith/sources/syscalls.c new file mode 100644 index 00000000..6a719326 --- /dev/null +++ b/scripts/csmith/sources/syscalls.c @@ -0,0 +1,471 @@ +// See LICENSE for license details. + +#include +#include +#include +#include +#include +#include +#include "util.h" + +#define SYS_write 64 + +#undef strcmp + +extern volatile uint64_t tohost; +extern volatile uint64_t fromhost; + +static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2) +{ + volatile uint64_t magic_mem[8] __attribute__((aligned(64))); + magic_mem[0] = which; + magic_mem[1] = arg0; + magic_mem[2] = arg1; + magic_mem[3] = arg2; + __sync_synchronize(); + + tohost = (uintptr_t)magic_mem; + while (fromhost == 0) + ; + fromhost = 0; + + __sync_synchronize(); + return magic_mem[0]; +} + +#define NUM_COUNTERS 2 +static uintptr_t counters[NUM_COUNTERS]; +static char* counter_names[NUM_COUNTERS]; + +void setStats(int enable) +{ + int i = 0; +#define READ_CTR(name) do { \ + while (i >= NUM_COUNTERS) ; \ + uintptr_t csr = read_csr(name); \ + if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \ + counters[i++] = csr; \ + } while (0) + + READ_CTR(mcycle); + READ_CTR(minstret); + +#undef READ_CTR +} + +void __attribute__((noreturn)) tohost_exit(uintptr_t code) +{ + tohost = (code << 1) | 1; + while (1); +} + +uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) +{ + tohost_exit(1337); +} + +void exit(int code) +{ + tohost_exit(code); +} + +void abort() +{ + exit(128 + SIGABRT); +} + +void printstr(const char* s) +{ + syscall(SYS_write, 1, (uintptr_t)s, strlen(s)); +} + +void __attribute__((weak)) thread_entry(int cid, int nc) +{ + // multi-threaded programs override this function. + // for the case of single-threaded programs, only let core 0 proceed. + while (cid != 0); +} + +int __attribute__((weak)) main(int argc, char** argv) +{ + // single-threaded programs override this function. + printstr("Implement main(), foo!\n"); + return -1; +} + +static void init_tls() +{ + register void* thread_pointer asm("tp"); + extern char _tls_data; + extern __thread char _tdata_begin, _tdata_end, _tbss_end; + size_t tdata_size = &_tdata_end - &_tdata_begin; + memcpy(thread_pointer, &_tls_data, tdata_size); + size_t tbss_size = &_tbss_end - &_tdata_end; + memset(thread_pointer + tdata_size, 0, tbss_size); +} + +void _init(int cid, int nc) +{ + init_tls(); + thread_entry(cid, nc); + + // only single-threaded programs should ever get here. + int ret = main(0, 0); + + char buf[NUM_COUNTERS * 32] __attribute__((aligned(64))); + char* pbuf = buf; + for (int i = 0; i < NUM_COUNTERS; i++) + if (counters[i]) + pbuf += sprintf(pbuf, "%s = %d\n", counter_names[i], counters[i]); + if (pbuf != buf) + printstr(buf); + + exit(ret); +} + +#undef putchar +int putchar(int ch) +{ + static __thread char buf[64] __attribute__((aligned(64))); + static __thread int buflen = 0; + + buf[buflen++] = ch; + + if (ch == '\n' || buflen == sizeof(buf)) + { + syscall(SYS_write, 1, (uintptr_t)buf, buflen); + buflen = 0; + } + + return 0; +} + +void printhex(uint64_t x) +{ + char str[17]; + int i; + for (i = 0; i < 16; i++) + { + str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); + x >>= 4; + } + str[16] = 0; + + printstr(str); +} + +static inline void printnum(void (*putch)(int, void**), void **putdat, + unsigned long long num, unsigned base, int width, int padc) +{ + unsigned digs[sizeof(num)*CHAR_BIT]; + int pos = 0; + + while (1) + { + digs[pos++] = num % base; + if (num < base) + break; + num /= base; + } + + while (width-- > pos) + putch(padc, putdat); + + while (pos-- > 0) + putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); +} + +static unsigned long long getuint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, unsigned long long); + else if (lflag) + return va_arg(*ap, unsigned long); + else + return va_arg(*ap, unsigned int); +} + +static long long getint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, long long); + else if (lflag) + return va_arg(*ap, long); + else + return va_arg(*ap, int); +} + +static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) +{ + register const char* p; + const char* last_fmt; + register int ch, err; + unsigned long long num; + int base, lflag, width, precision, altflag; + char padc; + + while (1) { + while ((ch = *(unsigned char *) fmt) != '%') { + if (ch == '\0') + return; + fmt++; + putch(ch, putdat); + } + fmt++; + + // Process a %-escape sequence + last_fmt = fmt; + padc = ' '; + width = -1; + precision = -1; + lflag = 0; + altflag = 0; + reswitch: + switch (ch = *(unsigned char *) fmt++) { + + // flag to pad on the right + case '-': + padc = '-'; + goto reswitch; + + // flag to pad with 0's instead of spaces + case '0': + padc = '0'; + goto reswitch; + + // width field + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (precision = 0; ; ++fmt) { + precision = precision * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + goto process_precision; + + case '*': + precision = va_arg(ap, int); + goto process_precision; + + case '.': + if (width < 0) + width = 0; + goto reswitch; + + case '#': + altflag = 1; + goto reswitch; + + process_precision: + if (width < 0) + width = precision, precision = -1; + goto reswitch; + + // long flag (doubled for long long) + case 'l': + lflag++; + goto reswitch; + + // character + case 'c': + putch(va_arg(ap, int), putdat); + break; + + // string + case 's': + if ((p = va_arg(ap, char *)) == NULL) + p = "(null)"; + if (width > 0 && padc != '-') + for (width -= strnlen(p, precision); width > 0; width--) + putch(padc, putdat); + for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { + putch(ch, putdat); + p++; + } + for (; width > 0; width--) + putch(' ', putdat); + break; + + // (signed) decimal + case 'd': + num = getint(&ap, lflag); + if ((long long) num < 0) { + putch('-', putdat); + num = -(long long) num; + } + base = 10; + goto signed_number; + + // unsigned decimal + case 'u': + base = 10; + goto unsigned_number; + + // (unsigned) octal + case 'o': + // should do something with padding so it's always 3 octits + base = 8; + goto unsigned_number; + + // pointer + case 'p': + static_assert(sizeof(long) == sizeof(void*)); + lflag = 1; + putch('0', putdat); + putch('x', putdat); + /* fall through to 'x' */ + + // (unsigned) hexadecimal + case 'X': + case 'x': + base = 16; + unsigned_number: + num = getuint(&ap, lflag); + signed_number: + printnum(putch, putdat, num, base, width, padc); + break; + + // escaped '%' character + case '%': + putch(ch, putdat); + break; + + // unrecognized escape sequence - just print it literally + default: + putch('%', putdat); + fmt = last_fmt; + break; + } + } +} + +int printf(const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + + vprintfmt((void*)putchar, 0, fmt, ap); + + va_end(ap); + return 0; // incorrect return value, but who cares, anyway? +} + +int sprintf(char* str, const char* fmt, ...) +{ + va_list ap; + char* str0 = str; + va_start(ap, fmt); + + void sprintf_putch(int ch, void** data) + { + char** pstr = (char**)data; + **pstr = ch; + (*pstr)++; + } + + vprintfmt(sprintf_putch, (void**)&str, fmt, ap); + *str = 0; + + va_end(ap); + return str - str0; +} + +void* memcpy(void* dest, const void* src, size_t len) +{ + if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* s = src; + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = *s++; + } else { + const char* s = src; + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = *s++; + } + return dest; +} + +void* memset(void* dest, int byte, size_t len) +{ + if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { + uintptr_t word = byte & 0xFF; + word |= word << 8; + word |= word << 16; + word |= word << 16 << 16; + + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = word; + } else { + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = byte; + } + return dest; +} + +size_t strlen(const char *s) +{ + const char *p = s; + while (*p) + p++; + return p - s; +} + +size_t strnlen(const char *s, size_t n) +{ + const char *p = s; + while (n-- && *p) + p++; + return p - s; +} + +int strcmp(const char* s1, const char* s2) +{ + unsigned char c1, c2; + + do { + c1 = *s1++; + c2 = *s2++; + } while (c1 != 0 && c1 == c2); + + return c1 - c2; +} + +char* strcpy(char* dest, const char* src) +{ + char* d = dest; + while ((*d++ = *src++)) + ; + return dest; +} + +long atol(const char* str) +{ + long res = 0; + int sign = 0; + + while (*str == ' ') + str++; + + if (*str == '-' || *str == '+') { + sign = *str == '-'; + str++; + } + + while (*str) { + res *= 10; + res += *str++ - '0'; + } + + return sign ? -res : res; +} diff --git a/scripts/csmith/sources/util.h b/scripts/csmith/sources/util.h new file mode 100644 index 00000000..081cfd63 --- /dev/null +++ b/scripts/csmith/sources/util.h @@ -0,0 +1,90 @@ +// See LICENSE for license details. + +#ifndef __UTIL_H +#define __UTIL_H + +extern void setStats(int enable); + +#include + +#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; } + +static int verify(int n, const volatile int* test, const int* verify) +{ + int i; + // Unrolled for faster verification + for (i = 0; i < n/2*2; i+=2) + { + int t0 = test[i], t1 = test[i+1]; + int v0 = verify[i], v1 = verify[i+1]; + if (t0 != v0) return i+1; + if (t1 != v1) return i+2; + } + if (n % 2 != 0 && test[n-1] != verify[n-1]) + return n; + return 0; +} + +static int verifyDouble(int n, const volatile double* test, const double* verify) +{ + int i; + // Unrolled for faster verification + for (i = 0; i < n/2*2; i+=2) + { + double t0 = test[i], t1 = test[i+1]; + double v0 = verify[i], v1 = verify[i+1]; + int eq1 = t0 == v0, eq2 = t1 == v1; + if (!(eq1 & eq2)) return i+1+eq1; + } + if (n % 2 != 0 && test[n-1] != verify[n-1]) + return n; + return 0; +} + +static void __attribute__((noinline)) barrier(int ncores) +{ + static volatile int sense; + static volatile int count; + static __thread int threadsense; + + __sync_synchronize(); + + threadsense = !threadsense; + if (__sync_fetch_and_add(&count, 1) == ncores-1) + { + count = 0; + sense = threadsense; + } + else while(sense != threadsense) + ; + + __sync_synchronize(); +} + +static uint64_t lfsr(uint64_t x) +{ + uint64_t bit = (x ^ (x >> 1)) & 1; + return (x >> 1) | (bit << 62); +} + +static uintptr_t insn_len(uintptr_t pc) +{ + return (*(unsigned short*)pc & 3) ? 4 : 2; +} + +#ifdef __riscv +#include "encoding.h" +#endif + +#define stringify_1(s) #s +#define stringify(s) stringify_1(s) +#define stats(code, iter) do { \ + unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \ + code; \ + _c += read_csr(mcycle), _i += read_csr(minstret); \ + if (cid == 0) \ + printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \ + stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \ + } while(0) + +#endif //__UTIL_H diff --git a/tools/torture b/tools/torture new file mode 160000 index 00000000..59b0f0f2 --- /dev/null +++ b/tools/torture @@ -0,0 +1 @@ +Subproject commit 59b0f0f224ff4f1eb6ebb1b4dd7eaf1ab3fac2e5 From f45369365bb2f5c9b486c3be3384aaf4a05968bf Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Mar 2019 17:20:53 -0800 Subject: [PATCH 017/120] rename build.sh and move to scripts --- build.sh => scripts/init-submodules-no-riscv-tools.sh | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename build.sh => scripts/init-submodules-no-riscv-tools.sh (100%) mode change 100644 => 100755 diff --git a/build.sh b/scripts/init-submodules-no-riscv-tools.sh old mode 100644 new mode 100755 similarity index 100% rename from build.sh rename to scripts/init-submodules-no-riscv-tools.sh From 30ef609fb817018970fb78b311266a8e51eac4cf Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 8 Mar 2019 18:20:42 -0800 Subject: [PATCH 018/120] allow sbt runMain from sbt subproject --- common.mk | 2 +- variables.mk | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/common.mk b/common.mk index 43097731..7dee4727 100644 --- a/common.mk +++ b/common.mk @@ -61,7 +61,7 @@ CHISEL_ARGS ?= $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) mkdir -p $(build_dir) - cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" + cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" ######################################################################################### # create verilog files rules and variables diff --git a/variables.mk b/variables.mk index f44286c5..c944af1c 100644 --- a/variables.mk +++ b/variables.mk @@ -9,6 +9,7 @@ # MODEL = the top level module of the project (normally the harness) # CONFIG = the configuration class to give the parameters for the project # CFG_PROJECT = the scala package to find the CONFIG class +# SBT_PROJECT = the SBT project that you should find the Generator class in # TB = wrapper over the TestHarness needed to simulate in VCS # TOP = top level module of the project (normally the module instantiated by the harness) ######################################################################################### @@ -16,6 +17,7 @@ PROJECT ?= example MODEL ?= TestHarness CONFIG ?= DefaultExampleConfig CFG_PROJECT ?= $(PROJECT) +SBT_PROJECT ?= $(PROJECT) TB ?= TestDriver TOP ?= ExampleTop From 7d887b212ce755088fed811739a3db3376f37268 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Apr 2019 16:02:44 -0700 Subject: [PATCH 019/120] align rebar with tip of project-template master | fixes build issues --- common.mk | 43 ++++++-------------------- project/plugins.sbt | 2 ++ sims/verisim/Makefile | 4 +-- sims/vsim/Makefile | 3 +- src/main/scala/example/Simulator.scala | 1 + tools/barstools | 2 +- variables.mk | 10 ++++-- 7 files changed, 24 insertions(+), 41 deletions(-) diff --git a/common.mk b/common.mk index 2f99a048..0f9e176e 100644 --- a/common.mk +++ b/common.mk @@ -22,32 +22,12 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class ######################################################################################### FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar -# this should match whatever the commonSettings version is in build.sbt -BARSTOOLS_VER=1.0 -TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar -MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar - $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala) $(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala mkdir -p $(dir $@) cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@ touch $@ -$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala) - cd $(base_dir) && $(SBT) "tapeout/assembly" - -$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/tools/barstools/mdf/scalalib/src/main/scala) - cd $(base_dir) && $(SBT) "barstools-macros/assembly" - -.PHONY: jars -jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) - -######################################################################################### -# tapeout and macrocompiler commands -######################################################################################### -TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR) -MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR) - ######################################################################################### # create simulation args file rule ######################################################################################### @@ -68,15 +48,18 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) ######################################################################################### REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) -$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) - $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir) +$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" + cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) -$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) - $(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir) +$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)" + grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs -$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR) - $(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops +MACROCOMPILER_MODE ?= --mode synflops +$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) + cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)" ######################################################################################### # helper rule to just make verilog files @@ -139,11 +122,3 @@ regression-tests = \ run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) - -######################################################################################### -# general jar cleanup rule -######################################################################################### -.PHONY: clean-scala -clean-scala: - rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) - diff --git a/project/plugins.sbt b/project/plugins.sbt index 15a88b09..df29eabe 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1 +1,3 @@ addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.5") +addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") + diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 8049bab9..ee04e656 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -56,7 +56,7 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \ - -o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \ + -o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" touch $@ @@ -64,7 +64,7 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \ - -o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \ + -o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" touch $@ diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 022e8079..3742a895 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -55,7 +55,8 @@ VCS_NONCC_OPTS = \ +v2k \ +vcs+lic+wait \ +vc+list \ - -f $(sim_blackboxes) \ + -f $(sim_top_blackboxes) \ + -f $(sim_harness_blackboxes) \ -f $(sim_dotf) \ -sverilog \ +incdir+$(build_dir) \ diff --git a/src/main/scala/example/Simulator.scala b/src/main/scala/example/Simulator.scala index 0f142fd7..240f930f 100644 --- a/src/main/scala/example/Simulator.scala +++ b/src/main/scala/example/Simulator.scala @@ -82,6 +82,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { out.close() } def resources(sim: Simulator): Seq[String] = Seq( + "/testchipip/csrc/SimSerial.cc", "/csrc/SimDTM.cc", "/csrc/SimJTAG.cc", "/csrc/remote_bitbang.h", diff --git a/tools/barstools b/tools/barstools index 0b9d74ad..e548210e 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 0b9d74ada7e3271e82d665b09b3b9ff087c70f91 +Subproject commit e548210ef42e634e75cf283292685728114694c6 diff --git a/variables.mk b/variables.mk index f44286c5..29a48c6c 100644 --- a/variables.mk +++ b/variables.mk @@ -33,10 +33,17 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG) FIRRTL_FILE ?= $(build_dir)/$(long_name).fir ANNO_FILE ?= $(build_dir)/$(long_name).anno.json VERILOG_FILE ?= $(build_dir)/$(long_name).top.v +TOP_FIR ?= $(build_dir)/$(long_name).top.fir +TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v +HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir +HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf +SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir sim_dotf ?= $(build_dir)/sim_files.f +sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f +sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f ######################################################################################### # default sbt launch command @@ -64,9 +71,6 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc ######################################################################################### # sources needed to run simulators ######################################################################################### -sim_blackboxes = \ - $(build_dir)/firrtl_black_box_resource_files.f - sim_vsrcs = \ $(VERILOG_FILE) \ $(HARNESS_FILE) \ From 68b2da6b3a8e03f6fba8e50a195032df1a6a2fe8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Apr 2019 16:06:42 -0700 Subject: [PATCH 020/120] update boom | match build.sbt --- build.sbt | 6 +++--- generators/boom | 2 +- variables.mk | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/build.sbt b/build.sbt index a251d86d..52de1ba5 100644 --- a/build.sbt +++ b/build.sbt @@ -24,9 +24,6 @@ lazy val rocketchip = RootProject(file("generators/rocket-chip")) lazy val testchipip = (project in file("generators/testchipip")).settings(commonSettings) .dependsOn(rocketchip) -lazy val boom = (project in file("generators/boom")).settings(commonSettings) - .dependsOn(rocketchip) - // Checks for -DROCKET_USE_MAVEN. // If it's there, use a maven dependency. // Else, depend on subprojects in git submodules. @@ -42,6 +39,9 @@ def conditionalDependsOn(prj: Project): Project = { lazy val example = conditionalDependsOn(project in file(".")) .settings(commonSettings) +lazy val boom = conditionalDependsOn(project in file("generators/boom")) + .settings(commonSettings) + lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) .settings(commonSettings) diff --git a/generators/boom b/generators/boom index c7489137..f1caea81 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit c7489137d420b5095a78ab6c64ded56a4581397a +Subproject commit f1caea81c6daa183c8a9fc82d2a5dee1625640ad diff --git a/variables.mk b/variables.mk index c944af1c..f57abead 100644 --- a/variables.mk +++ b/variables.mk @@ -5,7 +5,7 @@ ######################################################################################### # default variables to invoke the generator # descriptions: -# PROJECT = the scala package to find the MODEL in +# PROJECT = the scala package to find the MODEL/Generator in # MODEL = the top level module of the project (normally the harness) # CONFIG = the configuration class to give the parameters for the project # CFG_PROJECT = the scala package to find the CONFIG class From 885c5f74db287d63411e4c0b1ca500c7985287a0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Apr 2019 17:08:08 -0700 Subject: [PATCH 021/120] bump boom/firrtl | support building boom | update genfiles in simulator to make rv32 bootrom | misc cleanup --- generators/boom | 2 +- sims/verisim/Makefile | 2 +- sims/vsim/Makefile | 2 +- src/main/scala/example/Simulator.scala | 1 + tools/firrtl | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-) diff --git a/generators/boom b/generators/boom index f1caea81..4cd347ed 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit f1caea81c6daa183c8a9fc82d2a5dee1625640ad +Subproject commit 4cd347ed51f8bdf98d2d1868cf1530d845539613 diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index ee04e656..89d9c6e8 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -89,5 +89,5 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) # general cleanup rule ######################################################################################### .PHONY: clean -clean: clean-scala +clean: rm -rf $(build_dir) $(sim_prefix)-* diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 3742a895..be8fd716 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -93,5 +93,5 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) # general cleanup rule ######################################################################################### .PHONY: clean -clean: clean-scala +clean: rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h diff --git a/src/main/scala/example/Simulator.scala b/src/main/scala/example/Simulator.scala index 240f930f..09c2cd77 100644 --- a/src/main/scala/example/Simulator.scala +++ b/src/main/scala/example/Simulator.scala @@ -101,6 +101,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { def writeBootrom(): Unit = { firrtl.FileUtils.makeDirectory("./bootrom/") writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/") + writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/") } def writeFiles(cfg: GenerateSimConfig): Unit = { diff --git a/tools/firrtl b/tools/firrtl index 2272044c..bf66997b 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit 2272044c6ab46b5148c39c124e66e1a8e9073a24 +Subproject commit bf66997b1a2438a322cd619ca2b6aeb0f0ac0ba0 From e71bf2139f1fca65c42a3fac2776b915c9760a4a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Apr 2019 17:52:31 -0700 Subject: [PATCH 022/120] Update README | add shortcut to build boom --- README.md | 22 +++++++++++++++++++++- variables.mk | 10 ++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 8f07c855..b03df195 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,7 @@ **THIS BRANCH IS UNDER DEVELOPMENT** **IT CURRENTLY HAS MANY SUBMODULES** -**PLEASE RUN ./build.sh TO UPDATE SUBMODULES, UNLESS YOU WANT TO SPEND A LONG TIME WAITING FOR SUBMODULE TO CLONE** +**PLEASE RUN ./scripts/init-submodules-no-riscv-tools.sh TO UPDATE SUBMODULES, UNLESS YOU WANT TO SPEND A LONG TIME WAITING FOR SUBMODULE TO CLONE** This is a starter template for your custom RISC-V project. It will allow you to leverage the Chisel HDL and RocketChip SoC generator to produce a @@ -62,6 +62,26 @@ follows. * bootrom - sources for the first-stage bootloader included in the Boot ROM * src/main/scala - scala source files for your project go here +## For submodule developers + +Depending on the submodule that you develop in, you might want to run things out of the submodule. +For example, `boom` has its own Generator, package, top module, and configurations separate from +the `example` package in `src/main/scala`. Thus, to build a `boom` project you do something like +the following: + + make SBT_PROJECT=boom PROJECT=boom.system CONFIG= TOP=ExampleBoomSystem + +However, that is very long to write everytime there is a compile. Thus, a shorthand way to build +the subproject is the following: + + make SUB_PROJECT=boom CONFIG= + +This sets the proper configuration flags for make to work correctly. + +Currently, the supported `SUB_PROJECT` flags are: + + * boom - to build and run `boom` subproject configurations + ## Using the block device The default example project just provides the Rocket coreplex, memory, and diff --git a/variables.mk b/variables.mk index 4fa2ff48..df0bba10 100644 --- a/variables.mk +++ b/variables.mk @@ -12,6 +12,9 @@ # SBT_PROJECT = the SBT project that you should find the Generator class in # TB = wrapper over the TestHarness needed to simulate in VCS # TOP = top level module of the project (normally the module instantiated by the harness) +# +# project specific: +# SUB_PROJECT = use the specific subproject default variables ######################################################################################### PROJECT ?= example MODEL ?= TestHarness @@ -21,6 +24,13 @@ SBT_PROJECT ?= $(PROJECT) TB ?= TestDriver TOP ?= ExampleTop +SUB_PROJECT ?= example +ifeq ($(SUB_PROJECT),boom) # make it so that you only change 1 param to change them all! + SBT_PROJECT=boom + PROJECT=boom.system + TOP=ExampleBoomSystem +endif + ######################################################################################### # path to rocket-chip and testchipip ######################################################################################### From adb8897e354b0a6b4699786213aac6de1dd8210e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Apr 2019 23:11:14 -0700 Subject: [PATCH 023/120] add firrtl dependency to build.sbt | point to different firrtl jar | a bunch of sbt plugins --- build.sbt | 29 ++++++++++++++++++----------- common.mk | 11 ++++++----- project/plugins.sbt | 18 ++++++++++++++++-- 3 files changed, 40 insertions(+), 18 deletions(-) diff --git a/build.sbt b/build.sbt index 52de1ba5..035fed27 100644 --- a/build.sbt +++ b/build.sbt @@ -8,26 +8,30 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.1" % "test", - libraryDependencies += "org.json4s" %% "json4s-native" % "3.5.3", + libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.5" % "test", + libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.1", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, libraryDependencies += "edu.berkeley.cs" %% "firrtl-interpreter" % "1.2-SNAPSHOT", - libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.1", + libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), resolvers ++= Seq( Resolver.sonatypeRepo("snapshots"), Resolver.sonatypeRepo("releases"), Resolver.mavenLocal)) +lazy val rebarFirrtl = (project in file("tools/firrtl")) + .settings(commonSettings) + lazy val rocketchip = RootProject(file("generators/rocket-chip")) -lazy val testchipip = (project in file("generators/testchipip")).settings(commonSettings) +lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip) + .settings(commonSettings) // Checks for -DROCKET_USE_MAVEN. // If it's there, use a maven dependency. // Else, depend on subprojects in git submodules. -def conditionalDependsOn(prj: Project): Project = { +def testchipIpDependsOn(prj: Project): Project = { if (sys.props.contains("ROCKET_USE_MAVEN")) { prj.settings(Seq( libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT", @@ -36,19 +40,22 @@ def conditionalDependsOn(prj: Project): Project = { prj.dependsOn(testchipip) } } -lazy val example = conditionalDependsOn(project in file(".")) + +lazy val example = testchipIpDependsOn(project in file(".")) .settings(commonSettings) -lazy val boom = conditionalDependsOn(project in file("generators/boom")) +lazy val boom = (project in file("generators/boom")) + .dependsOn(rocketchip) .settings(commonSettings) -lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) +lazy val tapeout = (project in file("./tools/barstools/tapeout/")) + .dependsOn(rebarFirrtl, rocketchip) .settings(commonSettings) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) + .settings(commonSettings) -lazy val `barstools-macros` = conditionalDependsOn(project in file("./tools/barstools/macros/")) +lazy val `barstools-macros` = (project in file("./tools/barstools/macros/")) + .dependsOn(mdf, rocketchip, rebarFirrtl) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) - .dependsOn(mdf) - diff --git a/common.mk b/common.mk index 3c434848..d53fb4c8 100644 --- a/common.mk +++ b/common.mk @@ -20,12 +20,13 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class ######################################################################################### # jar creation variables and rules ######################################################################################### -FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar +FIRRTL_DIR = $(base_dir)/tools/firrtl +FIRRTL_JAR ?= $(base_dir)/lib/firrtl.jar -$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala) - $(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala +$(FIRRTL_JAR): $(call lookup_scala_srcs, $(FIRRTL_DIR)/firrtl/src/main/scala) + $(MAKE) -C $(FIRRTL_DIR) SBT="$(SBT)" root_dir=$(FIRRTL_DIR) build-scala mkdir -p $(dir $@) - cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@ + cp -p $(FIRRTL_DIR)/utils/bin/firrtl.jar $@ touch $@ ######################################################################################### @@ -49,7 +50,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -ll info -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) diff --git a/project/plugins.sbt b/project/plugins.sbt index df29eabe..9d35b376 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,3 +1,17 @@ -addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.5") -addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") +resolvers += Resolver.url("scalasbt", new URL("http://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) +resolvers += Classpaths.sbtPluginReleases +resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven" +addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") +addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") +addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") +addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0") +addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3") +addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1") +addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") +addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") +addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6") +addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") +addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") + +libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" From 46f2cd3f9d0d4b8960277904144334698b8637bc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Apr 2019 23:14:07 -0700 Subject: [PATCH 024/120] remove debug firrtl prints --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index d53fb4c8..abe9041f 100644 --- a/common.mk +++ b/common.mk @@ -50,7 +50,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -ll info -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) From 739fcec16043e543c12598a8b7f802b4f472488c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Apr 2019 23:16:04 -0700 Subject: [PATCH 025/120] remove csmith scripts --- scripts/csmith/install-csmith.sh | 6 - scripts/csmith/run-csmith.sh | 188 ---- scripts/csmith/sources/crt.S | 237 ----- scripts/csmith/sources/encoding.h | 1471 ----------------------------- scripts/csmith/sources/link.ld | 66 -- scripts/csmith/sources/syscalls.c | 471 --------- scripts/csmith/sources/util.h | 90 -- 7 files changed, 2529 deletions(-) delete mode 100755 scripts/csmith/install-csmith.sh delete mode 100755 scripts/csmith/run-csmith.sh delete mode 100644 scripts/csmith/sources/crt.S delete mode 100644 scripts/csmith/sources/encoding.h delete mode 100644 scripts/csmith/sources/link.ld delete mode 100644 scripts/csmith/sources/syscalls.c delete mode 100644 scripts/csmith/sources/util.h diff --git a/scripts/csmith/install-csmith.sh b/scripts/csmith/install-csmith.sh deleted file mode 100755 index 5b7576a7..00000000 --- a/scripts/csmith/install-csmith.sh +++ /dev/null @@ -1,6 +0,0 @@ -git clone https://github.com/csmith-project/csmith.git -cd csmith -mkdir build -cd build -../configure --prefix=$RISCV -make install diff --git a/scripts/csmith/run-csmith.sh b/scripts/csmith/run-csmith.sh deleted file mode 100755 index e668fa89..00000000 --- a/scripts/csmith/run-csmith.sh +++ /dev/null @@ -1,188 +0,0 @@ -# Script to run the csmith random test generator multiple times - -TEST_NAME=test -SIM=$1 -RUN_AMT=-1 -P_INST=1 -SEED=-1 -WDEBUG_EXT=false -NDEBUG=false - -# Make output directory -OUTPUT_DIR=output -SRC_DIR=sources -mkdir -p output - -usage(){ - echo "run-csmith.sh --sim SIM_BINARY [--run RUN_AMT] [--parallel PARALLEL_INSTANCES] [--seed SEED] [--withdebugext] [--nodebug]" - echo " --sim -s SIM_BINARY is the simulator to test spike against" - echo " --run -r RUN_AMT is the amount of times to run the csmith tests" - echo " defaults to infinity" - echo " --parallel -p PARALLEL_INSTANCES is the amount of instances to spawn in parallel" - echo " defaults to one instance" - echo " --seed -e SEED runs a single test with the seed specified" - echo " ignores all other parameters" - echo " --withdebugext -d run debug version of simulator (used for when" - echo " main sim is not debug version)" - echo " (just appends -debug to sim name)" - echo " --nodebug -n just error when there is a sim mismatch (no vpd)" -} - -# Exit everything on one ctrl+c -trap kill_group SIGINT -kill_group(){ - echo "" - echo "[ALL] Killing instances." - kill 0 -} - -# Run the csmith test once -# -# Args: -# $1 instance that this test is running on -# $2 seed to run the test with -run_once () { - BASE_NAME=$OUTPUT_DIR/$TEST_NAME-$1-$2 - - echo "[$1] Running csmith test with seed=$2" - csmith --seed $2 > $BASE_NAME.c - - # Build both a RISCV binary and normal binary - - # Test x86-64 first - gcc -I$RISCV/include/csmith-2.4.0 -w $BASE_NAME.c -o $BASE_NAME.bin - timeout 1s ./$BASE_NAME.bin | awk '{print tolower($0)}' > $BASE_NAME.host.out - RV=$? - if [ $RV -ne 0 ]; then - echo "[$1] x86-64 binary timed out. Discard and start over." - rm $BASE_NAME.bin $BASE_NAME.host.out $BASE_NAME.c - return 0 - fi - - # Test RISCV spike version - riscv64-unknown-elf-gcc -w -I./$SRC_DIR -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -o $BASE_NAME.riscv $BASE_NAME.c $SRC_DIR/syscalls.c $SRC_DIR/crt.S -static -nostdlib -nostartfiles -lm -lgcc -T $SRC_DIR/link.ld -I$RISCV/include/csmith-2.4.0 - timeout --foreground 10s spike $BASE_NAME.riscv 1> $BASE_NAME.spike.out 2> $BASE_NAME.spike.log - RV=$? - if [ $RV -ne 0 ]; then - echo "[$1] Spike timed out. Discard and start over." - rm $BASE_NAME.bin $BASE_NAME.host.out $BASE_NAME.c $BASE_NAME.riscv $BASE_NAME.spike.out $BASE_NAME.spike.log - return 0 - fi - - # Compare x86-64 and Spike - cmp -s $BASE_NAME.spike.out $BASE_NAME.host.out - RV=$? - if [ $RV -ne 0 ]; then - echo "[$1] Spike produces wrong result compared to x86-64 binary. Discard and start over." - rm $BASE_NAME.bin $BASE_NAME.host.out $BASE_NAME.c $BASE_NAME.riscv $BASE_NAME.spike.out $BASE_NAME.spike.log - return 0 - fi - - # Compare simulator output versus spike - timeout 15m $SIM $BASE_NAME.riscv 1> $BASE_NAME.sim.out - RV=$? - if [ $RV == 124 ]; then - echo "[$1] Simulator timed out. Discard and start over." - rm $BASE_NAME.bin $BASE_NAME.host.out $BASE_NAME.c $BASE_NAME.riscv $BASE_NAME.spike.out $BASE_NAME.spike.log $BASE_NAME.sim.out - return 0 - fi - - cmp -s $BASE_NAME.sim.out $BASE_NAME.spike.out - RV=$? - if [ $RV -ne 0 ]; then - echo "[$1] Simulator produced wrong result." - if [ $NDEBUG == false ]; then - if [ $WDEBUG_EXT == true ]; then - ${SIM}-debug $BASE_NAME.riscv +verbose +vcdplusfile=$BASE_NAME.vpd 1> $BASE_NAME.sim.out 2> $BASE_NAME.sim.log - else - $SIM $BASE_NAME.riscv +verbose +vcdplusfile=$BASE_NAME.vpd 1> $BASE_NAME.sim.out 2> $BASE_NAME.sim.log - fi - echo "[$1] Vpd of error file: $BASE_NAME.vpd" - echo "[$1] Simulator output file: $BASE_NAME.sim.out" - echo "[$1] Simulator log file: $BASE_NAME.sim.log" - fi - kill_group - else - echo "[$1] Simulator and spike agree." - rm $BASE_NAME.bin $BASE_NAME.host.out $BASE_NAME.c $BASE_NAME.riscv $BASE_NAME.spike.out $BASE_NAME.spike.log $BASE_NAME.sim.out - return 0 - fi -} - -# Run the test for a certain amount of times -# Also setup a random seed -# -# Args: -# $1 instance that this is running on -run() { - if [ $SEED == -1 ]; then - if [ $RUN_AMT == -1 ]; then - while true; - do - SEED=$(od -N 4 -t uL -An /dev/urandom | tr -d " ") - run_once $1 $SEED - done - else - for j in `seq 1 $RUN_AMT`; - do - SEED=$(od -N 4 -t uL -An /dev/urandom | tr -d " ") - run_once $1 $SEED - done - fi - else - run_once $1 $SEED - fi -} - -# Parse arguments -while [ "$1" != "" ]; -do - case $1 in - -s | --sim ) shift - SIM=$1 - ;; - -r | --run ) shift - RUN_AMT=$1 - ;; - -p | --parallel ) shift - P_INST=$1 - ;; - -e | --seed ) shift - SEED=$1 - ;; - --withdebugext | -d ) shift - WDEBUG_EXT=true - ;; - --nodebug | -n ) shift - NDEBUG=true - ;; - -h | --help ) usage - exit 0 - esac - shift -done - -# Start of script -if [ -z "$SIM" ]; then - echo "Forgot simulator binary." - usage - exit 1 -fi - -if [ $SEED == -1 ]; then - if [ $RUN_AMT == -1 ]; then - echo "Spawning $P_INST instance(s), running csmith infinite times" - else - echo "Spawning $P_INST instance(s), running csmith $RUN_AMT times" - fi - - for i in `seq 1 $P_INST`; - do - run $i & - done - wait -else - RUN_AMT=1 - run 1 - wait -fi diff --git a/scripts/csmith/sources/crt.S b/scripts/csmith/sources/crt.S deleted file mode 100644 index d75e81e0..00000000 --- a/scripts/csmith/sources/crt.S +++ /dev/null @@ -1,237 +0,0 @@ -# See LICENSE for license details. - -#include "encoding.h" - -#if __riscv_xlen == 64 -# define LREG ld -# define SREG sd -# define REGBYTES 8 -#else -# define LREG lw -# define SREG sw -# define REGBYTES 4 -#endif - - .section ".text.init" - .globl _start -_start: - li x1, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10,0 - li x11,0 - li x12,0 - li x13,0 - li x14,0 - li x15,0 - li x16,0 - li x17,0 - li x18,0 - li x19,0 - li x20,0 - li x21,0 - li x22,0 - li x23,0 - li x24,0 - li x25,0 - li x26,0 - li x27,0 - li x28,0 - li x29,0 - li x30,0 - li x31,0 - - # enable FPU and accelerator if present - li t0, MSTATUS_FS | MSTATUS_XS - csrs mstatus, t0 - - # make sure XLEN agrees with compilation choice - li t0, 1 - slli t0, t0, 31 -#if __riscv_xlen == 64 - bgez t0, 1f -#else - bltz t0, 1f -#endif -2: - li a0, 1 - sw a0, tohost, t0 - j 2b -1: - -#ifdef __riscv_flen - # initialize FPU if we have one - la t0, 1f - csrw mtvec, t0 - - fssr x0 - fmv.s.x f0, x0 - fmv.s.x f1, x0 - fmv.s.x f2, x0 - fmv.s.x f3, x0 - fmv.s.x f4, x0 - fmv.s.x f5, x0 - fmv.s.x f6, x0 - fmv.s.x f7, x0 - fmv.s.x f8, x0 - fmv.s.x f9, x0 - fmv.s.x f10,x0 - fmv.s.x f11,x0 - fmv.s.x f12,x0 - fmv.s.x f13,x0 - fmv.s.x f14,x0 - fmv.s.x f15,x0 - fmv.s.x f16,x0 - fmv.s.x f17,x0 - fmv.s.x f18,x0 - fmv.s.x f19,x0 - fmv.s.x f20,x0 - fmv.s.x f21,x0 - fmv.s.x f22,x0 - fmv.s.x f23,x0 - fmv.s.x f24,x0 - fmv.s.x f25,x0 - fmv.s.x f26,x0 - fmv.s.x f27,x0 - fmv.s.x f28,x0 - fmv.s.x f29,x0 - fmv.s.x f30,x0 - fmv.s.x f31,x0 -1: -#endif - - # initialize trap vector - la t0, trap_entry - csrw mtvec, t0 - - # initialize global pointer -.option push -.option norelax - la gp, __global_pointer$ -.option pop - - la tp, _end + 63 - and tp, tp, -64 - - # get core id - csrr a0, mhartid - # for now, assume only 1 core - li a1, 1 -1:bgeu a0, a1, 1b - - # give each core 128KB of stack + TLS -#define STKSHIFT 17 - sll a2, a0, STKSHIFT - add tp, tp, a2 - add sp, a0, 1 - sll sp, sp, STKSHIFT - add sp, sp, tp - - j _init - - .align 2 -trap_entry: - addi sp, sp, -272 - - SREG x1, 1*REGBYTES(sp) - SREG x2, 2*REGBYTES(sp) - SREG x3, 3*REGBYTES(sp) - SREG x4, 4*REGBYTES(sp) - SREG x5, 5*REGBYTES(sp) - SREG x6, 6*REGBYTES(sp) - SREG x7, 7*REGBYTES(sp) - SREG x8, 8*REGBYTES(sp) - SREG x9, 9*REGBYTES(sp) - SREG x10, 10*REGBYTES(sp) - SREG x11, 11*REGBYTES(sp) - SREG x12, 12*REGBYTES(sp) - SREG x13, 13*REGBYTES(sp) - SREG x14, 14*REGBYTES(sp) - SREG x15, 15*REGBYTES(sp) - SREG x16, 16*REGBYTES(sp) - SREG x17, 17*REGBYTES(sp) - SREG x18, 18*REGBYTES(sp) - SREG x19, 19*REGBYTES(sp) - SREG x20, 20*REGBYTES(sp) - SREG x21, 21*REGBYTES(sp) - SREG x22, 22*REGBYTES(sp) - SREG x23, 23*REGBYTES(sp) - SREG x24, 24*REGBYTES(sp) - SREG x25, 25*REGBYTES(sp) - SREG x26, 26*REGBYTES(sp) - SREG x27, 27*REGBYTES(sp) - SREG x28, 28*REGBYTES(sp) - SREG x29, 29*REGBYTES(sp) - SREG x30, 30*REGBYTES(sp) - SREG x31, 31*REGBYTES(sp) - - csrr a0, mcause - csrr a1, mepc - mv a2, sp - jal handle_trap - csrw mepc, a0 - - # Remain in M-mode after eret - li t0, MSTATUS_MPP - csrs mstatus, t0 - - LREG x1, 1*REGBYTES(sp) - LREG x2, 2*REGBYTES(sp) - LREG x3, 3*REGBYTES(sp) - LREG x4, 4*REGBYTES(sp) - LREG x5, 5*REGBYTES(sp) - LREG x6, 6*REGBYTES(sp) - LREG x7, 7*REGBYTES(sp) - LREG x8, 8*REGBYTES(sp) - LREG x9, 9*REGBYTES(sp) - LREG x10, 10*REGBYTES(sp) - LREG x11, 11*REGBYTES(sp) - LREG x12, 12*REGBYTES(sp) - LREG x13, 13*REGBYTES(sp) - LREG x14, 14*REGBYTES(sp) - LREG x15, 15*REGBYTES(sp) - LREG x16, 16*REGBYTES(sp) - LREG x17, 17*REGBYTES(sp) - LREG x18, 18*REGBYTES(sp) - LREG x19, 19*REGBYTES(sp) - LREG x20, 20*REGBYTES(sp) - LREG x21, 21*REGBYTES(sp) - LREG x22, 22*REGBYTES(sp) - LREG x23, 23*REGBYTES(sp) - LREG x24, 24*REGBYTES(sp) - LREG x25, 25*REGBYTES(sp) - LREG x26, 26*REGBYTES(sp) - LREG x27, 27*REGBYTES(sp) - LREG x28, 28*REGBYTES(sp) - LREG x29, 29*REGBYTES(sp) - LREG x30, 30*REGBYTES(sp) - LREG x31, 31*REGBYTES(sp) - - addi sp, sp, 272 - mret - -.section ".tdata.begin" -.globl _tdata_begin -_tdata_begin: - -.section ".tdata.end" -.globl _tdata_end -_tdata_end: - -.section ".tbss.end" -.globl _tbss_end -_tbss_end: - -.section ".tohost","aw",@progbits -.align 6 -.globl tohost -tohost: .dword 0 -.align 6 -.globl fromhost -fromhost: .dword 0 diff --git a/scripts/csmith/sources/encoding.h b/scripts/csmith/sources/encoding.h deleted file mode 100644 index c109ce18..00000000 --- a/scripts/csmith/sources/encoding.h +++ /dev/null @@ -1,1471 +0,0 @@ -// See LICENSE for license details. - -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_HPP 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_TVM 0x00100000 -#define MSTATUS_TW 0x00200000 -#define MSTATUS_TSR 0x00400000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS_UXL 0x0000000300000000 -#define MSTATUS_SXL 0x0000000C00000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_SUM 0x00040000 -#define SSTATUS_MXR 0x00080000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS_UXL 0x0000000300000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define DCSR_XDEBUGVER (3U<<30) -#define DCSR_NDRESET (1<<29) -#define DCSR_FULLRESET (1<<28) -#define DCSR_EBREAKM (1<<15) -#define DCSR_EBREAKH (1<<14) -#define DCSR_EBREAKS (1<<13) -#define DCSR_EBREAKU (1<<12) -#define DCSR_STOPCYCLE (1<<10) -#define DCSR_STOPTIME (1<<9) -#define DCSR_CAUSE (7<<6) -#define DCSR_DEBUGINT (1<<5) -#define DCSR_HALT (1<<3) -#define DCSR_STEP (1<<2) -#define DCSR_PRV (3<<0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 - -#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) - -#define MCONTROL_SELECT (1<<19) -#define MCONTROL_TIMING (1<<18) -#define MCONTROL_ACTION (0x3f<<12) -#define MCONTROL_CHAIN (1<<11) -#define MCONTROL_MATCH (0xf<<7) -#define MCONTROL_M (1<<6) -#define MCONTROL_H (1<<5) -#define MCONTROL_S (1<<4) -#define MCONTROL_U (1<<3) -#define MCONTROL_EXECUTE (1<<2) -#define MCONTROL_STORE (1<<1) -#define MCONTROL_LOAD (1<<0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_H 2 -#define PRV_M 3 - -#define SATP32_MODE 0x80000000 -#define SATP32_ASID 0x7FC00000 -#define SATP32_PPN 0x003FFFFF -#define SATP64_MODE 0xF000000000000000 -#define SATP64_ASID 0x0FFFF00000000000 -#define SATP64_PPN 0x00000FFFFFFFFFFF - -#define SATP_MODE_OFF 0 -#define SATP_MODE_SV32 1 -#define SATP_MODE_SV39 8 -#define SATP_MODE_SV48 9 -#define SATP_MODE_SV57 10 -#define SATP_MODE_SV64 11 - -#define PMP_R 0x01 -#define PMP_W 0x02 -#define PMP_X 0x04 -#define PMP_A 0x18 -#define PMP_L 0x80 -#define PMP_SHIFT 2 - -#define PMP_TOR 0x08 -#define PMP_NA4 0x10 -#define PMP_NAPOT 0x18 - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -#define DEFAULT_RSTVEC 0x00001000 -#define CLINT_BASE 0x02000000 -#define CLINT_SIZE 0x000c0000 -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - -// page table entry (PTE) fields -#define PTE_V 0x001 // Valid -#define PTE_R 0x002 // Read -#define PTE_W 0x004 // Write -#define PTE_X 0x008 // Execute -#define PTE_U 0x010 // User -#define PTE_G 0x020 // Global -#define PTE_A 0x040 // Accessed -#define PTE_D 0x080 // Dirty -#define PTE_SOFT 0x300 // Reserved for Software - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#if __riscv_xlen == 64 -# define MSTATUS_SD MSTATUS64_SD -# define SSTATUS_SD SSTATUS64_SD -# define RISCV_PGLEVEL_BITS 9 -# define SATP_MODE SATP64_MODE -#else -# define MSTATUS_SD MSTATUS32_SD -# define SSTATUS_SD SSTATUS32_SD -# define RISCV_PGLEVEL_BITS 10 -# define SATP_MODE SATP32_MODE -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -#endif - -#endif - -#endif - -#endif -/* Automatically generated by parse-opcodes. */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_URET 0x200073 -#define MASK_URET 0xffffffff -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_SFENCE_VMA 0x12000073 -#define MASK_SFENCE_VMA 0xfe007fff -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FADD_Q 0x6000053 -#define MASK_FADD_Q 0xfe00007f -#define MATCH_FSUB_Q 0xe000053 -#define MASK_FSUB_Q 0xfe00007f -#define MATCH_FMUL_Q 0x16000053 -#define MASK_FMUL_Q 0xfe00007f -#define MATCH_FDIV_Q 0x1e000053 -#define MASK_FDIV_Q 0xfe00007f -#define MATCH_FSGNJ_Q 0x26000053 -#define MASK_FSGNJ_Q 0xfe00707f -#define MATCH_FSGNJN_Q 0x26001053 -#define MASK_FSGNJN_Q 0xfe00707f -#define MATCH_FSGNJX_Q 0x26002053 -#define MASK_FSGNJX_Q 0xfe00707f -#define MATCH_FMIN_Q 0x2e000053 -#define MASK_FMIN_Q 0xfe00707f -#define MATCH_FMAX_Q 0x2e001053 -#define MASK_FMAX_Q 0xfe00707f -#define MATCH_FCVT_S_Q 0x40300053 -#define MASK_FCVT_S_Q 0xfff0007f -#define MATCH_FCVT_Q_S 0x46000053 -#define MASK_FCVT_Q_S 0xfff0007f -#define MATCH_FCVT_D_Q 0x42300053 -#define MASK_FCVT_D_Q 0xfff0007f -#define MATCH_FCVT_Q_D 0x46100053 -#define MASK_FCVT_Q_D 0xfff0007f -#define MATCH_FSQRT_Q 0x5e000053 -#define MASK_FSQRT_Q 0xfff0007f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FLE_Q 0xa6000053 -#define MASK_FLE_Q 0xfe00707f -#define MATCH_FLT_Q 0xa6001053 -#define MASK_FLT_Q 0xfe00707f -#define MATCH_FEQ_Q 0xa6002053 -#define MASK_FEQ_Q 0xfe00707f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FMV_X_W 0xe0000053 -#define MASK_FMV_X_W 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCVT_W_Q 0xc6000053 -#define MASK_FCVT_W_Q 0xfff0007f -#define MATCH_FCVT_WU_Q 0xc6100053 -#define MASK_FCVT_WU_Q 0xfff0007f -#define MATCH_FCVT_L_Q 0xc6200053 -#define MASK_FCVT_L_Q 0xfff0007f -#define MATCH_FCVT_LU_Q 0xc6300053 -#define MASK_FCVT_LU_Q 0xfff0007f -#define MATCH_FMV_X_Q 0xe6000053 -#define MASK_FMV_X_Q 0xfff0707f -#define MATCH_FCLASS_Q 0xe6001053 -#define MASK_FCLASS_Q 0xfff0707f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FMV_W_X 0xf0000053 -#define MASK_FMV_W_X 0xfff0707f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FCVT_Q_W 0xd6000053 -#define MASK_FCVT_Q_W 0xfff0007f -#define MATCH_FCVT_Q_WU 0xd6100053 -#define MASK_FCVT_Q_WU 0xfff0007f -#define MATCH_FCVT_Q_L 0xd6200053 -#define MASK_FCVT_Q_L 0xfff0007f -#define MATCH_FCVT_Q_LU 0xd6300053 -#define MASK_FCVT_Q_LU 0xfff0007f -#define MATCH_FMV_Q_X 0xf6000053 -#define MASK_FMV_Q_X 0xfff0707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FLQ 0x4007 -#define MASK_FLQ 0x707f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FSQ 0x4027 -#define MASK_FSQ 0x707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_FMADD_Q 0x6000043 -#define MASK_FMADD_Q 0x600007f -#define MATCH_FMSUB_Q 0x6000047 -#define MASK_FMSUB_Q 0x600007f -#define MATCH_FNMSUB_Q 0x600004b -#define MASK_FNMSUB_Q 0x600007f -#define MATCH_FNMADD_Q 0x600004f -#define MASK_FNMADD_Q 0x600007f -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff -#define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 -#define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 -#define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 -#define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 -#define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 -#define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 -#define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 -#define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 -#define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 -#define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f -#define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f -#define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f -#define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f -#define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f -#define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f -#define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f -#define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f -#define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f -#define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f -#define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f -#define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f -#define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f -#define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f -#define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f -#define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f -#define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_SSTATUS 0x100 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SCOUNTEREN 0x106 -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_STVAL 0x143 -#define CSR_SIP 0x144 -#define CSR_SATP 0x180 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MTVAL 0x343 -#define CSR_MIP 0x344 -#define CSR_PMPCFG0 0x3a0 -#define CSR_PMPCFG1 0x3a1 -#define CSR_PMPCFG2 0x3a2 -#define CSR_PMPCFG3 0x3a3 -#define CSR_PMPADDR0 0x3b0 -#define CSR_PMPADDR1 0x3b1 -#define CSR_PMPADDR2 0x3b2 -#define CSR_PMPADDR3 0x3b3 -#define CSR_PMPADDR4 0x3b4 -#define CSR_PMPADDR5 0x3b5 -#define CSR_PMPADDR6 0x3b6 -#define CSR_PMPADDR7 0x3b7 -#define CSR_PMPADDR8 0x3b8 -#define CSR_PMPADDR9 0x3b9 -#define CSR_PMPADDR10 0x3ba -#define CSR_PMPADDR11 0x3bb -#define CSR_PMPADDR12 0x3bc -#define CSR_PMPADDR13 0x3bd -#define CSR_PMPADDR14 0x3be -#define CSR_PMPADDR15 0x3bf -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH 0x7b2 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FETCH_ACCESS 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_LOAD_ACCESS 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_STORE_ACCESS 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_FETCH_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_PAGE_FAULT 0xf -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(uret, MATCH_URET, MASK_URET) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) -DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) -DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) -DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) -DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) -DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) -DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) -DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) -DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) -DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) -DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) -DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) -DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) -DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) -DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) -DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) -DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) -DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) -DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) -DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) -DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) -DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) -DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) -DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) -DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) -DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) -DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) -DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -#endif -#ifdef DECLARE_CSR -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(scounteren, CSR_SCOUNTEREN) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(stval, CSR_STVAL) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(satp, CSR_SATP) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mtval, CSR_MTVAL) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) -DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) -DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) -DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) -DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) -DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) -DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) -DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) -DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) -DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) -DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) -DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) -DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) -DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) -DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) -DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) -DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) -DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) -DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) -DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch, CSR_DSCRATCH) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#ifdef DECLARE_CAUSE -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) -DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) -DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) -#endif diff --git a/scripts/csmith/sources/link.ld b/scripts/csmith/sources/link.ld deleted file mode 100644 index 4f8892ee..00000000 --- a/scripts/csmith/sources/link.ld +++ /dev/null @@ -1,66 +0,0 @@ -/*======================================================================*/ -/* Proxy kernel linker script */ -/*======================================================================*/ -/* This is the linker script used when building the proxy kernel. */ - -/*----------------------------------------------------------------------*/ -/* Setup */ -/*----------------------------------------------------------------------*/ - -/* The OUTPUT_ARCH command specifies the machine architecture where the - argument is one of the names used in the BFD library. More - specifically one of the entires in bfd/cpu-mips.c */ - -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -/*----------------------------------------------------------------------*/ -/* Sections */ -/*----------------------------------------------------------------------*/ - -SECTIONS -{ - - /* text: test code section */ - . = 0x80000000; - .text.init : { *(.text.init) } - - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - - .text : { *(.text) } - - /* data segment */ - .data : { *(.data) } - - .sdata : { - __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - } - - /* bss segment */ - .sbss : { - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } - .bss : { *(.bss) } - - /* thread-local data segment */ - .tdata : - { - _tls_data = .; - *(.tdata.begin) - *(.tdata) - *(.tdata.end) - } - .tbss : - { - *(.tbss) - *(.tbss.end) - } - - /* End of uninitalized data segement */ - _end = .; -} - diff --git a/scripts/csmith/sources/syscalls.c b/scripts/csmith/sources/syscalls.c deleted file mode 100644 index 6a719326..00000000 --- a/scripts/csmith/sources/syscalls.c +++ /dev/null @@ -1,471 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include -#include -#include -#include -#include "util.h" - -#define SYS_write 64 - -#undef strcmp - -extern volatile uint64_t tohost; -extern volatile uint64_t fromhost; - -static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2) -{ - volatile uint64_t magic_mem[8] __attribute__((aligned(64))); - magic_mem[0] = which; - magic_mem[1] = arg0; - magic_mem[2] = arg1; - magic_mem[3] = arg2; - __sync_synchronize(); - - tohost = (uintptr_t)magic_mem; - while (fromhost == 0) - ; - fromhost = 0; - - __sync_synchronize(); - return magic_mem[0]; -} - -#define NUM_COUNTERS 2 -static uintptr_t counters[NUM_COUNTERS]; -static char* counter_names[NUM_COUNTERS]; - -void setStats(int enable) -{ - int i = 0; -#define READ_CTR(name) do { \ - while (i >= NUM_COUNTERS) ; \ - uintptr_t csr = read_csr(name); \ - if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \ - counters[i++] = csr; \ - } while (0) - - READ_CTR(mcycle); - READ_CTR(minstret); - -#undef READ_CTR -} - -void __attribute__((noreturn)) tohost_exit(uintptr_t code) -{ - tohost = (code << 1) | 1; - while (1); -} - -uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) -{ - tohost_exit(1337); -} - -void exit(int code) -{ - tohost_exit(code); -} - -void abort() -{ - exit(128 + SIGABRT); -} - -void printstr(const char* s) -{ - syscall(SYS_write, 1, (uintptr_t)s, strlen(s)); -} - -void __attribute__((weak)) thread_entry(int cid, int nc) -{ - // multi-threaded programs override this function. - // for the case of single-threaded programs, only let core 0 proceed. - while (cid != 0); -} - -int __attribute__((weak)) main(int argc, char** argv) -{ - // single-threaded programs override this function. - printstr("Implement main(), foo!\n"); - return -1; -} - -static void init_tls() -{ - register void* thread_pointer asm("tp"); - extern char _tls_data; - extern __thread char _tdata_begin, _tdata_end, _tbss_end; - size_t tdata_size = &_tdata_end - &_tdata_begin; - memcpy(thread_pointer, &_tls_data, tdata_size); - size_t tbss_size = &_tbss_end - &_tdata_end; - memset(thread_pointer + tdata_size, 0, tbss_size); -} - -void _init(int cid, int nc) -{ - init_tls(); - thread_entry(cid, nc); - - // only single-threaded programs should ever get here. - int ret = main(0, 0); - - char buf[NUM_COUNTERS * 32] __attribute__((aligned(64))); - char* pbuf = buf; - for (int i = 0; i < NUM_COUNTERS; i++) - if (counters[i]) - pbuf += sprintf(pbuf, "%s = %d\n", counter_names[i], counters[i]); - if (pbuf != buf) - printstr(buf); - - exit(ret); -} - -#undef putchar -int putchar(int ch) -{ - static __thread char buf[64] __attribute__((aligned(64))); - static __thread int buflen = 0; - - buf[buflen++] = ch; - - if (ch == '\n' || buflen == sizeof(buf)) - { - syscall(SYS_write, 1, (uintptr_t)buf, buflen); - buflen = 0; - } - - return 0; -} - -void printhex(uint64_t x) -{ - char str[17]; - int i; - for (i = 0; i < 16; i++) - { - str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); - x >>= 4; - } - str[16] = 0; - - printstr(str); -} - -static inline void printnum(void (*putch)(int, void**), void **putdat, - unsigned long long num, unsigned base, int width, int padc) -{ - unsigned digs[sizeof(num)*CHAR_BIT]; - int pos = 0; - - while (1) - { - digs[pos++] = num % base; - if (num < base) - break; - num /= base; - } - - while (width-- > pos) - putch(padc, putdat); - - while (pos-- > 0) - putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); -} - -static unsigned long long getuint(va_list *ap, int lflag) -{ - if (lflag >= 2) - return va_arg(*ap, unsigned long long); - else if (lflag) - return va_arg(*ap, unsigned long); - else - return va_arg(*ap, unsigned int); -} - -static long long getint(va_list *ap, int lflag) -{ - if (lflag >= 2) - return va_arg(*ap, long long); - else if (lflag) - return va_arg(*ap, long); - else - return va_arg(*ap, int); -} - -static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) -{ - register const char* p; - const char* last_fmt; - register int ch, err; - unsigned long long num; - int base, lflag, width, precision, altflag; - char padc; - - while (1) { - while ((ch = *(unsigned char *) fmt) != '%') { - if (ch == '\0') - return; - fmt++; - putch(ch, putdat); - } - fmt++; - - // Process a %-escape sequence - last_fmt = fmt; - padc = ' '; - width = -1; - precision = -1; - lflag = 0; - altflag = 0; - reswitch: - switch (ch = *(unsigned char *) fmt++) { - - // flag to pad on the right - case '-': - padc = '-'; - goto reswitch; - - // flag to pad with 0's instead of spaces - case '0': - padc = '0'; - goto reswitch; - - // width field - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - for (precision = 0; ; ++fmt) { - precision = precision * 10 + ch - '0'; - ch = *fmt; - if (ch < '0' || ch > '9') - break; - } - goto process_precision; - - case '*': - precision = va_arg(ap, int); - goto process_precision; - - case '.': - if (width < 0) - width = 0; - goto reswitch; - - case '#': - altflag = 1; - goto reswitch; - - process_precision: - if (width < 0) - width = precision, precision = -1; - goto reswitch; - - // long flag (doubled for long long) - case 'l': - lflag++; - goto reswitch; - - // character - case 'c': - putch(va_arg(ap, int), putdat); - break; - - // string - case 's': - if ((p = va_arg(ap, char *)) == NULL) - p = "(null)"; - if (width > 0 && padc != '-') - for (width -= strnlen(p, precision); width > 0; width--) - putch(padc, putdat); - for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { - putch(ch, putdat); - p++; - } - for (; width > 0; width--) - putch(' ', putdat); - break; - - // (signed) decimal - case 'd': - num = getint(&ap, lflag); - if ((long long) num < 0) { - putch('-', putdat); - num = -(long long) num; - } - base = 10; - goto signed_number; - - // unsigned decimal - case 'u': - base = 10; - goto unsigned_number; - - // (unsigned) octal - case 'o': - // should do something with padding so it's always 3 octits - base = 8; - goto unsigned_number; - - // pointer - case 'p': - static_assert(sizeof(long) == sizeof(void*)); - lflag = 1; - putch('0', putdat); - putch('x', putdat); - /* fall through to 'x' */ - - // (unsigned) hexadecimal - case 'X': - case 'x': - base = 16; - unsigned_number: - num = getuint(&ap, lflag); - signed_number: - printnum(putch, putdat, num, base, width, padc); - break; - - // escaped '%' character - case '%': - putch(ch, putdat); - break; - - // unrecognized escape sequence - just print it literally - default: - putch('%', putdat); - fmt = last_fmt; - break; - } - } -} - -int printf(const char* fmt, ...) -{ - va_list ap; - va_start(ap, fmt); - - vprintfmt((void*)putchar, 0, fmt, ap); - - va_end(ap); - return 0; // incorrect return value, but who cares, anyway? -} - -int sprintf(char* str, const char* fmt, ...) -{ - va_list ap; - char* str0 = str; - va_start(ap, fmt); - - void sprintf_putch(int ch, void** data) - { - char** pstr = (char**)data; - **pstr = ch; - (*pstr)++; - } - - vprintfmt(sprintf_putch, (void**)&str, fmt, ap); - *str = 0; - - va_end(ap); - return str - str0; -} - -void* memcpy(void* dest, const void* src, size_t len) -{ - if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { - const uintptr_t* s = src; - uintptr_t *d = dest; - while (d < (uintptr_t*)(dest + len)) - *d++ = *s++; - } else { - const char* s = src; - char *d = dest; - while (d < (char*)(dest + len)) - *d++ = *s++; - } - return dest; -} - -void* memset(void* dest, int byte, size_t len) -{ - if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { - uintptr_t word = byte & 0xFF; - word |= word << 8; - word |= word << 16; - word |= word << 16 << 16; - - uintptr_t *d = dest; - while (d < (uintptr_t*)(dest + len)) - *d++ = word; - } else { - char *d = dest; - while (d < (char*)(dest + len)) - *d++ = byte; - } - return dest; -} - -size_t strlen(const char *s) -{ - const char *p = s; - while (*p) - p++; - return p - s; -} - -size_t strnlen(const char *s, size_t n) -{ - const char *p = s; - while (n-- && *p) - p++; - return p - s; -} - -int strcmp(const char* s1, const char* s2) -{ - unsigned char c1, c2; - - do { - c1 = *s1++; - c2 = *s2++; - } while (c1 != 0 && c1 == c2); - - return c1 - c2; -} - -char* strcpy(char* dest, const char* src) -{ - char* d = dest; - while ((*d++ = *src++)) - ; - return dest; -} - -long atol(const char* str) -{ - long res = 0; - int sign = 0; - - while (*str == ' ') - str++; - - if (*str == '-' || *str == '+') { - sign = *str == '-'; - str++; - } - - while (*str) { - res *= 10; - res += *str++ - '0'; - } - - return sign ? -res : res; -} diff --git a/scripts/csmith/sources/util.h b/scripts/csmith/sources/util.h deleted file mode 100644 index 081cfd63..00000000 --- a/scripts/csmith/sources/util.h +++ /dev/null @@ -1,90 +0,0 @@ -// See LICENSE for license details. - -#ifndef __UTIL_H -#define __UTIL_H - -extern void setStats(int enable); - -#include - -#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; } - -static int verify(int n, const volatile int* test, const int* verify) -{ - int i; - // Unrolled for faster verification - for (i = 0; i < n/2*2; i+=2) - { - int t0 = test[i], t1 = test[i+1]; - int v0 = verify[i], v1 = verify[i+1]; - if (t0 != v0) return i+1; - if (t1 != v1) return i+2; - } - if (n % 2 != 0 && test[n-1] != verify[n-1]) - return n; - return 0; -} - -static int verifyDouble(int n, const volatile double* test, const double* verify) -{ - int i; - // Unrolled for faster verification - for (i = 0; i < n/2*2; i+=2) - { - double t0 = test[i], t1 = test[i+1]; - double v0 = verify[i], v1 = verify[i+1]; - int eq1 = t0 == v0, eq2 = t1 == v1; - if (!(eq1 & eq2)) return i+1+eq1; - } - if (n % 2 != 0 && test[n-1] != verify[n-1]) - return n; - return 0; -} - -static void __attribute__((noinline)) barrier(int ncores) -{ - static volatile int sense; - static volatile int count; - static __thread int threadsense; - - __sync_synchronize(); - - threadsense = !threadsense; - if (__sync_fetch_and_add(&count, 1) == ncores-1) - { - count = 0; - sense = threadsense; - } - else while(sense != threadsense) - ; - - __sync_synchronize(); -} - -static uint64_t lfsr(uint64_t x) -{ - uint64_t bit = (x ^ (x >> 1)) & 1; - return (x >> 1) | (bit << 62); -} - -static uintptr_t insn_len(uintptr_t pc) -{ - return (*(unsigned short*)pc & 3) ? 4 : 2; -} - -#ifdef __riscv -#include "encoding.h" -#endif - -#define stringify_1(s) #s -#define stringify(s) stringify_1(s) -#define stats(code, iter) do { \ - unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \ - code; \ - _c += read_csr(mcycle), _i += read_csr(minstret); \ - if (cid == 0) \ - printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \ - stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \ - } while(0) - -#endif //__UTIL_H From 7faaa56f34f60fcf1ce4e0b0370f883be851b004 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 18 Apr 2019 11:39:19 -0700 Subject: [PATCH 026/120] revert condDependsOn | put new firrtl jar into rocket --- build.sbt | 4 ++-- common.mk | 9 ++++----- variables.mk | 5 +++-- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/build.sbt b/build.sbt index 035fed27..94d07eaf 100644 --- a/build.sbt +++ b/build.sbt @@ -31,7 +31,7 @@ lazy val testchipip = (project in file("generators/testchipip")) // Checks for -DROCKET_USE_MAVEN. // If it's there, use a maven dependency. // Else, depend on subprojects in git submodules. -def testchipIpDependsOn(prj: Project): Project = { +def conditionalDependsOn(prj: Project): Project = { if (sys.props.contains("ROCKET_USE_MAVEN")) { prj.settings(Seq( libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT", @@ -41,7 +41,7 @@ def testchipIpDependsOn(prj: Project): Project = { } } -lazy val example = testchipIpDependsOn(project in file(".")) +lazy val example = conditionalDependsOn(project in file(".")) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) diff --git a/common.mk b/common.mk index abe9041f..b090285d 100644 --- a/common.mk +++ b/common.mk @@ -20,13 +20,12 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class ######################################################################################### # jar creation variables and rules ######################################################################################### -FIRRTL_DIR = $(base_dir)/tools/firrtl -FIRRTL_JAR ?= $(base_dir)/lib/firrtl.jar +FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar -$(FIRRTL_JAR): $(call lookup_scala_srcs, $(FIRRTL_DIR)/firrtl/src/main/scala) - $(MAKE) -C $(FIRRTL_DIR) SBT="$(SBT)" root_dir=$(FIRRTL_DIR) build-scala +$(FIRRTL_JAR): $(call lookup_scala_srcs, $(REBAR_FIRRTL_DIR)/src/main/scala) + $(MAKE) -C $(REBAR_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(REBAR_FIRRTL_DIR) build-scala mkdir -p $(dir $@) - cp -p $(FIRRTL_DIR)/utils/bin/firrtl.jar $@ + cp -p $(REBAR_FIRRTL_DIR)/utils/bin/firrtl.jar $@ touch $@ ######################################################################################### diff --git a/variables.mk b/variables.mk index df0bba10..5aea54a5 100644 --- a/variables.mk +++ b/variables.mk @@ -34,8 +34,9 @@ endif ######################################################################################### # path to rocket-chip and testchipip ######################################################################################### -ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip -TESTCHIP_DIR = $(base_dir)/generators/testchipip +ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip +TESTCHIP_DIR = $(base_dir)/generators/testchipip +REBAR_FIRRTL_DIR = $(base_dir)/tools/firrtl ######################################################################################### # names of various files needed to compile and run things From e4aa81b2f8262001b94ffd7c5d5a8a35e13b1ba6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 18 Apr 2019 14:25:37 -0700 Subject: [PATCH 027/120] fix make clean --- sims/verisim/Makefile | 2 +- sims/vsim/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index ee04e656..89d9c6e8 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -89,5 +89,5 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) # general cleanup rule ######################################################################################### .PHONY: clean -clean: clean-scala +clean: rm -rf $(build_dir) $(sim_prefix)-* diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 3742a895..be8fd716 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -93,5 +93,5 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) # general cleanup rule ######################################################################################### .PHONY: clean -clean: clean-scala +clean: rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h From eec137e1ee940694118cb18b035f670557c6f40f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 18 Apr 2019 14:38:57 -0700 Subject: [PATCH 028/120] make tapeout depend on testchipip for resources --- build.sbt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 94d07eaf..41ccfc36 100644 --- a/build.sbt +++ b/build.sbt @@ -48,8 +48,8 @@ lazy val boom = (project in file("generators/boom")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val tapeout = (project in file("./tools/barstools/tapeout/")) - .dependsOn(rebarFirrtl, rocketchip) +lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) + .dependsOn(rebarFirrtl) .settings(commonSettings) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) From daed74b873f74c8ddca200b5a3b83ebe3b8374ea Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 18 Apr 2019 20:10:20 -0700 Subject: [PATCH 029/120] lowercase readme --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index b03df195..887dce08 100644 --- a/README.md +++ b/README.md @@ -1,8 +1,8 @@ # RISC-V Project Template -**THIS BRANCH IS UNDER DEVELOPMENT** -**IT CURRENTLY HAS MANY SUBMODULES** -**PLEASE RUN ./scripts/init-submodules-no-riscv-tools.sh TO UPDATE SUBMODULES, UNLESS YOU WANT TO SPEND A LONG TIME WAITING FOR SUBMODULE TO CLONE** +**This branch is under development** +**It currently has many submodules** +**Please run ./scripts/init-submodules-no-riscv-tools.sh to update submodules, unless you want to spend a long time waiting for submodule to clone** This is a starter template for your custom RISC-V project. It will allow you to leverage the Chisel HDL and RocketChip SoC generator to produce a From e9ed53424be6bf1a79aff39c96fe9617c7e2a7c1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 19 Apr 2019 21:06:32 -0700 Subject: [PATCH 030/120] add sifive blocks | add rebar configs for boom --- .gitmodules | 3 + build.sbt | 1 + generators/sifive-blocks | 1 + src/main/scala/boomexample/Configs.scala | 90 ++++++++++++++++++++ src/main/scala/boomexample/TestHarness.scala | 44 ++++++++++ src/main/scala/boomexample/Top.scala | 54 ++++++++++++ src/main/scala/example/Top.scala | 8 ++ 7 files changed, 201 insertions(+) create mode 160000 generators/sifive-blocks create mode 100644 src/main/scala/boomexample/Configs.scala create mode 100644 src/main/scala/boomexample/TestHarness.scala create mode 100644 src/main/scala/boomexample/Top.scala diff --git a/.gitmodules b/.gitmodules index 3d3a7a73..73e556a4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -25,3 +25,6 @@ [submodule "generators/boom"] path = generators/boom url = git@github.com:riscv-boom/riscv-boom.git +[submodule "generators/sifive-blocks"] + path = generators/sifive-blocks + url = git@github.com:sifive/sifive-blocks.git diff --git a/build.sbt b/build.sbt index 41ccfc36..0f379698 100644 --- a/build.sbt +++ b/build.sbt @@ -42,6 +42,7 @@ def conditionalDependsOn(prj: Project): Project = { } lazy val example = conditionalDependsOn(project in file(".")) + .dependsOn(boom) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) diff --git a/generators/sifive-blocks b/generators/sifive-blocks new file mode 160000 index 00000000..24dd5378 --- /dev/null +++ b/generators/sifive-blocks @@ -0,0 +1 @@ +Subproject commit 24dd537894379dc160ed9e15d33444439822ab5b diff --git a/src/main/scala/boomexample/Configs.scala b/src/main/scala/boomexample/Configs.scala new file mode 100644 index 00000000..738e2922 --- /dev/null +++ b/src/main/scala/boomexample/Configs.scala @@ -0,0 +1,90 @@ +package boomexample + +import chisel3._ +import freechips.rocketchip.config.{Parameters, Config} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels} +import freechips.rocketchip.diplomacy.{LazyModule, ValName} +import freechips.rocketchip.devices.tilelink.BootROMParams +import freechips.rocketchip.tile.XLen +import testchipip._ + +class WithBootROM extends Config((site, here, up) => { + case BootROMParams => BootROMParams( + contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") +}) + +object ConfigValName { + implicit val valName = ValName("TestHarness") +} +import ConfigValName._ + +class WithBoomExampleTop extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomExampleTop()(p)).module) + } +}) + +class WithPWM extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomExampleTopWithPWMTL()(p)).module) +}) + +class WithPWMAXI4 extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomExampleTopWithPWMAXI4()(p)).module) +}) + +class WithBlockDeviceModel extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomExampleTopWithBlockDevice()(p)).module) + top.connectBlockDeviceModel() + top + } +}) + +class WithSimBlockDevice extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomExampleTopWithBlockDevice()(p)).module) + top.connectSimBlockDevice(clock, reset) + top + } +}) + +class BaseBoomExampleConfig extends Config( + new WithBootROM ++ + new boom.system.SmallBoomConfig) + +class DefaultBoomExampleConfig extends Config( + new WithBoomExampleTop ++ + new BaseBoomExampleConfig) + +class RoccBoomExampleConfig extends Config( + new WithRoccExample ++ + new DefaultBoomExampleConfig) + +class PWMBoomExampleConfig extends Config( + new WithPWM ++ + new BaseBoomExampleConfig) + +class PWMAXI4BoomExampleConfig extends Config( + new WithPWMAXI4 ++ + new BaseBoomExampleConfig) + +class SimBlockDeviceBoomExampleConfig extends Config( + new WithBlockDevice ++ + new WithSimBlockDevice ++ + new BaseBoomExampleConfig) + +class BlockDeviceModelBoomExampleConfig extends Config( + new WithBlockDevice ++ + new WithBlockDeviceModel ++ + new BaseBoomExampleConfig) + +class DualCoreBoomExampleConfig extends Config( + // Core gets tacked onto existing list + new boom.system.WithNBoomCores(2) ++ + new DefaultBoomExampleConfig) + +class RV32BoomExampleConfig extends Config( + new WithBootROM ++ + new boom.system.SmallRV32UnifiedBoomConfig) diff --git a/src/main/scala/boomexample/TestHarness.scala b/src/main/scala/boomexample/TestHarness.scala new file mode 100644 index 00000000..fd5e766d --- /dev/null +++ b/src/main/scala/boomexample/TestHarness.scala @@ -0,0 +1,44 @@ +package boomexample + +import chisel3._ +import chisel3.experimental._ +import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} +import freechips.rocketchip.diplomacy.LazyModule +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.util.GeneratorApp + +case object BuildTop extends Field[(Clock, Bool, Parameters) => BoomExampleTopModule[BoomExampleTop]] + +class TestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + val dut = p(BuildTop)(clock, reset.toBool, p) + dut.debug := DontCare + dut.connectSimAXIMem() + dut.connectSimAXIMMIO() + dut.dontTouchPorts() + dut.tieOffInterrupts() + dut.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case core.ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case core.ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + io.success := dut.connectSimSerial() +} + +object Generator extends GeneratorApp { + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs + generateFirrtl + generateAnno + generateTestSuiteMakefrags + generateArtefacts +} diff --git a/src/main/scala/boomexample/Top.scala b/src/main/scala/boomexample/Top.scala new file mode 100644 index 00000000..312d43fd --- /dev/null +++ b/src/main/scala/boomexample/Top.scala @@ -0,0 +1,54 @@ +package boomexample + +import chisel3._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.util.DontTouch +import testchipip._ +import example.{HasPeripheryPWMTL, HasPeripheryPWMAXI4, HasPeripheryPWMTLModuleImp, HasPeripheryPWMAXI4ModuleImp} + +//--------------------------------------------------------------------------------------------------------- + +class BoomExampleTop(implicit p: Parameters) extends boom.system.ExampleBoomSystem + with HasNoDebug + with HasPeripherySerial { + override lazy val module = new BoomExampleTopModule(this) +} + +class BoomExampleTopModule[+L <: BoomExampleTop](l: L) extends boom.system.ExampleBoomSystemModule(l) + with HasRTCModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with DontTouch + +//--------------------------------------------------------------------------------------------------------- + +class BoomExampleTopWithPWMTL(implicit p: Parameters) extends BoomExampleTop + with HasPeripheryPWMTL { + override lazy val module = new BoomExampleTopWithPWMTLModule(this) +} + +class BoomExampleTopWithPWMTLModule(l: BoomExampleTopWithPWMTL) extends BoomExampleTopModule(l) + with HasPeripheryPWMTLModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomExampleTopWithPWMAXI4(implicit p: Parameters) extends BoomExampleTop + with HasPeripheryPWMAXI4 { + override lazy val module = new BoomExampleTopWithPWMAXI4Module(this) +} + +class BoomExampleTopWithPWMAXI4Module(l: BoomExampleTopWithPWMAXI4) extends BoomExampleTopModule(l) + with HasPeripheryPWMAXI4ModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomExampleTopWithBlockDevice(implicit p: Parameters) extends BoomExampleTop + with HasPeripheryBlockDevice { + override lazy val module = new BoomExampleTopWithBlockDeviceModule(this) +} + +class BoomExampleTopWithBlockDeviceModule(l: BoomExampleTopWithBlockDevice) extends BoomExampleTopModule(l) + with HasPeripheryBlockDeviceModuleImp diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala index bcc745ad..bb156575 100644 --- a/src/main/scala/example/Top.scala +++ b/src/main/scala/example/Top.scala @@ -8,6 +8,8 @@ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util.DontTouch import testchipip._ +//--------------------------------------------------------------------------------------------------------- + class ExampleTop(implicit p: Parameters) extends ExampleRocketSystem //RocketSubsystem with CanHaveMasterAXI4MemPort with HasPeripheryBootROM @@ -27,6 +29,8 @@ class ExampleTopModule[+L <: ExampleTop](l: L) extends ExampleRocketSystemModule with HasPeripherySerialModuleImp with DontTouch +//--------------------------------------------------------------------------------------------------------- + class ExampleTopWithPWMTL(implicit p: Parameters) extends ExampleTop with HasPeripheryPWMTL { override lazy val module = new ExampleTopWithPWMTLModule(this) @@ -35,6 +39,8 @@ class ExampleTopWithPWMTL(implicit p: Parameters) extends ExampleTop class ExampleTopWithPWMTLModule(l: ExampleTopWithPWMTL) extends ExampleTopModule(l) with HasPeripheryPWMTLModuleImp +//--------------------------------------------------------------------------------------------------------- + class ExampleTopWithPWMAXI4(implicit p: Parameters) extends ExampleTop with HasPeripheryPWMAXI4 { override lazy val module = new ExampleTopWithPWMAXI4Module(this) @@ -43,6 +49,8 @@ class ExampleTopWithPWMAXI4(implicit p: Parameters) extends ExampleTop class ExampleTopWithPWMAXI4Module(l: ExampleTopWithPWMAXI4) extends ExampleTopModule(l) with HasPeripheryPWMAXI4ModuleImp +//--------------------------------------------------------------------------------------------------------- + class ExampleTopWithBlockDevice(implicit p: Parameters) extends ExampleTop with HasPeripheryBlockDevice { override lazy val module = new ExampleTopWithBlockDeviceModule(this) From c0b0e293c5e3ee41be2a49eb5250de7c118afe81 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 20 Apr 2019 21:18:20 -0700 Subject: [PATCH 031/120] removed boom package and combined into example | removed example from naming | split generator file --- build.sbt | 6 +- src/main/scala/boomexample/Configs.scala | 90 --------- src/main/scala/boomexample/TestHarness.scala | 44 ----- src/main/scala/boomexample/Top.scala | 54 ------ src/main/scala/example/Configs.scala | 181 +++++++++++++++---- src/main/scala/example/Generator.scala | 16 ++ src/main/scala/example/TestHarness.scala | 46 ++++- src/main/scala/example/Top.scala | 83 +++++++-- 8 files changed, 269 insertions(+), 251 deletions(-) delete mode 100644 src/main/scala/boomexample/Configs.scala delete mode 100644 src/main/scala/boomexample/TestHarness.scala delete mode 100644 src/main/scala/boomexample/Top.scala create mode 100644 src/main/scala/example/Generator.scala diff --git a/build.sbt b/build.sbt index 0f379698..633ff032 100644 --- a/build.sbt +++ b/build.sbt @@ -42,7 +42,7 @@ def conditionalDependsOn(prj: Project): Project = { } lazy val example = conditionalDependsOn(project in file(".")) - .dependsOn(boom) + .dependsOn(boom, sifive_blocks) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) @@ -60,3 +60,7 @@ lazy val `barstools-macros` = (project in file("./tools/barstools/macros/")) .dependsOn(mdf, rocketchip, rebarFirrtl) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) + +lazy val sifive_blocks = (project in file("generators/sifive-blocks")) + .dependsOn(rocketchip) + .settings(commonSettings) diff --git a/src/main/scala/boomexample/Configs.scala b/src/main/scala/boomexample/Configs.scala deleted file mode 100644 index 738e2922..00000000 --- a/src/main/scala/boomexample/Configs.scala +++ /dev/null @@ -1,90 +0,0 @@ -package boomexample - -import chisel3._ -import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels} -import freechips.rocketchip.diplomacy.{LazyModule, ValName} -import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.XLen -import testchipip._ - -class WithBootROM extends Config((site, here, up) => { - case BootROMParams => BootROMParams( - contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") -}) - -object ConfigValName { - implicit val valName = ValName("TestHarness") -} -import ConfigValName._ - -class WithBoomExampleTop extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomExampleTop()(p)).module) - } -}) - -class WithPWM extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomExampleTopWithPWMTL()(p)).module) -}) - -class WithPWMAXI4 extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomExampleTopWithPWMAXI4()(p)).module) -}) - -class WithBlockDeviceModel extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomExampleTopWithBlockDevice()(p)).module) - top.connectBlockDeviceModel() - top - } -}) - -class WithSimBlockDevice extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomExampleTopWithBlockDevice()(p)).module) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -class BaseBoomExampleConfig extends Config( - new WithBootROM ++ - new boom.system.SmallBoomConfig) - -class DefaultBoomExampleConfig extends Config( - new WithBoomExampleTop ++ - new BaseBoomExampleConfig) - -class RoccBoomExampleConfig extends Config( - new WithRoccExample ++ - new DefaultBoomExampleConfig) - -class PWMBoomExampleConfig extends Config( - new WithPWM ++ - new BaseBoomExampleConfig) - -class PWMAXI4BoomExampleConfig extends Config( - new WithPWMAXI4 ++ - new BaseBoomExampleConfig) - -class SimBlockDeviceBoomExampleConfig extends Config( - new WithBlockDevice ++ - new WithSimBlockDevice ++ - new BaseBoomExampleConfig) - -class BlockDeviceModelBoomExampleConfig extends Config( - new WithBlockDevice ++ - new WithBlockDeviceModel ++ - new BaseBoomExampleConfig) - -class DualCoreBoomExampleConfig extends Config( - // Core gets tacked onto existing list - new boom.system.WithNBoomCores(2) ++ - new DefaultBoomExampleConfig) - -class RV32BoomExampleConfig extends Config( - new WithBootROM ++ - new boom.system.SmallRV32UnifiedBoomConfig) diff --git a/src/main/scala/boomexample/TestHarness.scala b/src/main/scala/boomexample/TestHarness.scala deleted file mode 100644 index fd5e766d..00000000 --- a/src/main/scala/boomexample/TestHarness.scala +++ /dev/null @@ -1,44 +0,0 @@ -package boomexample - -import chisel3._ -import chisel3.experimental._ -import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} -import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.util.GeneratorApp - -case object BuildTop extends Field[(Clock, Bool, Parameters) => BoomExampleTopModule[BoomExampleTop]] - -class TestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - val dut = p(BuildTop)(clock, reset.toBool, p) - dut.debug := DontCare - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - io.success := dut.connectSimSerial() -} - -object Generator extends GeneratorApp { - val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - generateFirrtl - generateAnno - generateTestSuiteMakefrags - generateArtefacts -} diff --git a/src/main/scala/boomexample/Top.scala b/src/main/scala/boomexample/Top.scala deleted file mode 100644 index 312d43fd..00000000 --- a/src/main/scala/boomexample/Top.scala +++ /dev/null @@ -1,54 +0,0 @@ -package boomexample - -import chisel3._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.util.DontTouch -import testchipip._ -import example.{HasPeripheryPWMTL, HasPeripheryPWMAXI4, HasPeripheryPWMTLModuleImp, HasPeripheryPWMAXI4ModuleImp} - -//--------------------------------------------------------------------------------------------------------- - -class BoomExampleTop(implicit p: Parameters) extends boom.system.ExampleBoomSystem - with HasNoDebug - with HasPeripherySerial { - override lazy val module = new BoomExampleTopModule(this) -} - -class BoomExampleTopModule[+L <: BoomExampleTop](l: L) extends boom.system.ExampleBoomSystemModule(l) - with HasRTCModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp - with DontTouch - -//--------------------------------------------------------------------------------------------------------- - -class BoomExampleTopWithPWMTL(implicit p: Parameters) extends BoomExampleTop - with HasPeripheryPWMTL { - override lazy val module = new BoomExampleTopWithPWMTLModule(this) -} - -class BoomExampleTopWithPWMTLModule(l: BoomExampleTopWithPWMTL) extends BoomExampleTopModule(l) - with HasPeripheryPWMTLModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomExampleTopWithPWMAXI4(implicit p: Parameters) extends BoomExampleTop - with HasPeripheryPWMAXI4 { - override lazy val module = new BoomExampleTopWithPWMAXI4Module(this) -} - -class BoomExampleTopWithPWMAXI4Module(l: BoomExampleTopWithPWMAXI4) extends BoomExampleTopModule(l) - with HasPeripheryPWMAXI4ModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomExampleTopWithBlockDevice(implicit p: Parameters) extends BoomExampleTop - with HasPeripheryBlockDevice { - override lazy val module = new BoomExampleTopWithBlockDeviceModule(this) -} - -class BoomExampleTopWithBlockDeviceModule(l: BoomExampleTopWithBlockDevice) extends BoomExampleTopModule(l) - with HasPeripheryBlockDeviceModuleImp diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala index b7664614..72c40a1b 100644 --- a/src/main/scala/example/Configs.scala +++ b/src/main/scala/example/Configs.scala @@ -8,77 +8,190 @@ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.tile.XLen import testchipip._ +/** + * Class to specify where the BootRom file is (from `rebar` top) + */ class WithBootROM extends Config((site, here, up) => { case BootROMParams => BootROMParams( contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") }) +/** + * TODO: Why do we need this? + */ object ConfigValName { implicit val valName = ValName("TestHarness") } import ConfigValName._ -class WithExampleTop extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new ExampleTop()(p)).module) +// ------------------------------- +// Rocket Top Level System Configs +// ------------------------------- + +/** + * Class to specify a "plain" top level rocket-chip system + */ +class WithNormalRocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new RocketTop()(p)).module) } }) -class WithPWM extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new ExampleTopWithPWMTL()(p)).module) +/** + * Class to specify a top level rocket-chip system with PWM + */ +class WithPWMRocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new RocketTopWithPWMTL()(p)).module) }) -class WithPWMAXI4 extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new ExampleTopWithPWMAXI4()(p)).module) +/** + * Class to specify a top level rocket-chip system with a PWM AXI4 + */ +class WithPWMAXI4RocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new RocketTopWithPWMAXI4()(p)).module) }) -class WithBlockDeviceModel extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module) +/** + * Class to specify a top level rocket-chip system with a block device + */ +class WithBlockDeviceModelRocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) top.connectBlockDeviceModel() top } }) -class WithSimBlockDevice extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module) +/** + * Class to specify a top level rocket-chip system with a simulator block device + */ +class WithSimBlockDeviceRocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) top.connectSimBlockDevice(clock, reset) top } }) -class BaseExampleConfig extends Config( +// -------------- +// Rocket Configs +// -------------- + +class BaseRocketConfig extends Config( new WithBootROM ++ new freechips.rocketchip.system.DefaultConfig) -class DefaultExampleConfig extends Config( - new WithExampleTop ++ new BaseExampleConfig) +class DefaultRocketConfig extends Config( + new WithNormalRocketTop ++ + new BaseRocketConfig) -class RoccExampleConfig extends Config( - new WithRoccExample ++ new DefaultExampleConfig) +class RoccRocketConfig extends Config( + new WithRoccExample ++ + new DefaultRocketConfig) -class PWMConfig extends Config(new WithPWM ++ new BaseExampleConfig) +class PWMRocketConfig extends Config( + new WithPWMRocketTop ++ + new BaseRocketConfig) -class PWMAXI4Config extends Config(new WithPWMAXI4 ++ new BaseExampleConfig) +class PWMAXI4RocketConfig extends Config( + new WithPWMAXI4RocketTop ++ + new BaseRocketConfig) -class SimBlockDeviceConfig extends Config( - new WithBlockDevice ++ new WithSimBlockDevice ++ new BaseExampleConfig) +class SimBlockDeviceRocketConfig extends Config( + new WithBlockDevice ++ + new WithSimBlockDeviceRocketTop ++ + new BaseRocketConfig) -class BlockDeviceModelConfig extends Config( - new WithBlockDevice ++ new WithBlockDeviceModel ++ new BaseExampleConfig) +class BlockDeviceModelRocketConfig extends Config( + new WithBlockDevice ++ + new WithBlockDeviceModelRocketTop ++ + new BaseRocketConfig) -class WithTwoTrackers extends WithNBlockDeviceTrackers(2) -class WithFourTrackers extends WithNBlockDeviceTrackers(4) +class DualCoreRocketConfig extends Config( + new WithNBigCores(2) ++ + new DefaultRocketConfig) -class WithTwoMemChannels extends WithNMemoryChannels(2) -class WithFourMemChannels extends WithNMemoryChannels(4) +class RV32RocketConfig extends Config( + new WithRV32 ++ + new DefaultRocketConfig) -class DualCoreConfig extends Config( +// ----------------------------- +// BOOM Top Level System Configs +// ----------------------------- + +class WithNormalBoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomTop()(p)).module) + } +}) + +class WithPWMBoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomTopWithPWMTL()(p)).module) +}) + +class WithPWMAXI4BoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomTopWithPWMAXI4()(p)).module) +}) + +class WithBlockDeviceModelBoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) + top.connectBlockDeviceModel() + top + } +}) + +class WithSimBlockDeviceBoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) + top.connectSimBlockDevice(clock, reset) + top + } +}) + +// ------------ +// BOOM Configs +// ------------ + +class BaseBoomConfig extends Config( + new WithBootROM ++ + new boom.system.SmallBoomConfig) + +class DefaultBoomConfig extends Config( + new WithNormalBoomTop ++ + new BaseBoomConfig) + +class RoccBoomConfig extends Config( + new WithRoccExample ++ + new DefaultBoomConfig) + +class PWMBoomConfig extends Config( + new WithPWMBoomTop ++ + new BaseBoomConfig) + +class PWMAXI4BoomConfig extends Config( + new WithPWMAXI4BoomTop ++ + new BaseBoomConfig) + +class SimBlockDeviceBoomConfig extends Config( + new WithBlockDevice ++ + new WithSimBlockDeviceBoomTop ++ + new BaseBoomConfig) + +class BlockDeviceModelBoomConfig extends Config( + new WithBlockDevice ++ + new WithBlockDeviceModelBoomTop ++ + new BaseBoomConfig) + +class DualCoreBoomConfig extends Config( // Core gets tacked onto existing list - new WithNBigCores(2) ++ new DefaultExampleConfig) + new boom.system.WithNBoomCores(2) ++ + new DefaultBoomConfig) -class RV32ExampleConfig extends Config( - new WithRV32 ++ new DefaultExampleConfig) +class RV32BoomConfig extends Config( + new WithBootROM ++ + new boom.system.SmallRV32UnifiedBoomConfig) diff --git a/src/main/scala/example/Generator.scala b/src/main/scala/example/Generator.scala new file mode 100644 index 00000000..9b86a826 --- /dev/null +++ b/src/main/scala/example/Generator.scala @@ -0,0 +1,16 @@ +package example + +import chisel3._ +import chisel3.experimental._ +import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} +import freechips.rocketchip.diplomacy.LazyModule +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.util.GeneratorApp + +object Generator extends GeneratorApp { + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs + generateFirrtl + generateAnno + generateTestSuiteMakefrags + generateArtefacts +} diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala index a5af6240..a278c46b 100644 --- a/src/main/scala/example/TestHarness.scala +++ b/src/main/scala/example/TestHarness.scala @@ -7,14 +7,18 @@ import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp -case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]] +// ------------------- +// Rocket Test Harness +// ------------------- -class TestHarness(implicit val p: Parameters) extends Module { +case object BuildRocketTop extends Field[(Clock, Bool, Parameters) => RocketTopModule[RocketTop]] + +class RocketTestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) - val dut = p(BuildTop)(clock, reset.toBool, p) + val dut = p(BuildRocketTop)(clock, reset.toBool, p) dut.debug := DontCare dut.connectSimAXIMem() dut.connectSimAXIMMIO() @@ -35,10 +39,34 @@ class TestHarness(implicit val p: Parameters) extends Module { io.success := dut.connectSimSerial() } -object Generator extends GeneratorApp { - val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - generateFirrtl - generateAnno - generateTestSuiteMakefrags - generateArtefacts +// ----------------- +// BOOM Test Harness +// ----------------- + +case object BuildBoomTop extends Field[(Clock, Bool, Parameters) => BoomTopModule[BoomTop]] + +class BoomTestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + val dut = p(BuildBoomTop)(clock, reset.toBool, p) + dut.debug := DontCare + dut.connectSimAXIMem() + dut.connectSimAXIMMIO() + dut.dontTouchPorts() + dut.tieOffInterrupts() + dut.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case core.ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case core.ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + io.success := dut.connectSimSerial() } diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala index bb156575..4dbf5a53 100644 --- a/src/main/scala/example/Top.scala +++ b/src/main/scala/example/Top.scala @@ -8,54 +8,99 @@ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util.DontTouch import testchipip._ -//--------------------------------------------------------------------------------------------------------- +// ------------------------ +// Rocket Top Level Systems +// ------------------------ -class ExampleTop(implicit p: Parameters) extends ExampleRocketSystem //RocketSubsystem +class RocketTop(implicit p: Parameters) extends RocketSystem with CanHaveMasterAXI4MemPort with HasPeripheryBootROM -// with HasSystemErrorSlave -// with HasSyncExtInterrupts with HasNoDebug with HasPeripherySerial { - override lazy val module = new ExampleTopModule(this) + override lazy val module = new RocketTopModule(this) } -class ExampleTopModule[+L <: ExampleTop](l: L) extends ExampleRocketSystemModuleImp(l) // RocketSubsystemModuleImp(l) +class RocketTopModule[+L <: RocketTop](l: L) extends RocketSystemModuleImp(l) with HasRTCModuleImp with CanHaveMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp -// with HasExtInterruptsModuleImp with HasNoDebugModuleImp with HasPeripherySerialModuleImp with DontTouch //--------------------------------------------------------------------------------------------------------- -class ExampleTopWithPWMTL(implicit p: Parameters) extends ExampleTop +class RocketTopWithPWMTL(implicit p: Parameters) extends RocketTop with HasPeripheryPWMTL { - override lazy val module = new ExampleTopWithPWMTLModule(this) + override lazy val module = new RocketTopWithPWMTLModule(this) } -class ExampleTopWithPWMTLModule(l: ExampleTopWithPWMTL) - extends ExampleTopModule(l) with HasPeripheryPWMTLModuleImp +class RocketTopWithPWMTLModule(l: RocketTopWithPWMTL) + extends RocketTopModule(l) with HasPeripheryPWMTLModuleImp //--------------------------------------------------------------------------------------------------------- -class ExampleTopWithPWMAXI4(implicit p: Parameters) extends ExampleTop +class RocketTopWithPWMAXI4(implicit p: Parameters) extends RocketTop with HasPeripheryPWMAXI4 { - override lazy val module = new ExampleTopWithPWMAXI4Module(this) + override lazy val module = new RocketTopWithPWMAXI4Module(this) } -class ExampleTopWithPWMAXI4Module(l: ExampleTopWithPWMAXI4) - extends ExampleTopModule(l) with HasPeripheryPWMAXI4ModuleImp +class RocketTopWithPWMAXI4Module(l: RocketTopWithPWMAXI4) + extends RocketTopModule(l) with HasPeripheryPWMAXI4ModuleImp //--------------------------------------------------------------------------------------------------------- -class ExampleTopWithBlockDevice(implicit p: Parameters) extends ExampleTop +class RocketTopWithBlockDevice(implicit p: Parameters) extends RocketTop with HasPeripheryBlockDevice { - override lazy val module = new ExampleTopWithBlockDeviceModule(this) + override lazy val module = new RocketTopWithBlockDeviceModule(this) } -class ExampleTopWithBlockDeviceModule(l: ExampleTopWithBlockDevice) - extends ExampleTopModule(l) +class RocketTopWithBlockDeviceModule(l: RocketTopWithBlockDevice) + extends RocketTopModule(l) + with HasPeripheryBlockDeviceModuleImp + +// ---------------------- +// BOOM Top Level Systems +// ---------------------- + +class BoomTop(implicit p: Parameters) extends boom.system.BoomSystem + with HasNoDebug + with HasPeripherySerial { + override lazy val module = new BoomTopModule(this) +} + +class BoomTopModule[+L <: BoomTop](l: L) extends boom.system.BoomSystemModule(l) + with HasRTCModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with DontTouch + +//--------------------------------------------------------------------------------------------------------- + +class BoomTopWithPWMTL(implicit p: Parameters) extends BoomTop + with HasPeripheryPWMTL { + override lazy val module = new BoomTopWithPWMTLModule(this) +} + +class BoomTopWithPWMTLModule(l: BoomTopWithPWMTL) extends BoomTopModule(l) + with HasPeripheryPWMTLModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomTopWithPWMAXI4(implicit p: Parameters) extends BoomTop + with HasPeripheryPWMAXI4 { + override lazy val module = new BoomTopWithPWMAXI4Module(this) +} + +class BoomTopWithPWMAXI4Module(l: BoomTopWithPWMAXI4) extends BoomTopModule(l) + with HasPeripheryPWMAXI4ModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomTopWithBlockDevice(implicit p: Parameters) extends BoomTop + with HasPeripheryBlockDevice { + override lazy val module = new BoomTopWithBlockDeviceModule(this) +} + +class BoomTopWithBlockDeviceModule(l: BoomTopWithBlockDevice) extends BoomTopModule(l) with HasPeripheryBlockDeviceModuleImp From b8eadb99eb68a9b80afa5d25160a6f0c491fa37b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 20 Apr 2019 21:20:20 -0700 Subject: [PATCH 032/120] add back example to rocket system --- src/main/scala/example/Top.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala index 4dbf5a53..aa2f8d0d 100644 --- a/src/main/scala/example/Top.scala +++ b/src/main/scala/example/Top.scala @@ -12,7 +12,7 @@ import testchipip._ // Rocket Top Level Systems // ------------------------ -class RocketTop(implicit p: Parameters) extends RocketSystem +class RocketTop(implicit p: Parameters) extends ExampleRocketSystem with CanHaveMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -20,7 +20,7 @@ class RocketTop(implicit p: Parameters) extends RocketSystem override lazy val module = new RocketTopModule(this) } -class RocketTopModule[+L <: RocketTop](l: L) extends RocketSystemModuleImp(l) +class RocketTopModule[+L <: RocketTop](l: L) extends ExampleRocketSystemModuleImp(l) with HasRTCModuleImp with CanHaveMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp From eda0b113c1e7f9cd8c2aad49932fae72d019cfcc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 21 Apr 2019 14:41:02 -0700 Subject: [PATCH 033/120] more default subprojects | fix example builds --- src/main/scala/example/Top.scala | 4 ++-- variables.mk | 23 +++++++++++++++++------ 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala index aa2f8d0d..6850580f 100644 --- a/src/main/scala/example/Top.scala +++ b/src/main/scala/example/Top.scala @@ -63,13 +63,13 @@ class RocketTopWithBlockDeviceModule(l: RocketTopWithBlockDevice) // BOOM Top Level Systems // ---------------------- -class BoomTop(implicit p: Parameters) extends boom.system.BoomSystem +class BoomTop(implicit p: Parameters) extends boom.system.ExampleBoomSystem with HasNoDebug with HasPeripherySerial { override lazy val module = new BoomTopModule(this) } -class BoomTopModule[+L <: BoomTop](l: L) extends boom.system.BoomSystemModule(l) +class BoomTopModule[+L <: BoomTop](l: L) extends boom.system.ExampleBoomSystemModule(l) with HasRTCModuleImp with HasNoDebugModuleImp with HasPeripherySerialModuleImp diff --git a/variables.mk b/variables.mk index 5aea54a5..7b2f6ba0 100644 --- a/variables.mk +++ b/variables.mk @@ -3,7 +3,7 @@ ######################################################################################### ######################################################################################### -# default variables to invoke the generator +# default variables to invoke the generator for a example Rocket system # descriptions: # PROJECT = the scala package to find the MODEL/Generator in # MODEL = the top level module of the project (normally the harness) @@ -17,17 +17,28 @@ # SUB_PROJECT = use the specific subproject default variables ######################################################################################### PROJECT ?= example -MODEL ?= TestHarness -CONFIG ?= DefaultExampleConfig +MODEL ?= RocketTestHarness +CONFIG ?= DefaultRocketConfig CFG_PROJECT ?= $(PROJECT) SBT_PROJECT ?= $(PROJECT) TB ?= TestDriver -TOP ?= ExampleTop +TOP ?= RocketTop +# make it so that you only change 1 param to change most or all of them! SUB_PROJECT ?= example -ifeq ($(SUB_PROJECT),boom) # make it so that you only change 1 param to change them all! - SBT_PROJECT=boom +ifeq ($(SUB_PROJECT),boomexample) + # for a BOOM based system (provides all necessary params) + MODEL=BoomTestHarness + CONFIG=DefaultBoomConfig + TOP=BoomTop +endif +ifeq ($(SUB_PROJECT),boom) + # for BOOM developers (only need to provide a CONFIG) PROJECT=boom.system + MODEL=TestHarness + #CONFIG: User specified + CFG_PROJECT=boom.system + SBT_PROJECT=boom TOP=ExampleBoomSystem endif From 668047e3fdad7f6c0ca6dabf2e12014e40bb77b2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 21 Apr 2019 15:19:15 -0700 Subject: [PATCH 034/120] added GPIO config | breaks on building test harness --- src/main/scala/example/Configs.scala | 68 ++++++++++++++++++++++-- src/main/scala/example/TestHarness.scala | 1 + src/main/scala/example/Top.scala | 23 ++++++++ 3 files changed, 87 insertions(+), 5 deletions(-) diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala index 72c40a1b..3ace5fb2 100644 --- a/src/main/scala/example/Configs.scala +++ b/src/main/scala/example/Configs.scala @@ -7,6 +7,19 @@ import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.tile.XLen import testchipip._ +import sifive.blocks.devices.gpio._ + +/** + * TODO: Why do we need this? + */ +object ConfigValName { + implicit val valName = ValName("TestHarness") +} +import ConfigValName._ + +// ------------------------------- +// Common Configs +// ------------------------------- /** * Class to specify where the BootRom file is (from `rebar` top) @@ -17,12 +30,12 @@ class WithBootROM extends Config((site, here, up) => { }) /** - * TODO: Why do we need this? + * Class to add in GPIO */ -object ConfigValName { - implicit val valName = ValName("TestHarness") -} -import ConfigValName._ +class WithGPIO extends Config((site, here, up) => { + case PeripheryGPIOKey => List( + GPIOParams(address = 0x10012000, width = 4, includeIOF = true)) +}) // ------------------------------- // Rocket Top Level System Configs @@ -75,6 +88,16 @@ class WithSimBlockDeviceRocketTop extends Config((site, here, up) => { } }) +/** + * Class to specify a top level rocket-chip system with GPIO + */ +class WithGPIORocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new RocketTopWithGPIO()(p)).module) + top + } +}) + // -------------- // Rocket Configs // -------------- @@ -117,26 +140,43 @@ class RV32RocketConfig extends Config( new WithRV32 ++ new DefaultRocketConfig) +class GPIORocketConfig extends Config( + new WithGPIO ++ + new WithGPIORocketTop ++ + new BaseRocketConfig) + // ----------------------------- // BOOM Top Level System Configs // ----------------------------- +/** + * Class to specify a "plain" top level BOOM system + */ class WithNormalBoomTop extends Config((site, here, up) => { case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { Module(LazyModule(new BoomTop()(p)).module) } }) +/** + * Class to specify a top level BOOM system with PWM + */ class WithPWMBoomTop extends Config((site, here, up) => { case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => Module(LazyModule(new BoomTopWithPWMTL()(p)).module) }) +/** + * Class to specify a top level BOOM system with a PWM AXI4 + */ class WithPWMAXI4BoomTop extends Config((site, here, up) => { case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => Module(LazyModule(new BoomTopWithPWMAXI4()(p)).module) }) +/** + * Class to specify a top level BOOM system with a block device + */ class WithBlockDeviceModelBoomTop extends Config((site, here, up) => { case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) @@ -145,6 +185,9 @@ class WithBlockDeviceModelBoomTop extends Config((site, here, up) => { } }) +/** + * Class to specify a top level BOOM system with a simulator block device + */ class WithSimBlockDeviceBoomTop extends Config((site, here, up) => { case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) @@ -153,6 +196,16 @@ class WithSimBlockDeviceBoomTop extends Config((site, here, up) => { } }) +/** + * Class to specify a top level BOOM system with GPIO + */ +class WithGPIOBoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomTopWithGPIO()(p)).module) + top + } +}) + // ------------ // BOOM Configs // ------------ @@ -195,3 +248,8 @@ class DualCoreBoomConfig extends Config( class RV32BoomConfig extends Config( new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) + +class GPIOBoomConfig extends Config( + new WithGPIO ++ + new WithGPIOBoomTop ++ + new BaseBoomConfig) diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala index a278c46b..61296545 100644 --- a/src/main/scala/example/TestHarness.scala +++ b/src/main/scala/example/TestHarness.scala @@ -36,6 +36,7 @@ class RocketTestHarness(implicit val p: Parameters) extends Module { axi.w.bits := DontCare } }) + io.success := dut.connectSimSerial() } diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala index 6850580f..8a39e3d1 100644 --- a/src/main/scala/example/Top.scala +++ b/src/main/scala/example/Top.scala @@ -7,6 +7,7 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util.DontTouch import testchipip._ +import sifive.blocks.devices.gpio._ // ------------------------ // Rocket Top Level Systems @@ -59,6 +60,17 @@ class RocketTopWithBlockDeviceModule(l: RocketTopWithBlockDevice) extends RocketTopModule(l) with HasPeripheryBlockDeviceModuleImp +//--------------------------------------------------------------------------------------------------------- + +class RocketTopWithGPIO(implicit p: Parameters) extends RocketTop + with HasPeripheryGPIO { + override lazy val module = new RocketTopWithGPIOModule(this) +} + +class RocketTopWithGPIOModule(l: RocketTopWithGPIO) + extends RocketTopModule(l) + with HasPeripheryGPIOModuleImp + // ---------------------- // BOOM Top Level Systems // ---------------------- @@ -104,3 +116,14 @@ class BoomTopWithBlockDevice(implicit p: Parameters) extends BoomTop class BoomTopWithBlockDeviceModule(l: BoomTopWithBlockDevice) extends BoomTopModule(l) with HasPeripheryBlockDeviceModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop + with HasPeripheryGPIO { + override lazy val module = new BoomTopWithGPIOModule(this) +} + +class BoomTopWithGPIOModule(l: BoomTopWithGPIO) + extends BoomTopModule(l) + with HasPeripheryGPIOModuleImp From 180a2ab4a8f01f301127257f6ad7f6183505234a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 21 Apr 2019 16:07:30 -0700 Subject: [PATCH 035/120] harness builds with gpio tied off --- src/main/scala/example/Configs.scala | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala index 3ace5fb2..4326dadb 100644 --- a/src/main/scala/example/Configs.scala +++ b/src/main/scala/example/Configs.scala @@ -34,7 +34,7 @@ class WithBootROM extends Config((site, here, up) => { */ class WithGPIO extends Config((site, here, up) => { case PeripheryGPIOKey => List( - GPIOParams(address = 0x10012000, width = 4, includeIOF = true)) + GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) }) // ------------------------------- @@ -94,6 +94,11 @@ class WithSimBlockDeviceRocketTop extends Config((site, here, up) => { class WithGPIORocketTop extends Config((site, here, up) => { case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { val top = Module(LazyModule(new RocketTopWithGPIO()(p)).module) + for (gpio <- top.gpio) { + for (pin <- gpio.pins) { + pin.i.ival := false.B + } + } top } }) @@ -202,6 +207,11 @@ class WithSimBlockDeviceBoomTop extends Config((site, here, up) => { class WithGPIOBoomTop extends Config((site, here, up) => { case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { val top = Module(LazyModule(new BoomTopWithGPIO()(p)).module) + for (gpio <- top.gpio) { + for (pin <- gpio.pins) { + pin.i.ival := false.B + } + } top } }) From 47149a0649709dc48346c3964a221bcf84ad3e53 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 22 Apr 2019 14:47:53 -0700 Subject: [PATCH 036/120] change smallboom to boomconfig --- src/main/scala/example/Configs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala index 4326dadb..7c7faf47 100644 --- a/src/main/scala/example/Configs.scala +++ b/src/main/scala/example/Configs.scala @@ -222,7 +222,7 @@ class WithGPIOBoomTop extends Config((site, here, up) => { class BaseBoomConfig extends Config( new WithBootROM ++ - new boom.system.SmallBoomConfig) + new boom.system.BoomConfig) class DefaultBoomConfig extends Config( new WithNormalBoomTop ++ From 0278845009b772c9fe9c9ec607a0f93cf6da760a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 22 Apr 2019 16:28:37 -0700 Subject: [PATCH 037/120] separated mixins from configs --- src/main/scala/example/Configs.scala | 166 +-------------------------- 1 file changed, 1 insertion(+), 165 deletions(-) diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala index 7c7faf47..52ee21de 100644 --- a/src/main/scala/example/Configs.scala +++ b/src/main/scala/example/Configs.scala @@ -1,107 +1,9 @@ package example import chisel3._ -import freechips.rocketchip.config.{Parameters, Config} +import freechips.rocketchip.config.{Config} import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} -import freechips.rocketchip.diplomacy.{LazyModule, ValName} -import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.XLen import testchipip._ -import sifive.blocks.devices.gpio._ - -/** - * TODO: Why do we need this? - */ -object ConfigValName { - implicit val valName = ValName("TestHarness") -} -import ConfigValName._ - -// ------------------------------- -// Common Configs -// ------------------------------- - -/** - * Class to specify where the BootRom file is (from `rebar` top) - */ -class WithBootROM extends Config((site, here, up) => { - case BootROMParams => BootROMParams( - contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") -}) - -/** - * Class to add in GPIO - */ -class WithGPIO extends Config((site, here, up) => { - case PeripheryGPIOKey => List( - GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) -}) - -// ------------------------------- -// Rocket Top Level System Configs -// ------------------------------- - -/** - * Class to specify a "plain" top level rocket-chip system - */ -class WithNormalRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new RocketTop()(p)).module) - } -}) - -/** - * Class to specify a top level rocket-chip system with PWM - */ -class WithPWMRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new RocketTopWithPWMTL()(p)).module) -}) - -/** - * Class to specify a top level rocket-chip system with a PWM AXI4 - */ -class WithPWMAXI4RocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new RocketTopWithPWMAXI4()(p)).module) -}) - -/** - * Class to specify a top level rocket-chip system with a block device - */ -class WithBlockDeviceModelRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) - top.connectBlockDeviceModel() - top - } -}) - -/** - * Class to specify a top level rocket-chip system with a simulator block device - */ -class WithSimBlockDeviceRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -/** - * Class to specify a top level rocket-chip system with GPIO - */ -class WithGPIORocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithGPIO()(p)).module) - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } -}) // -------------- // Rocket Configs @@ -150,72 +52,6 @@ class GPIORocketConfig extends Config( new WithGPIORocketTop ++ new BaseRocketConfig) -// ----------------------------- -// BOOM Top Level System Configs -// ----------------------------- - -/** - * Class to specify a "plain" top level BOOM system - */ -class WithNormalBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomTop()(p)).module) - } -}) - -/** - * Class to specify a top level BOOM system with PWM - */ -class WithPWMBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomTopWithPWMTL()(p)).module) -}) - -/** - * Class to specify a top level BOOM system with a PWM AXI4 - */ -class WithPWMAXI4BoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomTopWithPWMAXI4()(p)).module) -}) - -/** - * Class to specify a top level BOOM system with a block device - */ -class WithBlockDeviceModelBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) - top.connectBlockDeviceModel() - top - } -}) - -/** - * Class to specify a top level BOOM system with a simulator block device - */ -class WithSimBlockDeviceBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -/** - * Class to specify a top level BOOM system with GPIO - */ -class WithGPIOBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithGPIO()(p)).module) - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } -}) - // ------------ // BOOM Configs // ------------ From f11901a393c6dfa68bc4f7dc0711a5db53b4ab4d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 22 Apr 2019 16:41:11 -0700 Subject: [PATCH 038/120] added configmixin file --- src/main/scala/example/ConfigMixins.scala | 170 ++++++++++++++++++++++ 1 file changed, 170 insertions(+) create mode 100644 src/main/scala/example/ConfigMixins.scala diff --git a/src/main/scala/example/ConfigMixins.scala b/src/main/scala/example/ConfigMixins.scala new file mode 100644 index 00000000..e9b113b1 --- /dev/null +++ b/src/main/scala/example/ConfigMixins.scala @@ -0,0 +1,170 @@ +package example + +import chisel3._ +import freechips.rocketchip.config.{Parameters, Config} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.diplomacy.{LazyModule, ValName} +import freechips.rocketchip.devices.tilelink.BootROMParams +import freechips.rocketchip.tile.XLen +import testchipip._ +import sifive.blocks.devices.gpio._ + +/** + * TODO: Why do we need this? + */ +object ConfigValName { + implicit val valName = ValName("TestHarness") +} +import ConfigValName._ + +// ----------------------- +// Common Parameter Mixins +// ----------------------- + +/** + * Class to specify where the BootRom file is (from `rebar` top) + */ +class WithBootROM extends Config((site, here, up) => { + case BootROMParams => BootROMParams( + contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") +}) + +/** + * Class to add in GPIO + */ +class WithGPIO extends Config((site, here, up) => { + case PeripheryGPIOKey => List( + GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) +}) + +// ---------------------------------------- +// Rocket Top Level System Parameter Mixins +// ---------------------------------------- + +/** + * Class to specify a "plain" top level rocket-chip system + */ +class WithNormalRocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new RocketTop()(p)).module) + } +}) + +/** + * Class to specify a top level rocket-chip system with PWM + */ +class WithPWMRocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new RocketTopWithPWMTL()(p)).module) +}) + +/** + * Class to specify a top level rocket-chip system with a PWM AXI4 + */ +class WithPWMAXI4RocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new RocketTopWithPWMAXI4()(p)).module) +}) + +/** + * Class to specify a top level rocket-chip system with a block device + */ +class WithBlockDeviceModelRocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) + top.connectBlockDeviceModel() + top + } +}) + +/** + * Class to specify a top level rocket-chip system with a simulator block device + */ +class WithSimBlockDeviceRocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) + top.connectSimBlockDevice(clock, reset) + top + } +}) + +/** + * Class to specify a top level rocket-chip system with GPIO + */ +class WithGPIORocketTop extends Config((site, here, up) => { + case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new RocketTopWithGPIO()(p)).module) + for (gpio <- top.gpio) { + for (pin <- gpio.pins) { + pin.i.ival := false.B + } + } + top + } +}) + +// -------------------------------------- +// BOOM Top Level System Parameter Mixins +// -------------------------------------- + +/** + * Class to specify a "plain" top level BOOM system + */ +class WithNormalBoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomTop()(p)).module) + } +}) + +/** + * Class to specify a top level BOOM system with PWM + */ +class WithPWMBoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomTopWithPWMTL()(p)).module) +}) + +/** + * Class to specify a top level BOOM system with a PWM AXI4 + */ +class WithPWMAXI4BoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomTopWithPWMAXI4()(p)).module) +}) + +/** + * Class to specify a top level BOOM system with a block device + */ +class WithBlockDeviceModelBoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) + top.connectBlockDeviceModel() + top + } +}) + +/** + * Class to specify a top level BOOM system with a simulator block device + */ +class WithSimBlockDeviceBoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) + top.connectSimBlockDevice(clock, reset) + top + } +}) + +/** + * Class to specify a top level BOOM system with GPIO + */ +class WithGPIOBoomTop extends Config((site, here, up) => { + case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomTopWithGPIO()(p)).module) + for (gpio <- top.gpio) { + for (pin <- gpio.pins) { + pin.i.ival := false.B + } + } + top + } +}) From 0e5e1bac15dcb064a4757966dacb4e9e444859db Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 22 Apr 2019 22:36:04 -0700 Subject: [PATCH 039/120] fix test harness builds --- README.md | 2 +- common.mk | 2 +- src/main/scala/example/TestHarness.scala | 6 ++++++ variables.mk | 19 ++++++++++--------- 4 files changed, 18 insertions(+), 11 deletions(-) diff --git a/README.md b/README.md index 887dce08..7748e53e 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,7 @@ **This branch is under development** **It currently has many submodules** -**Please run ./scripts/init-submodules-no-riscv-tools.sh to update submodules, unless you want to spend a long time waiting for submodule to clone** +**Please run ./scripts/init-submodules-no-riscv-tools.sh to update submodules, unless you want to spend a long time waiting for submodules to clone** This is a starter template for your custom RISC-V project. It will allow you to leverage the Chisel HDL and RocketChip SoC generator to produce a diff --git a/common.mk b/common.mk index b090285d..e2603be7 100644 --- a/common.mk +++ b/common.mk @@ -53,7 +53,7 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)" + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(FIRRTL_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)" grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala index 61296545..b7120329 100644 --- a/src/main/scala/example/TestHarness.scala +++ b/src/main/scala/example/TestHarness.scala @@ -18,6 +18,9 @@ class RocketTestHarness(implicit val p: Parameters) extends Module { val success = Output(Bool()) }) + // force Chisel to rename module + override def desiredName = "TestHarness" + val dut = p(BuildRocketTop)(clock, reset.toBool, p) dut.debug := DontCare dut.connectSimAXIMem() @@ -51,6 +54,9 @@ class BoomTestHarness(implicit val p: Parameters) extends Module { val success = Output(Bool()) }) + // force Chisel to rename module + override def desiredName = "TestHarness" + val dut = p(BuildBoomTop)(clock, reset.toBool, p) dut.debug := DontCare dut.connectSimAXIMem() diff --git a/variables.mk b/variables.mk index 7b2f6ba0..baf18d6a 100644 --- a/variables.mk +++ b/variables.mk @@ -6,7 +6,8 @@ # default variables to invoke the generator for a example Rocket system # descriptions: # PROJECT = the scala package to find the MODEL/Generator in -# MODEL = the top level module of the project (normally the harness) +# MODEL = the top level module of the project in Chisel (normally the harness) +# FIRRTL_MODEL = the top level module of the project in Firrtl (normally the harness) # CONFIG = the configuration class to give the parameters for the project # CFG_PROJECT = the scala package to find the CONFIG class # SBT_PROJECT = the SBT project that you should find the Generator class in @@ -16,13 +17,14 @@ # project specific: # SUB_PROJECT = use the specific subproject default variables ######################################################################################### -PROJECT ?= example -MODEL ?= RocketTestHarness -CONFIG ?= DefaultRocketConfig -CFG_PROJECT ?= $(PROJECT) -SBT_PROJECT ?= $(PROJECT) -TB ?= TestDriver -TOP ?= RocketTop +PROJECT ?= example +MODEL ?= RocketTestHarness +FIRRTL_MODEL ?= TestHarness +CONFIG ?= DefaultRocketConfig +CFG_PROJECT ?= $(PROJECT) +SBT_PROJECT ?= $(PROJECT) +TB ?= TestDriver +TOP ?= RocketTop # make it so that you only change 1 param to change most or all of them! SUB_PROJECT ?= example @@ -36,7 +38,6 @@ ifeq ($(SUB_PROJECT),boom) # for BOOM developers (only need to provide a CONFIG) PROJECT=boom.system MODEL=TestHarness - #CONFIG: User specified CFG_PROJECT=boom.system SBT_PROJECT=boom TOP=ExampleBoomSystem From 2bd70937cbe002173aad6e6b98875313cbb33fd7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 22 Apr 2019 23:26:13 -0700 Subject: [PATCH 040/120] support verilator | rename build variable --- common.mk | 2 +- sims/verisim/Makefile | 12 ++++++------ sims/verisim/verilator.mk | 4 ++-- variables.mk | 18 +++++++++--------- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/common.mk b/common.mk index e2603be7..d7703f7e 100644 --- a/common.mk +++ b/common.mk @@ -53,7 +53,7 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(FIRRTL_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)" + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)" grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 89d9c6e8..93f45d5a 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -41,11 +41,11 @@ include $(sim_dir)/verilator.mk model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug -model_header = $(model_dir)/V$(MODEL).h -model_header_debug = $(model_dir_debug)/V$(MODEL).h +model_header = $(model_dir)/V$(VLOG_MODEL).h +model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h -model_mk = $(model_dir)/V$(MODEL).mk -model_mk_debug = $(model_dir_debug)/V$(MODEL).mk +model_mk = $(model_dir)/V$(VLOG_MODEL).mk +model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules @@ -72,10 +72,10 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) # invoke make to make verilator sim rules ######################################################################################### $(sim): $(model_mk) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(VLOG_MODEL).mk $(sim_debug): $(model_mk_debug) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk ######################################################################################### # create a vcs vpd rule diff --git a/sims/verisim/verilator.mk b/sims/verisim/verilator.mk index 3af9b335..b0aaae62 100644 --- a/sims/verisim/verilator.mk +++ b/sims/verisim/verilator.mk @@ -39,9 +39,9 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz: ######################################################################################### VERILATOR := $(INSTALLED_VERILATOR) --cc --exe CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS -VERILATOR_FLAGS := --top-module $(MODEL) \ +VERILATOR_FLAGS := --top-module $(VLOG_MODEL) \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ --output-split 20000 \ -Wno-STMTDLY --x-assign unique \ - -O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR" + -O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" diff --git a/variables.mk b/variables.mk index baf18d6a..34d829fe 100644 --- a/variables.mk +++ b/variables.mk @@ -7,7 +7,7 @@ # descriptions: # PROJECT = the scala package to find the MODEL/Generator in # MODEL = the top level module of the project in Chisel (normally the harness) -# FIRRTL_MODEL = the top level module of the project in Firrtl (normally the harness) +# VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) # CONFIG = the configuration class to give the parameters for the project # CFG_PROJECT = the scala package to find the CONFIG class # SBT_PROJECT = the SBT project that you should find the Generator class in @@ -17,14 +17,14 @@ # project specific: # SUB_PROJECT = use the specific subproject default variables ######################################################################################### -PROJECT ?= example -MODEL ?= RocketTestHarness -FIRRTL_MODEL ?= TestHarness -CONFIG ?= DefaultRocketConfig -CFG_PROJECT ?= $(PROJECT) -SBT_PROJECT ?= $(PROJECT) -TB ?= TestDriver -TOP ?= RocketTop +PROJECT ?= example +MODEL ?= RocketTestHarness +VLOG_MODEL ?= TestHarness +CONFIG ?= DefaultRocketConfig +CFG_PROJECT ?= $(PROJECT) +SBT_PROJECT ?= $(PROJECT) +TB ?= TestDriver +TOP ?= RocketTop # make it so that you only change 1 param to change most or all of them! SUB_PROJECT ?= example From c1a0916e401c3febbc69c6a37e5a7c80fff11c85 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 23 Apr 2019 09:20:47 -0700 Subject: [PATCH 041/120] add asm/bmark tests to generator --- src/main/scala/example/Generator.scala | 126 ++++++++++++++++++++++++- 1 file changed, 124 insertions(+), 2 deletions(-) diff --git a/src/main/scala/example/Generator.scala b/src/main/scala/example/Generator.scala index 9b86a826..3a1300b4 100644 --- a/src/main/scala/example/Generator.scala +++ b/src/main/scala/example/Generator.scala @@ -1,13 +1,135 @@ package example +import scala.collection.mutable.LinkedHashSet import chisel3._ import chisel3.experimental._ import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} -import freechips.rocketchip.diplomacy.LazyModule +import freechips.rocketchip.subsystem.{RocketTilesKey} +import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.util.GeneratorApp +import freechips.rocketchip.util.{GeneratorApp} +import freechips.rocketchip.tile.{XLen} +import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} +import boom.system.{BoomTilesKey, BoomTestSuites} object Generator extends GeneratorApp { + val rv64RegrTestNames = LinkedHashSet( + "rv64ud-v-fcvt", + "rv64ud-p-fdiv", + "rv64ud-v-fadd", + "rv64uf-v-fadd", + "rv64um-v-mul", + "rv64mi-p-breakpoint", + "rv64uc-v-rvc", + "rv64ud-v-structural", + "rv64si-p-wfi", + "rv64um-v-divw", + "rv64ua-v-lrsc", + "rv64ui-v-fence_i", + "rv64ud-v-fcvt_w", + "rv64uf-v-fmin", + "rv64ui-v-sb", + "rv64ua-v-amomax_d", + "rv64ud-v-move", + "rv64ud-v-fclass", + "rv64ua-v-amoand_d", + "rv64ua-v-amoxor_d", + "rv64si-p-sbreak", + "rv64ud-v-fmadd", + "rv64uf-v-ldst", + "rv64um-v-mulh", + "rv64si-p-dirty") + + val rv32RegrTestNames = LinkedHashSet( + "rv32mi-p-ma_addr", + "rv32mi-p-csr", + "rv32ui-p-sh", + "rv32ui-p-lh", + "rv32uc-p-rvc", + "rv32mi-p-sbreak", + "rv32ui-p-sll") + + override def addTestSuites { + import freechips.rocketchip.system.DefaultTestSuites._ + val xlen = params(XLen) + + // TODO: for now only generate tests for the first rocket/boom tile in the subsystem + // TODO: support heterogenous systems? + + // rocket specific tests + params(RocketTilesKey).headOption.map { tileParams => + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv32ud)) + } else { + TestGeneration.addSuite(rv32udBenchmarks) + TestGeneration.addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv64ud)) + } + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + + // boom specific tests + params(BoomTilesKey).headOption.map { tileParams => + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) { + TestGeneration.addSuites(env.map(rv32ud)) + } + } else if (cfg.fLen >= 64) { + TestGeneration.addSuites(env.map(rv64ud)) + TestGeneration.addSuites(env.map(rv64uf)) + TestGeneration.addSuite(rv32udBenchmarks) + } + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) { + TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + } else { + TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + } + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + + // Include our BOOM-specific overrides. + val (rvi, rvu) = + if (xlen == 64) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites(rvu.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + rv64RegrTestNames -= "rv64mi-p-breakpoint" // TODO: breakpoints not implemented yet + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + } + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs generateFirrtl generateAnno From 862c217ff41ceb23bb4709a5ce497dd3aa2ecaa6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 23 Apr 2019 11:50:36 -0700 Subject: [PATCH 042/120] allow rocket builds | asm tests pass --- build.sbt | 12 ++++++++---- src/main/scala/example/Simulator.scala | 1 + variables.mk | 14 ++++++++++++++ 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/build.sbt b/build.sbt index 633ff032..55a28adf 100644 --- a/build.sbt +++ b/build.sbt @@ -24,10 +24,14 @@ lazy val rebarFirrtl = (project in file("tools/firrtl")) lazy val rocketchip = RootProject(file("generators/rocket-chip")) -lazy val testchipip = (project in file("generators/testchipip")) +lazy val rebarrocketchip = project .dependsOn(rocketchip) .settings(commonSettings) +lazy val testchipip = (project in file("generators/testchipip")) + .dependsOn(rebarrocketchip) + .settings(commonSettings) + // Checks for -DROCKET_USE_MAVEN. // If it's there, use a maven dependency. // Else, depend on subprojects in git submodules. @@ -46,7 +50,7 @@ lazy val example = conditionalDependsOn(project in file(".")) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) - .dependsOn(rocketchip) + .dependsOn(rebarrocketchip) .settings(commonSettings) lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) @@ -57,10 +61,10 @@ lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) .settings(commonSettings) lazy val `barstools-macros` = (project in file("./tools/barstools/macros/")) - .dependsOn(mdf, rocketchip, rebarFirrtl) + .dependsOn(mdf, rebarrocketchip, rebarFirrtl) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) - .dependsOn(rocketchip) + .dependsOn(rebarrocketchip) .settings(commonSettings) diff --git a/src/main/scala/example/Simulator.scala b/src/main/scala/example/Simulator.scala index 09c2cd77..98d69c8a 100644 --- a/src/main/scala/example/Simulator.scala +++ b/src/main/scala/example/Simulator.scala @@ -102,6 +102,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { firrtl.FileUtils.makeDirectory("./bootrom/") writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/") writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/") + writeResource("/project-template/bootrom/bootrom.img", "./bootrom/") } def writeFiles(cfg: GenerateSimConfig): Unit = { diff --git a/variables.mk b/variables.mk index 34d829fe..9b52c45c 100644 --- a/variables.mk +++ b/variables.mk @@ -42,6 +42,15 @@ ifeq ($(SUB_PROJECT),boom) SBT_PROJECT=boom TOP=ExampleBoomSystem endif +ifeq ($(SUB_PROJECT),rocketchip) + # for Rocket-chip developers + PROJECT=freechips.rocketchip.system + MODEL=TestHarness + CONFIG=DefaultConfig + CFG_PROJECT=freechips.rocketchip.system + SBT_PROJECT=rebarrocketchip + TOP=ExampleRocketSystem +endif ######################################################################################### # path to rocket-chip and testchipip @@ -55,6 +64,11 @@ REBAR_FIRRTL_DIR = $(base_dir)/tools/firrtl ######################################################################################### long_name = $(PROJECT).$(MODEL).$(CONFIG) +# if building from rocketchip, override the long_name to match what they expect +ifeq ($(SBT_PROJECT),rebarrocketchip) + long_name=$(PROJECT).$(CONFIG) +endif + FIRRTL_FILE ?= $(build_dir)/$(long_name).fir ANNO_FILE ?= $(build_dir)/$(long_name).anno.json VERILOG_FILE ?= $(build_dir)/$(long_name).top.v From 978832df9346ae4252211b7f2512a22dd0a09018 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 23 Apr 2019 11:53:18 -0700 Subject: [PATCH 043/120] added bootrom symlink to support rocket --- src/main/resources/project-template/bootrom | 1 + 1 file changed, 1 insertion(+) create mode 120000 src/main/resources/project-template/bootrom diff --git a/src/main/resources/project-template/bootrom b/src/main/resources/project-template/bootrom new file mode 120000 index 00000000..a77fb516 --- /dev/null +++ b/src/main/resources/project-template/bootrom @@ -0,0 +1 @@ +../../../../generators/rocket-chip/bootrom/ \ No newline at end of file From e0d1ba285d27367deed7f1cdec45834e7f0ecef9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 23 Apr 2019 16:20:23 -0700 Subject: [PATCH 044/120] Add Hwacha config to example project --- .gitmodules | 3 +++ build.sbt | 6 +++++- generators/hwacha | 1 + src/main/scala/example/Configs.scala | 8 ++++++++ variables.mk | 16 +++++++++++++--- 5 files changed, 30 insertions(+), 4 deletions(-) create mode 160000 generators/hwacha diff --git a/.gitmodules b/.gitmodules index 73e556a4..698c53b9 100644 --- a/.gitmodules +++ b/.gitmodules @@ -28,3 +28,6 @@ [submodule "generators/sifive-blocks"] path = generators/sifive-blocks url = git@github.com:sifive/sifive-blocks.git +[submodule "generators/hwacha"] + path = generators/hwacha + url = git@github.com:ucb-bar/hwacha.git diff --git a/build.sbt b/build.sbt index 55a28adf..9fdc386a 100644 --- a/build.sbt +++ b/build.sbt @@ -46,7 +46,11 @@ def conditionalDependsOn(prj: Project): Project = { } lazy val example = conditionalDependsOn(project in file(".")) - .dependsOn(boom, sifive_blocks) + .dependsOn(boom, hwacha, sifive_blocks) + .settings(commonSettings) + +lazy val hwacha = (project in file ("generators/hwacha")) + .dependsOn(rebarrocketchip) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) diff --git a/generators/hwacha b/generators/hwacha new file mode 160000 index 00000000..bc89157b --- /dev/null +++ b/generators/hwacha @@ -0,0 +1 @@ +Subproject commit bc89157b28b22ba59af6ddad1130f61749d648c1 diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala index 52ee21de..57e4300f 100644 --- a/src/main/scala/example/Configs.scala +++ b/src/main/scala/example/Configs.scala @@ -17,6 +17,10 @@ class DefaultRocketConfig extends Config( new WithNormalRocketTop ++ new BaseRocketConfig) +class HwachaConfig extends Config( + new hwacha.DefaultHwachaConfig ++ + new DefaultRocketConfig) + class RoccRocketConfig extends Config( new WithRoccExample ++ new DefaultRocketConfig) @@ -64,6 +68,10 @@ class DefaultBoomConfig extends Config( new WithNormalBoomTop ++ new BaseBoomConfig) +class HwachaBoomConfig extends Config( + new hwacha.DefaultHwachaConfig ++ + new DefaultBoomConfig) + class RoccBoomConfig extends Config( new WithRoccExample ++ new DefaultBoomConfig) diff --git a/variables.mk b/variables.mk index 9b52c45c..606bf47f 100644 --- a/variables.mk +++ b/variables.mk @@ -28,22 +28,22 @@ TOP ?= RocketTop # make it so that you only change 1 param to change most or all of them! SUB_PROJECT ?= example +# for a BOOM based system (provides all necessary params) ifeq ($(SUB_PROJECT),boomexample) - # for a BOOM based system (provides all necessary params) MODEL=BoomTestHarness CONFIG=DefaultBoomConfig TOP=BoomTop endif +# for BOOM developers (only need to provide a CONFIG) ifeq ($(SUB_PROJECT),boom) - # for BOOM developers (only need to provide a CONFIG) PROJECT=boom.system MODEL=TestHarness CFG_PROJECT=boom.system SBT_PROJECT=boom TOP=ExampleBoomSystem endif +# for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) - # for Rocket-chip developers PROJECT=freechips.rocketchip.system MODEL=TestHarness CONFIG=DefaultConfig @@ -51,6 +51,16 @@ ifeq ($(SUB_PROJECT),rocketchip) SBT_PROJECT=rebarrocketchip TOP=ExampleRocketSystem endif +# for Hwacha developers (only need to provide a CONFIG) +ifeq ($(SUB_PROJECT),hwacha) + PROJECT=freechips.rocketchip.system + MODEL=TestHarness + CFG_PROJECT=hwacha + SBT_PROJECT=hwacha + TOP=ExampleRocketSystem + TB=TestDriver + CONFIG=HwachaConfig +endif ######################################################################################### # path to rocket-chip and testchipip From 017a3c23507f922fdbdc894dd3233d7e20ec4a9a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 23 Apr 2019 18:34:42 -0700 Subject: [PATCH 045/120] support rocketchip longname from generator | extra comments | subprojects specify configs --- variables.mk | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/variables.mk b/variables.mk index 606bf47f..8e4947a7 100644 --- a/variables.mk +++ b/variables.mk @@ -26,15 +26,21 @@ SBT_PROJECT ?= $(PROJECT) TB ?= TestDriver TOP ?= RocketTop -# make it so that you only change 1 param to change most or all of them! +######################################################################################### +# subproject overrides +# description: +# - make it so that you only change 1 param to change most or all of them! +# - mainly intended for quick developer setup for common flags +# - for each you only need to specify a CONFIG +######################################################################################### SUB_PROJECT ?= example -# for a BOOM based system (provides all necessary params) + +# for a BOOM based example system ifeq ($(SUB_PROJECT),boomexample) MODEL=BoomTestHarness - CONFIG=DefaultBoomConfig TOP=BoomTop endif -# for BOOM developers (only need to provide a CONFIG) +# for BOOM developers ifeq ($(SUB_PROJECT),boom) PROJECT=boom.system MODEL=TestHarness @@ -46,12 +52,11 @@ endif ifeq ($(SUB_PROJECT),rocketchip) PROJECT=freechips.rocketchip.system MODEL=TestHarness - CONFIG=DefaultConfig CFG_PROJECT=freechips.rocketchip.system SBT_PROJECT=rebarrocketchip TOP=ExampleRocketSystem endif -# for Hwacha developers (only need to provide a CONFIG) +# for Hwacha developers ifeq ($(SUB_PROJECT),hwacha) PROJECT=freechips.rocketchip.system MODEL=TestHarness @@ -59,7 +64,6 @@ ifeq ($(SUB_PROJECT),hwacha) SBT_PROJECT=hwacha TOP=ExampleRocketSystem TB=TestDriver - CONFIG=HwachaConfig endif ######################################################################################### @@ -75,8 +79,8 @@ REBAR_FIRRTL_DIR = $(base_dir)/tools/firrtl long_name = $(PROJECT).$(MODEL).$(CONFIG) # if building from rocketchip, override the long_name to match what they expect -ifeq ($(SBT_PROJECT),rebarrocketchip) - long_name=$(PROJECT).$(CONFIG) +ifeq ($(PROJECT),freechips.rocketchip.system) + long_name=$(CFG_PROJECT).$(CONFIG) endif FIRRTL_FILE ?= $(build_dir)/$(long_name).fir From 4c3dc0889ce5fc9391def2a4af912cdc335ebaed Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Apr 2019 00:43:44 -0700 Subject: [PATCH 046/120] update make variable names | change hwacha to use its own generator --- common.mk | 2 +- sims/verisim/Makefile | 4 +-- sims/vsim/Makefile | 4 +-- variables.mk | 57 ++++++++++++++++++++++++------------------- 4 files changed, 37 insertions(+), 30 deletions(-) diff --git a/common.mk b/common.mk index d7703f7e..f5aea9b8 100644 --- a/common.mk +++ b/common.mk @@ -41,7 +41,7 @@ CHISEL_ARGS ?= $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) mkdir -p $(build_dir) - cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" + cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(CHISEL_ARGS) $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" ######################################################################################### # create verilog files rules and variables diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 93f45d5a..7de100d8 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -22,8 +22,8 @@ sim_name = verilator # vcs simulator types and rules ######################################################################################### sim_prefix = simulator -sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG) -sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug +sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) +sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug .PHONY: default debug default: $(sim) diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index be8fd716..374e2f89 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -22,8 +22,8 @@ sim_name = vcs # vcs simulator types and rules ######################################################################################### sim_prefix = simv -sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG) -sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug +sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) +sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug .PHONY: default debug default: $(sim) diff --git a/variables.mk b/variables.mk index 8e4947a7..6917f763 100644 --- a/variables.mk +++ b/variables.mk @@ -5,26 +5,28 @@ ######################################################################################### # default variables to invoke the generator for a example Rocket system # descriptions: -# PROJECT = the scala package to find the MODEL/Generator in +# SBT_PROJECT = the SBT project that you should find the classes/packages in # MODEL = the top level module of the project in Chisel (normally the harness) # VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) +# MODEL_PACKAGE = the scala package to find the MODEL in # CONFIG = the configuration class to give the parameters for the project -# CFG_PROJECT = the scala package to find the CONFIG class -# SBT_PROJECT = the SBT project that you should find the Generator class in +# CONFIG_PACKAGE = the scala package to find the CONFIG class +# GENERATOR_PACKAGE = the scala package to find the Generator class in # TB = wrapper over the TestHarness needed to simulate in VCS # TOP = top level module of the project (normally the module instantiated by the harness) # # project specific: # SUB_PROJECT = use the specific subproject default variables ######################################################################################### -PROJECT ?= example -MODEL ?= RocketTestHarness -VLOG_MODEL ?= TestHarness -CONFIG ?= DefaultRocketConfig -CFG_PROJECT ?= $(PROJECT) -SBT_PROJECT ?= $(PROJECT) -TB ?= TestDriver -TOP ?= RocketTop +SBT_PROJECT ?= example +MODEL ?= RocketTestHarness +VLOG_MODEL ?= TestHarness +MODEL_PACKAGE ?= $(SBT_PROJECT) +CONFIG ?= DefaultRocketConfig +CONFIG_PACKAGE ?= $(SBT_PROJECT) +GENERATOR_PACKAGE ?= $(SBT_PROJECT) +TB ?= TestDriver +TOP ?= RocketTop ######################################################################################### # subproject overrides @@ -42,28 +44,30 @@ ifeq ($(SUB_PROJECT),boomexample) endif # for BOOM developers ifeq ($(SUB_PROJECT),boom) - PROJECT=boom.system - MODEL=TestHarness - CFG_PROJECT=boom.system SBT_PROJECT=boom + MODEL_PACKAGE=boom.system + MODEL=TestHarness + CONFIG_PACKAGE=boom.system + GENERATOR_PACKAGE=boom.system TOP=ExampleBoomSystem endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) - PROJECT=freechips.rocketchip.system - MODEL=TestHarness - CFG_PROJECT=freechips.rocketchip.system SBT_PROJECT=rebarrocketchip + MODEL_PACKAGE=freechips.rocketchip.system + MODEL=TestHarness + CONFIG_PACKAGE=freechips.rocketchip.system + GENERATOR_PACKAGE=freechips.rocketchip.system TOP=ExampleRocketSystem endif # for Hwacha developers ifeq ($(SUB_PROJECT),hwacha) - PROJECT=freechips.rocketchip.system - MODEL=TestHarness - CFG_PROJECT=hwacha SBT_PROJECT=hwacha + MODEL_PACKAGE=freechips.rocketchip.system + MODEL=TestHarness + CONFIG_PACKAGE=hwacha + GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem - TB=TestDriver endif ######################################################################################### @@ -76,11 +80,14 @@ REBAR_FIRRTL_DIR = $(base_dir)/tools/firrtl ######################################################################################### # names of various files needed to compile and run things ######################################################################################### -long_name = $(PROJECT).$(MODEL).$(CONFIG) +long_name = $(MODEL_PACKAGE).$(MODEL).$(CONFIG) -# if building from rocketchip, override the long_name to match what they expect -ifeq ($(PROJECT),freechips.rocketchip.system) - long_name=$(CFG_PROJECT).$(CONFIG) +# match the long_name to what the specific generator will output +ifeq ($(GENERATOR_PACKAGE),freechips.rocketchip.system) + long_name=$(CONFIG_PACKAGE).$(CONFIG) +endif +ifeq ($(GENERATOR_PACKAGE),hwacha) + long_name=$(MODEL_PACKAGE).$(CONFIG) endif FIRRTL_FILE ?= $(build_dir)/$(long_name).fir From 575980e337e48446884c14f674f6f3592fd80356 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Apr 2019 11:18:12 -0700 Subject: [PATCH 047/120] track src changes correctly in make --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index f5aea9b8..16afa6f6 100644 --- a/common.mk +++ b/common.mk @@ -8,7 +8,7 @@ SHELL=/bin/bash ######################################################################################### lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null) -PACKAGES=rocket-chip testchipip boom +PACKAGES=rocket-chip testchipip boom hwacha sifive-blocks SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) ######################################################################################### From b88937b8a0cb664baea7d57f09360c07cb37c129 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 24 Apr 2019 18:23:26 -0700 Subject: [PATCH 048/120] Fix vcs tests for rocketchip and hwacha --- common.mk | 2 +- sims/verisim/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index 16afa6f6..f93e44a6 100644 --- a/common.mk +++ b/common.mk @@ -78,7 +78,7 @@ $(output_dir)/%.run: $(output_dir)/% $(sim) $(sim) +max-cycles=$(timeout_cycles) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) +verbose +max-cycles=$(timeout_cycles) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + $(sim) +permissive +verbose +max-cycles=$(timeout_cycles) +permissive-off $< 3>&1 1>&2 2>&3 | spike-dasm > $@ ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 7de100d8..485b2357 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -78,7 +78,7 @@ $(sim_debug): $(model_mk_debug) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk ######################################################################################### -# create a vcs vpd rule +# create a verisim vpd rule ######################################################################################### $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd From eedaeded177b6ba5aa417fdb56803c34ee32a50d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Apr 2019 18:33:23 -0700 Subject: [PATCH 049/120] add basic regression script --- scripts/regression.sh | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100755 scripts/regression.sh diff --git a/scripts/regression.sh b/scripts/regression.sh new file mode 100755 index 00000000..5908d40d --- /dev/null +++ b/scripts/regression.sh @@ -0,0 +1,22 @@ +#!/bin/bash + +# NOTE: TEMPORARY UNTIL CI IS ONLINE + +# Run by just giving the test to run (run-bmark-tests | run-asm-tests) +# Runs in vsim and verisim + +set -xe + +cd sims/vsim/ + +make SUB_PROJECT=example CONFIG=DefaultRocketConfig && make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 +make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig && make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 +make SUB_PROJECT=boom CONFIG=BoomConfig && make SUB_PROJECT=boom CONFIG=BoomConfig $1 +make SUB_PROJECT=rocketchip CONFIG=DefaultConfig && make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 + +cd ../verisim/ + +make SUB_PROJECT=example CONFIG=DefaultRocketConfig && make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 +make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig && make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 +make SUB_PROJECT=boom CONFIG=BoomConfig && make SUB_PROJECT=boom CONFIG=BoomConfig $1 +make SUB_PROJECT=rocketchip CONFIG=DefaultConfig && make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 From 8d190ee7e0222505c3d5766e47df362a3286b43e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Apr 2019 18:42:12 -0700 Subject: [PATCH 050/120] do subprojects first --- scripts/regression.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/scripts/regression.sh b/scripts/regression.sh index 5908d40d..3a893a51 100755 --- a/scripts/regression.sh +++ b/scripts/regression.sh @@ -9,14 +9,14 @@ set -xe cd sims/vsim/ +make SUB_PROJECT=rocketchip CONFIG=DefaultConfig && make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 +make SUB_PROJECT=boom CONFIG=BoomConfig && make SUB_PROJECT=boom CONFIG=BoomConfig $1 make SUB_PROJECT=example CONFIG=DefaultRocketConfig && make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig && make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 -make SUB_PROJECT=boom CONFIG=BoomConfig && make SUB_PROJECT=boom CONFIG=BoomConfig $1 -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig && make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 cd ../verisim/ +make SUB_PROJECT=rocketchip CONFIG=DefaultConfig && make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 +make SUB_PROJECT=boom CONFIG=BoomConfig && make SUB_PROJECT=boom CONFIG=BoomConfig $1 make SUB_PROJECT=example CONFIG=DefaultRocketConfig && make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig && make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 -make SUB_PROJECT=boom CONFIG=BoomConfig && make SUB_PROJECT=boom CONFIG=BoomConfig $1 -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig && make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 From 91ea25999dfa8429cb66c394b9dd9686a58c8ca9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Apr 2019 19:08:29 -0700 Subject: [PATCH 051/120] better exits --- scripts/regression.sh | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/scripts/regression.sh b/scripts/regression.sh index 3a893a51..3175891c 100755 --- a/scripts/regression.sh +++ b/scripts/regression.sh @@ -5,18 +5,27 @@ # Run by just giving the test to run (run-bmark-tests | run-asm-tests) # Runs in vsim and verisim -set -xe +set -ex +set -euo pipefail cd sims/vsim/ -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig && make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 -make SUB_PROJECT=boom CONFIG=BoomConfig && make SUB_PROJECT=boom CONFIG=BoomConfig $1 -make SUB_PROJECT=example CONFIG=DefaultRocketConfig && make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 -make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig && make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 +make SUB_PROJECT=rocketchip CONFIG=DefaultConfig +make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 +make SUB_PROJECT=boom CONFIG=BoomConfig +make SUB_PROJECT=boom CONFIG=BoomConfig $1 +make SUB_PROJECT=example CONFIG=DefaultRocketConfig +make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 +make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig +make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 cd ../verisim/ -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig && make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 -make SUB_PROJECT=boom CONFIG=BoomConfig && make SUB_PROJECT=boom CONFIG=BoomConfig $1 -make SUB_PROJECT=example CONFIG=DefaultRocketConfig && make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 -make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig && make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 +make SUB_PROJECT=rocketchip CONFIG=DefaultConfig +make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 +make SUB_PROJECT=boom CONFIG=BoomConfig +make SUB_PROJECT=boom CONFIG=BoomConfig $1 +make SUB_PROJECT=example CONFIG=DefaultRocketConfig +make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 +make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig +make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 From 2e53de6f2220886f561b7f7bf1b39995a5fd309f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 25 Apr 2019 13:33:08 -0700 Subject: [PATCH 052/120] Allow default configs for sub projects | have separate build_dir based on long_name --- variables.mk | 81 +++++++++++++++++++++++++++++++--------------------- 1 file changed, 49 insertions(+), 32 deletions(-) diff --git a/variables.mk b/variables.mk index 6917f763..bc1f78c1 100644 --- a/variables.mk +++ b/variables.mk @@ -3,7 +3,7 @@ ######################################################################################### ######################################################################################### -# default variables to invoke the generator for a example Rocket system +# variables to invoke the generator # descriptions: # SBT_PROJECT = the SBT project that you should find the classes/packages in # MODEL = the top level module of the project in Chisel (normally the harness) @@ -18,56 +18,73 @@ # project specific: # SUB_PROJECT = use the specific subproject default variables ######################################################################################### -SBT_PROJECT ?= example -MODEL ?= RocketTestHarness -VLOG_MODEL ?= TestHarness -MODEL_PACKAGE ?= $(SBT_PROJECT) -CONFIG ?= DefaultRocketConfig -CONFIG_PACKAGE ?= $(SBT_PROJECT) -GENERATOR_PACKAGE ?= $(SBT_PROJECT) -TB ?= TestDriver -TOP ?= RocketTop ######################################################################################### # subproject overrides # description: # - make it so that you only change 1 param to change most or all of them! # - mainly intended for quick developer setup for common flags -# - for each you only need to specify a CONFIG ######################################################################################### SUB_PROJECT ?= example +ifeq ($(SUB_PROJECT),example) + SBT_PROJECT ?= example + MODEL ?= RocketTestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= $(SBT_PROJECT) + CONFIG ?= DefaultRocketConfig + CONFIG_PACKAGE ?= $(SBT_PROJECT) + GENERATOR_PACKAGE ?= $(SBT_PROJECT) + TB ?= TestDriver + TOP ?= RocketTop +endif # for a BOOM based example system ifeq ($(SUB_PROJECT),boomexample) - MODEL=BoomTestHarness - TOP=BoomTop + SBT_PROJECT ?= example + MODEL ?= BoomTestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= $(SBT_PROJECT) + CONFIG ?= DefaultBoomConfig + CONFIG_PACKAGE ?= $(SBT_PROJECT) + GENERATOR_PACKAGE ?= $(SBT_PROJECT) + TB ?= TestDriver + TOP ?= BoomTop endif # for BOOM developers ifeq ($(SUB_PROJECT),boom) - SBT_PROJECT=boom - MODEL_PACKAGE=boom.system - MODEL=TestHarness - CONFIG_PACKAGE=boom.system - GENERATOR_PACKAGE=boom.system - TOP=ExampleBoomSystem + SBT_PROJECT ?= boom + MODEL ?= TestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= boom.system + CONFIG ?= BoomConfig + CONFIG_PACKAGE ?= boom.system + GENERATOR_PACKAGE ?= boom.system + TB ?= TestDriver + TOP ?= ExampleBoomSystem endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) - SBT_PROJECT=rebarrocketchip - MODEL_PACKAGE=freechips.rocketchip.system - MODEL=TestHarness - CONFIG_PACKAGE=freechips.rocketchip.system - GENERATOR_PACKAGE=freechips.rocketchip.system - TOP=ExampleRocketSystem + SBT_PROJECT ?= rebarrocketchip + MODEL ?= TestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= freechips.rocketchip.system + CONFIG ?= DefaultConfig + CONFIG_PACKAGE ?= freechips.rocketchip.system + GENERATOR_PACKAGE ?= freechips.rocketchip.system + TB ?= TestDriver + TOP ?= ExampleRocketSystem endif # for Hwacha developers ifeq ($(SUB_PROJECT),hwacha) - SBT_PROJECT=hwacha - MODEL_PACKAGE=freechips.rocketchip.system - MODEL=TestHarness - CONFIG_PACKAGE=hwacha - GENERATOR_PACKAGE=hwacha - TOP=ExampleRocketSystem + SBT_PROJECT ?= hwacha + MODEL ?= TestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= freechips.rocketchip.system + CONFIG ?= HwachaConfig + CONFIG_PACKAGE ?= hwacha + GENERATOR_PACKAGE ?= hwacha + TB ?= TestDriver + TOP ?= ExampleRocketSystem endif ######################################################################################### @@ -121,7 +138,7 @@ output_dir=$(sim_dir)/output ######################################################################################### # build output directory for compilation ######################################################################################### -build_dir=$(sim_dir)/generated-src +build_dir=$(sim_dir)/generated-src/$(long_name) ######################################################################################### # vsrcs needed to run projects From fa0cc26737437d56e12d1d051ce81fd7203f34d1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 29 Apr 2019 15:11:23 -0700 Subject: [PATCH 053/120] Remove references to VCS in variables.mk --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index bc1f78c1..43e1f0c5 100644 --- a/variables.mk +++ b/variables.mk @@ -12,7 +12,7 @@ # CONFIG = the configuration class to give the parameters for the project # CONFIG_PACKAGE = the scala package to find the CONFIG class # GENERATOR_PACKAGE = the scala package to find the Generator class in -# TB = wrapper over the TestHarness needed to simulate in VCS +# TB = wrapper over the TestHarness needed to simulate in a verilog simulator # TOP = top level module of the project (normally the module instantiated by the harness) # # project specific: From 2f2243df40e01b7cab75eba8c6023184ef15ed66 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 7 May 2019 21:49:48 -0700 Subject: [PATCH 054/120] Minor Makefile fixes --- sims/vsim/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 374e2f89..637dada0 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -61,7 +61,7 @@ VCS_NONCC_OPTS = \ -sverilog \ +incdir+$(build_dir) \ +define+CLOCK_PERIOD=1.0 \ - $(sim_vsrcs) \ + $(sim_vsrcs) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE_MEM_INIT \ @@ -94,4 +94,4 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) ######################################################################################### .PHONY: clean clean: - rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h + rm -rf $(sim_dir)/generated-src/* csrc $(sim_prefix)-* ucli.key vc_hdrs.h From cf9ef976768197a7ad004936c3eaaa68cecdb5bf Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 7 May 2019 23:05:13 -0700 Subject: [PATCH 055/120] Fix verilator clean --- sims/verisim/Makefile | 2 +- sims/vsim/Makefile | 4 ++-- variables.mk | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 485b2357..74c92244 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -90,4 +90,4 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) ######################################################################################### .PHONY: clean clean: - rm -rf $(build_dir) $(sim_prefix)-* + rm -rf $(gen_dir)/* $(sim_prefix)-* diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 637dada0..78242fd5 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -61,7 +61,7 @@ VCS_NONCC_OPTS = \ -sverilog \ +incdir+$(build_dir) \ +define+CLOCK_PERIOD=1.0 \ - $(sim_vsrcs) \ + $(sim_vsrcs) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE_MEM_INIT \ @@ -94,4 +94,4 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) ######################################################################################### .PHONY: clean clean: - rm -rf $(sim_dir)/generated-src/* csrc $(sim_prefix)-* ucli.key vc_hdrs.h + rm -rf $(gen_dir)/* csrc $(sim_prefix)-* ucli.key vc_hdrs.h diff --git a/variables.mk b/variables.mk index 43e1f0c5..15839578 100644 --- a/variables.mk +++ b/variables.mk @@ -138,7 +138,8 @@ output_dir=$(sim_dir)/output ######################################################################################### # build output directory for compilation ######################################################################################### -build_dir=$(sim_dir)/generated-src/$(long_name) +gen_dir=$(sim_dir)/generated-src +build_dir=$(gen_dir)/$(long_name) ######################################################################################### # vsrcs needed to run projects From 17bc3bf60dc13014f04f1f364081b565319072a8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 10 May 2019 02:24:10 -0700 Subject: [PATCH 056/120] Decouple SUB_PROJECT builds from example --- build.sbt | 5 ++++- common.mk | 4 ++-- .../example => example/src/main/scala}/ConfigMixins.scala | 0 .../scala/example => example/src/main/scala}/Configs.scala | 0 .../scala/example => example/src/main/scala}/Generator.scala | 0 {src/main/scala/example => example/src/main/scala}/PWM.scala | 0 .../example => example/src/main/scala}/TestHarness.scala | 0 {src/main/scala/example => example/src/main/scala}/Top.scala | 0 .../src/main/resources}/bootrom | 0 .../src/main/resources}/csrc/emulator.cc | 0 .../example => utilities/src/main/scala}/Simulator.scala | 4 ++-- 11 files changed, 8 insertions(+), 5 deletions(-) rename {src/main/scala/example => example/src/main/scala}/ConfigMixins.scala (100%) rename {src/main/scala/example => example/src/main/scala}/Configs.scala (100%) rename {src/main/scala/example => example/src/main/scala}/Generator.scala (100%) rename {src/main/scala/example => example/src/main/scala}/PWM.scala (100%) rename {src/main/scala/example => example/src/main/scala}/TestHarness.scala (100%) rename {src/main/scala/example => example/src/main/scala}/Top.scala (100%) rename {src/main/resources/project-template => utilities/src/main/resources}/bootrom (100%) rename {src/main/resources/project-template => utilities/src/main/resources}/csrc/emulator.cc (100%) rename {src/main/scala/example => utilities/src/main/scala}/Simulator.scala (97%) diff --git a/build.sbt b/build.sbt index 9fdc386a..faea4333 100644 --- a/build.sbt +++ b/build.sbt @@ -45,10 +45,13 @@ def conditionalDependsOn(prj: Project): Project = { } } -lazy val example = conditionalDependsOn(project in file(".")) +lazy val example = conditionalDependsOn(project in file("example")) .dependsOn(boom, hwacha, sifive_blocks) .settings(commonSettings) +lazy val utilities = conditionalDependsOn(project in file("utilities")) + .settings(commonSettings) + lazy val hwacha = (project in file ("generators/hwacha")) .dependsOn(rebarrocketchip) .settings(commonSettings) diff --git a/common.mk b/common.mk index f93e44a6..41ad6a84 100644 --- a/common.mk +++ b/common.mk @@ -9,7 +9,7 @@ SHELL=/bin/bash lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null) PACKAGES=rocket-chip testchipip boom hwacha sifive-blocks -SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) +SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/example/src/main/scala) $(call lookup_scala_srcs,$(base_dir)/utilities/src/main/scala) ######################################################################################### # rocket and testchipip classes @@ -32,7 +32,7 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(REBAR_FIRRTL_DIR)/src/main/scala) # create simulation args file rule ######################################################################################### $(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR) - cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" + cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" ######################################################################################### # create firrtl file rule and variables diff --git a/src/main/scala/example/ConfigMixins.scala b/example/src/main/scala/ConfigMixins.scala similarity index 100% rename from src/main/scala/example/ConfigMixins.scala rename to example/src/main/scala/ConfigMixins.scala diff --git a/src/main/scala/example/Configs.scala b/example/src/main/scala/Configs.scala similarity index 100% rename from src/main/scala/example/Configs.scala rename to example/src/main/scala/Configs.scala diff --git a/src/main/scala/example/Generator.scala b/example/src/main/scala/Generator.scala similarity index 100% rename from src/main/scala/example/Generator.scala rename to example/src/main/scala/Generator.scala diff --git a/src/main/scala/example/PWM.scala b/example/src/main/scala/PWM.scala similarity index 100% rename from src/main/scala/example/PWM.scala rename to example/src/main/scala/PWM.scala diff --git a/src/main/scala/example/TestHarness.scala b/example/src/main/scala/TestHarness.scala similarity index 100% rename from src/main/scala/example/TestHarness.scala rename to example/src/main/scala/TestHarness.scala diff --git a/src/main/scala/example/Top.scala b/example/src/main/scala/Top.scala similarity index 100% rename from src/main/scala/example/Top.scala rename to example/src/main/scala/Top.scala diff --git a/src/main/resources/project-template/bootrom b/utilities/src/main/resources/bootrom similarity index 100% rename from src/main/resources/project-template/bootrom rename to utilities/src/main/resources/bootrom diff --git a/src/main/resources/project-template/csrc/emulator.cc b/utilities/src/main/resources/csrc/emulator.cc similarity index 100% rename from src/main/resources/project-template/csrc/emulator.cc rename to utilities/src/main/resources/csrc/emulator.cc diff --git a/src/main/scala/example/Simulator.scala b/utilities/src/main/scala/Simulator.scala similarity index 97% rename from src/main/scala/example/Simulator.scala rename to utilities/src/main/scala/Simulator.scala index 98d69c8a..01edb066 100644 --- a/src/main/scala/example/Simulator.scala +++ b/utilities/src/main/scala/Simulator.scala @@ -1,4 +1,4 @@ -package example +package utilities import java.io.File @@ -102,7 +102,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { firrtl.FileUtils.makeDirectory("./bootrom/") writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/") writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/") - writeResource("/project-template/bootrom/bootrom.img", "./bootrom/") + writeResource("/bootrom/bootrom.img", "./bootrom/") } def writeFiles(cfg: GenerateSimConfig): Unit = { From db8b8f50cfa285cfe12e3513212164a69957d397 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 10 May 2019 15:29:28 -0700 Subject: [PATCH 057/120] Move example/utilities to generator directory --- common.mk | 4 ++-- .../example}/src/main/scala/ConfigMixins.scala | 0 .../example}/src/main/scala/Configs.scala | 6 +++++- .../example}/src/main/scala/Generator.scala | 0 {example => generators/example}/src/main/scala/PWM.scala | 0 .../example}/src/main/scala/TestHarness.scala | 0 {example => generators/example}/src/main/scala/Top.scala | 0 .../utilities}/src/main/resources/bootrom | 0 .../utilities}/src/main/resources/csrc/emulator.cc | 0 .../utilities}/src/main/scala/Simulator.scala | 0 10 files changed, 7 insertions(+), 3 deletions(-) rename {example => generators/example}/src/main/scala/ConfigMixins.scala (100%) rename {example => generators/example}/src/main/scala/Configs.scala (94%) rename {example => generators/example}/src/main/scala/Generator.scala (100%) rename {example => generators/example}/src/main/scala/PWM.scala (100%) rename {example => generators/example}/src/main/scala/TestHarness.scala (100%) rename {example => generators/example}/src/main/scala/Top.scala (100%) rename {utilities => generators/utilities}/src/main/resources/bootrom (100%) rename {utilities => generators/utilities}/src/main/resources/csrc/emulator.cc (100%) rename {utilities => generators/utilities}/src/main/scala/Simulator.scala (100%) diff --git a/common.mk b/common.mk index 41ad6a84..990304d5 100644 --- a/common.mk +++ b/common.mk @@ -8,8 +8,8 @@ SHELL=/bin/bash ######################################################################################### lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null) -PACKAGES=rocket-chip testchipip boom hwacha sifive-blocks -SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/example/src/main/scala) $(call lookup_scala_srcs,$(base_dir)/utilities/src/main/scala) +PACKAGES=rocket-chip testchipip boom hwacha sifive-blocks utilities example +SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) ######################################################################################### # rocket and testchipip classes diff --git a/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala similarity index 100% rename from example/src/main/scala/ConfigMixins.scala rename to generators/example/src/main/scala/ConfigMixins.scala diff --git a/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala similarity index 94% rename from example/src/main/scala/Configs.scala rename to generators/example/src/main/scala/Configs.scala index 57e4300f..4b6f1dcb 100644 --- a/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -2,7 +2,7 @@ package example import chisel3._ import freechips.rocketchip.config.{Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize} import testchipip._ // -------------- @@ -56,6 +56,10 @@ class GPIORocketConfig extends Config( new WithGPIORocketTop ++ new BaseRocketConfig) +class GB1MemoryConfig extends Config( + new WithExtMemSize((1<<30) * 1L) ++ + new DefaultRocketConfig) + // ------------ // BOOM Configs // ------------ diff --git a/example/src/main/scala/Generator.scala b/generators/example/src/main/scala/Generator.scala similarity index 100% rename from example/src/main/scala/Generator.scala rename to generators/example/src/main/scala/Generator.scala diff --git a/example/src/main/scala/PWM.scala b/generators/example/src/main/scala/PWM.scala similarity index 100% rename from example/src/main/scala/PWM.scala rename to generators/example/src/main/scala/PWM.scala diff --git a/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala similarity index 100% rename from example/src/main/scala/TestHarness.scala rename to generators/example/src/main/scala/TestHarness.scala diff --git a/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala similarity index 100% rename from example/src/main/scala/Top.scala rename to generators/example/src/main/scala/Top.scala diff --git a/utilities/src/main/resources/bootrom b/generators/utilities/src/main/resources/bootrom similarity index 100% rename from utilities/src/main/resources/bootrom rename to generators/utilities/src/main/resources/bootrom diff --git a/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc similarity index 100% rename from utilities/src/main/resources/csrc/emulator.cc rename to generators/utilities/src/main/resources/csrc/emulator.cc diff --git a/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala similarity index 100% rename from utilities/src/main/scala/Simulator.scala rename to generators/utilities/src/main/scala/Simulator.scala From ca3678087cda561b6b3d784dae625df83b870a1c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 10 May 2019 17:06:03 -0700 Subject: [PATCH 058/120] Add verilator_install make target for CI purposes --- sims/verisim/verilator.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sims/verisim/verilator.mk b/sims/verisim/verilator.mk index b0aaae62..a5c953c1 100644 --- a/sims/verisim/verilator.mk +++ b/sims/verisim/verilator.mk @@ -15,6 +15,9 @@ INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) $(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata touch $@ + +.PHONY: +verilator_install: $(INSTALLED_VERILATOR) $(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile $(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin From 01067df07ef220ea20d916f1ebb9b2779a92a0b2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 10 May 2019 21:09:00 -0700 Subject: [PATCH 059/120] Update build.sbt with correct locations of example/utilities --- build.sbt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index faea4333..6a06fcba 100644 --- a/build.sbt +++ b/build.sbt @@ -45,11 +45,11 @@ def conditionalDependsOn(prj: Project): Project = { } } -lazy val example = conditionalDependsOn(project in file("example")) +lazy val example = conditionalDependsOn(project in file("generators/example")) .dependsOn(boom, hwacha, sifive_blocks) .settings(commonSettings) -lazy val utilities = conditionalDependsOn(project in file("utilities")) +lazy val utilities = conditionalDependsOn(project in file("generators/utilities")) .settings(commonSettings) lazy val hwacha = (project in file ("generators/hwacha")) From a4d4101cf4c09c9d7f5a7310798f6086c13e5c0b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 11 May 2019 13:26:31 -0700 Subject: [PATCH 060/120] Fix bootrom symlink, update .gitignore to only ignore bootrom directory --- .gitignore | 2 +- generators/utilities/src/main/resources/bootrom | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 3866cf2f..551a8e97 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,4 @@ -bootrom +bootrom/* /Makefrag.pkgs target *.jar diff --git a/generators/utilities/src/main/resources/bootrom b/generators/utilities/src/main/resources/bootrom index a77fb516..fb0b1375 120000 --- a/generators/utilities/src/main/resources/bootrom +++ b/generators/utilities/src/main/resources/bootrom @@ -1 +1 @@ -../../../../generators/rocket-chip/bootrom/ \ No newline at end of file +../../../../rocket-chip/bootrom \ No newline at end of file From 462d3de5c9110db41dbacffd75f3b39d3d48cff9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 11 May 2019 17:14:09 -0700 Subject: [PATCH 061/120] Fix pointer to emulator.cc in GenerateSimFiles --- generators/utilities/src/main/scala/Simulator.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index 01edb066..b1b2c4c4 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -90,7 +90,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { "/vsrc/EICG_wrapper.v", ) ++ (sim match { // simulator specific files to include case VerilatorSimulator => Seq( - "/project-template/csrc/emulator.cc", + "/csrc/emulator.cc", "/csrc/verilator.h", ) case VCSSimulator => Seq( From 340ed90652c58ec3228706f49463cb12920f1307 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 11 May 2019 19:59:49 -0700 Subject: [PATCH 062/120] Remove permissive flag for verisim --- common.mk | 2 +- sims/verisim/Makefile | 3 +++ sims/vsim/Makefile | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/common.mk b/common.mk index 990304d5..c59d38b6 100644 --- a/common.mk +++ b/common.mk @@ -78,7 +78,7 @@ $(output_dir)/%.run: $(output_dir)/% $(sim) $(sim) +max-cycles=$(timeout_cycles) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) +permissive +verbose +max-cycles=$(timeout_cycles) +permissive-off $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + $(sim) $(PERMISSIVEON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVEOFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 74c92244..0c5644b8 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -25,6 +25,9 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug +PERMISSIVEON= +PERMISSIVEOFF= + .PHONY: default debug default: $(sim) debug: $(sim_debug) diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 78242fd5..212c3e6f 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -25,6 +25,9 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug +PERMISSIVEON=+permissive +PERMISSIVEOFF=+permissive-off + .PHONY: default debug default: $(sim) debug: $(sim_debug) From e5d9f539c56db9111bb44e4c58ef9fee61427567 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 11 May 2019 17:16:32 -0700 Subject: [PATCH 063/120] initial ci commit --- .circleci/build-toolchains.sh | 22 +++++ .circleci/build-verilator.sh | 18 ++++ .circleci/config.yml | 154 ++++++++++++++++++++++++++++++++++ .circleci/create-hash.sh | 17 ++++ .circleci/do-rtl-build.sh | 13 +++ 5 files changed, 224 insertions(+) create mode 100755 .circleci/build-toolchains.sh create mode 100755 .circleci/build-verilator.sh create mode 100644 .circleci/config.yml create mode 100755 .circleci/create-hash.sh create mode 100755 .circleci/do-rtl-build.sh diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh new file mode 100755 index 00000000..32560b27 --- /dev/null +++ b/.circleci/build-toolchains.sh @@ -0,0 +1,22 @@ +#!/bin/bash + +# create the riscv tools binaries from riscv-boom/boom-template with rocket-chip hash given by riscv-boom + +# turn echo on and error on earliest command +set -ex + +if [ ! -d "$HOME/esp-tools-install" ]; then + + cd $HOME/ + + # init all submodules including the tools + ./project/scripts/build-toolchains.sh esp-tools +fi + +if [ ! -d "$HOME/riscv-tools-install" ]; then + + cd $HOME/ + + # init all submodules including the tools + ./project/scripts/build-toolchains.sh riscv-tools +fi diff --git a/.circleci/build-verilator.sh b/.circleci/build-verilator.sh new file mode 100755 index 00000000..ae41be3a --- /dev/null +++ b/.circleci/build-verilator.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +# build verilator and init submodules with rocket-chip hash given by riscv-boom + +# turn echo on and error on earliest command +set -ex + +cd $HOME/project + +# init all submodules (according to what boom-template wants) +./scripts/init-submodules-no-riscv-tools.sh + +cd sims/verisim + +if [ ! -d "$HOME/project/sims/verisim/verilator" ]; then + # make boom-template verilator version + make verilator_install +fi diff --git a/.circleci/config.yml b/.circleci/config.yml new file mode 100644 index 00000000..45ad274e --- /dev/null +++ b/.circleci/config.yml @@ -0,0 +1,154 @@ +# CircleCI Configuration File + +# version of circleci +version: 2 + +# set of jobs to run +jobs: + install-toolchains: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} + + - run: + name: Building toolchains + command: | + .circleci/build-toolchains.sh + no_output_timeout: 120m + + - save_cache: + key: riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + paths: + - "/home/riscvuser/riscv-tools-install" + + - save_cache: + key: esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} + paths: + - "/home/riscvuser/esp-tools-install" + + install-verilator: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - restore_cache: + keys: + - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + + - run: + name: Build Verilator + command: | + .circleci/build-verilator.sh + no_output_timeout: 120m + + - save_cache: + key: verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + paths: + - "/home/riscvuser/project/sims/verisim/verilator" + + prepare-example: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - restore_cache: + keys: + - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + + - run: + name: Building BoomConfig using Verilator + command: .circleci/do-rtl-build.sh example + no_output_timeout: 120m + + - save_cache: + key: example-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project/sims/verisim" + + example-run-benchmark-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} + + - restore_cache: + keys: + - example-{{ .Branch }}-{{ .Revision }} + + - run: + name: Run example benchmark tests + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example + +# Order and dependencies of jobs to run +workflows: + version: 2 + build-and-test-boom-configs: + jobs: + # Make the toolchain + - install-toolchains + + # Build verilator + - install-verilator: + requires: + - install-toolchains + + # Prepare the verilator builds + - prepare-example: + requires: + - install-verilator + + # Run the respective tests + + # Run the example tests + - example-run-benchmark-tests: + requires: + - prepare-example diff --git a/.circleci/create-hash.sh b/.circleci/create-hash.sh new file mode 100755 index 00000000..2aff9727 --- /dev/null +++ b/.circleci/create-hash.sh @@ -0,0 +1,17 @@ +#!/bin/bash + +# get the hash of riscv-tools + +# turn echo on and error on earliest command +set -ex + +# enter bhd repo +cd $HOME/project + +# get the version of riscv-tools from the git submodule hash +git submodule status | grep "riscv-tools" | awk '{print$1}' | grep -o "[[:alnum:]]*" >> $HOME/riscv-tools.hash +git submodule status | grep "esp-tools" | awk '{print$1}' | grep -o "[[:alnum:]]*" >> $HOME/esp-tools.hash + +echo "Hashfile for riscv-tools and esp-tools created in $HOME" +echo "Contents: riscv-tools:$(cat $HOME/riscv-tools.hash)" +echo "Contents: esp-tools:$(cat $HOME/esp-tools.hash)" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh new file mode 100755 index 00000000..dcfaa8db --- /dev/null +++ b/.circleci/do-rtl-build.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +# create the different verilator builds of BOOM based on arg + +# turn echo on and error on earliest command +set -ex + +# this file assumes cache is updated correctly + +# enter the verisim directory and build the specific config +cd $HOME/project/sims/verisim +make clean +make SUB_PROJECT=$1 JAVA_ARGS="-Xmx2G -Xss8M" From 2dbe087fce3ae436175a211f4632d0ce283d6ef0 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 11 May 2019 17:29:10 -0700 Subject: [PATCH 064/120] have toolchain script point to rebar correctly --- .circleci/build-toolchains.sh | 4 ++-- scripts/build-toolchains.sh | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index 32560b27..1305617f 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -10,7 +10,7 @@ if [ ! -d "$HOME/esp-tools-install" ]; then cd $HOME/ # init all submodules including the tools - ./project/scripts/build-toolchains.sh esp-tools + REBAR_DIR=$HOME/project ./project/scripts/build-toolchains.sh esp-tools fi if [ ! -d "$HOME/riscv-tools-install" ]; then @@ -18,5 +18,5 @@ if [ ! -d "$HOME/riscv-tools-install" ]; then cd $HOME/ # init all submodules including the tools - ./project/scripts/build-toolchains.sh riscv-tools + REBAR_DIR=$HOME/project ./project/scripts/build-toolchains.sh riscv-tools fi diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index ddf9b462..3cc25c6a 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -6,6 +6,7 @@ set -o pipefail unamestr=$(uname) RDIR=$(pwd) +: ${REBAR_DIR:=$(pwd)} #default value is the PWD unless overridden if [ $# -ne 0 ]; then TOOLCHAIN=$1 @@ -25,7 +26,7 @@ RISCV="$(pwd)/$INSTALL_DIR" # install risc-v tools export RISCV="$RISCV" -git submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 +git -C $REBAR_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 cd "toolchains/$TOOLCHAIN" export MAKEFLAGS="-j16" ./build.sh From 22599520874c378a710225a6134fec2d9a0a7473 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 11 May 2019 17:33:06 -0700 Subject: [PATCH 065/120] rename the workflow --- .circleci/config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 45ad274e..50466a24 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -131,7 +131,7 @@ jobs: # Order and dependencies of jobs to run workflows: version: 2 - build-and-test-boom-configs: + build-and-test-rebar-integration: jobs: # Make the toolchain - install-toolchains From 1ef687605d057c2a6b85169a5f9a744e809d64e5 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 11 May 2019 17:43:20 -0700 Subject: [PATCH 066/120] remove old boom references | build-toolchain rebar directory fix --- .circleci/config.yml | 2 +- scripts/build-toolchains.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 50466a24..e0274023 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -87,7 +87,7 @@ jobs: - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - run: - name: Building BoomConfig using Verilator + name: Building the example subproject using Verilator command: .circleci/do-rtl-build.sh example no_output_timeout: 120m diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 3cc25c6a..9b659109 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -27,7 +27,7 @@ RISCV="$(pwd)/$INSTALL_DIR" # install risc-v tools export RISCV="$RISCV" git -C $REBAR_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 -cd "toolchains/$TOOLCHAIN" +cd "$REBAR_DIR/toolchains/$TOOLCHAIN" export MAKEFLAGS="-j16" ./build.sh cd $RDIR From e109831b0b5b15fa7d750a3ea7a0e0567201e4ef Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 11 May 2019 18:23:38 -0700 Subject: [PATCH 067/120] more renaming | proper place to git submodule update --- .circleci/build-toolchains.sh | 2 +- .circleci/build-verilator.sh | 7 ++----- .circleci/do-rtl-build.sh | 8 +++++--- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index 1305617f..a2e37381 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -1,6 +1,6 @@ #!/bin/bash -# create the riscv tools binaries from riscv-boom/boom-template with rocket-chip hash given by riscv-boom +# create the riscv tools/esp tools binaries # turn echo on and error on earliest command set -ex diff --git a/.circleci/build-verilator.sh b/.circleci/build-verilator.sh index ae41be3a..00cd7217 100755 --- a/.circleci/build-verilator.sh +++ b/.circleci/build-verilator.sh @@ -1,18 +1,15 @@ #!/bin/bash -# build verilator and init submodules with rocket-chip hash given by riscv-boom +# build verilator # turn echo on and error on earliest command set -ex cd $HOME/project -# init all submodules (according to what boom-template wants) -./scripts/init-submodules-no-riscv-tools.sh - cd sims/verisim if [ ! -d "$HOME/project/sims/verisim/verilator" ]; then - # make boom-template verilator version + # make verilator make verilator_install fi diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index dcfaa8db..e8336ae2 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -1,13 +1,15 @@ #!/bin/bash -# create the different verilator builds of BOOM based on arg +# create the different verilator builds arg (subproject) # turn echo on and error on earliest command set -ex -# this file assumes cache is updated correctly +# init all submodules +cd $HOME/project +./scripts/init-submodules-no-riscv-tools.sh # enter the verisim directory and build the specific config -cd $HOME/project/sims/verisim +cd sims/verisim make clean make SUB_PROJECT=$1 JAVA_ARGS="-Xmx2G -Xss8M" From 9f7f94b6f979ecb9f39a5e796516c95c359ec0b9 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 11 May 2019 18:35:34 -0700 Subject: [PATCH 068/120] parallelize toolchain builds with verilator --- .circleci/build-toolchains.sh | 13 +++------- .circleci/config.yml | 47 ++++++++++++++++++++++++++--------- 2 files changed, 38 insertions(+), 22 deletions(-) diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index a2e37381..28b87caa 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -1,22 +1,15 @@ #!/bin/bash # create the riscv tools/esp tools binaries +# passed in as # turn echo on and error on earliest command set -ex -if [ ! -d "$HOME/esp-tools-install" ]; then +if [ ! -d "$HOME/$1-install" ]; then cd $HOME/ # init all submodules including the tools - REBAR_DIR=$HOME/project ./project/scripts/build-toolchains.sh esp-tools -fi - -if [ ! -d "$HOME/riscv-tools-install" ]; then - - cd $HOME/ - - # init all submodules including the tools - REBAR_DIR=$HOME/project ./project/scripts/build-toolchains.sh riscv-tools + REBAR_DIR=$HOME/project ./project/scripts/build-toolchains.sh $1 fi diff --git a/.circleci/config.yml b/.circleci/config.yml index e0274023..26a162e0 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -5,7 +5,7 @@ version: 2 # set of jobs to run jobs: - install-toolchains: + install-riscv-toolchain: docker: - image: riscvboom/riscvboom-images:0.0.5 environment: @@ -25,14 +25,10 @@ jobs: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} - - run: - name: Building toolchains + name: Building riscv-tools toolchain command: | - .circleci/build-toolchains.sh + .circleci/build-toolchains.sh riscv-tools no_output_timeout: 120m - save_cache: @@ -40,6 +36,32 @@ jobs: paths: - "/home/riscvuser/riscv-tools-install" + install-esp-toolchain: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} + + - run: + name: Building esp-tools toolchain + command: | + .circleci/build-toolchains.sh esp-tools + no_output_timeout: 120m + - save_cache: key: esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} paths: @@ -133,13 +155,13 @@ workflows: version: 2 build-and-test-rebar-integration: jobs: - # Make the toolchain - - install-toolchains + # Make the toolchains + - install-riscv-toolchain + + - install-esp-toolchain # Build verilator - - install-verilator: - requires: - - install-toolchains + - install-verilator # Prepare the verilator builds - prepare-example: @@ -152,3 +174,4 @@ workflows: - example-run-benchmark-tests: requires: - prepare-example + - install-riscv-toolchain From 8f3426362dff2613ab3f680bde0c4bff84e9dd53 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 11 May 2019 18:52:13 -0700 Subject: [PATCH 069/120] need riscv-tools for verilator build --- .circleci/config.yml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 26a162e0..be9c6372 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -104,6 +104,15 @@ jobs: # Checkout the code - checkout + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - restore_cache: keys: - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} @@ -138,10 +147,6 @@ jobs: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} - - restore_cache: keys: - example-{{ .Branch }}-{{ .Revision }} From 1a6a5ea875164312ff6bc1b583729f1c62bcfa86 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 11 May 2019 18:55:04 -0700 Subject: [PATCH 070/120] correct dependencies for runs --- .circleci/config.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index be9c6372..a93642d8 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -171,6 +171,7 @@ workflows: # Prepare the verilator builds - prepare-example: requires: + - install-riscv-toolchain - install-verilator # Run the respective tests @@ -178,5 +179,5 @@ workflows: # Run the example tests - example-run-benchmark-tests: requires: - - prepare-example - install-riscv-toolchain + - prepare-example From e35d299ad413e1b1d89aff2da7d9f4f7be383334 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 11 May 2019 20:31:00 -0700 Subject: [PATCH 071/120] store all source/collateral when moving to test run --- .circleci/config.yml | 2 +- .circleci/do-rtl-build.sh | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index a93642d8..63db649e 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -125,7 +125,7 @@ jobs: - save_cache: key: example-{{ .Branch }}-{{ .Revision }} paths: - - "/home/riscvuser/project/sims/verisim" + - "/home/riscvuser/project" example-run-benchmark-tests: docker: diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index e8336ae2..02d02984 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -13,3 +13,5 @@ cd $HOME/project cd sims/verisim make clean make SUB_PROJECT=$1 JAVA_ARGS="-Xmx2G -Xss8M" + +rm -rf ../../project From b2d46037a59e29924d5333fd2f0c2d54137d4d93 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sun, 12 May 2019 12:16:10 -0700 Subject: [PATCH 072/120] add status badge for master | add ci readme | add more benchmark tests --- .circleci/README.md | 54 ++++++++ .circleci/config.yml | 290 ++++++++++++++++++++++++++++++++++++++++++- README.md | 2 +- 3 files changed, 344 insertions(+), 2 deletions(-) create mode 100644 .circleci/README.md diff --git a/.circleci/README.md b/.circleci/README.md new file mode 100644 index 00000000..50ede340 --- /dev/null +++ b/.circleci/README.md @@ -0,0 +1,54 @@ +REBAR CI +======== + +Website: https://circleci.com/gh/ucb-bar/project-template + +CircleCI Brief Explanation +--------------------------- + +CircleCI is controlled by the `config.yml` script. +It consists of a *workflow* which has a series of *jobs* within it that do particular tasks. +All jobs in the workflow must pass for the CI run to be successful. + +At the bottom of the `config.yml` there is a `workflows:` section that specifies the order in which the jobs of the workflow should run. +For example: + + - prepare-rocketchip: + requires: + - install-riscv-toolchain + - install-verilator + +This specifies that the `prepare-rocketchip` job needs the `install-riscv-toolchain` and `install-verilator` steps to run before it can run. + +All jobs in the CI workflow are specified at the top of `config.yml` +They specify a docker image to use (in this case a riscv-boom image since that is already available and works nicely) and an environment. +Finally, in the `steps:` section, the steps are run sequentially and state persists throughout a job. +So when you run something like `checkout` the next step has the checked out code. +Caching in the job is done by giving a file to cache on. +`restore_cache:` loads the cache into the environment if the key matches while `save_cache:` writes to the cache with the key IF IT IS NOT PRESENT. +Note, if the cache is already present for that key, the write to it is ignored. +Here the key is built from a string where the `checksum` portion converts the file given into a hash. + +.circleci directory +------------------- + +This directory contains all the collateral for the REBAR CI to work. +The following is included: + + build-toolchains.sh # build either riscv-tools or esp-tools + build-verilator.sh # build verilator + create-hash.sh # create hashes of riscv-tools/esp-tools so circleci caching can work + do-rtl-build.sh # use verilator to build a sim executable + config.yml # main circleci config script to enumerate jobs/workflows + +How things are setup for REBAR +------------------------------ + +The steps for CI to run are as follows. +1st, build the toolchains in parallel (note: `esp-tools` is currently not used in the run). +The docker image sets up the `PATH` and `RISCV` variable so that `riscv-tools` is the default (currently the `env.sh` script that is created at tool build is unused). +2nd, install verilator using the `*.mk` to cache unique versions of verilator (mainly for if verilator is bumped). +3rd, create the simulator binary. +This requires the `riscv-tools` for `fesvr` and `verilator` to be able to build the binary. +This stores all collateral for the tests (srcs, generated-srcs, sim binary, etc) to run "out of the gate" in the next job (make needs everything or else it will run again). +4th, finally run the tests that were wanted. diff --git a/.circleci/config.yml b/.circleci/config.yml index 63db649e..4a1d063b 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -127,6 +127,142 @@ jobs: paths: - "/home/riscvuser/project" + prepare-boomexample: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + + - run: + name: Building the boomexample subproject using Verilator + command: .circleci/do-rtl-build.sh boomexample + no_output_timeout: 120m + + - save_cache: + key: boomexample-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project" + + prepare-boom: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + + - run: + name: Building the boom subproject using Verilator + command: .circleci/do-rtl-build.sh boom + no_output_timeout: 120m + + - save_cache: + key: boom-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project" + + prepare-rocketchip: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + + - run: + name: Building the rocketchip subproject using Verilator + command: .circleci/do-rtl-build.sh rocketchip + no_output_timeout: 120m + + - save_cache: + key: rocketchip-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project" + + prepare-hwacha: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + + - run: + name: Building the hwacha subproject using Verilator + command: .circleci/do-rtl-build.sh hwacha + no_output_timeout: 120m + + - save_cache: + key: hwacha-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project" + example-run-benchmark-tests: docker: - image: riscvboom/riscvboom-images:0.0.5 @@ -155,6 +291,118 @@ jobs: name: Run example benchmark tests command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example + boomexample-run-benchmark-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - boomexample-{{ .Branch }}-{{ .Revision }} + + - run: + name: Run boomexample benchmark tests + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample + + boom-run-benchmark-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - boom-{{ .Branch }}-{{ .Revision }} + + - run: + name: Run boom benchmark tests + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boom + + rocketchip-run-benchmark-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - rocketchip-{{ .Branch }}-{{ .Revision }} + + - run: + name: Run rocketchip benchmark tests + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=rocketchip + + hwacha-run-benchmark-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - hwacha-{{ .Branch }}-{{ .Revision }} + + - run: + name: Run hwacha benchmark tests + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha + # Order and dependencies of jobs to run workflows: version: 2 @@ -172,7 +420,27 @@ workflows: - prepare-example: requires: - install-riscv-toolchain - - install-verilator + - install-verilator + + - prepare-boomexample: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-boom: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-rocketchip: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-hwacha: + requires: + - install-riscv-toolchain + - install-verilator # Run the respective tests @@ -181,3 +449,23 @@ workflows: requires: - install-riscv-toolchain - prepare-example + + - boomexample-run-benchmark-tests: + requires: + - install-riscv-toolchain + - prepare-boomexample + + - boom-run-benchmark-tests: + requires: + - install-riscv-toolchain + - prepare-boom + + - rocketchip-run-benchmark-tests: + requires: + - install-riscv-toolchain + - prepare-rocketchip + + - hwacha-run-benchmark-tests: + requires: + - install-riscv-toolchain + - prepare-hwacha diff --git a/README.md b/README.md index 7748e53e..9e2b31fa 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# RISC-V Project Template +# RISC-V Project Template [![CircleCI](https://circleci.com/gh/ucb-bar/project-template/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/project-template/tree/master) **This branch is under development** **It currently has many submodules** From e1292fdfa86f2164bd68327e1d0e80fd0e616988 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sun, 12 May 2019 13:11:06 -0700 Subject: [PATCH 073/120] revert to smaller boom config and support in ci --- .circleci/config.yml | 2 +- .circleci/do-rtl-build.sh | 18 ++++++++++++++++-- .../example/src/main/scala/Configs.scala | 8 ++++++++ 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 4a1d063b..c9d75d98 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -153,7 +153,7 @@ jobs: - run: name: Building the boomexample subproject using Verilator - command: .circleci/do-rtl-build.sh boomexample + command: .circleci/do-rtl-build.sh boomexample SmallDefaultBoomConfig no_output_timeout: 120m - save_cache: diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 02d02984..e7056e53 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -1,6 +1,8 @@ #!/bin/bash -# create the different verilator builds arg (subproject) +# create the different verilator builds +# 1st argument is the subproject +# 2nd argument is the config (can be unspecified) # turn echo on and error on earliest command set -ex @@ -12,6 +14,18 @@ cd $HOME/project # enter the verisim directory and build the specific config cd sims/verisim make clean -make SUB_PROJECT=$1 JAVA_ARGS="-Xmx2G -Xss8M" + +# run the particular build command +if [ $# -ne 0 ]; then + if [ $# -eq 1 ]; then + make SUB_PROJECT=$1 JAVA_ARGS="-Xmx2G -Xss8M" + elif [ $# -eq 2 ]; then + make SUB_PROJECT=$1 CONFIG=$2 JAVA_ARGS="-Xmx2G -Xss8M" + else + exit 1 # wrong amount of args + fi +else + exit 1 # need to provide at least the arg +fi rm -rf ../../project diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 4b6f1dcb..dc0a07ba 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -68,10 +68,18 @@ class BaseBoomConfig extends Config( new WithBootROM ++ new boom.system.BoomConfig) +class SmallBaseBoomConfig extends Config( + new WithBootROM ++ + new boom.system.SmallBoomConfig) + class DefaultBoomConfig extends Config( new WithNormalBoomTop ++ new BaseBoomConfig) +class SmallDefaultBoomConfig extends Config( + new WithNormalBoomTop ++ + new SmallBaseBoomConfig) + class HwachaBoomConfig extends Config( new hwacha.DefaultHwachaConfig ++ new DefaultBoomConfig) From 2697cdc29b4c7fd16cd15282ab0d6fd47a5c6d22 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sun, 12 May 2019 14:09:12 -0700 Subject: [PATCH 074/120] add small config string to config.yml --- .circleci/config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index c9d75d98..b0e8cf8b 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -317,7 +317,7 @@ jobs: - run: name: Run boomexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig boom-run-benchmark-tests: docker: From 2d644f1352666ba4de2617ac246553c295c14bc0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 13 May 2019 09:50:55 -0700 Subject: [PATCH 075/120] make hwacha smaller --- .circleci/config.yml | 6 +++--- .circleci/do-rtl-build.sh | 7 ++++--- generators/example/src/main/scala/Configs.scala | 5 +++++ 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index b0e8cf8b..5eda3c15 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -153,7 +153,7 @@ jobs: - run: name: Building the boomexample subproject using Verilator - command: .circleci/do-rtl-build.sh boomexample SmallDefaultBoomConfig + command: .circleci/do-rtl-build.sh boomexample example SmallDefaultBoomConfig no_output_timeout: 120m - save_cache: @@ -255,7 +255,7 @@ jobs: - run: name: Building the hwacha subproject using Verilator - command: .circleci/do-rtl-build.sh hwacha + command: .circleci/do-rtl-build.sh hwacha example SmallHwachaConfig no_output_timeout: 120m - save_cache: @@ -401,7 +401,7 @@ jobs: - run: name: Run hwacha benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha CONFIG_PACKAGE=example CONFIG=SmallHwachaConfig # Order and dependencies of jobs to run workflows: diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index e7056e53..eabce7c1 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -2,7 +2,8 @@ # create the different verilator builds # 1st argument is the subproject -# 2nd argument is the config (can be unspecified) +# 2nd argument is the config package (can be unspecified) +# 3nd argument is the config (can be unspecified) # turn echo on and error on earliest command set -ex @@ -19,8 +20,8 @@ make clean if [ $# -ne 0 ]; then if [ $# -eq 1 ]; then make SUB_PROJECT=$1 JAVA_ARGS="-Xmx2G -Xss8M" - elif [ $# -eq 2 ]; then - make SUB_PROJECT=$1 CONFIG=$2 JAVA_ARGS="-Xmx2G -Xss8M" + elif [ $# -eq 3 ]; then + make SUB_PROJECT=$1 CONFIG_PACKAGE=$2 CONFIG=$3 JAVA_ARGS="-Xmx2G -Xss8M" else exit 1 # wrong amount of args fi diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index dc0a07ba..90b6cf89 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -21,6 +21,11 @@ class HwachaConfig extends Config( new hwacha.DefaultHwachaConfig ++ new DefaultRocketConfig) +class SmallHwachaConfig extends Config( + new hwacha.WithNBanks(1) ++ + new hwacha.DefaultHwachaConfig ++ + new DefaultConfig) + class RoccRocketConfig extends Config( new WithRoccExample ++ new DefaultRocketConfig) From 12265912311b6f0e645fb9edd7cbbfe1ffd115a3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 13 May 2019 10:27:36 -0700 Subject: [PATCH 076/120] use example config for hwacha (otherwise use other hwacha params) --- .circleci/config.yml | 12 ++++++------ .circleci/do-rtl-build.sh | 16 ++-------------- generators/example/src/main/scala/Configs.scala | 6 +++--- 3 files changed, 11 insertions(+), 23 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 5eda3c15..61b62e17 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -119,7 +119,7 @@ jobs: - run: name: Building the example subproject using Verilator - command: .circleci/do-rtl-build.sh example + command: .circleci/do-rtl-build.sh SUB_PROJECT=example no_output_timeout: 120m - save_cache: @@ -153,7 +153,7 @@ jobs: - run: name: Building the boomexample subproject using Verilator - command: .circleci/do-rtl-build.sh boomexample example SmallDefaultBoomConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig no_output_timeout: 120m - save_cache: @@ -187,7 +187,7 @@ jobs: - run: name: Building the boom subproject using Verilator - command: .circleci/do-rtl-build.sh boom + command: .circleci/do-rtl-build.sh SUB_PROJECT=boom no_output_timeout: 120m - save_cache: @@ -221,7 +221,7 @@ jobs: - run: name: Building the rocketchip subproject using Verilator - command: .circleci/do-rtl-build.sh rocketchip + command: .circleci/do-rtl-build.sh SUB_PROJECT=rocketchip no_output_timeout: 120m - save_cache: @@ -255,7 +255,7 @@ jobs: - run: name: Building the hwacha subproject using Verilator - command: .circleci/do-rtl-build.sh hwacha example SmallHwachaConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallHwachaConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem no_output_timeout: 120m - save_cache: @@ -401,7 +401,7 @@ jobs: - run: name: Run hwacha benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha CONFIG_PACKAGE=example CONFIG=SmallHwachaConfig + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallHwachaConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem # Order and dependencies of jobs to run workflows: diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index eabce7c1..51ad760b 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -1,9 +1,7 @@ #!/bin/bash # create the different verilator builds -# 1st argument is the subproject -# 2nd argument is the config package (can be unspecified) -# 3nd argument is the config (can be unspecified) +# argument is the make command string # turn echo on and error on earliest command set -ex @@ -17,16 +15,6 @@ cd sims/verisim make clean # run the particular build command -if [ $# -ne 0 ]; then - if [ $# -eq 1 ]; then - make SUB_PROJECT=$1 JAVA_ARGS="-Xmx2G -Xss8M" - elif [ $# -eq 3 ]; then - make SUB_PROJECT=$1 CONFIG_PACKAGE=$2 CONFIG=$3 JAVA_ARGS="-Xmx2G -Xss8M" - else - exit 1 # wrong amount of args - fi -else - exit 1 # need to provide at least the arg -fi +make JAVA_ARGS="-Xmx2G -Xss8M" $@ rm -rf ../../project diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 90b6cf89..aa9e6e3f 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -2,7 +2,7 @@ package example import chisel3._ import freechips.rocketchip.config.{Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks} import testchipip._ // -------------- @@ -22,9 +22,9 @@ class HwachaConfig extends Config( new DefaultRocketConfig) class SmallHwachaConfig extends Config( - new hwacha.WithNBanks(1) ++ + new WithNBanks(1) ++ new hwacha.DefaultHwachaConfig ++ - new DefaultConfig) + new freechips.rocketchip.system.DefaultConfig) class RoccRocketConfig extends Config( new WithRoccExample ++ From a377c520a6c453ea8ce10ba1dbcbf8732ff24891 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 13 May 2019 13:34:29 -0700 Subject: [PATCH 077/120] smaller rocket For hwacha ci --- .circleci/config.yml | 4 +- .../example/src/main/scala/ConfigMixins.scala | 37 ++++++++++++++++++- .../example/src/main/scala/Configs.scala | 5 ++- 3 files changed, 40 insertions(+), 6 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 61b62e17..b6273995 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -255,7 +255,7 @@ jobs: - run: name: Building the hwacha subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallHwachaConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem + command: .circleci/do-rtl-build.sh SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallRocketForHwachaCIConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem no_output_timeout: 120m - save_cache: @@ -401,7 +401,7 @@ jobs: - run: name: Run hwacha benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallHwachaConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallRocketForHwachaCIConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem # Order and dependencies of jobs to run workflows: diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index e9b113b1..0b168868 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -2,10 +2,11 @@ package example import chisel3._ import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, CacheBlockBytes, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.XLen +import freechips.rocketchip.tile.{XLen, RocketTileParams} +import freechips.rocketchip.rocket.{RocketCoreParams, DCacheParams, ICacheParams, MulDivParams} import testchipip._ import sifive.blocks.devices.gpio._ @@ -168,3 +169,35 @@ class WithGPIOBoomTop extends Config((site, here, up) => { top } }) + +// ------------- +// Mixins for CI +// ------------- + +/** + * Class to specify a smaller Rocket core for Hwacha CI + */ +class WithNHwachaSmallCores(n: Int) extends Config((site, here, up) => { + case RocketTilesKey => { + val small = RocketTileParams( + core = RocketCoreParams(mulDiv = Some(MulDivParams( + mulUnroll = 8, + mulEarlyOut = true, + divEarlyOut = true))), + btb = None, + dcache = Some(DCacheParams( + rowBits = site(SystemBusKey).beatBits, + nSets = 32, + nWays = 1, + nTLBEntries = 4, + nMSHRs = 0, + blockBytes = site(CacheBlockBytes))), + icache = Some(ICacheParams( + rowBits = site(SystemBusKey).beatBits, + nSets = 32, + nWays = 1, + nTLBEntries = 4, + blockBytes = site(CacheBlockBytes)))) + List.tabulate(n)(i => small.copy(hartId = i)) + } +}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index aa9e6e3f..544ac27f 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -21,10 +21,11 @@ class HwachaConfig extends Config( new hwacha.DefaultHwachaConfig ++ new DefaultRocketConfig) -class SmallHwachaConfig extends Config( +class SmallRocketForHwachaCIConfig extends Config( new WithNBanks(1) ++ + new WithNHwachaSmallCores(1) ++ new hwacha.DefaultHwachaConfig ++ - new freechips.rocketchip.system.DefaultConfig) + new DefaultRocketConfig) class RoccRocketConfig extends Config( new WithRoccExample ++ From 7ba56b58d35ec4802bf7cfa7b2293b214c475c52 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 13 May 2019 14:15:05 -0700 Subject: [PATCH 078/120] for now just support verilog build of hwacha (no tests run on it) --- .circleci/config.yml | 64 +++++++++---------- .../example/src/main/scala/ConfigMixins.scala | 37 +---------- .../example/src/main/scala/Configs.scala | 6 -- 3 files changed, 34 insertions(+), 73 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index b6273995..dfc39518 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -255,7 +255,7 @@ jobs: - run: name: Building the hwacha subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallRocketForHwachaCIConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem + command: .circleci/do-rtl-build.sh SUB_PROJECT=hwacha verilog no_output_timeout: 120m - save_cache: @@ -375,33 +375,33 @@ jobs: name: Run rocketchip benchmark tests command: make run-bmark-tests -C sims/verisim SUB_PROJECT=rocketchip - hwacha-run-benchmark-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.5 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb - - steps: - # Checkout the code - - checkout - - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - - restore_cache: - keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - - restore_cache: - keys: - - hwacha-{{ .Branch }}-{{ .Revision }} - - - run: - name: Run hwacha benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallRocketForHwachaCIConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem +# hwacha-run-benchmark-tests: +# docker: +# - image: riscvboom/riscvboom-images:0.0.5 +# environment: +# JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit +# TERM: dumb +# +# steps: +# # Checkout the code +# - checkout +# +# - run: +# name: Create hash of toolchains +# command: | +# .circleci/create-hash.sh +# +# - restore_cache: +# keys: +# - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} +# +# - restore_cache: +# keys: +# - hwacha-{{ .Branch }}-{{ .Revision }} +# +# - run: +# name: Run hwacha benchmark tests +# command: make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha # Order and dependencies of jobs to run workflows: @@ -465,7 +465,7 @@ workflows: - install-riscv-toolchain - prepare-rocketchip - - hwacha-run-benchmark-tests: - requires: - - install-riscv-toolchain - - prepare-hwacha +# - hwacha-run-benchmark-tests: +# requires: +# - install-riscv-toolchain +# - prepare-hwacha diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 0b168868..5551a66d 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -2,11 +2,10 @@ package example import chisel3._ import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, CacheBlockBytes, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.{XLen, RocketTileParams} -import freechips.rocketchip.rocket.{RocketCoreParams, DCacheParams, ICacheParams, MulDivParams} +import freechips.rocketchip.tile.{XLen} import testchipip._ import sifive.blocks.devices.gpio._ @@ -169,35 +168,3 @@ class WithGPIOBoomTop extends Config((site, here, up) => { top } }) - -// ------------- -// Mixins for CI -// ------------- - -/** - * Class to specify a smaller Rocket core for Hwacha CI - */ -class WithNHwachaSmallCores(n: Int) extends Config((site, here, up) => { - case RocketTilesKey => { - val small = RocketTileParams( - core = RocketCoreParams(mulDiv = Some(MulDivParams( - mulUnroll = 8, - mulEarlyOut = true, - divEarlyOut = true))), - btb = None, - dcache = Some(DCacheParams( - rowBits = site(SystemBusKey).beatBits, - nSets = 32, - nWays = 1, - nTLBEntries = 4, - nMSHRs = 0, - blockBytes = site(CacheBlockBytes))), - icache = Some(ICacheParams( - rowBits = site(SystemBusKey).beatBits, - nSets = 32, - nWays = 1, - nTLBEntries = 4, - blockBytes = site(CacheBlockBytes)))) - List.tabulate(n)(i => small.copy(hartId = i)) - } -}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 544ac27f..68ca289c 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -21,12 +21,6 @@ class HwachaConfig extends Config( new hwacha.DefaultHwachaConfig ++ new DefaultRocketConfig) -class SmallRocketForHwachaCIConfig extends Config( - new WithNBanks(1) ++ - new WithNHwachaSmallCores(1) ++ - new hwacha.DefaultHwachaConfig ++ - new DefaultRocketConfig) - class RoccRocketConfig extends Config( new WithRoccExample ++ new DefaultRocketConfig) From 59acd688e62970d5130a7cd4b2ebbd6d28888feb Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 13 May 2019 14:16:11 -0700 Subject: [PATCH 079/120] clearer job naming for verilog only hwacha --- .circleci/config.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index dfc39518..7b1ed7a9 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -229,7 +229,7 @@ jobs: paths: - "/home/riscvuser/project" - prepare-hwacha: + prepare-hwacha-verilog-only: docker: - image: riscvboom/riscvboom-images:0.0.5 environment: @@ -437,7 +437,7 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-hwacha: + - prepare-hwacha-verilog-only: requires: - install-riscv-toolchain - install-verilator From deccae4959350fbb820c30032b358ac95f306dc6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 13 May 2019 17:17:32 -0700 Subject: [PATCH 080/120] hwacha depends on esp-tools | support java args --- .circleci/config.yml | 6 ++++-- variables.mk | 7 ++++++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 7b1ed7a9..1e5146bb 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -439,7 +439,8 @@ workflows: - prepare-hwacha-verilog-only: requires: - - install-riscv-toolchain + - install-riscv-toolchain # TODO: Remove when esp-tools is used + - install-esp-toolchain - install-verilator # Run the respective tests @@ -467,5 +468,6 @@ workflows: # - hwacha-run-benchmark-tests: # requires: -# - install-riscv-toolchain +# - install-riscv-toolchain # TODO: Remove when esp-tools is used +# - install-esp-toolchain # - prepare-hwacha diff --git a/variables.mk b/variables.mk index 15839578..94709245 100644 --- a/variables.mk +++ b/variables.mk @@ -122,13 +122,18 @@ sim_dotf ?= $(build_dir)/sim_files.f sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f +######################################################################################### +# java arguments used in sbt +######################################################################################### +JAVA_ARGS ?= -Xmx8G -Xss8M -XX:MaxPermSize=256M + ######################################################################################### # default sbt launch command ######################################################################################### SCALA_VERSION=2.12.4 SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) -SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION) +SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION) ######################################################################################### # output directory for tests From 9f4fdccf5de854eb34196595c244c6ca08e4f14a Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 14 May 2019 22:13:50 -0700 Subject: [PATCH 081/120] readthedocs config --- .readthedocs.yml | 7 +++++++ requirements.txt | 4 ++++ 2 files changed, 11 insertions(+) create mode 100644 .readthedocs.yml create mode 100644 requirements.txt diff --git a/.readthedocs.yml b/.readthedocs.yml new file mode 100644 index 00000000..233816b6 --- /dev/null +++ b/.readthedocs.yml @@ -0,0 +1,7 @@ +version: 2 +formats: all +sphinx: + configuration: docs/conf.py +python: + install: + - requirements: requirements/local-docs-build.txt diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 00000000..2abac52d --- /dev/null +++ b/requirements.txt @@ -0,0 +1,4 @@ +Sphinx==1.7.4 +Pygments==2.2.0 +sphinx-autobuild +sphinx_rtd_theme==0.2.5b1 From 04c5fcf35055d7b84db8a9622fc3667eb6d167d8 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 14 May 2019 22:16:29 -0700 Subject: [PATCH 082/120] readthedocs fix --- .readthedocs.yml | 2 +- requirements.txt => docs/requirements.txt | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename requirements.txt => docs/requirements.txt (100%) diff --git a/.readthedocs.yml b/.readthedocs.yml index 233816b6..43e2d306 100644 --- a/.readthedocs.yml +++ b/.readthedocs.yml @@ -4,4 +4,4 @@ sphinx: configuration: docs/conf.py python: install: - - requirements: requirements/local-docs-build.txt + - requirements: docs/requirements.txt diff --git a/requirements.txt b/docs/requirements.txt similarity index 100% rename from requirements.txt rename to docs/requirements.txt From 2ca18a44084d12a661f75c8740cee5f6d2286020 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 14 May 2019 22:44:54 -0700 Subject: [PATCH 083/120] docs --- docs/ReBAR-Basics/index.rst | 19 +++++++++++++++++++ docs/index.rst | 28 +++++++++++----------------- 2 files changed, 30 insertions(+), 17 deletions(-) create mode 100644 docs/ReBAR-Basics/index.rst diff --git a/docs/ReBAR-Basics/index.rst b/docs/ReBAR-Basics/index.rst new file mode 100644 index 00000000..af625cca --- /dev/null +++ b/docs/ReBAR-Basics/index.rst @@ -0,0 +1,19 @@ +.. _ReBAR Basics: + +ReBAR Basics +================================ + +These guides will walk you through the basics of the ReBAR framework: + +- First, we will go over the different configurations avaliable. + +- Then, we will walk through adding a custom accelerator. + +Hit next to get started! + +.. toctree:: + :maxdepth: 2 + :caption: ReBAR Basics: + + rebar-generator-mixins + Adding-An-Accelerator-Tutorial diff --git a/docs/index.rst b/docs/index.rst index 4afa90d9..74d754d6 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -8,10 +8,10 @@ Welcome to ReBAR's documentation! ReBAR is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. New to ReBAR? Jump to the :ref:`rebar-basics` page for more info. -.. toctree:: - :maxdepth: 3 - :caption: Getting Started: - :numbered: + +The documentation outline should look like this + + Getting Started: ReBAR-Basics Initial-Setup/index @@ -20,18 +20,14 @@ ReBAR is a a framework for designing and evaluating full-system hardware using a Running-Simulations-Tutorial/index Building-Chips-Tutorial/index -.. toctree:: - :maxdepth: 3 - :caption: Generators: + Generators: Generators/Rocketchip/index Generators/BOOM/index Generators/Hwacha/index -.. toctree:: - :maxdepth: 3 - :caption: Simulation: + Simulation: Simulation/Open-Source-Simulators/index Simulation/Commercial-Simulators/index @@ -39,19 +35,17 @@ ReBAR is a a framework for designing and evaluating full-system hardware using a -.. toctree:: - :maxdepth: 3 - :caption: Production: + Production: Production/VLSI-Physical-Design/index - + Software/Toolchains/index .. toctree:: :maxdepth: 3 - :caption: Software: - - Software/Toolchains/index + :caption: Getting Started: + :numbered: + ReBAR-Basics/index Indices and tables From 86e2e5c458962ace637855bcbd34aa3a42663314 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 14 May 2019 22:53:04 -0700 Subject: [PATCH 084/120] docs theme --- docs/conf.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index 6864fc63..64757ea1 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -88,13 +88,17 @@ todo_include_todos = True # The theme to use for HTML and HTML Help pages. See the documentation for # a list of builtin themes. # -html_theme = 'alabaster' +html_theme = 'sphinx_rtd_theme' # Theme options are theme-specific and customize the look and feel of a theme # further. For a list of options available for each theme, see the # documentation. # -# html_theme_options = {} +html_theme_options = { + 'collapse_navigation': False, +# 'display_version': True, +# 'navigation_depth': 4, +} # Add any paths that contain custom static files (such as style sheets) here, # relative to this directory. They are copied after the builtin static files, From f5c191871d7430617abcfcaabe290da95010efe4 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 16 May 2019 00:26:32 -0700 Subject: [PATCH 085/120] more docs --- .../Adding-An-Accelerator-Tutorial.rst | 0 .../Configs-Parameters-Mixins.rst | 79 ++++++++++++++ docs/Getting-Started/ReBAR-Basics.rst | 86 +++++++++++++++ docs/Getting-Started/Running-A-Simulation.rst | 100 ++++++++++++++++++ .../index.rst | 7 +- .../rebar-generator-mixins.rst | 0 docs/index.rst | 2 +- 7 files changed, 271 insertions(+), 3 deletions(-) rename docs/{ReBAR-Basics => Getting-Started}/Adding-An-Accelerator-Tutorial.rst (100%) create mode 100644 docs/Getting-Started/Configs-Parameters-Mixins.rst create mode 100644 docs/Getting-Started/ReBAR-Basics.rst create mode 100644 docs/Getting-Started/Running-A-Simulation.rst rename docs/{ReBAR-Basics => Getting-Started}/index.rst (78%) rename docs/{ReBAR-Basics => Getting-Started}/rebar-generator-mixins.rst (100%) diff --git a/docs/ReBAR-Basics/Adding-An-Accelerator-Tutorial.rst b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst similarity index 100% rename from docs/ReBAR-Basics/Adding-An-Accelerator-Tutorial.rst rename to docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst diff --git a/docs/Getting-Started/Configs-Parameters-Mixins.rst b/docs/Getting-Started/Configs-Parameters-Mixins.rst new file mode 100644 index 00000000..8333816f --- /dev/null +++ b/docs/Getting-Started/Configs-Parameters-Mixins.rst @@ -0,0 +1,79 @@ +Configs, Parameters, Mix-ins, and Everything In Between +======================================================== + +A significant portion of generators in the ReBAR framework use the Rocket chip parameter system. +This parameter system enables for the flexible configuration of the SoC without invasive RTL changes. +In order to use the parameter system correctly, we will use several terms and conventions: + +**Parameter** + +TODO: Need to explain up, site, field, and other stuff from Henry's thesis. + +It is important to note that a significant challenge with the Rocket parameter system is being able to identify the correct parameter to use, and the impact that parameter has on the overall system. We are still investigating methods to facilitate parameter exploration and discovery. + + +**Config** +A *Config* is a collection of multiple parameters being set to specific values. +Configs are additive, and can override each other. +A Config can be composed of other configs. +The naming convetion for an additive config is `With`, while the naming convention for a non-additive config will be ``. +Configs can take arguments which will in-turn set parameters in the specific configs. + +Example config: + +.. + class WithMyAcceleratorParams extends Config((site, here, up) => { + case MyAcceleratorKey => + MyAcceleratorConfig( + Rows = 2, + rowBits = 64, + Columns = 16, + hartId = 1, + some_length = 256, + ) + }) + +Example config which uses a higher level config: + +.. + class WithMyMoreComplexAcceleratorConfig extends Config((site, here, up) => { + case MyAcceleratorKey => + MyAcceleratorConfig( + Rows = 2, + rowBits = site(SystemBusKey).beatBits, + hartId = up(RocketTilesKey, site).length, + ) + }) + +Example of additive configs: + +.. + class SomeAdditiveConfig extends Config( + new WithMyMoreComplexAcceleratorConfig ++ + new WithMyAcceleratorParams ++ + new DefaultExampleConfig + ) + + +**Cake Pattern** +The cake pattern is a scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes refered to as dependancy injection). It is used in the Rocket chip SoC library and ReBAR framework in merging multiple system components and IO interfaces into a large system component. + +Example of using the cake pattern to merge multiple system components into a single top-level design, extending a basic Rocket SoC: + +.. + class MySoC(implicit p: Parameters) extends RocketSubsystem + with CanHaveMisalignedMasterAXI4MemPort + with HasPeripheryBootROM + with HasNoDebug + with HasPeripherySerial + with HasPeripheryUART + with HasPeripheryIceNIC + { + //Additional top-level specific instantiations or wiring + } + + +**Mix-in** +A mix-in is a scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. +The naming convetion for an additive mix-in is `Has`. + diff --git a/docs/Getting-Started/ReBAR-Basics.rst b/docs/Getting-Started/ReBAR-Basics.rst new file mode 100644 index 00000000..eb54033e --- /dev/null +++ b/docs/Getting-Started/ReBAR-Basics.rst @@ -0,0 +1,86 @@ + + +ReBAR Basics +=============================== + + +Generators +------------------------------------------- +Generators are parametrized programs written as RTL code, designed to generate verilog code based on configuration specifications. +Generators can be used to generate Systems-on-Chip (SoCs) using a collection of system components organized in unique generator projects. +The ReBAR Framework currently consists of the following generators: + +Processor Cores +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +**Rocket** + An in-order RISC-V core. + +**BOOM (Berkeley Out-of-Order Machine)** + An out-of-order RISC-V core. + +Data-Parallel Accelerators +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +**Hwacha** + A decoupled vector architecture co-processor. Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model. + Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface + + +System Components: +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +**icenet** + A Network Interface Controller (NIC) designed to achieve up to 200 Gbps. + +**sifive-blocks** + System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket chip generator. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices. + +**AWL (Analog Widget Library)** + Digital components required for integration with high speed serial links. + +**testchipip** + A collection of utilites used for testing chips and interfacing them with larger test environments. + + +Fixed Function Accelerators: +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +TBD + + + +Tools +------------------------------------------- +**Chisel** + A hardware description library embedded in Scala. Chisel is used to write RTL generators using meta-programming, by emdedding hardware generation primitives in the Scala programming language. The Chisel compilter elaborate the generator into a FIRRTL output. + +**FIRRTL** + An intermediate representation library for RTL description of digital designs. FIRRTL is used as a formalized digital circuit representation between Chisel and Verilog. FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation. + +**BARSTOOLS** + A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL. + + +Toolchains +------------------------------------------- +**riscv-tools** + A collection of software toolchains used to develope and execute software on the RISC-V ISA. The include compiler and assembler toolchains, functional ISA simulator (spike), the Berkeley Boot Loader (BBL) and proxy kernel. The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.). Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the ReBAR framework. + + +**esp-tools** + A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension. This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.) + + +Sims +------------------------------------------- +**verisim (Verilator wrapper)** + Verilator is an open source Verilog simulator. The verisim directory provides wrappers which construct verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). + +**vsim (VCS wrapper)** + VCS is a proprietary Verilog simulator. Assuming the user has valid VCS licenses and installations, the vsim directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). + +**FireSim** + FireSim is an open-source FPGA-accelerated simulation platform, using Amazon Web Services (AWS) EC2 F1 instances on the public cloud. FireSim automatically transforms and instruments open-hardware designs into fast (10s-100s MHz), deterministic, FPGA-based simulators that enable productive pre-silicon verification and performance validation. To model I/O, FireSim includes synthesizeable and timing-accurate models for standard interfaces like DRAM, Ethernet, UART, and others. The use of the elastic public clound enable FireSim to scale simulations up to thousands of nodes. In order to use FireSim, the repository must be cloned and executed on AWS instances. + + +VLSI +------------------------------------------- +**HAMMER** + HAMMER is a VLSI flow designed to provide a layer of abstraction between general physical design concepts to vendor-specific EDA tool commands. The HAMMER flow provide automated scripts which generate relevant tool commands based on a higher level description of physical desing contraints. The HAMMER flow also allows for re-use of process technology knowledge by enabling the construction of process-technology-specific plug-ins, which describe particular contraints relating to that process technology (obsolete standard cells, metal layer routing contraints, etc.). The HAMMER flow requires access to proprietry EDA tools and process technology libraries. diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst new file mode 100644 index 00000000..3be148fa --- /dev/null +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -0,0 +1,100 @@ +Running A Simulation +======================================================== + +ReBAR provides support and intergration for multiple simulation flows, for various user levels and requirments. +In the majority of cases during a digital design development process, simple software RTL. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. + + +Software RTL Simulation +------------------------ +The ReBAR framework provides wrappers for two common software RTL simulators: the open-source Verilator simulator. and the proprietry VCS simulator.The following instructions assume at least one of these simulators is installed. + +Verilator +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Verilator is an open-source RTL simulator. We run Verilator simulations from within the `sims/verisim` directory. +In order to construct the simulator with our custom design, we run the following command within the `sims/verisim` directory: + +.. + make TOP= CONFIG= SBT_PROJECT= MODEL= + +Where `` is the class name of the top level design, ` CONFIG= SBT_PROJECT= MODEL= + +or + +.. + make run-asm-tests SUB_PROJECT=example + + + +VCS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +VCS is a proprietry RTL simulator. This guide assumes that the VCS installation is found on our PATH. We run VCS simulations from within the `sims/vsim` directory. +In order to construct the simulator with our custom design, we run the following command within the `sims/vsim` directory: + +.. + make TOP= CONFIG= SBT_PROJECT= MODEL= + +Where `` is the class name of the top level design, ` CONFIG= SBT_PROJECT= MODEL= + +or + +.. + make run-asm-tests SUB_PROJECT=example + + + +FPGA Accelerated Simulation +--------------------------- +FireSim enables simulations at 1000x-100000x the speed of standard software simulation. This is enabled using FPGA-acceleration on F1 instances of the AWS (Amazon Web Services) public cloud. There FireSim simulation require to be set-up on the AWS public cloud rather than on our local development machine. + +To run an FPGA-accelerated simulation using FireSim, a we need to clone the ReBAR repository (or our fork of the ReBAR repository) to an AWS EC2, and follow the setup instructions specificied in the FireSim Initial Setup documentation page. + +After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design. We will work from within the `sims/firesim` directory. + +TODO: Continue from here + diff --git a/docs/ReBAR-Basics/index.rst b/docs/Getting-Started/index.rst similarity index 78% rename from docs/ReBAR-Basics/index.rst rename to docs/Getting-Started/index.rst index af625cca..50a753cc 100644 --- a/docs/ReBAR-Basics/index.rst +++ b/docs/Getting-Started/index.rst @@ -13,7 +13,10 @@ Hit next to get started! .. toctree:: :maxdepth: 2 - :caption: ReBAR Basics: + :caption: Getting Started: - rebar-generator-mixins + ReBAR-Basics + Configs-Parameters-Mixins Adding-An-Accelerator-Tutorial + Running-A-Simulation + rebar-generator-mixins diff --git a/docs/ReBAR-Basics/rebar-generator-mixins.rst b/docs/Getting-Started/rebar-generator-mixins.rst similarity index 100% rename from docs/ReBAR-Basics/rebar-generator-mixins.rst rename to docs/Getting-Started/rebar-generator-mixins.rst diff --git a/docs/index.rst b/docs/index.rst index 74d754d6..4123f632 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -45,7 +45,7 @@ The documentation outline should look like this :caption: Getting Started: :numbered: - ReBAR-Basics/index + Getting-Started/index Indices and tables From d091fe8b229e8d077abf550a177d2f3daefc3a8f Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 16 May 2019 00:41:33 -0700 Subject: [PATCH 086/120] fix docs --- .../Configs-Parameters-Mixins.rst | 20 +++--- docs/Getting-Started/Running-A-Simulation.rst | 71 ++++++++++++------- docs/Getting-Started/index.rst | 4 +- 3 files changed, 61 insertions(+), 34 deletions(-) diff --git a/docs/Getting-Started/Configs-Parameters-Mixins.rst b/docs/Getting-Started/Configs-Parameters-Mixins.rst index 8333816f..f186e01d 100644 --- a/docs/Getting-Started/Configs-Parameters-Mixins.rst +++ b/docs/Getting-Started/Configs-Parameters-Mixins.rst @@ -1,7 +1,7 @@ Configs, Parameters, Mix-ins, and Everything In Between ======================================================== -A significant portion of generators in the ReBAR framework use the Rocket chip parameter system. +A significant portion of generators in the ReBAR framework use the Rocket chip parameter system. This parameter system enables for the flexible configuration of the SoC without invasive RTL changes. In order to use the parameter system correctly, we will use several terms and conventions: @@ -13,15 +13,16 @@ It is important to note that a significant challenge with the Rocket parameter s **Config** -A *Config* is a collection of multiple parameters being set to specific values. +A `Config` is a collection of multiple parameters being set to specific values. Configs are additive, and can override each other. A Config can be composed of other configs. -The naming convetion for an additive config is `With`, while the naming convention for a non-additive config will be ``. +The naming convetion for an additive config is ``With``, while the naming convention for a non-additive config will be ````. Configs can take arguments which will in-turn set parameters in the specific configs. Example config: -.. +.. code-block:: scala + class WithMyAcceleratorParams extends Config((site, here, up) => { case MyAcceleratorKey => MyAcceleratorConfig( @@ -35,7 +36,8 @@ Example config: Example config which uses a higher level config: -.. +.. code-block:: scala + class WithMyMoreComplexAcceleratorConfig extends Config((site, here, up) => { case MyAcceleratorKey => MyAcceleratorConfig( @@ -47,7 +49,8 @@ Example config which uses a higher level config: Example of additive configs: -.. +.. code-block:: scala + class SomeAdditiveConfig extends Config( new WithMyMoreComplexAcceleratorConfig ++ new WithMyAcceleratorParams ++ @@ -60,7 +63,8 @@ The cake pattern is a scala programming pattern, which enable "mixing" of multip Example of using the cake pattern to merge multiple system components into a single top-level design, extending a basic Rocket SoC: -.. +.. code-block:: scala + class MySoC(implicit p: Parameters) extends RocketSubsystem with CanHaveMisalignedMasterAXI4MemPort with HasPeripheryBootROM @@ -75,5 +79,5 @@ Example of using the cake pattern to merge multiple system components into a sin **Mix-in** A mix-in is a scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. -The naming convetion for an additive mix-in is `Has`. +The naming convetion for an additive mix-in is ``Has``. diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index 3be148fa..c9f48689 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -11,39 +11,50 @@ The ReBAR framework provides wrappers for two common software RTL simulators: th Verilator ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Verilator is an open-source RTL simulator. We run Verilator simulations from within the `sims/verisim` directory. -In order to construct the simulator with our custom design, we run the following command within the `sims/verisim` directory: +Verilator is an open-source RTL simulator. We run Verilator simulations from within the ``sims/verisim`` directory. Therefore, we will start by entering that directory: + +.. code-block:: shell + + cd sims/verisim + +In order to construct the simulator with our custom design, we run the following command within the ``sims/verisim`` directory: + +.. code-block:: shell -.. make TOP= CONFIG= SBT_PROJECT= MODEL= -Where `` is the class name of the top level design, ``` is the class name of the top level design, ```` is the name of the class we create for our parameters configuration, ```` is the name of the sbt package the include both our top-level class and our config class, and ```` is the name of the class which defines the test harness for our system. +The ``make`` command may have additional parameters (such as ``CONFIG_PACKAGE`` or ``MODEL_PACKAGE``) depending on the complexity of the design and integration with multiple sub-project repositories in the sbt-based build system. -Common configurations are package using a `SUB_PROJECT` make variable. There, in order to simulate a simple Rocket-based example system we can use: +Common configurations are package using a ``SUB_PROJECT`` make variable. There, in order to simulate a simple Rocket-based example system we can use: + +.. code-block:: shell -.. make SUB_PROJECT=example Alternatively, if we would like to simulate a simple BOOM-based example system we can use: -.. +.. code-block:: shell + make SUB_PROJECT=exampleboom Once the simulator has been constructed, we would like to run RISC-V programs on it. In the `sims/verisim` directory, we will find an executable file called `TODO`. We run this executable with out target RISC-V program as a command line argument. For example: -.. +.. code-block:: shell + TODO Alternatively, we can run a pre-packaged suite of RISC-V assembly tests, by adding the make target run-asm-tests. For example -.. +.. code-block:: shell + make run-asm-tests TOP= CONFIG= SBT_PROJECT= MODEL= or -.. +.. code-block:: shell + make run-asm-tests SUB_PROJECT=example @@ -51,39 +62,51 @@ or VCS ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -VCS is a proprietry RTL simulator. This guide assumes that the VCS installation is found on our PATH. We run VCS simulations from within the `sims/vsim` directory. -In order to construct the simulator with our custom design, we run the following command within the `sims/vsim` directory: +VCS is a proprietry RTL simulator. This guide assumes that the VCS installation is found on our PATH. We run VCS simulations from within the ``sims/vsim`` directory. Therefore, we will start by entering the directory: + +.. code-block:: shell + + cd sims/vsim + + +In order to construct the simulator with our custom design, we run the following command within the ``sims/vsim`` directory: + +.. code-block:: shell -.. make TOP= CONFIG= SBT_PROJECT= MODEL= -Where `` is the class name of the top level design, ``` is the class name of the top level design, ```` is the name of the class we create for our parameters configuration, ```` is the name of the sbt package the include both our top-level class and our config class, and ```` is the name of the class which defines the test harness for our system. +The ``make`` command my have additional parameters (such as ``CONFIG_PACKAGE`` or ``MODEL_PACKAGE``) depending on the complexity of the design and integration with multiple sub-project repositories in the sbt-based build system. -Common configurations are package using a `SUB_PROJECT` make variable. There, in order to simulate a simple Rocket-based example system we can use: +Common configurations are package using a ``SUB_PROJECT`` make variable. There, in order to simulate a simple Rocket-based example system we can use: + +.. code-block:: shell -.. make SUB_PROJECT=example Alternatively, if we would like to simulate a simple BOOM-based example system we can use: -.. +.. code-block:: shell + make SUB_PROJECT=exampleboom -Once the simulator has been constructed, we would like to run RISC-V programs on it. In the `sims/vsim` directory, we will find an executable file called `TODO`. We run this executable with out target RISC-V program as a command line argument. For example: +Once the simulator has been constructed, we would like to run RISC-V programs on it. In the ``sims/vsim`` directory, we will find an executable file called ``TODO``. We run this executable with out target RISC-V program as a command line argument. For example: + +.. code-block:: shell -.. TODO Alternatively, we can run a pre-packaged suite of RISC-V assembly tests, by adding the make target run-asm-tests. For example -.. +.. code-block:: shell + make run-asm-tests TOP= CONFIG= SBT_PROJECT= MODEL= or -.. +.. code-block:: shell + make run-asm-tests SUB_PROJECT=example @@ -94,7 +117,7 @@ FireSim enables simulations at 1000x-100000x the speed of standard software simu To run an FPGA-accelerated simulation using FireSim, a we need to clone the ReBAR repository (or our fork of the ReBAR repository) to an AWS EC2, and follow the setup instructions specificied in the FireSim Initial Setup documentation page. -After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design. We will work from within the `sims/firesim` directory. +After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design. We will work from within the ``sims/firesim`` directory. TODO: Continue from here diff --git a/docs/Getting-Started/index.rst b/docs/Getting-Started/index.rst index 50a753cc..5976cea6 100644 --- a/docs/Getting-Started/index.rst +++ b/docs/Getting-Started/index.rst @@ -1,6 +1,6 @@ -.. _ReBAR Basics: +.. _Getting Started: -ReBAR Basics +Getting Started ================================ These guides will walk you through the basics of the ReBAR framework: From e0aed90714199050cb91fc9968640bcf843b5939 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 16 May 2019 00:45:46 -0700 Subject: [PATCH 087/120] subtitles --- docs/Getting-Started/Configs-Parameters-Mixins.rst | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/docs/Getting-Started/Configs-Parameters-Mixins.rst b/docs/Getting-Started/Configs-Parameters-Mixins.rst index f186e01d..b87a47c1 100644 --- a/docs/Getting-Started/Configs-Parameters-Mixins.rst +++ b/docs/Getting-Started/Configs-Parameters-Mixins.rst @@ -5,14 +5,15 @@ A significant portion of generators in the ReBAR framework use the Rocket chip p This parameter system enables for the flexible configuration of the SoC without invasive RTL changes. In order to use the parameter system correctly, we will use several terms and conventions: -**Parameter** - +Parameter +-------------------- TODO: Need to explain up, site, field, and other stuff from Henry's thesis. It is important to note that a significant challenge with the Rocket parameter system is being able to identify the correct parameter to use, and the impact that parameter has on the overall system. We are still investigating methods to facilitate parameter exploration and discovery. -**Config** +Config +--------------------- A `Config` is a collection of multiple parameters being set to specific values. Configs are additive, and can override each other. A Config can be composed of other configs. @@ -58,7 +59,8 @@ Example of additive configs: ) -**Cake Pattern** +Cake Pattern +------------------------- The cake pattern is a scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes refered to as dependancy injection). It is used in the Rocket chip SoC library and ReBAR framework in merging multiple system components and IO interfaces into a large system component. Example of using the cake pattern to merge multiple system components into a single top-level design, extending a basic Rocket SoC: @@ -77,7 +79,8 @@ Example of using the cake pattern to merge multiple system components into a sin } -**Mix-in** +Mix-in +--------------------------- A mix-in is a scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. The naming convetion for an additive mix-in is ``Has``. From fa1c4ae221505b246bbf5829c372c1b775ee6fd2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 16 May 2019 22:57:18 -0700 Subject: [PATCH 088/120] reduce amount of sbt calls for sim --- common.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index c59d38b6..b1195ee5 100644 --- a/common.mk +++ b/common.mk @@ -8,7 +8,7 @@ SHELL=/bin/bash ######################################################################################### lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null) -PACKAGES=rocket-chip testchipip boom hwacha sifive-blocks utilities example +PACKAGES=rocket-chip testchipip boom hwacha sifive-blocks example SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) ######################################################################################### @@ -31,7 +31,7 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(REBAR_FIRRTL_DIR)/src/main/scala) ######################################################################################### # create simulation args file rule ######################################################################################### -$(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR) +$(sim_dotf): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" ######################################################################################### From 7e1365f142c3640ad9e5c2754971733bf0927f69 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 17 May 2019 14:33:58 -0700 Subject: [PATCH 089/120] more docs skeleton --- docs/Generators/BOOM.rst | 10 +++++++++ docs/Generators/Rocket.rst | 3 +++ docs/Generators/index.rst | 13 ++++++++++++ docs/Getting-Started/Running-A-Simulation.rst | 4 ++-- docs/Simulation/Commercial-Simulators.rst | 2 +- docs/Simulation/FPGA-Based-Simulators.rst | 6 +++--- docs/Simulation/Open-Source-Simulators.rst | 2 +- docs/Simulation/index.rst | 13 ++++++++++++ docs/Tools/Barstools.rst | 3 +++ docs/Tools/Chisel.rst | 3 +++ docs/Tools/FIRRTL.rst | 3 +++ docs/Tools/index.rst | 13 ++++++++++++ docs/VLSI/index.rst | 8 +++++++ docs/conf.py | 4 +++- docs/index.rst | 21 ++++++++++++++++++- 15 files changed, 99 insertions(+), 9 deletions(-) create mode 100644 docs/Generators/BOOM.rst create mode 100644 docs/Generators/Rocket.rst create mode 100644 docs/Generators/index.rst create mode 100644 docs/Simulation/index.rst create mode 100644 docs/Tools/Barstools.rst create mode 100644 docs/Tools/Chisel.rst create mode 100644 docs/Tools/FIRRTL.rst create mode 100644 docs/Tools/index.rst create mode 100644 docs/VLSI/index.rst diff --git a/docs/Generators/BOOM.rst b/docs/Generators/BOOM.rst new file mode 100644 index 00000000..f0cac535 --- /dev/null +++ b/docs/Generators/BOOM.rst @@ -0,0 +1,10 @@ +Berkeley Out-of-Order Machine (BOOM) +============================================== + +The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. + +BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 outoforder processors. Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”). + +Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). + +Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages __`. diff --git a/docs/Generators/Rocket.rst b/docs/Generators/Rocket.rst new file mode 100644 index 00000000..06bf26eb --- /dev/null +++ b/docs/Generators/Rocket.rst @@ -0,0 +1,3 @@ +Rocket +==================================== +TODO: Basic rocket introduction diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst new file mode 100644 index 00000000..7aa22141 --- /dev/null +++ b/docs/Generators/index.rst @@ -0,0 +1,13 @@ +Generators +============================ +Generator can be thought of as generalized RTL designs, written using a mix of meta-programming and standard RTL. +This type of meta-programming is enabled by the Chisel hardware description framework embedded in Scala. +A standard RTL design is esentially a degenerate form of a generator. However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. The following pages introduce the generators integrated with the ReBAR framework. + +.. toctree:: + :maxdepth: 2 + :caption: Generators: + + Rocket + BOOM + diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index c9f48689..a86eb7e8 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -43,7 +43,7 @@ Once the simulator has been constructed, we would like to run RISC-V programs on .. code-block:: shell - TODO + ./simulator-- my_program_binary Alternatively, we can run a pre-packaged suite of RISC-V assembly tests, by adding the make target run-asm-tests. For example @@ -95,7 +95,7 @@ Once the simulator has been constructed, we would like to run RISC-V programs on .. code-block:: shell - TODO + ./simulator-- my_program_binary Alternatively, we can run a pre-packaged suite of RISC-V assembly tests, by adding the make target run-asm-tests. For example diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Commercial-Simulators.rst index e107d703..27fa5271 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/Commercial-Simulators.rst @@ -1,4 +1,4 @@ -Commericial Simulators +Commericial Software RTL Simulators ============================== The ReBAR framework currently supports only the VCS commerical simulator diff --git a/docs/Simulation/FPGA-Based-Simulators.rst b/docs/Simulation/FPGA-Based-Simulators.rst index fbacafa4..37bc3b16 100644 --- a/docs/Simulation/FPGA-Based-Simulators.rst +++ b/docs/Simulation/FPGA-Based-Simulators.rst @@ -4,10 +4,10 @@ FPGA-Based Simulators FireSim ----------------------- FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). -FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. FireSim also provide additional device models to allow full-system simulation, including memory models and network models. +FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. FireSim also provides additional device models to allow full-system simulation, including memory models and network models. FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. In order to simulate your ReBAR design using FireSim, you should follow the following steps: -Follow the initial EC2 setup instructions as detailed in the FireSim documentatino . Then clone your full ReBAR repository onto your Amazon EC2 FireSim manager instance. +Follow the initial EC2 setup instructions as detailed in the `FireSim documentation `__ .. Then clone your full ReBAR repository onto your Amazon EC2 FireSim manager instance. -Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for running a simulation +Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for `running a simulation `__. diff --git a/docs/Simulation/Open-Source-Simulators.rst b/docs/Simulation/Open-Source-Simulators.rst index 2b8e1f4e..87edc5ef 100644 --- a/docs/Simulation/Open-Source-Simulators.rst +++ b/docs/Simulation/Open-Source-Simulators.rst @@ -1,4 +1,4 @@ -Open Source Simulators +Open Source Software RTL Simulators ============================== Verilator diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst new file mode 100644 index 00000000..c5ee90a5 --- /dev/null +++ b/docs/Simulation/index.rst @@ -0,0 +1,13 @@ +Simulators +======================= + +ReBAR provides support and intergration for multiple simulation flows, for various user levels and requirments. +In the majority of cases during a digital design development process, simple software RTL. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. The following pages provide detailed information about the simulation possibilities within the ReBAR framework. + +.. toctree:: + :maxdepth: 2 + :caption: Simulators: + + Open-Source-Simulators + Commercial-Simulators + FPGA-Based-Simulators diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst new file mode 100644 index 00000000..137d95a7 --- /dev/null +++ b/docs/Tools/Barstools.rst @@ -0,0 +1,3 @@ +Barstools +=============================== +Barstools is a collection of useful FIRRTL transformations diff --git a/docs/Tools/Chisel.rst b/docs/Tools/Chisel.rst new file mode 100644 index 00000000..1b0c37ce --- /dev/null +++ b/docs/Tools/Chisel.rst @@ -0,0 +1,3 @@ +Chisel +=========================== +TODO: Chisel intro and pointer to chisel bootcamp diff --git a/docs/Tools/FIRRTL.rst b/docs/Tools/FIRRTL.rst new file mode 100644 index 00000000..ab5df854 --- /dev/null +++ b/docs/Tools/FIRRTL.rst @@ -0,0 +1,3 @@ +FIRRTL +================================ + diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst new file mode 100644 index 00000000..6b3ad2da --- /dev/null +++ b/docs/Tools/index.rst @@ -0,0 +1,13 @@ +Tools +============================== +The ReBAR framework relays heavily on a set of scala-based tools. While the framework attempts to hide the complexities of these tools, the following pages will introduce them, and how we can use them in order to generate flexible designs + + +.. toctree:: + :maxdepth: 2 + :caption: Tools: + + Chisel + FIRRTL + Barstools + diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst new file mode 100644 index 00000000..5f680b4d --- /dev/null +++ b/docs/VLSI/index.rst @@ -0,0 +1,8 @@ +VLSI Production +================================ +The ReBAR framework aim to provide wrappers to a general VLSI flow. +In particular, we aim to support the HAMMER flow. + +.. toctree:: + :maxdepth: 2 + :caption: VLSI Production: diff --git a/docs/conf.py b/docs/conf.py index 64757ea1..bdddec6c 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -181,4 +181,6 @@ texinfo_documents = [ # Example configuration for intersphinx: refer to the Python standard library. -intersphinx_mapping = {'https://docs.python.org/': None} +intersphinx_mapping = {'python' : ('https://docs.python.org/', None), + 'boom' : ('https://docs.boom-core.org/en/latest/', None), + 'firesim' : ('http://docs.fires.im/en/latest/', None) } diff --git a/docs/index.rst b/docs/index.rst index 4123f632..a696f691 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -28,7 +28,6 @@ The documentation outline should look like this Simulation: - Simulation/Open-Source-Simulators/index Simulation/Commercial-Simulators/index Simulation/FPGA-Based-Simulation/index @@ -47,6 +46,26 @@ The documentation outline should look like this Getting-Started/index + :maxdepth: 3 + :caption: Simulation: + :numbered: + Simulation/index + + :maxdepth: 3 + :caption: Generators: + :numbered: + Generators/index + + :maxdepth: 3 + :caption: Tools: + :numbered: + Tools/index + + :maxdepth: 3 + :caption: VLSI Production: + :numbered: + VLSI/index + Indices and tables ================== From a7a4dd345b5f2af56d93bdde420b66040efd2d97 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 13 May 2019 13:25:58 -0700 Subject: [PATCH 090/120] Bump to May rocketchip | Support for BigInt mems --- common.mk | 7 ++++++- generators/rocket-chip | 2 +- toolchains/riscv-tools | 2 +- tools/barstools | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- variables.mk | 32 ++++++++++++++++++-------------- 7 files changed, 29 insertions(+), 20 deletions(-) diff --git a/common.mk b/common.mk index c59d38b6..cf79fb26 100644 --- a/common.mk +++ b/common.mk @@ -47,13 +47,14 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) # create verilog files rules and variables ######################################################################################### REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) +HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF) $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)" + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)" grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs @@ -61,6 +62,10 @@ MACROCOMPILER_MODE ?= --mode synflops $(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)" +HARNESS_MACROCOMPILER_MODE = --mode synflops +$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) + cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" + ######################################################################################### # helper rule to just make verilog files ######################################################################################### diff --git a/generators/rocket-chip b/generators/rocket-chip index a05728c4..b8baef6f 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit a05728c4fab84a13585e14ac684b47c875b17b57 +Subproject commit b8baef6f26fa36c9b4e0b2a5eec12cd76ae5daf8 diff --git a/toolchains/riscv-tools b/toolchains/riscv-tools index 962bc098..bce7b5e3 160000 --- a/toolchains/riscv-tools +++ b/toolchains/riscv-tools @@ -1 +1 @@ -Subproject commit 962bc09873071aa7816d5f805c6e5797a3b5bcf7 +Subproject commit bce7b5e363957c134f944769e677354467b7e4ed diff --git a/tools/barstools b/tools/barstools index e548210e..9193c67e 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit e548210ef42e634e75cf283292685728114694c6 +Subproject commit 9193c67ec916c76414a4e72a1ce84e9ffb8accec diff --git a/tools/chisel3 b/tools/chisel3 index 9a0ce227..e1aa5f3f 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit 9a0ce2272c9d5d0a8bdc90e84269749ce054664d +Subproject commit e1aa5f3f5c0cdeb204047c3ca50801d9f7ea25f1 diff --git a/tools/firrtl b/tools/firrtl index bf66997b..99ae1d66 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit bf66997b1a2438a322cd619ca2b6aeb0f0ac0ba0 +Subproject commit 99ae1d6649f1731c5dec2098b10733735232b72c diff --git a/variables.mk b/variables.mk index 94709245..611f1dd9 100644 --- a/variables.mk +++ b/variables.mk @@ -107,20 +107,23 @@ ifeq ($(GENERATOR_PACKAGE),hwacha) long_name=$(MODEL_PACKAGE).$(CONFIG) endif -FIRRTL_FILE ?= $(build_dir)/$(long_name).fir -ANNO_FILE ?= $(build_dir)/$(long_name).anno.json -VERILOG_FILE ?= $(build_dir)/$(long_name).top.v -TOP_FIR ?= $(build_dir)/$(long_name).top.fir -TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json -HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v -HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir -HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json -SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v -SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf -SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir -sim_dotf ?= $(build_dir)/sim_files.f +FIRRTL_FILE ?= $(build_dir)/$(long_name).fir +ANNO_FILE ?= $(build_dir)/$(long_name).anno.json +VERILOG_FILE ?= $(build_dir)/$(long_name).top.v +TOP_FIR ?= $(build_dir)/$(long_name).top.fir +TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json +HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v +HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir +HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json +HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v +HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf +HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir +SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v +SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf +SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir +sim_dotf ?= $(build_dir)/sim_files.f sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f -sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f +sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f ######################################################################################### # java arguments used in sbt @@ -157,7 +160,8 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc sim_vsrcs = \ $(VERILOG_FILE) \ $(HARNESS_FILE) \ - $(SMEMS_FILE) + $(SMEMS_FILE) \ + $(HARNESS_SMEMS_FILE) ######################################################################################### # assembly/benchmark variables From 408dbcafa27c6cc572dc630c7dda111a6abae8fa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 17 May 2019 18:26:00 -0700 Subject: [PATCH 091/120] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 9193c67e..82636b3f 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 9193c67ec916c76414a4e72a1ce84e9ffb8accec +Subproject commit 82636b3ff43ecf6a0f0a7d46ebc2456b31e9703f From 206221323c44b35d94a05ad9fb6cf505a905bba5 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 17 May 2019 18:36:59 -0700 Subject: [PATCH 092/120] Bump hwacha --- generators/hwacha | 2 +- toolchains/esp-tools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/hwacha b/generators/hwacha index bc89157b..ff4605f5 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit bc89157b28b22ba59af6ddad1130f61749d648c1 +Subproject commit ff4605f5d10d91b7ae8c4a006b965d4706009a06 diff --git a/toolchains/esp-tools b/toolchains/esp-tools index f2e562c0..aba7bd82 160000 --- a/toolchains/esp-tools +++ b/toolchains/esp-tools @@ -1 +1 @@ -Subproject commit f2e562c0f9089746c6beb15f04b00fbb48f2e9ae +Subproject commit aba7bd828d4fd1c5fc3ac227524ccfd350410ade From 65d6a900c373b33cac27a1cc64d8530d1ddc4fca Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 May 2019 16:15:08 -0700 Subject: [PATCH 093/120] rename output | helper rules to run binaries --- common.mk | 6 ++++++ sims/verisim/Makefile | 6 ++++++ sims/vsim/Makefile | 6 ++++++ variables.mk | 8 +++++++- 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/common.mk b/common.mk index b1195ee5..2136080b 100644 --- a/common.mk +++ b/common.mk @@ -67,6 +67,12 @@ $(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) .PHONY: verilog verilog: $(sim_vsrcs) +######################################################################################### +# helper rules to run simulator +######################################################################################### +run-binary: $(sim) + $(sim) $(PERMISSIVEON) $(SIM_FLAGS) $(PERMISSIVEOFF) $(BINARY) + ######################################################################################### # run assembly/benchmarks rules ######################################################################################### diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 0c5644b8..35a36369 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -80,6 +80,12 @@ $(sim): $(model_mk) $(sim_debug): $(model_mk_debug) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk +######################################################################################### +# helper rules to run simulator with debug +######################################################################################### +run-binary-debug: $(sim_debug) + $(sim_debug) $(SIM_FLAGS) -v$(long_name).vcd $(BINARY) + ######################################################################################### # create a verisim vpd rule ######################################################################################### diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 212c3e6f..9931bc03 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -86,6 +86,12 @@ $(sim_debug) : $(sim_vsrcs) $(sim_dotf) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp +######################################################################################### +# helper rules to run simulator with debug +######################################################################################### +run-binary-debug: $(sim_debug) + $(sim_debug) $(PERMISSIVEON) $(SIM_FLAGS) +vcdplusfile=$(long_name).vpd $(PERMISSIVEOFF) $(BINARY) + ######################################################################################### # create a vcs vpd rule ######################################################################################### diff --git a/variables.mk b/variables.mk index 94709245..22efd535 100644 --- a/variables.mk +++ b/variables.mk @@ -138,7 +138,13 @@ SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION ######################################################################################### # output directory for tests ######################################################################################### -output_dir=$(sim_dir)/output +output_dir=$(sim_dir)/output/$(long_name) + +######################################################################################### +# helper variables to run binaries +######################################################################################### +BINARY ?= none +SIM_FLAGS ?= +verbose ######################################################################################### # build output directory for compilation From 30d54a6851b511b017070619f67141e0fb927e22 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 May 2019 17:12:22 -0700 Subject: [PATCH 094/120] readme addition | pipe out output | renamed output files --- README.md | 10 ++++++++++ common.mk | 2 +- sims/verisim/Makefile | 2 +- sims/vsim/Makefile | 2 +- variables.mk | 3 ++- 5 files changed, 15 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 9e2b31fa..a4ef1c81 100644 --- a/README.md +++ b/README.md @@ -50,6 +50,16 @@ build an alternate configuration. make PROJECT=yourproject CONFIG=YourConfig ./simulator-yourproject-YourConfig ... +Additionally, you can use a helper make rule to run your simulation binary. The output will be in the "verisim" +directory under the file names: `..*` + + # first make your verisim rtl simulator binary + make SUB_PROJECT=example + # then run the binary (with no vcd generation) + make SUB_PROJECT=example BINARY= run-binary + # then run the binary (with vcd generation) + make SUB_PROJECT=example BINARY= run-binary-debug + ## Submodules and Subdirectories The submodules and subdirectories for the project template are organized as diff --git a/common.mk b/common.mk index 2136080b..b6519df0 100644 --- a/common.mk +++ b/common.mk @@ -71,7 +71,7 @@ verilog: $(sim_vsrcs) # helper rules to run simulator ######################################################################################### run-binary: $(sim) - $(sim) $(PERMISSIVEON) $(SIM_FLAGS) $(PERMISSIVEOFF) $(BINARY) + $(sim) $(PERMISSIVEON) $(SIM_FLAGS) $(PERMISSIVEOFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out ######################################################################################### # run assembly/benchmarks rules diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 35a36369..9264b43f 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -84,7 +84,7 @@ $(sim_debug): $(model_mk_debug) # helper rules to run simulator with debug ######################################################################################### run-binary-debug: $(sim_debug) - $(sim_debug) $(SIM_FLAGS) -v$(long_name).vcd $(BINARY) + $(sim_debug) $(SIM_FLAGS) -v$(sim_out_name).vcd $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out ######################################################################################### # create a verisim vpd rule diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 9931bc03..a9edcdc5 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -90,7 +90,7 @@ $(sim_debug) : $(sim_vsrcs) $(sim_dotf) # helper rules to run simulator with debug ######################################################################################### run-binary-debug: $(sim_debug) - $(sim_debug) $(PERMISSIVEON) $(SIM_FLAGS) +vcdplusfile=$(long_name).vpd $(PERMISSIVEOFF) $(BINARY) + $(sim_debug) $(PERMISSIVEON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVEOFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out ######################################################################################### # create a vcs vpd rule diff --git a/variables.mk b/variables.mk index 22efd535..dfc9d9fa 100644 --- a/variables.mk +++ b/variables.mk @@ -143,8 +143,9 @@ output_dir=$(sim_dir)/output/$(long_name) ######################################################################################### # helper variables to run binaries ######################################################################################### -BINARY ?= none +BINARY ?= SIM_FLAGS ?= +verbose +sim_out_name = $(notdir $(basename $(BINARY))).$(long_name) ######################################################################################### # build output directory for compilation From cc0d33ee4dcb6cc2519df2571f52408c6f08578c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 May 2019 17:19:46 -0700 Subject: [PATCH 095/120] updated permissive naming | small bugfix for vcd/vpd dumping --- common.mk | 6 +++--- sims/verisim/Makefile | 4 ++-- sims/vsim/Makefile | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/common.mk b/common.mk index b6519df0..ce5f845c 100644 --- a/common.mk +++ b/common.mk @@ -71,7 +71,7 @@ verilog: $(sim_vsrcs) # helper rules to run simulator ######################################################################################### run-binary: $(sim) - $(sim) $(PERMISSIVEON) $(SIM_FLAGS) $(PERMISSIVEOFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out + $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out ######################################################################################### # run assembly/benchmarks rules @@ -81,10 +81,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) +max-cycles=$(timeout_cycles) $< && touch $@ + $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVEON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVEOFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 9264b43f..655d67cc 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -25,8 +25,8 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVEON= -PERMISSIVEOFF= +PERMISSIVE_ON= +PERMISSIVE_OFF= .PHONY: default debug default: $(sim) diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index a9edcdc5..d34fb5eb 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -25,8 +25,8 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVEON=+permissive -PERMISSIVEOFF=+permissive-off +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off .PHONY: default debug default: $(sim) @@ -90,13 +90,13 @@ $(sim_debug) : $(sim_vsrcs) $(sim_dotf) # helper rules to run simulator with debug ######################################################################################### run-binary-debug: $(sim_debug) - $(sim_debug) $(PERMISSIVEON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVEOFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out + $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out ######################################################################################### # create a vcs vpd rule ######################################################################################### $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - $(sim_debug) +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $< + $(sim_debug) $(PERMISSIVE_ON) +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< ######################################################################################### # general cleanup rule From 1bf27d0fa9d5f5bc617b535a83a49ebb5fb772dd Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 21 May 2019 22:05:20 -0700 Subject: [PATCH 096/120] Bump boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 4cd347ed..8d3162cb 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 4cd347ed51f8bdf98d2d1868cf1530d845539613 +Subproject commit 8d3162cbbe6f0db19a39a2f22226ab9eb6edea31 From 8b3fef85cefdb98938e85e5cc01d7f529ba51b15 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 May 2019 17:44:47 -0700 Subject: [PATCH 097/120] first attempt at heter. port --- .../main/scala/BoomAndRocketSubsystem.scala | 94 ++++++++++++++ .../example/src/main/scala/ConfigMixins.scala | 66 ++++++++++ .../example/src/main/scala/Configs.scala | 120 +++++++++++++++++- .../scala/ExampleBoomAndRocketSystem.scala | 62 +++++++++ .../example/src/main/scala/TestHarness.scala | 35 +++++ generators/example/src/main/scala/Top.scala | 57 +++++++++ variables.mk | 12 ++ 7 files changed, 444 insertions(+), 2 deletions(-) create mode 100644 generators/example/src/main/scala/BoomAndRocketSubsystem.scala create mode 100644 generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala diff --git a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala new file mode 100644 index 00000000..275414ff --- /dev/null +++ b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala @@ -0,0 +1,94 @@ +package example + +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo} + +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.amba.axi4._ + +import boom.system.{BoomTilesKey} + +trait HasBoomAndRocketTiles extends HasTiles + with CanHavePeripheryPLIC + with CanHavePeripheryCLINT + with HasPeripheryDebug +{ this: BaseSubsystem => + + val module: HasBoomAndRocketTilesModuleImp + + protected val rocketTileParams = p(RocketTilesKey) + protected val boomTileParams = p(BoomTilesKey) + private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) + private val boomCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), boomTileParams.size) + + // Make a tile and wire its nodes into the system, + // according to the specified type of clock crossing. + // Note that we also inject new nodes into the tile itself, + // also based on the crossing type. + val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) => + val rocket = LazyModule(new RocketTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) + + connectMasterPortsToSBus(rocket, crossing) + connectSlavePortsToCBus(rocket, crossing) + connectInterrupts(rocket, Some(debug), clintOpt, plicOpt) + + rocket + } + + println(s"DEBUG: Amount of rocket tiles: ${rocketTiles.length}") + + val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) => + val boomCore = LazyModule( + new boom.common.BoomTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) + + connectMasterPortsToSBus(boomCore, crossing) + connectSlavePortsToCBus(boomCore, crossing) + connectInterrupts(boomCore, Some(debug), clintOpt, plicOpt) + + boomCore + } + + println(s"DEBUG: Amount of boom tiles: ${boomTiles.length}") + + val boomAndRocketTiles = rocketTiles ++ boomTiles + println(s"DEBUG: Amount of both tiles: ${boomAndRocketTiles.length}") + + def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++ + (boomTiles map { t => t.module.core.coreMonitorBundle}).toList + + def getOMRocketInterruptTargets(): Seq[OMInterruptTarget] = + boomAndRocketTiles.flatMap(c => c.cpuDevice.getInterruptTargets()) + + def getOMRocketCores(resourceBindingsMap: ResourceBindingsMap): Seq[OMComponent] = + boomAndRocketTiles.flatMap(c => c.cpuDevice.getOMComponents(resourceBindingsMap)) +} + +trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp + with HasPeripheryDebugModuleImp { + val outer: HasBoomAndRocketTiles +} + +class BoomAndRocketSubsystem(implicit p: Parameters) extends BaseSubsystem + with HasBoomAndRocketTiles { + val tiles = boomAndRocketTiles + override lazy val module = new BoomAndRocketSubsystemModuleImp(this) +} + +class BoomAndRocketSubsystemModuleImp[+L <: BoomAndRocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) + with HasBoomAndRocketTilesModuleImp { + tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => + wire.clock := clock + wire.reset := reset + wire.hartid := i.U + wire.reset_vector := global_reset_vector + } +} diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 5551a66d..02e4ea22 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -168,3 +168,69 @@ class WithGPIOBoomTop extends Config((site, here, up) => { top } }) + +// -------------------------------------- +// BOOM + Rocket Top Level System Parameter Mixins +// -------------------------------------- + +/** + * Class to specify a "plain" top level BOOM + Rocket system + */ +class WithNormalBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomAndRocketTop()(p)).module) + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with PWM + */ +class WithPWMBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomAndRocketTopWithPWMTL()(p)).module) +}) + +/** + * Class to specify a top level BOOM + Rocket system with a PWM AXI4 + */ +class WithPWMAXI4BoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomAndRocketTopWithPWMAXI4()(p)).module) +}) + +/** + * Class to specify a top level BOOM + Rocket system with a block device + */ +class WithBlockDeviceModelBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) + top.connectBlockDeviceModel() + top + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with a simulator block device + */ +class WithSimBlockDeviceBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) + top.connectSimBlockDevice(clock, reset) + top + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with GPIO + */ +class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithGPIO()(p)).module) + for (gpio <- top.gpio) { + for (pin <- gpio.pins) { + pin.i.ival := false.B + } + } + top + } +}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 68ca289c..97f08d62 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -106,10 +106,28 @@ class BlockDeviceModelBoomConfig extends Config( new WithBlockDeviceModelBoomTop ++ new BaseBoomConfig) +/** + * Slightly different looking configs since we need to override + * the `WithNBoomCores` with the DefaultBoomConfig params + */ class DualCoreBoomConfig extends Config( - // Core gets tacked onto existing list + new WithNormalBoomTop ++ + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(2) ++ - new DefaultBoomConfig) + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.system.BaseConfig) + +class DualCoreSmallBoomConfig extends Config( + new WithNormalBoomTop ++ + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.WithSmallBooms ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.system.BaseConfig) class RV32BoomConfig extends Config( new WithBootROM ++ @@ -119,3 +137,101 @@ class GPIOBoomConfig extends Config( new WithGPIO ++ new WithGPIOBoomTop ++ new BaseBoomConfig) + +// --------------------- +// BOOM + Rocket Configs +// --------------------- + +//class BaseRocketConfig extends Config( +// new WithBootROM ++ +// new freechips.rocketchip.system.DefaultConfig) +// +//class DefaultRocketConfig extends Config( +// new WithNormalRocketTop ++ +// new BaseRocketConfig) +// +//class BaseConfig extends Config( +// new WithDefaultMemPort() ++ +// new WithDefaultMMIOPort() ++ +// new WithDefaultSlavePort() ++ +// new WithTimebase(BigInt(1000000)) ++ // 1 MHz +// new WithDTS("freechips,rocketchip-unknown", Nil) ++ +// new WithNExtTopInterrupts(2) ++ +// new BaseSubsystemConfig() +//) +// +//class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig) +// +////boom +// new WithRVC ++ +// new DefaultBoomConfig ++ +// new WithNBoomCores(1) ++ +// new WithoutTLMonitors ++ +// new freechips.rocketchip.system.BaseConfig) + +class BaseBoomAndRocketConfig extends Config( + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +//class BaseBoomAndRocketConfig extends Config( +// new WithBootROM ++ +// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ +// new boom.system.BoomConfig) + +class SmallBaseBoomAndRocketConfig extends Config( + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new boom.system.SmallBoomConfig) + +class DefaultBoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class SmallDefaultBoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new SmallBaseBoomAndRocketConfig) + +class HwachaBoomAndRocketConfig extends Config( + new hwacha.DefaultHwachaConfig ++ + new DefaultBoomAndRocketConfig) + +class RoccBoomAndRocketConfig extends Config( + new WithRoccExample ++ + new DefaultBoomAndRocketConfig) + +class PWMBoomAndRocketConfig extends Config( + new WithPWMBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class PWMAXI4BoomAndRocketConfig extends Config( + new WithPWMAXI4BoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class SimBlockDeviceBoomAndRocketConfig extends Config( + new WithBlockDevice ++ + new WithSimBlockDeviceBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class BlockDeviceModelBoomAndRocketConfig extends Config( + new WithBlockDevice ++ + new WithBlockDeviceModelBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class DualCoreBoomAndOneRocketConfig extends Config( + // Core gets tacked onto existing list + new boom.system.WithNBoomCores(2) ++ + new DefaultBoomAndRocketConfig) + +class RV32BoomAndNormalRocketConfig extends Config( + new WithBootROM ++ + new boom.system.SmallRV32UnifiedBoomConfig) + +class GPIOBoomAndRocketConfig extends Config( + new WithGPIO ++ + new WithGPIOBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) diff --git a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala new file mode 100644 index 00000000..cc7fd3db --- /dev/null +++ b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala @@ -0,0 +1,62 @@ +package example + +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo} + +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.amba.axi4._ + +import boom.system.{BoomTilesKey} + +/** + * Example top with periphery devices and ports, and a BOOM subsystem + */ +class ExampleBoomAndRocketSystem(implicit p: Parameters) extends BoomAndRocketSubsystem + with HasAsyncExtInterrupts + with boom.system.CanHaveMisalignedMasterAXI4MemPort + with CanHaveMasterAXI4MMIOPort + with CanHaveSlaveAXI4Port + with HasPeripheryBootROM +{ + override lazy val module = new ExampleBoomAndRocketSystemModule(this) + + // The sbus masters the cbus; here we convert TL-UH -> TL-UL + sbus.crossToBus(cbus, NoCrossing) + + // The cbus masters the pbus; which might be clocked slower + cbus.crossToBus(pbus, SynchronousCrossing()) + + // The fbus masters the sbus; both are TL-UH or TL-C + FlipRendering { implicit p => + sbus.crossFromBus(fbus, SynchronousCrossing()) + } + + // The sbus masters the mbus; here we convert TL-C -> TL-UH + private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) + private val (in, out, halt) = coherenceManager(this) + if (nBanks != 0) { + sbus.coupleTo("coherence_manager") { in :*= _ } + mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } + } +} + +/** + * Example top module with periphery devices and ports, and a BOOM subsystem + */ +class ExampleBoomAndRocketSystemModule[+L <: ExampleBoomAndRocketSystem](_outer: L) extends BoomAndRocketSubsystemModuleImp(_outer) + with HasRTCModuleImp + with HasExtInterruptsModuleImp + with boom.system.CanHaveMisalignedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MMIOPortModuleImp + with CanHaveSlaveAXI4PortModuleImp + with HasPeripheryBootROMModuleImp + with DontTouch diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index b7120329..a517b6b8 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -77,3 +77,38 @@ class BoomTestHarness(implicit val p: Parameters) extends Module { }) io.success := dut.connectSimSerial() } + +// -------------------------- +// BOOM + Rocket Test Harness +// -------------------------- + +case object BuildBoomAndRocketTop extends Field[(Clock, Bool, Parameters) => BoomAndRocketTopModule[BoomAndRocketTop]] + +class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + // force Chisel to rename module + override def desiredName = "TestHarness" + + val dut = p(BuildBoomAndRocketTop)(clock, reset.toBool, p) + dut.debug := DontCare + dut.connectSimAXIMem() + dut.connectSimAXIMMIO() + dut.dontTouchPorts() + dut.tieOffInterrupts() + dut.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case core.ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case core.ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + io.success := dut.connectSimSerial() +} diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 8a39e3d1..50e5d0c6 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -127,3 +127,60 @@ class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop class BoomTopWithGPIOModule(l: BoomTopWithGPIO) extends BoomTopModule(l) with HasPeripheryGPIOModuleImp + +// ------------------------------- +// BOOM + Rocket Top Level Systems +// ------------------------------- + +class BoomAndRocketTop(implicit p: Parameters) extends ExampleBoomAndRocketSystem + with HasNoDebug + with HasPeripherySerial { + override lazy val module = new BoomAndRocketTopModule(this) +} + +class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends ExampleBoomAndRocketSystemModule(l) + with HasRTCModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with DontTouch + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithPWMTL(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryPWMTL { + override lazy val module = new BoomAndRocketTopWithPWMTLModule(this) +} + +class BoomAndRocketTopWithPWMTLModule(l: BoomAndRocketTopWithPWMTL) extends BoomAndRocketTopModule(l) + with HasPeripheryPWMTLModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryPWMAXI4 { + override lazy val module = new BoomAndRocketTopWithPWMAXI4Module(this) +} + +class BoomAndRocketTopWithPWMAXI4Module(l: BoomAndRocketTopWithPWMAXI4) extends BoomAndRocketTopModule(l) + with HasPeripheryPWMAXI4ModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithBlockDevice(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryBlockDevice { + override lazy val module = new BoomAndRocketTopWithBlockDeviceModule(this) +} + +class BoomAndRocketTopWithBlockDeviceModule(l: BoomAndRocketTopWithBlockDevice) extends BoomAndRocketTopModule(l) + with HasPeripheryBlockDeviceModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithGPIO(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryGPIO { + override lazy val module = new BoomAndRocketTopWithGPIOModule(this) +} + +class BoomAndRocketTopWithGPIOModule(l: BoomAndRocketTopWithGPIO) + extends BoomAndRocketTopModule(l) + with HasPeripheryGPIOModuleImp diff --git a/variables.mk b/variables.mk index 0808003c..62cd35ce 100644 --- a/variables.mk +++ b/variables.mk @@ -50,6 +50,18 @@ ifeq ($(SUB_PROJECT),boomexample) TB ?= TestDriver TOP ?= BoomTop endif +# for a BOOM + Rocket based example system +ifeq ($(SUB_PROJECT),boomrocketexample) + SBT_PROJECT ?= example + MODEL ?= BoomAndRocketTestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= $(SBT_PROJECT) + CONFIG ?= DefaultBoomAndRocketConfig + CONFIG_PACKAGE ?= $(SBT_PROJECT) + GENERATOR_PACKAGE ?= $(SBT_PROJECT) + TB ?= TestDriver + TOP ?= BoomAndRocketTop +endif # for BOOM developers ifeq ($(SUB_PROJECT),boom) SBT_PROJECT ?= boom From cae63ad13fffce885fe704e8f26861920be392cd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 May 2019 23:29:48 -0700 Subject: [PATCH 098/120] working heterogenous cores --- .../example/src/main/scala/ConfigMixins.scala | 26 ++++- .../example/src/main/scala/Configs.scala | 99 +++++++++---------- 2 files changed, 70 insertions(+), 55 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 02e4ea22..2816352d 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -1,14 +1,20 @@ package example import chisel3._ +import chisel3.util.{log2Up} + import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.{XLen} +import freechips.rocketchip.tile.{XLen, MaxHartIdBits} + import testchipip._ + import sifive.blocks.devices.gpio._ +import boom.system.{BoomTilesKey} + /** * TODO: Why do we need this? */ @@ -234,3 +240,19 @@ class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { top } }) + +/** + * Class to renumber BOOM + Rocket harts so that there are no overlapped harts + * This mixin assumes Rocket tiles are numbered before BOOM tiles + * Also makes support for multiple harts depend on Rocket + BOOM + * Note: Must come after all harts are assigned for it to apply + */ +class WithRenumberHarts extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => + r.copy(hartId = i) + } + case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => + b.copy(hartId = i + up(RocketTilesKey, site).length) + } + case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) +}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 97f08d62..74e9a131 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -1,8 +1,10 @@ package example import chisel3._ + import freechips.rocketchip.config.{Config} import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks} + import testchipip._ // -------------- @@ -43,6 +45,11 @@ class BlockDeviceModelRocketConfig extends Config( new WithBlockDeviceModelRocketTop ++ new BaseRocketConfig) +class GPIORocketConfig extends Config( + new WithGPIO ++ + new WithGPIORocketTop ++ + new BaseRocketConfig) + class DualCoreRocketConfig extends Config( new WithNBigCores(2) ++ new DefaultRocketConfig) @@ -51,11 +58,6 @@ class RV32RocketConfig extends Config( new WithRV32 ++ new DefaultRocketConfig) -class GPIORocketConfig extends Config( - new WithGPIO ++ - new WithGPIORocketTop ++ - new BaseRocketConfig) - class GB1MemoryConfig extends Config( new WithExtMemSize((1<<30) * 1L) ++ new DefaultRocketConfig) @@ -106,6 +108,11 @@ class BlockDeviceModelBoomConfig extends Config( new WithBlockDeviceModelBoomTop ++ new BaseBoomConfig) +class GPIOBoomConfig extends Config( + new WithGPIO ++ + new WithGPIOBoomTop ++ + new BaseBoomConfig) + /** * Slightly different looking configs since we need to override * the `WithNBoomCores` with the DefaultBoomConfig params @@ -129,48 +136,18 @@ class DualCoreSmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) -class RV32BoomConfig extends Config( +class RV32UnifiedBoomConfig extends Config( + new WithNormalBoomTop ++ new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) -class GPIOBoomConfig extends Config( - new WithGPIO ++ - new WithGPIOBoomTop ++ - new BaseBoomConfig) - // --------------------- // BOOM + Rocket Configs // --------------------- -//class BaseRocketConfig extends Config( -// new WithBootROM ++ -// new freechips.rocketchip.system.DefaultConfig) -// -//class DefaultRocketConfig extends Config( -// new WithNormalRocketTop ++ -// new BaseRocketConfig) -// -//class BaseConfig extends Config( -// new WithDefaultMemPort() ++ -// new WithDefaultMMIOPort() ++ -// new WithDefaultSlavePort() ++ -// new WithTimebase(BigInt(1000000)) ++ // 1 MHz -// new WithDTS("freechips,rocketchip-unknown", Nil) ++ -// new WithNExtTopInterrupts(2) ++ -// new BaseSubsystemConfig() -//) -// -//class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig) -// -////boom -// new WithRVC ++ -// new DefaultBoomConfig ++ -// new WithNBoomCores(1) ++ -// new WithoutTLMonitors ++ -// new freechips.rocketchip.system.BaseConfig) - class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ + new WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(1) ++ @@ -178,15 +155,16 @@ class BaseBoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) -//class BaseBoomAndRocketConfig extends Config( -// new WithBootROM ++ -// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ -// new boom.system.BoomConfig) - class SmallBaseBoomAndRocketConfig extends Config( new WithBootROM ++ + new WithRenumberHarts ++ + new boom.common.WithRVC ++ + new boom.common.WithSmallBooms ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new boom.system.SmallBoomConfig) + new freechips.rocketchip.system.BaseConfig) class DefaultBoomAndRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ @@ -222,16 +200,31 @@ class BlockDeviceModelBoomAndRocketConfig extends Config( new WithBlockDeviceModelBoomAndRocketTop ++ new BaseBoomAndRocketConfig) -class DualCoreBoomAndOneRocketConfig extends Config( - // Core gets tacked onto existing list - new boom.system.WithNBoomCores(2) ++ - new DefaultBoomAndRocketConfig) - -class RV32BoomAndNormalRocketConfig extends Config( - new WithBootROM ++ - new boom.system.SmallRV32UnifiedBoomConfig) - class GPIOBoomAndRocketConfig extends Config( new WithGPIO ++ new WithGPIOBoomAndRocketTop ++ new BaseBoomAndRocketConfig) + +class DualCoreBoomAndOneRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new WithBootROM ++ + new WithRenumberHarts ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class RV32BoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new WithBootROM ++ + new WithRenumberHarts ++ + new boom.common.WithBoomRV32 ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new WithRV32 ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) From e538e333a5be1af1903d89932554234b61302c88 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 21 May 2019 10:47:24 -0700 Subject: [PATCH 099/120] updated boom for fixes \ better printf From 838a34be51e57832b72d13b9b35172f068236437 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 19:26:08 -0700 Subject: [PATCH 100/120] move subsystem to boom | misc cleanup | bump boom --- generators/boom | 2 +- .../main/scala/BoomAndRocketSubsystem.scala | 94 ------------------- .../example/src/main/scala/ConfigMixins.scala | 82 ---------------- .../example/src/main/scala/Configs.scala | 28 +++--- .../scala/ExampleBoomAndRocketSystem.scala | 62 ------------ .../example/src/main/scala/TestHarness.scala | 35 ------- generators/example/src/main/scala/Top.scala | 61 +----------- variables.mk | 5 +- 8 files changed, 19 insertions(+), 350 deletions(-) delete mode 100644 generators/example/src/main/scala/BoomAndRocketSubsystem.scala delete mode 100644 generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala diff --git a/generators/boom b/generators/boom index 8d3162cb..ff8c25af 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 8d3162cbbe6f0db19a39a2f22226ab9eb6edea31 +Subproject commit ff8c25af0b14c7eba67451f574e1ddacaaf8a5b6 diff --git a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala deleted file mode 100644 index 275414ff..00000000 --- a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala +++ /dev/null @@ -1,94 +0,0 @@ -package example - -import chisel3._ -import chisel3.internal.sourceinfo.{SourceInfo} - -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.axi4._ - -import boom.system.{BoomTilesKey} - -trait HasBoomAndRocketTiles extends HasTiles - with CanHavePeripheryPLIC - with CanHavePeripheryCLINT - with HasPeripheryDebug -{ this: BaseSubsystem => - - val module: HasBoomAndRocketTilesModuleImp - - protected val rocketTileParams = p(RocketTilesKey) - protected val boomTileParams = p(BoomTilesKey) - private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) - private val boomCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), boomTileParams.size) - - // Make a tile and wire its nodes into the system, - // according to the specified type of clock crossing. - // Note that we also inject new nodes into the tile itself, - // also based on the crossing type. - val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) => - val rocket = LazyModule(new RocketTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) - - connectMasterPortsToSBus(rocket, crossing) - connectSlavePortsToCBus(rocket, crossing) - connectInterrupts(rocket, Some(debug), clintOpt, plicOpt) - - rocket - } - - println(s"DEBUG: Amount of rocket tiles: ${rocketTiles.length}") - - val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) => - val boomCore = LazyModule( - new boom.common.BoomTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) - - connectMasterPortsToSBus(boomCore, crossing) - connectSlavePortsToCBus(boomCore, crossing) - connectInterrupts(boomCore, Some(debug), clintOpt, plicOpt) - - boomCore - } - - println(s"DEBUG: Amount of boom tiles: ${boomTiles.length}") - - val boomAndRocketTiles = rocketTiles ++ boomTiles - println(s"DEBUG: Amount of both tiles: ${boomAndRocketTiles.length}") - - def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++ - (boomTiles map { t => t.module.core.coreMonitorBundle}).toList - - def getOMRocketInterruptTargets(): Seq[OMInterruptTarget] = - boomAndRocketTiles.flatMap(c => c.cpuDevice.getInterruptTargets()) - - def getOMRocketCores(resourceBindingsMap: ResourceBindingsMap): Seq[OMComponent] = - boomAndRocketTiles.flatMap(c => c.cpuDevice.getOMComponents(resourceBindingsMap)) -} - -trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp - with HasPeripheryDebugModuleImp { - val outer: HasBoomAndRocketTiles -} - -class BoomAndRocketSubsystem(implicit p: Parameters) extends BaseSubsystem - with HasBoomAndRocketTiles { - val tiles = boomAndRocketTiles - override lazy val module = new BoomAndRocketSubsystemModuleImp(this) -} - -class BoomAndRocketSubsystemModuleImp[+L <: BoomAndRocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) - with HasBoomAndRocketTilesModuleImp { - tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => - wire.clock := clock - wire.reset := reset - wire.hartid := i.U - wire.reset_vector := global_reset_vector - } -} diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 2816352d..363f0895 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -109,72 +109,6 @@ class WithGPIORocketTop extends Config((site, here, up) => { } }) -// -------------------------------------- -// BOOM Top Level System Parameter Mixins -// -------------------------------------- - -/** - * Class to specify a "plain" top level BOOM system - */ -class WithNormalBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomTop()(p)).module) - } -}) - -/** - * Class to specify a top level BOOM system with PWM - */ -class WithPWMBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomTopWithPWMTL()(p)).module) -}) - -/** - * Class to specify a top level BOOM system with a PWM AXI4 - */ -class WithPWMAXI4BoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomTopWithPWMAXI4()(p)).module) -}) - -/** - * Class to specify a top level BOOM system with a block device - */ -class WithBlockDeviceModelBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) - top.connectBlockDeviceModel() - top - } -}) - -/** - * Class to specify a top level BOOM system with a simulator block device - */ -class WithSimBlockDeviceBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -/** - * Class to specify a top level BOOM system with GPIO - */ -class WithGPIOBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithGPIO()(p)).module) - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } -}) - // -------------------------------------- // BOOM + Rocket Top Level System Parameter Mixins // -------------------------------------- @@ -240,19 +174,3 @@ class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { top } }) - -/** - * Class to renumber BOOM + Rocket harts so that there are no overlapped harts - * This mixin assumes Rocket tiles are numbered before BOOM tiles - * Also makes support for multiple harts depend on Rocket + BOOM - * Note: Must come after all harts are assigned for it to apply - */ -class WithRenumberHarts extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => - r.copy(hartId = i) - } - case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => - b.copy(hartId = i + up(RocketTilesKey, site).length) - } - case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) -}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 74e9a131..ee17916f 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -75,11 +75,11 @@ class SmallBaseBoomConfig extends Config( new boom.system.SmallBoomConfig) class DefaultBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new BaseBoomConfig) class SmallDefaultBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new SmallBaseBoomConfig) class HwachaBoomConfig extends Config( @@ -91,26 +91,26 @@ class RoccBoomConfig extends Config( new DefaultBoomConfig) class PWMBoomConfig extends Config( - new WithPWMBoomTop ++ + new WithPWMBoomAndRocketTop ++ new BaseBoomConfig) class PWMAXI4BoomConfig extends Config( - new WithPWMAXI4BoomTop ++ + new WithPWMAXI4BoomAndRocketTop ++ new BaseBoomConfig) class SimBlockDeviceBoomConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomTop ++ + new WithSimBlockDeviceBoomAndRocketTop ++ new BaseBoomConfig) class BlockDeviceModelBoomConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomTop ++ + new WithBlockDeviceModelBoomAndRocketTop ++ new BaseBoomConfig) class GPIOBoomConfig extends Config( new WithGPIO ++ - new WithGPIOBoomTop ++ + new WithGPIOBoomAndRocketTop ++ new BaseBoomConfig) /** @@ -118,7 +118,7 @@ class GPIOBoomConfig extends Config( * the `WithNBoomCores` with the DefaultBoomConfig params */ class DualCoreBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ @@ -127,7 +127,7 @@ class DualCoreBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreSmallBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ @@ -137,7 +137,7 @@ class DualCoreSmallBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class RV32UnifiedBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) @@ -147,7 +147,7 @@ class RV32UnifiedBoomConfig extends Config( class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(1) ++ @@ -157,7 +157,7 @@ class BaseBoomAndRocketConfig extends Config( class SmallBaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ new boom.common.DefaultBoomConfig ++ @@ -208,7 +208,7 @@ class GPIOBoomAndRocketConfig extends Config( class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(2) ++ @@ -219,7 +219,7 @@ class DualCoreBoomAndOneRocketConfig extends Config( class RV32BoomAndRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ diff --git a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala deleted file mode 100644 index cc7fd3db..00000000 --- a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala +++ /dev/null @@ -1,62 +0,0 @@ -package example - -import chisel3._ -import chisel3.internal.sourceinfo.{SourceInfo} - -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.axi4._ - -import boom.system.{BoomTilesKey} - -/** - * Example top with periphery devices and ports, and a BOOM subsystem - */ -class ExampleBoomAndRocketSystem(implicit p: Parameters) extends BoomAndRocketSubsystem - with HasAsyncExtInterrupts - with boom.system.CanHaveMisalignedMasterAXI4MemPort - with CanHaveMasterAXI4MMIOPort - with CanHaveSlaveAXI4Port - with HasPeripheryBootROM -{ - override lazy val module = new ExampleBoomAndRocketSystemModule(this) - - // The sbus masters the cbus; here we convert TL-UH -> TL-UL - sbus.crossToBus(cbus, NoCrossing) - - // The cbus masters the pbus; which might be clocked slower - cbus.crossToBus(pbus, SynchronousCrossing()) - - // The fbus masters the sbus; both are TL-UH or TL-C - FlipRendering { implicit p => - sbus.crossFromBus(fbus, SynchronousCrossing()) - } - - // The sbus masters the mbus; here we convert TL-C -> TL-UH - private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) - private val (in, out, halt) = coherenceManager(this) - if (nBanks != 0) { - sbus.coupleTo("coherence_manager") { in :*= _ } - mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } - } -} - -/** - * Example top module with periphery devices and ports, and a BOOM subsystem - */ -class ExampleBoomAndRocketSystemModule[+L <: ExampleBoomAndRocketSystem](_outer: L) extends BoomAndRocketSubsystemModuleImp(_outer) - with HasRTCModuleImp - with HasExtInterruptsModuleImp - with boom.system.CanHaveMisalignedMasterAXI4MemPortModuleImp - with CanHaveMasterAXI4MMIOPortModuleImp - with CanHaveSlaveAXI4PortModuleImp - with HasPeripheryBootROMModuleImp - with DontTouch diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index a517b6b8..3d488c1c 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -43,41 +43,6 @@ class RocketTestHarness(implicit val p: Parameters) extends Module { io.success := dut.connectSimSerial() } -// ----------------- -// BOOM Test Harness -// ----------------- - -case object BuildBoomTop extends Field[(Clock, Bool, Parameters) => BoomTopModule[BoomTop]] - -class BoomTestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - // force Chisel to rename module - override def desiredName = "TestHarness" - - val dut = p(BuildBoomTop)(clock, reset.toBool, p) - dut.debug := DontCare - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - io.success := dut.connectSimSerial() -} - // -------------------------- // BOOM + Rocket Test Harness // -------------------------- diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 50e5d0c6..a481deef 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -71,74 +71,17 @@ class RocketTopWithGPIOModule(l: RocketTopWithGPIO) extends RocketTopModule(l) with HasPeripheryGPIOModuleImp -// ---------------------- -// BOOM Top Level Systems -// ---------------------- - -class BoomTop(implicit p: Parameters) extends boom.system.ExampleBoomSystem - with HasNoDebug - with HasPeripherySerial { - override lazy val module = new BoomTopModule(this) -} - -class BoomTopModule[+L <: BoomTop](l: L) extends boom.system.ExampleBoomSystemModule(l) - with HasRTCModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp - with DontTouch - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithPWMTL(implicit p: Parameters) extends BoomTop - with HasPeripheryPWMTL { - override lazy val module = new BoomTopWithPWMTLModule(this) -} - -class BoomTopWithPWMTLModule(l: BoomTopWithPWMTL) extends BoomTopModule(l) - with HasPeripheryPWMTLModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithPWMAXI4(implicit p: Parameters) extends BoomTop - with HasPeripheryPWMAXI4 { - override lazy val module = new BoomTopWithPWMAXI4Module(this) -} - -class BoomTopWithPWMAXI4Module(l: BoomTopWithPWMAXI4) extends BoomTopModule(l) - with HasPeripheryPWMAXI4ModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithBlockDevice(implicit p: Parameters) extends BoomTop - with HasPeripheryBlockDevice { - override lazy val module = new BoomTopWithBlockDeviceModule(this) -} - -class BoomTopWithBlockDeviceModule(l: BoomTopWithBlockDevice) extends BoomTopModule(l) - with HasPeripheryBlockDeviceModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop - with HasPeripheryGPIO { - override lazy val module = new BoomTopWithGPIOModule(this) -} - -class BoomTopWithGPIOModule(l: BoomTopWithGPIO) - extends BoomTopModule(l) - with HasPeripheryGPIOModuleImp - // ------------------------------- // BOOM + Rocket Top Level Systems // ------------------------------- -class BoomAndRocketTop(implicit p: Parameters) extends ExampleBoomAndRocketSystem +class BoomAndRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem with HasNoDebug with HasPeripherySerial { override lazy val module = new BoomAndRocketTopModule(this) } -class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends ExampleBoomAndRocketSystemModule(l) +class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) with HasRTCModuleImp with HasNoDebugModuleImp with HasPeripherySerialModuleImp diff --git a/variables.mk b/variables.mk index 62cd35ce..fb4f3632 100644 --- a/variables.mk +++ b/variables.mk @@ -48,7 +48,7 @@ ifeq ($(SUB_PROJECT),boomexample) CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= BoomTop + TOP ?= BoomAndRocketTop endif # for a BOOM + Rocket based example system ifeq ($(SUB_PROJECT),boomrocketexample) @@ -72,7 +72,7 @@ ifeq ($(SUB_PROJECT),boom) CONFIG_PACKAGE ?= boom.system GENERATOR_PACKAGE ?= boom.system TB ?= TestDriver - TOP ?= ExampleBoomSystem + TOP ?= ExampleBoomAndRocketSystem endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) @@ -186,4 +186,3 @@ sim_vsrcs = \ # assembly/benchmark variables ######################################################################################### timeout_cycles = 10000000 -bmark_timeout_cycles = 100000000 From 9182c1394abd19858534413915052819eadb0c34 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 21:46:37 -0700 Subject: [PATCH 101/120] update boom | fix comments and remove extra code --- generators/boom | 2 +- generators/example/src/main/scala/ConfigMixins.scala | 4 ++-- generators/example/src/main/scala/Top.scala | 1 - 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/generators/boom b/generators/boom index ff8c25af..734d62c6 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit ff8c25af0b14c7eba67451f574e1ddacaaf8a5b6 +Subproject commit 734d62c6a91920f62730a4a076f8dfce29c52bf2 diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 363f0895..1380b90b 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -109,9 +109,9 @@ class WithGPIORocketTop extends Config((site, here, up) => { } }) -// -------------------------------------- +// ----------------------------------------------- // BOOM + Rocket Top Level System Parameter Mixins -// -------------------------------------- +// ----------------------------------------------- /** * Class to specify a "plain" top level BOOM + Rocket system diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index a481deef..59493492 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -82,7 +82,6 @@ class BoomAndRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAn } class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) - with HasRTCModuleImp with HasNoDebugModuleImp with HasPeripherySerialModuleImp with DontTouch From 612aa48e65c2441de46d87e02f8690e0e4826694 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 21:51:42 -0700 Subject: [PATCH 102/120] remove extra imports --- generators/example/src/main/scala/ConfigMixins.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 1380b90b..8e8f017b 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -4,17 +4,15 @@ import chisel3._ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.{XLen, MaxHartIdBits} +import freechips.rocketchip.tile.{XLen} import testchipip._ import sifive.blocks.devices.gpio._ -import boom.system.{BoomTilesKey} - /** * TODO: Why do we need this? */ From 6d622e7555f63fed80c7ed13e778b1b903be8ebe Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 22:00:04 -0700 Subject: [PATCH 103/120] add boomrocketexample to ci --- .circleci/config.yml | 72 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index 1e5146bb..50577af7 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -161,6 +161,40 @@ jobs: paths: - "/home/riscvuser/project" + prepare-boomrocketexample: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + + - run: + name: Building the boomrocketexample subproject using Verilator + command: .circleci/do-rtl-build.sh SUB_PROJECT=boomrocketexample CONFIG=SmallDefaultBoomAndRocketConfig + no_output_timeout: 120m + + - save_cache: + key: boomrocketexample-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project" + prepare-boom: docker: - image: riscvboom/riscvboom-images:0.0.5 @@ -319,6 +353,34 @@ jobs: name: Run boomexample benchmark tests command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig + boomrocketexample-run-benchmark-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - boomrocketexample-{{ .Branch }}-{{ .Revision }} + + - run: + name: Run boomrocketexample benchmark tests + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomAndRocketConfig + boom-run-benchmark-tests: docker: - image: riscvboom/riscvboom-images:0.0.5 @@ -427,6 +489,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-boomrocketexample: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-boom: requires: - install-riscv-toolchain @@ -456,6 +523,11 @@ workflows: - install-riscv-toolchain - prepare-boomexample + - boomrocketexample-run-benchmark-tests: + requires: + - install-riscv-toolchain + - prepare-boomrocketexample + - boom-run-benchmark-tests: requires: - install-riscv-toolchain From f071b522b2b58b4e38041aacab19ddefc554fb2e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 22:01:50 -0700 Subject: [PATCH 104/120] ci harness fix for boomexample --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index fb4f3632..16e69d02 100644 --- a/variables.mk +++ b/variables.mk @@ -41,7 +41,7 @@ endif # for a BOOM based example system ifeq ($(SUB_PROJECT),boomexample) SBT_PROJECT ?= example - MODEL ?= BoomTestHarness + MODEL ?= BoomAndRocketTestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultBoomConfig From 5408d6ecbef7c7d972ce5c3fc3417a03739faaf2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 22:58:28 -0700 Subject: [PATCH 105/120] bump boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 734d62c6..4b0365f4 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 734d62c6a91920f62730a4a076f8dfce29c52bf2 +Subproject commit 4b0365f4ff6eda6018b1f6fb116f54d0ace35486 From 4af9ea9846097305eec3cf0e56d4800dc3ca33f6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 09:47:50 -0700 Subject: [PATCH 106/120] make default flags include timeout | all sims share flags --- common.mk | 4 ++-- variables.mk | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index f7e46608..3d67cebd 100644 --- a/common.mk +++ b/common.mk @@ -86,10 +86,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< && touch $@ + $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/variables.mk b/variables.mk index 0808003c..55c64871 100644 --- a/variables.mk +++ b/variables.mk @@ -147,7 +147,7 @@ output_dir=$(sim_dir)/output/$(long_name) # helper variables to run binaries ######################################################################################### BINARY ?= -SIM_FLAGS ?= +verbose +SIM_FLAGS ?= +verbose +max-cycles=$(timeout_cycles) sim_out_name = $(notdir $(basename $(BINARY))).$(long_name) ######################################################################################### From 08dd5b53758aadcc80845bba325f9fa10feea43b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 17:37:16 -0700 Subject: [PATCH 107/120] update boom to master --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 4b0365f4..92313af2 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 4b0365f4ff6eda6018b1f6fb116f54d0ace35486 +Subproject commit 92313af2a0ed4d8a93591a08f42ede1a0ffd808a From c341ffe57d96348e559b8b582858b19066b8266a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 21:22:46 -0700 Subject: [PATCH 108/120] remove verbose for default --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index 55c64871..7753e0ea 100644 --- a/variables.mk +++ b/variables.mk @@ -147,7 +147,7 @@ output_dir=$(sim_dir)/output/$(long_name) # helper variables to run binaries ######################################################################################### BINARY ?= -SIM_FLAGS ?= +verbose +max-cycles=$(timeout_cycles) +SIM_FLAGS ?= +max-cycles=$(timeout_cycles) sim_out_name = $(notdir $(basename $(BINARY))).$(long_name) ######################################################################################### From c19855bfa66406186738fac9363b08f2725f5f5c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 26 May 2019 15:46:19 -0700 Subject: [PATCH 109/120] shared heter-subsystem | single example SUB_PROJECT --- .circleci/config.yml | 8 +-- .../example/src/main/scala/ConfigMixins.scala | 66 ------------------- .../example/src/main/scala/Configs.scala | 12 ++-- .../example/src/main/scala/Generator.scala | 4 ++ .../example/src/main/scala/TestHarness.scala | 38 +---------- generators/example/src/main/scala/Top.scala | 65 +----------------- variables.mk | 26 +------- 7 files changed, 20 insertions(+), 199 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 50577af7..d2354fde 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -153,7 +153,7 @@ jobs: - run: name: Building the boomexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig no_output_timeout: 120m - save_cache: @@ -187,7 +187,7 @@ jobs: - run: name: Building the boomrocketexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=boomrocketexample CONFIG=SmallDefaultBoomAndRocketConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig no_output_timeout: 120m - save_cache: @@ -351,7 +351,7 @@ jobs: - run: name: Run boomexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig boomrocketexample-run-benchmark-tests: docker: @@ -379,7 +379,7 @@ jobs: - run: name: Run boomrocketexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomAndRocketConfig + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig boom-run-benchmark-tests: docker: diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 8e8f017b..dbfc1c34 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -41,72 +41,6 @@ class WithGPIO extends Config((site, here, up) => { GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) }) -// ---------------------------------------- -// Rocket Top Level System Parameter Mixins -// ---------------------------------------- - -/** - * Class to specify a "plain" top level rocket-chip system - */ -class WithNormalRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new RocketTop()(p)).module) - } -}) - -/** - * Class to specify a top level rocket-chip system with PWM - */ -class WithPWMRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new RocketTopWithPWMTL()(p)).module) -}) - -/** - * Class to specify a top level rocket-chip system with a PWM AXI4 - */ -class WithPWMAXI4RocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new RocketTopWithPWMAXI4()(p)).module) -}) - -/** - * Class to specify a top level rocket-chip system with a block device - */ -class WithBlockDeviceModelRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) - top.connectBlockDeviceModel() - top - } -}) - -/** - * Class to specify a top level rocket-chip system with a simulator block device - */ -class WithSimBlockDeviceRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -/** - * Class to specify a top level rocket-chip system with GPIO - */ -class WithGPIORocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithGPIO()(p)).module) - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } -}) - // ----------------------------------------------- // BOOM + Rocket Top Level System Parameter Mixins // ----------------------------------------------- diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index ee17916f..98a37bc7 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -16,7 +16,7 @@ class BaseRocketConfig extends Config( new freechips.rocketchip.system.DefaultConfig) class DefaultRocketConfig extends Config( - new WithNormalRocketTop ++ + new WithNormalBoomAndRocketTop ++ new BaseRocketConfig) class HwachaConfig extends Config( @@ -28,26 +28,26 @@ class RoccRocketConfig extends Config( new DefaultRocketConfig) class PWMRocketConfig extends Config( - new WithPWMRocketTop ++ + new WithPWMBoomAndRocketTop ++ new BaseRocketConfig) class PWMAXI4RocketConfig extends Config( - new WithPWMAXI4RocketTop ++ + new WithPWMAXI4BoomAndRocketTop ++ new BaseRocketConfig) class SimBlockDeviceRocketConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceRocketTop ++ + new WithSimBlockDeviceBoomAndRocketTop ++ new BaseRocketConfig) class BlockDeviceModelRocketConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelRocketTop ++ + new WithBlockDeviceModelBoomAndRocketTop ++ new BaseRocketConfig) class GPIORocketConfig extends Config( new WithGPIO ++ - new WithGPIORocketTop ++ + new WithGPIOBoomAndRocketTop ++ new BaseRocketConfig) class DualCoreRocketConfig extends Config( diff --git a/generators/example/src/main/scala/Generator.scala b/generators/example/src/main/scala/Generator.scala index 3a1300b4..c5df8cb1 100644 --- a/generators/example/src/main/scala/Generator.scala +++ b/generators/example/src/main/scala/Generator.scala @@ -1,15 +1,19 @@ package example import scala.collection.mutable.LinkedHashSet + import chisel3._ import chisel3.experimental._ + import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} + import freechips.rocketchip.subsystem.{RocketTilesKey} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.{GeneratorApp} import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} + import boom.system.{BoomTilesKey, BoomTestSuites} object Generator extends GeneratorApp { diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index 3d488c1c..7bad5cbc 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -2,47 +2,13 @@ package example import chisel3._ import chisel3.experimental._ + import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} + import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp -// ------------------- -// Rocket Test Harness -// ------------------- - -case object BuildRocketTop extends Field[(Clock, Bool, Parameters) => RocketTopModule[RocketTop]] - -class RocketTestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - // force Chisel to rename module - override def desiredName = "TestHarness" - - val dut = p(BuildRocketTop)(clock, reset.toBool, p) - dut.debug := DontCare - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - - io.success := dut.connectSimSerial() -} - // -------------------------- // BOOM + Rocket Test Harness // -------------------------- diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 59493492..ddd4a20f 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -1,76 +1,17 @@ package example import chisel3._ + import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util.DontTouch + import testchipip._ + import sifive.blocks.devices.gpio._ -// ------------------------ -// Rocket Top Level Systems -// ------------------------ - -class RocketTop(implicit p: Parameters) extends ExampleRocketSystem - with CanHaveMasterAXI4MemPort - with HasPeripheryBootROM - with HasNoDebug - with HasPeripherySerial { - override lazy val module = new RocketTopModule(this) -} - -class RocketTopModule[+L <: RocketTop](l: L) extends ExampleRocketSystemModuleImp(l) - with HasRTCModuleImp - with CanHaveMasterAXI4MemPortModuleImp - with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp - with DontTouch - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithPWMTL(implicit p: Parameters) extends RocketTop - with HasPeripheryPWMTL { - override lazy val module = new RocketTopWithPWMTLModule(this) -} - -class RocketTopWithPWMTLModule(l: RocketTopWithPWMTL) - extends RocketTopModule(l) with HasPeripheryPWMTLModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithPWMAXI4(implicit p: Parameters) extends RocketTop - with HasPeripheryPWMAXI4 { - override lazy val module = new RocketTopWithPWMAXI4Module(this) -} - -class RocketTopWithPWMAXI4Module(l: RocketTopWithPWMAXI4) - extends RocketTopModule(l) with HasPeripheryPWMAXI4ModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithBlockDevice(implicit p: Parameters) extends RocketTop - with HasPeripheryBlockDevice { - override lazy val module = new RocketTopWithBlockDeviceModule(this) -} - -class RocketTopWithBlockDeviceModule(l: RocketTopWithBlockDevice) - extends RocketTopModule(l) - with HasPeripheryBlockDeviceModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithGPIO(implicit p: Parameters) extends RocketTop - with HasPeripheryGPIO { - override lazy val module = new RocketTopWithGPIOModule(this) -} - -class RocketTopWithGPIOModule(l: RocketTopWithGPIO) - extends RocketTopModule(l) - with HasPeripheryGPIOModuleImp - // ------------------------------- // BOOM + Rocket Top Level Systems // ------------------------------- diff --git a/variables.mk b/variables.mk index 16e69d02..f73d7f7a 100644 --- a/variables.mk +++ b/variables.mk @@ -29,37 +29,13 @@ SUB_PROJECT ?= example ifeq ($(SUB_PROJECT),example) SBT_PROJECT ?= example - MODEL ?= RocketTestHarness + MODEL ?= BoomAndRocketTestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultRocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= RocketTop -endif -# for a BOOM based example system -ifeq ($(SUB_PROJECT),boomexample) - SBT_PROJECT ?= example - MODEL ?= BoomAndRocketTestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= $(SBT_PROJECT) - CONFIG ?= DefaultBoomConfig - CONFIG_PACKAGE ?= $(SBT_PROJECT) - GENERATOR_PACKAGE ?= $(SBT_PROJECT) - TB ?= TestDriver - TOP ?= BoomAndRocketTop -endif -# for a BOOM + Rocket based example system -ifeq ($(SUB_PROJECT),boomrocketexample) - SBT_PROJECT ?= example - MODEL ?= BoomAndRocketTestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= $(SBT_PROJECT) - CONFIG ?= DefaultBoomAndRocketConfig - CONFIG_PACKAGE ?= $(SBT_PROJECT) - GENERATOR_PACKAGE ?= $(SBT_PROJECT) - TB ?= TestDriver TOP ?= BoomAndRocketTop endif # for BOOM developers From dde22a969b2a2b167836d21dd5c0b5d7b0a077b8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 15:29:09 -0700 Subject: [PATCH 110/120] add more to docs | 1st spelling pass | more links | proper formatting --- docs/Generators/BOOM.rst | 13 +- docs/Generators/Hwacha.rst | 8 + docs/Generators/Rocket.rst | 11 +- docs/Generators/index.rst | 10 +- .../Adding-An-Accelerator-Tutorial.rst | 216 ++++++++---------- .../Configs-Parameters-Mixins.rst | 64 ++++-- .../Getting-Started/Development-Ecosystem.rst | 25 ++ docs/Getting-Started/REBAR-Basics.rst | 110 +++++++++ docs/Getting-Started/ReBAR-Basics.rst | 86 ------- docs/Getting-Started/Running-A-Simulation.rst | 144 +++++------- docs/Getting-Started/index.rst | 8 +- .../rebar-generator-mixins.rst | 6 +- docs/Makefile | 4 +- docs/Simulation/Commercial-Simulators.rst | 38 +-- docs/Simulation/FPGA-Based-Simulators.rst | 12 +- docs/Simulation/Open-Source-Simulators.rst | 38 +-- docs/Simulation/index.rst | 6 +- docs/Tools/Barstools.rst | 4 +- docs/Tools/Chisel.rst | 18 +- docs/Tools/FIRRTL.rst | 9 + docs/Tools/index.rst | 3 +- docs/VLSI/HAMMER.rst | 7 + docs/VLSI/index.rst | 5 +- docs/conf.py | 14 +- docs/index.rst | 41 +--- 25 files changed, 471 insertions(+), 429 deletions(-) create mode 100644 docs/Generators/Hwacha.rst create mode 100644 docs/Getting-Started/Development-Ecosystem.rst create mode 100644 docs/Getting-Started/REBAR-Basics.rst delete mode 100644 docs/Getting-Started/ReBAR-Basics.rst create mode 100644 docs/VLSI/HAMMER.rst diff --git a/docs/Generators/BOOM.rst b/docs/Generators/BOOM.rst index f0cac535..e04bed8f 100644 --- a/docs/Generators/BOOM.rst +++ b/docs/Generators/BOOM.rst @@ -1,10 +1,11 @@ Berkeley Out-of-Order Machine (BOOM) ============================================== -The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. +The `Berkeley Out-of-Order Machine (BOOM) `__ is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. +It serves as a drop-in replacement to the Rocket core given by Rocket Chip. +BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 outoforder processors. +Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”). +Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. +However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). -BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 outoforder processors. Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”). - -Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). - -Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages __`. +Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages __`. diff --git a/docs/Generators/Hwacha.rst b/docs/Generators/Hwacha.rst new file mode 100644 index 00000000..d040d35d --- /dev/null +++ b/docs/Generators/Hwacha.rst @@ -0,0 +1,8 @@ +Hwacha +==================================== + +The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption. +Inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures Scale and Maven, we are bringing back elegant, performant, and energy-efficient aspects of vector processing to modern data-parallel architectures. +We propose a new vector-fetch architectural paradigm, which focuses on the following aspects for higher performance, better energy efficiency, and lower complexity. + +For more information, please visit the `Hwacha website `__. diff --git a/docs/Generators/Rocket.rst b/docs/Generators/Rocket.rst index 06bf26eb..401b9e36 100644 --- a/docs/Generators/Rocket.rst +++ b/docs/Generators/Rocket.rst @@ -1,3 +1,12 @@ Rocket ==================================== -TODO: Basic rocket introduction + +`Rocket `__ is a 5-stage in-order scalar core generator that is supported by `SiFive `__. +It supports the open source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language. +It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction. +Branch prediction is configurable and provided by a branch target buffer (BTB), branch history table (BHT), and a return address stack (RAS). +For floating-point, Rocket makes use of Berkeley’s Chisel implementations of floating-point units. +Rocket also supports the RISC-V machine, supervisor, and user privilege levels. +A number of parameters are exposed, including the optional support of some ISA extensions (M, A, F, D), the number of floating-point pipeline stages, and the cache and TLB sizes. + +For more information, please refer to the `GitHub repository `__, `technical report `__ or to `this Chisel Community Conference video `__. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 7aa22141..765b2549 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -1,8 +1,11 @@ Generators ============================ -Generator can be thought of as generalized RTL designs, written using a mix of meta-programming and standard RTL. -This type of meta-programming is enabled by the Chisel hardware description framework embedded in Scala. -A standard RTL design is esentially a degenerate form of a generator. However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. The following pages introduce the generators integrated with the ReBAR framework. + +Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL. +This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Chisel`). +A standard RTL design is essentially just a single instance of a design coming from a generator. +However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. +The following pages introduce the generators integrated with the REBAR framework. .. toctree:: :maxdepth: 2 @@ -10,4 +13,5 @@ A standard RTL design is esentially a degenerate form of a generator. However, b Rocket BOOM + Hwacha diff --git a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst index 1df6b0d5..6b4c58c5 100644 --- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst +++ b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst @@ -1,80 +1,69 @@ - - Adding An Accelerator/Device =============================== Accelerators or custom IO devices can be added to your SoC in several ways: -+ MMIO Peripheral (a.k.a TileLink-Attached Accelerator) -+ Tightly-Coupled RoCC Accelerator -These approaches differ in the method of the communication between the processor and the custom block. +* MMIO Peripheral (a.k.a TileLink-Attached Accelerator) +* Tightly-Coupled RoCC Accelerator -With the TileLink-Attached approach, the processor communicates with MMIO peripherals through memory-mapped registers. +These approaches differ in the method of the communication between the processor and the custom block. -In contrast, the processor communicates with a RoCC accelerators through a custom protocol and custom non-standard ISA instructions reserved in the RISC-V ISA encoding space. Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU. +With the TileLink-Attached approach, the processor communicates with MMIO peripherals through memory-mapped registers. + +In contrast, the processor communicates with a RoCC accelerators through a custom protocol and custom non-standard ISA instructions reserved in the RISC-V ISA encoding space. +Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU. RoCC coprocessor instructions have the following form. -:: +.. code-block:: customX rd, rs1, rs2, funct -The X will be a number 0-3, and determines the opcode of the instruction, -which controls which accelerator an instruction will be routed to. -The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination -register and two source registers. The ``funct`` field is a 7-bit integer that -the accelerator can use to distinguish different instructions from each other. - -Note that communication through a RoCC interfaces requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with approriate driver support. +The X will be a number 0-3, and determines the opcode of the instruction, which controls which accelerator an instruction will be routed to. +The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination register and two source registers. +The ``funct`` field is a 7-bit integer that the accelerator can use to distinguish different instructions from each other. +Note that communication through a RoCC interface requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with approriate driver support. Integrating into the Generator Build System ------------------------------------------- -While developing, you want to include Chisel code in a submodule so that it -can be shared by different projects. To add a submodule to the project -template, make sure that your project is organized as follows. +While developing, you want to include Chisel code in a submodule so that it can be shared by different projects. +To add a submodule to the REBAR framework, make sure that your project is organized as follows. +.. code-block:: yourproject/ build.sbt src/main/scala/ YourFile.scala -Put this in a git repository and make it accessible. Then add it as a submodule -to under the following directory hierarchy: ``rebar/generators/yourproject``. +Put this in a git repository and make it accessible. +Then add it as a submodule to under the following directory hierarchy: ``generators/yourproject``. -:: +.. code-block:: shell + cd generators/ git submodule add https://git-repository.com/yourproject.git -Then add `yourproject` to the ReBAR top-level build.sbt file. +Then add ``yourproject`` to the REBAR top-level build.sbt file. -:: +.. code-block:: scala lazy val yourproject = project.settings(commonSettings).dependsOn(rocketchip) - You can then import the classes defined in the submodule in a new project if you add it as a dependency. For instance, if you want to use this code in -the `example` project, change the final line in build.sbt to the following. +the ``example`` project, change the final line in build.sbt to the following. -:: +.. code-block:: scala lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) - -Finally, add `yourproject` to the `PACKAGES` variable in the `Makefrag`. This will allow make to detect -that your source files have changed when building the verilog/firrtl files. - - +Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the REBAR top level. +This will allow make to detect that your source files have changed when building the Verilog/FIRRTL files. MMIO Peripheral ------------------ -The easiest way to create a TileLink peripheral is to use the -TLRegisterRouter, which abstracts away the details of handling the TileLink -protocol and provides a convenient interface for specifying memory-mapped -registers. To create a RegisterRouter-based peripheral, you will need to -specify a parameter case class for the configuration settings, a bundle trait -with the extra top-level ports, and a module implementation containing the -actual RTL. +The easiest way to create a TileLink peripheral is to use the ``TLRegisterRouter``, which abstracts away the details of handling the TileLink protocol and provides a convenient interface for specifying memory-mapped registers. +To create a RegisterRouter-based peripheral, you will need to specify a parameter case class for the configuration settings, a bundle trait with the extra top-level ports, and a module implementation containing the actual RTL. -:: +.. code-block:: scala case class PWMParams(address: BigInt, beatBytes: Int) trait PWMTLBundle extends Bundle { @@ -103,16 +92,12 @@ actual RTL. } -Once you have these classes, you can construct the final peripheral by -extending the TLRegisterRouter and passing the proper arguments. The first -set of arguments determines where the register router will be placed in the -global address map and what information will be put in its device tree entry. -The second set of arguments is the IO bundle constructor, which we create -by extending TLRegBundle with our bundle trait. The final set of arguments -is the module constructor, which we create by extends TLRegModule with our -module trait. +Once you have these classes, you can construct the final peripheral by extending the ``TLRegisterRouter`` and passing the proper arguments. +The first set of arguments determines where the register router will be placed in the global address map and what information will be put in its device tree entry. +The second set of arguments is the IO bundle constructor, which we create by extending ``TLRegBundle`` with our bundle trait. +The final set of arguments is the module constructor, which we create by extends ``TLRegModule`` with our module trait. -:: +.. code-block:: scala class PWMTL(c: PWMParams)(implicit p: Parameters) extends TLRegisterRouter( c.address, "pwm", Seq("ucbbar,pwm"), @@ -120,20 +105,17 @@ module trait. new TLRegBundle(c, _) with PWMTLBundle)( new TLRegModule(c, _, _) with PWMTLModule) +The full module code can be found in ``generators/example/src/main/scala/PWM.scala``. -The full module code with comments can be found in src/main/scala/example/PWM.scala. +After creating the module, we need to hook it up to our SoC. +Rocket Chip accomplishes this using the cake pattern. +This basically involves placing code inside traits. +In the Rocket Chip cake, there are two kinds of traits: a ``LazyModule`` trait and a module implementation trait. -After creating the module, we need to hook it up to our SoC. Rocketchip -accomplishes this using the [cake pattern](http://www.cakesolutions.net/teamblogs/2011/12/19/cake-pattern-in-depth). -This basically involves placing code inside traits. In the RocketChip cake, -there are two kinds of traits: a LazyModule trait and a module implementation -trait. +The ``LazyModule`` trait runs setup code that must execute before all the hardware gets elaborated. +For a simple memory-mapped peripheral, this just involves connecting the peripheral's TileLink node to the MMIO crossbar. -The LazyModule trait runs setup code that must execute before all the hardware -gets elaborated. For a simple memory-mapped peripheral, this just involves -connecting the peripheral's TileLink node to the MMIO crossbar. - -:: +.. code-block:: scala trait HasPeripheryPWM extends HasSystemNetworks { implicit val p: Parameters @@ -147,17 +129,15 @@ connecting the peripheral's TileLink node to the MMIO crossbar. } -Note that the PWMTL class we created from the register router is itself a -LazyModule. Register routers have a TileLike node simply named "node", which -we can hook up to the RocketChip peripheryBus. This will automatically add -address map and device tree entries for the peripheral. +Note that the ``PWMTL`` class we created from the register router is itself a ``LazyModule``. +Register routers have a TileLike node simply named "node", which we can hook up to the Rocket Chip bus. +This will automatically add address map and device tree entries for the peripheral. -The module implementation trait is where we instantiate our PWM module and -connect it to the rest of the SoC. Since this module has an extra `pwmout` -output, we declare that in this trait, using Chisel's multi-IO -functionality. We then connect the PWMTL's pwmout to the pwmout we declared. +The module implementation trait is where we instantiate our PWM module and connect it to the rest of the SoC. +Since this module has an extra `pwmout` output, we declare that in this trait, using Chisel's multi-IO functionality. +We then connect the ``PWMTL``'s pwmout to the pwmout we declared. -:: +.. code-block:: scala trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp { implicit val p: Parameters val outer: HasPeripheryPWM @@ -167,11 +147,10 @@ functionality. We then connect the PWMTL's pwmout to the pwmout we declared. pwmout := outer.pwm.module.io.pwmout } +Now we want to mix our traits into the system as a whole. +This code is from ``generators/example/src/main/scala/Top.scala``. -Now we want to mix our traits into the system as a whole. This code is from -src/main/scala/example/Top.scala. - -:: +.. code-block:: scala class ExampleTopWithPWM(q: Parameters) extends ExampleTop(q) with PeripheryPWM { override lazy val module = Module( @@ -182,19 +161,15 @@ src/main/scala/example/Top.scala. extends ExampleTopModule(l) with HasPeripheryPWMModuleImp -Just as we need separate traits for LazyModule and module implementation, we -need two classes to build the system. The ExampleTop classes already have the -basic peripherals included for us, so we will just extend those. +Just as we need separate traits for ``LazyModule`` and module implementation, we need two classes to build the system. +The ``ExampleTop`` classes already have the basic peripherals included for us, so we will just extend those. -The ExampleTop class includes the pre-elaboration code and also a lazy val to -produce the module implementation (hence LazyModule). The ExampleTopModule -class is the actual RTL that gets synthesized. +The ``ExampleTop`` class includes the pre-elaboration code and also a ``lazy val`` to produce the module implementation (hence ``LazyModule``). +The ``ExampleTopModule`` class is the actual RTL that gets synthesized. -Finally, we need to add a configuration class in -src/main/scala/example/Configs.scala that tells the TestHarness to instantiate -ExampleTopWithPWM instead of the default ExampleTop. +Finally, we need to add a configuration class in ``generators/example/src/main/scala/Configs.scala`` that tells the ``TestHarness`` to instantiate ``ExampleTopWithPWM`` instead of the default ``ExampleTop``. -:: +.. code-block:: scala class WithPWM extends Config((site, here, up) => { case BuildTop => (p: Parameters) => Module(LazyModule(new ExampleTopWithPWM()(p)).module) @@ -203,9 +178,9 @@ ExampleTopWithPWM instead of the default ExampleTop. class PWMConfig extends Config(new WithPWM ++ new BaseExampleConfig) -Now we can test that the PWM is working. The test program is in tests/pwm.c +Now we can test that the PWM is working. The test program is in ``tests/pwm.c``. -:: +.. code-block:: c #define PWM_PERIOD 0x2000 #define PWM_DUTY 0x2008 #define PWM_ENABLE 0x2010 @@ -230,29 +205,26 @@ Now we can test that the PWM is working. The test program is in tests/pwm.c } -This just writes out to the registers we defined earlier. The base of the -module's MMIO region is at 0x2000. This will be printed out in the address -map portion when you generated the verilog code. +This just writes out to the registers we defined earlier. +The base of the module's MMIO region is at 0x2000. +This will be printed out in the address map portion when you generated the verilog code. -Compiling this program with make produces a `pwm.riscv` executable. +Compiling this program with make produces a ``pwm.riscv`` executable. Now with all of that done, we can go ahead and run our simulation. -:: +.. code-block:: shell cd verisim make CONFIG=PWMConfig ./simulator-example-PWMConfig ../tests/pwm.riscv - - - Adding a RoCC Accelerator ---------------------------- -RoCC accelerators are lazy modules that extend the LazyRoCC class. -Their implementation should extends the LazyRoCCModule class. +RoCC accelerators are lazy modules that extend the ``LazyRoCC`` class. +Their implementation should extends the ``LazyRoCCModule`` class. -:: +.. code-block:: scala class CustomAccelerator(opcodes: OpcodeSet) (implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new CustomAcceleratorModule(this) @@ -277,34 +249,30 @@ Their implementation should extends the LazyRoCCModule class. } -The ``opcodes`` parameter for ``LazyRoCC`` is -the set of custom opcodes that will map to this accelerator. More on this -in the next subsection. +The ``opcodes`` parameter for ``LazyRoCC`` is the set of custom opcodes that will map to this accelerator. +More on this in the next subsection. The ``LazyRoCC`` class contains two TLOutputNode instances, ``atlNode`` and ``tlNode``. -The former connects into a tile-local arbiter along with the backside of the -L1 instruction cache. The latter connects directly to the L1-L2 crossbar. -The corresponding Tilelink ports in the module implementation's IO bundle -are ``atl`` and ``tl``, respectively. +The former connects into a tile-local arbiter along with the backside of the L1 instruction cache. +The latter connects directly to the L1-L2 crossbar. +The corresponding Tilelink ports in the module implementation's IO bundle are ``atl`` and ``tl``, respectively. -The other interfaces available to the accelerator are ``mem``, which provides -access to the L1 cache; ``ptw`` which provides access to the page-table walker; -the ``busy`` signal, which indicates when the accelerator is still handling an -instruction; and the ``interrupt`` signal, which can be used to interrupt the CPU. +The other interfaces available to the accelerator are ``mem``, which provides access to the L1 cache; +``ptw`` which provides access to the page-table walker; +the ``busy`` signal, which indicates when the accelerator is still handling an instruction; +and the ``interrupt`` signal, which can be used to interrupt the CPU. -Look at the examples in rocket-chip/src/main/scala/tile/LazyRocc.scala for -detailed information on the different IOs. +Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRocc.scala`` for detailed information on the different IOs. -### Adding RoCC accelerator to Config +Adding RoCC accelerator to Config +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -RoCC accelerators can be added to a core by overriding the ``BuildRoCC`` parameter -in the configuration. This takes a sequence of functions producing ``LazyRoCC`` -objects, one for each accelerator you wish to add. +RoCC accelerators can be added to a core by overriding the ``BuildRoCC`` parameter in the configuration. +This takes a sequence of functions producing ``LazyRoCC`` objects, one for each accelerator you wish to add. -For instance, if we wanted to add the previously defined accelerator and -route custom0 and custom1 instructions to it, we could do the following. +For instance, if we wanted to add the previously defined accelerator and route custom0 and custom1 instructions to it, we could do the following. -:: +.. code-block:: scala class WithCustomAccelerator extends Config((site, here, up) => { case BuildRoCC => Seq((p: Parameters) => LazyModule( new CustomAccelerator(OpcodeSet.custom0 | OpcodeSet.custom1)(p))) @@ -313,17 +281,13 @@ route custom0 and custom1 instructions to it, we could do the following. class CustomAcceleratorConfig extends Config( new WithCustomAccelerator ++ new DefaultExampleConfig) - - - Adding a DMA port ------------------- -IO devices or accelerators (like a disk or network -driver), we may want to have the device write directly to the coherent -memory system instead. To add a device like that, you would do the following. +IO devices or accelerators (like a disk or network driver), we may want to have the device write directly to the coherent memory system instead. +To add a device like that, you would do the following. -:: +.. code-block:: scala class DMADevice(implicit p: Parameters) extends LazyModule { val node = TLClientNode(TLClientParameters( name = "dma-device", sourceId = IdRange(0, 1))) @@ -355,8 +319,6 @@ memory system instead. To add a device like that, you would do the following. The ``ExtBundle`` contains the signals we connect off-chip that we get data from. -The DMADevice also has a Tilelink client port that we connect into the L1-L2 -crossbar through the front-side buffer (fsb). The sourceId variable given in -the TLClientNode instantiation determines the range of ids that can be used -in acquire messages from this device. Since we specified [0, 1) as our range, -only the ID 0 can be used. +The DMADevice also has a Tilelink client port that we connect into the L1-L2 crossbar through the front-side buffer (fsb). +The sourceId variable given in the ``TLClientNode`` instantiation determines the range of ids that can be used in acquire messages from this device. +Since we specified [0, 1) as our range, only the ID 0 can be used. diff --git a/docs/Getting-Started/Configs-Parameters-Mixins.rst b/docs/Getting-Started/Configs-Parameters-Mixins.rst index b87a47c1..852f85af 100644 --- a/docs/Getting-Started/Configs-Parameters-Mixins.rst +++ b/docs/Getting-Started/Configs-Parameters-Mixins.rst @@ -1,55 +1,62 @@ Configs, Parameters, Mix-ins, and Everything In Between ======================================================== -A significant portion of generators in the ReBAR framework use the Rocket chip parameter system. +A significant portion of generators in the REBAR framework use the Rocket Chip parameter system. This parameter system enables for the flexible configuration of the SoC without invasive RTL changes. In order to use the parameter system correctly, we will use several terms and conventions: -Parameter +Parameters -------------------- + TODO: Need to explain up, site, field, and other stuff from Henry's thesis. -It is important to note that a significant challenge with the Rocket parameter system is being able to identify the correct parameter to use, and the impact that parameter has on the overall system. We are still investigating methods to facilitate parameter exploration and discovery. +It is important to note that a significant challenge with the Rocket parameter system is being able to identify the correct parameter to use, and the impact that parameter has on the overall system. +We are still investigating methods to facilitate parameter exploration and discovery. - -Config +Configs --------------------- -A `Config` is a collection of multiple parameters being set to specific values. -Configs are additive, and can override each other. -A Config can be composed of other configs. -The naming convetion for an additive config is ``With``, while the naming convention for a non-additive config will be ````. -Configs can take arguments which will in-turn set parameters in the specific configs. -Example config: +A *Config* is a collection of multiple generator parameters being set to specific values. +Configs are additive, can override each other, and can be composed of other Configs. +The naming convention for an additive Config is ``With``, while the naming convention for a non-additive Config will be ````. +Configs can take arguments which will in-turn set parameters in the design or reference other parameters in the design (see :ref:`Parameters`). +:numref:`basic-config-example` shows a basic additive Config class that takes in zero arguments and instead uses hardcoded values to set the RTL design parameters. +In this example, ``MyAcceleratorConfig`` is a Scala case class that defines a set of variables that the generator can use when referencing the ``MyAcceleratorKey`` in the design. + +.. _basic-config-example: .. code-block:: scala class WithMyAcceleratorParams extends Config((site, here, up) => { + case BusWidthBits => 128 case MyAcceleratorKey => MyAcceleratorConfig( - Rows = 2, + rows = 2, rowBits = 64, - Columns = 16, + columns = 16, hartId = 1, - some_length = 256, - ) + someLength = 256) }) -Example config which uses a higher level config: +This next example (:numref:`complex-config-example`) shows a "higher-level" additive Config that uses prior parameters that were set to derive other parameters. +.. _complex-config-example: .. code-block:: scala class WithMyMoreComplexAcceleratorConfig extends Config((site, here, up) => { + case BusWidthBits => 128 case MyAcceleratorKey => MyAcceleratorConfig( Rows = 2, rowBits = site(SystemBusKey).beatBits, - hartId = up(RocketTilesKey, site).length, - ) + hartId = up(RocketTilesKey, site).length) }) -Example of additive configs: +:numref:`top-level-config` shows a non-additive Config that combines the prior two additive Configs using ``++``. +The additive Configs are applied from the right to left in the list (or bottom to top in the example). +Thus, the order of the parameters being set will first start with the ``DefaultExampleConfig``, then ``WithMyAcceleratorParams``, then ``WithMyMoreComplexAcceleratorConfig``. +.. _top-level-config: .. code-block:: scala class SomeAdditiveConfig extends Config( @@ -58,13 +65,15 @@ Example of additive configs: new DefaultExampleConfig ) - Cake Pattern ------------------------- -The cake pattern is a scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes refered to as dependancy injection). It is used in the Rocket chip SoC library and ReBAR framework in merging multiple system components and IO interfaces into a large system component. -Example of using the cake pattern to merge multiple system components into a single top-level design, extending a basic Rocket SoC: +A cake pattern is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection). +It is used in the Rocket Chip SoC library and REBAR framework in merging multiple system components and IO interfaces into a large system component. +:numref:`cake-example` shows a Rocket Chip based SoC that merges multiple system components (BootROM, UART, etc) into a single top-level design. + +.. _cake-example: .. code-block:: scala class MySoC(implicit p: Parameters) extends RocketSubsystem @@ -78,9 +87,14 @@ Example of using the cake pattern to merge multiple system components into a sin //Additional top-level specific instantiations or wiring } - Mix-in --------------------------- -A mix-in is a scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. -The naming convetion for an additive mix-in is ``Has``. +A mix-in is a Scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. +The naming convention for an additive mix-in is ``Has``. +This is show in :numref:`cake-example` where things such as ``HasPeripherySerial`` connect a RTL component to a bus and expose signals to the top-level. + +Additional References +--------------------------- + +A brief explanation of some of these topics is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY. diff --git a/docs/Getting-Started/Development-Ecosystem.rst b/docs/Getting-Started/Development-Ecosystem.rst new file mode 100644 index 00000000..8946a319 --- /dev/null +++ b/docs/Getting-Started/Development-Ecosystem.rst @@ -0,0 +1,25 @@ +Development Ecosystem +=============================== + +REBAR Approach +------------------------------------------- + +The trend towards agile hardware design and evaluation provides an ecosystem of debugging and implementation tools, that make it easier for computer architecture researchers to develop novel concepts. +REBAR hopes to build on this prior work in order to create a singular location to which multiple projects within the `Berkeley Architecture Research `__ can coexist and be used together. +REBAR aims to be the "one-stop shop" for creating and testing your own unique System on a Chip (SoC). + +Chisel/FIRRTL +------------------------------------------- + +One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language `__ and the `FIRRTL Compiler `__. +Chisel is an embedded language within Scala that provides a set of libraries to help hardware designers create highly parameterizable RTL. +FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimation, circuit analysis, connectivity checks, and much more! +These two tools in combination allow quick design space exploration and development of new RTL. + +Generators +------------------------------------------- + +Within this repository, all of the Chisel RTL is written as generators. +Generators are parametrized programs designed to generate RTL code based on configuration specifications. +Generators can be used to generate Systems-on-Chip (SoCs) using a collection of system components organized in unique generator projects. +Generators allow you to create a family of SoC designs instead of a single instance of a design! diff --git a/docs/Getting-Started/REBAR-Basics.rst b/docs/Getting-Started/REBAR-Basics.rst new file mode 100644 index 00000000..69963b3e --- /dev/null +++ b/docs/Getting-Started/REBAR-Basics.rst @@ -0,0 +1,110 @@ +REBAR Basics +=============================== + +Generators +------------------------------------------- + +The REBAR Framework currently consists of the following RTL generators: + +Processor Cores +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +**Rocket** + An in-order RISC-V core. + See :ref:`Rocket` for more information. + +**BOOM (Berkeley Out-of-Order Machine)** + An out-of-order RISC-V core. + See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. + +Data-Parallel Accelerators +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +**Hwacha** + A decoupled vector architecture co-processor. + Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model. + Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface. + See :ref:`Hwacha` for more information. + +System Components: +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +**icenet** + A Network Interface Controller (NIC) designed to achieve up to 200 Gbps. + +**sifive-blocks** + System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator. + These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices. + +**AWL (Analog Widget Library)** + Digital components required for integration with high speed serial links. + +**testchipip** + A collection of utilities used for testing chips and interfacing them with larger test environments. + +.. Fixed Function Accelerators: + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + TBD + +Tools +------------------------------------------- + +**Chisel** + A hardware description library embedded in Scala. + Chisel is used to write RTL generators using meta-programming, by embedding hardware generation primitives in the Scala programming language. + The Chisel compiler elaborates the generator into a FIRRTL output. + See :ref:`Chisel` for more information. + +**FIRRTL** + An intermediate representation library for RTL description of digital designs. + FIRRTL is used as a formalized digital circuit representation between Chisel and Verilog. + FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation. + See :ref:`FIRRTL` for more information. + +**Barstools** + A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL. + See :ref:`Barstools` for more information. + +Toolchains +------------------------------------------- + +**riscv-tools** + A collection of software toolchains used to develop and execute software on the RISC-V ISA. + The include compiler and assembler toolchains, functional ISA simulator (spike), the Berkeley Boot Loader (BBL) and proxy kernel. + The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.). + Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the REBAR framework. + +**esp-tools** + A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension. + This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.) + +Sims +------------------------------------------- + +**verisim (Verilator wrapper)** + Verilator is an open source Verilog simulator. + The ``verisim`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). + See :ref:`Verilator` for more information. + +**vsim (VCS wrapper)** + VCS is a proprietary Verilog simulator. + Assuming the user has valid VCS licenses and installations, the ``vsim`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). + See :ref:`VCS` for more information. + +**FireSim** + FireSim is an open-source FPGA-accelerated simulation platform, using Amazon Web Services (AWS) EC2 F1 instances on the public cloud. + FireSim automatically transforms and instruments open-hardware designs into fast (10s-100s MHz), deterministic, FPGA-based simulators that enable productive pre-silicon verification and performance validation. + To model I/O, FireSim includes synthesizeable and timing-accurate models for standard interfaces like DRAM, Ethernet, UART, and others. + The use of the elastic public cloud enable FireSim to scale simulations up to thousands of nodes. + In order to use FireSim, the repository must be cloned and executed on AWS instances. + See :ref:`FireSim` for more information. + +VLSI +------------------------------------------- + +**HAMMER** + HAMMER is a VLSI flow designed to provide a layer of abstraction between general physical design concepts to vendor-specific EDA tool commands. + The HAMMER flow provide automated scripts which generate relevant tool commands based on a higher level description of physical design constraints. + The HAMMER flow also allows for re-use of process technology knowledge by enabling the construction of process-technology-specific plug-ins, which describe particular constraints relating to that process technology (obsolete standard cells, metal layer routing constraints, etc.). + The HAMMER flow requires access to proprietary EDA tools and process technology libraries. + See :ref:`HAMMER` for more information. diff --git a/docs/Getting-Started/ReBAR-Basics.rst b/docs/Getting-Started/ReBAR-Basics.rst deleted file mode 100644 index eb54033e..00000000 --- a/docs/Getting-Started/ReBAR-Basics.rst +++ /dev/null @@ -1,86 +0,0 @@ - - -ReBAR Basics -=============================== - - -Generators -------------------------------------------- -Generators are parametrized programs written as RTL code, designed to generate verilog code based on configuration specifications. -Generators can be used to generate Systems-on-Chip (SoCs) using a collection of system components organized in unique generator projects. -The ReBAR Framework currently consists of the following generators: - -Processor Cores -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**Rocket** - An in-order RISC-V core. - -**BOOM (Berkeley Out-of-Order Machine)** - An out-of-order RISC-V core. - -Data-Parallel Accelerators -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**Hwacha** - A decoupled vector architecture co-processor. Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model. - Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface - - -System Components: -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**icenet** - A Network Interface Controller (NIC) designed to achieve up to 200 Gbps. - -**sifive-blocks** - System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket chip generator. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices. - -**AWL (Analog Widget Library)** - Digital components required for integration with high speed serial links. - -**testchipip** - A collection of utilites used for testing chips and interfacing them with larger test environments. - - -Fixed Function Accelerators: -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -TBD - - - -Tools -------------------------------------------- -**Chisel** - A hardware description library embedded in Scala. Chisel is used to write RTL generators using meta-programming, by emdedding hardware generation primitives in the Scala programming language. The Chisel compilter elaborate the generator into a FIRRTL output. - -**FIRRTL** - An intermediate representation library for RTL description of digital designs. FIRRTL is used as a formalized digital circuit representation between Chisel and Verilog. FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation. - -**BARSTOOLS** - A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL. - - -Toolchains -------------------------------------------- -**riscv-tools** - A collection of software toolchains used to develope and execute software on the RISC-V ISA. The include compiler and assembler toolchains, functional ISA simulator (spike), the Berkeley Boot Loader (BBL) and proxy kernel. The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.). Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the ReBAR framework. - - -**esp-tools** - A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension. This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.) - - -Sims -------------------------------------------- -**verisim (Verilator wrapper)** - Verilator is an open source Verilog simulator. The verisim directory provides wrappers which construct verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). - -**vsim (VCS wrapper)** - VCS is a proprietary Verilog simulator. Assuming the user has valid VCS licenses and installations, the vsim directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). - -**FireSim** - FireSim is an open-source FPGA-accelerated simulation platform, using Amazon Web Services (AWS) EC2 F1 instances on the public cloud. FireSim automatically transforms and instruments open-hardware designs into fast (10s-100s MHz), deterministic, FPGA-based simulators that enable productive pre-silicon verification and performance validation. To model I/O, FireSim includes synthesizeable and timing-accurate models for standard interfaces like DRAM, Ethernet, UART, and others. The use of the elastic public clound enable FireSim to scale simulations up to thousands of nodes. In order to use FireSim, the repository must be cloned and executed on AWS instances. - - -VLSI -------------------------------------------- -**HAMMER** - HAMMER is a VLSI flow designed to provide a layer of abstraction between general physical design concepts to vendor-specific EDA tool commands. The HAMMER flow provide automated scripts which generate relevant tool commands based on a higher level description of physical desing contraints. The HAMMER flow also allows for re-use of process technology knowledge by enabling the construction of process-technology-specific plug-ins, which describe particular contraints relating to that process technology (obsolete standard cells, metal layer routing contraints, etc.). The HAMMER flow requires access to proprietry EDA tools and process technology libraries. diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index a86eb7e8..e67b3813 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -1,123 +1,103 @@ Running A Simulation ======================================================== -ReBAR provides support and intergration for multiple simulation flows, for various user levels and requirments. -In the majority of cases during a digital design development process, simple software RTL. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. - +REBAR provides support and integration for multiple simulation flows, for various user levels and requirements. +In the majority of cases during a digital design development process, simple software RTL simulation is needed. +When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. Software RTL Simulation ------------------------ -The ReBAR framework provides wrappers for two common software RTL simulators: the open-source Verilator simulator. and the proprietry VCS simulator.The following instructions assume at least one of these simulators is installed. +The REBAR framework provides wrappers for two common software RTL simulators: +the open-source Verilator simulator and the proprietary VCS simulator. +For more information on either of these simulators, please refer to :ref:`Verilator` or :ref:`VCS`. +The following instructions assume at least one of these simulators is installed. -Verilator +Verilator/VCS Flows ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Verilator is an open-source RTL simulator. We run Verilator simulations from within the ``sims/verisim`` directory. Therefore, we will start by entering that directory: +Verilator is an open-source RTL simulator. +We run Verilator simulations from within the ``sims/verisim`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations. +On the other hand, VCS is a proprietary RTL simulator. +We run VCS simulations from within the ``sims/vsim`` directory. +Assuming VCS is already installed on the machine running simulations (and is found on our ``PATH``), then this guide is the same for both Verilator and VCS. + +First, we will start by entering the Verilator or VCS directory: .. code-block:: shell - cd sims/verisim + # Enter Verilator directory + cd sims/verisim -In order to construct the simulator with our custom design, we run the following command within the ``sims/verisim`` directory: + # OR + + # Enter VCS directory + cd sims/vsim + +In order to construct the simulator with our custom design, we run the following command within the simulator directory: .. code-block:: shell - make TOP= CONFIG= SBT_PROJECT= MODEL= + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... -Where ```` is the class name of the top level design, ```` is the name of the class we create for our parameters configuration, ```` is the name of the sbt package the include both our top-level class and our config class, and ```` is the name of the class which defines the test harness for our system. -The ``make`` command may have additional parameters (such as ``CONFIG_PACKAGE`` or ``MODEL_PACKAGE``) depending on the complexity of the design and integration with multiple sub-project repositories in the sbt-based build system. +Each of these make variables correspond to a particular part of the design/codebase and are needed so that the make system can correctly build and make a RTL simulation. +The ``SBT_PROJECT`` is the ``build.sbt`` project that holds all of the source files and that will be run during the RTL build. +The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design. +Normally, these are the same, but in some cases these can differ (if the Chisel class differs than what is emitted in the Verilog). +The ``MODEL_PACKAGE`` is the Scala package (in the Scala code that says ``package ...``) that holds the ``MODEL`` class. +The ``CONFIG`` is the name of the class used for the parameter Config while the ``CONFIG_PACKAGE`` is the Scala package it resides in. +The ``GENERATOR_PACKAGE`` is the Scala package that holds the Generator class that elaborates the design. +The ``TB`` is the name of the Verilog wrapper that connects the ``TestHarness`` to VCS/Verilator for simulation. +Finally, the ``TOP`` variable is used to distinguish between the top-level of the design and the ``TestHarness`` in our system. +For example, in the normal case, the ``MODEL`` variable specifies the ``TestHarness`` as the top-level of the design. +However, the true top-level design, the SoC being simulated, is pointed to by the ``TOP`` variable. +This separation allows the infrastructure to separate files based on the harness or the SoC top level. -Common configurations are package using a ``SUB_PROJECT`` make variable. There, in order to simulate a simple Rocket-based example system we can use: +Common configurations of all these variables are packaged using a ``SUB_PROJECT`` make variable. +Therefore, in order to simulate a simple Rocket-based example system we can use: .. code-block:: shell - make SUB_PROJECT=example + make SUB_PROJECT=example Alternatively, if we would like to simulate a simple BOOM-based example system we can use: .. code-block:: shell - make SUB_PROJECT=exampleboom + make SUB_PROJECT=exampleboom - -Once the simulator has been constructed, we would like to run RISC-V programs on it. In the `sims/verisim` directory, we will find an executable file called `TODO`. We run this executable with out target RISC-V program as a command line argument. For example: +Once the simulator has been constructed, we would like to run RISC-V programs on it. +In the simulation directory, we will find an executable file called ``<...>--``. +We run this executable with our target RISC-V program as a command line argument in one of two ways. +One, we can directly call the simulator binary or use make to run the binary for us with extra simulation flags. +For example: .. code-block:: shell - ./simulator-- my_program_binary + # directly calling the simulation binary + ./<...>-- my_program_binary -Alternatively, we can run a pre-packaged suite of RISC-V assembly tests, by adding the make target run-asm-tests. For example + # using make to do it + make SUB_PROJECT=example BINARY=my_program_binary run-binary + +Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. +For example: .. code-block:: shell - make run-asm-tests TOP= CONFIG= SBT_PROJECT= MODEL= - -or - -.. code-block:: shell - - make run-asm-tests SUB_PROJECT=example - - - -VCS -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -VCS is a proprietry RTL simulator. This guide assumes that the VCS installation is found on our PATH. We run VCS simulations from within the ``sims/vsim`` directory. Therefore, we will start by entering the directory: - -.. code-block:: shell - - cd sims/vsim - - -In order to construct the simulator with our custom design, we run the following command within the ``sims/vsim`` directory: - -.. code-block:: shell - - make TOP= CONFIG= SBT_PROJECT= MODEL= - -Where ```` is the class name of the top level design, ```` is the name of the class we create for our parameters configuration, ```` is the name of the sbt package the include both our top-level class and our config class, and ```` is the name of the class which defines the test harness for our system. -The ``make`` command my have additional parameters (such as ``CONFIG_PACKAGE`` or ``MODEL_PACKAGE``) depending on the complexity of the design and integration with multiple sub-project repositories in the sbt-based build system. - -Common configurations are package using a ``SUB_PROJECT`` make variable. There, in order to simulate a simple Rocket-based example system we can use: - -.. code-block:: shell - - make SUB_PROJECT=example - -Alternatively, if we would like to simulate a simple BOOM-based example system we can use: - -.. code-block:: shell - - make SUB_PROJECT=exampleboom - - -Once the simulator has been constructed, we would like to run RISC-V programs on it. In the ``sims/vsim`` directory, we will find an executable file called ``TODO``. We run this executable with out target RISC-V program as a command line argument. For example: - -.. code-block:: shell - - ./simulator-- my_program_binary - -Alternatively, we can run a pre-packaged suite of RISC-V assembly tests, by adding the make target run-asm-tests. For example - -.. code-block:: shell - - make run-asm-tests TOP= CONFIG= SBT_PROJECT= MODEL= - -or - -.. code-block:: shell - - make run-asm-tests SUB_PROJECT=example - + make SUB_PROJECT=example run-asm-tests + make SUB_PROJECT=example run-bmark-tests +Note: You need to specify all the make variables once again to match what the build gave to run the assembly tests or the benchmarks or the binaries if you are using the make option. FPGA Accelerated Simulation --------------------------- -FireSim enables simulations at 1000x-100000x the speed of standard software simulation. This is enabled using FPGA-acceleration on F1 instances of the AWS (Amazon Web Services) public cloud. There FireSim simulation require to be set-up on the AWS public cloud rather than on our local development machine. +FireSim enables simulations at 1000x-100000x the speed of standard software simulation. +This is enabled using FPGA-acceleration on F1 instances of the AWS (Amazon Web Services) public cloud. +Therefore FireSim simulation requires to be set-up on the AWS public cloud rather than on our local development machine. -To run an FPGA-accelerated simulation using FireSim, a we need to clone the ReBAR repository (or our fork of the ReBAR repository) to an AWS EC2, and follow the setup instructions specificied in the FireSim Initial Setup documentation page. +To run an FPGA-accelerated simulation using FireSim, a we need to clone the REBAR repository (or our fork of the REBAR repository) to an AWS EC2, and follow the setup instructions specificied in the FireSim Initial Setup documentation page. -After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design. We will work from within the ``sims/firesim`` directory. +After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design. +We will work from within the ``sims/firesim`` directory. TODO: Continue from here - + diff --git a/docs/Getting-Started/index.rst b/docs/Getting-Started/index.rst index 5976cea6..41eb0392 100644 --- a/docs/Getting-Started/index.rst +++ b/docs/Getting-Started/index.rst @@ -1,9 +1,7 @@ -.. _Getting Started: - Getting Started ================================ -These guides will walk you through the basics of the ReBAR framework: +These guides will walk you through the basics of the REBAR framework: - First, we will go over the different configurations avaliable. @@ -15,8 +13,8 @@ Hit next to get started! :maxdepth: 2 :caption: Getting Started: - ReBAR-Basics - Configs-Parameters-Mixins + REBAR-Basics + Configs-Parameters-Mixins Adding-An-Accelerator-Tutorial Running-A-Simulation rebar-generator-mixins diff --git a/docs/Getting-Started/rebar-generator-mixins.rst b/docs/Getting-Started/rebar-generator-mixins.rst index e950ffda..7599edc3 100644 --- a/docs/Getting-Started/rebar-generator-mixins.rst +++ b/docs/Getting-Started/rebar-generator-mixins.rst @@ -1,5 +1,3 @@ - - SoC Generator Config Mix-ins: ============================== @@ -88,8 +86,8 @@ SiFive Blocks - HasSPIProtocol - HasSPIEndian - HasSPILength - - HasSPICSMode - - HasPeripherySPIFlash + - HasSPICSMode + - HasPeripherySPIFlash - HasPeripheryUART diff --git a/docs/Makefile b/docs/Makefile index 14ce8965..b3492e6c 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -4,7 +4,7 @@ # You can set these variables from the command line. SPHINXOPTS = SPHINXBUILD = python -msphinx -SPHINXPROJ = ReBAR +SPHINXPROJ = REBAR SOURCEDIR = . BUILDDIR = _build @@ -17,4 +17,4 @@ help: # Catch-all target: route all unknown targets to Sphinx using the new # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). %: Makefile - @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) \ No newline at end of file + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Commercial-Simulators.rst index 27fa5271..1d2f8d35 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/Commercial-Simulators.rst @@ -1,33 +1,37 @@ Commericial Software RTL Simulators ============================== -The ReBAR framework currently supports only the VCS commerical simulator VCS ----------------------- -VCS is a commercial RTL simulator developed by Synopsys. It requires commerical licenses. -The ReBAR framework can compile and execute simulations using VCS. VCS simulation will generally compile -faster than Verilator simulations. + +`VCS `__ is a commercial RTL simulator developed by Synopsys. +It requires commerical licenses. +The REBAR framework can compile and execute simulations using VCS. +VCS simulation will generally compile faster than Verilator simulations. To run a simulation using VCS, perform the following steps: -Make sure that the VCS simulator is on your `PATH`. +Make sure that the VCS simulator is on your ``PATH``. To compile the example design, run make in the ``sims/vsim`` directory. -This will elaborate the DefaultExampleConfig in the example project. +This will elaborate the ``DefaultRocketConfig`` in the example project. -An executable called simulator-example-DefaultExampleConfig will be produced. +An executable called ``simulator-example-DefaultRocketConfig`` will be produced. This executable is a simulator that has been compiled based on the design that was built. -You can then use this executable to run any compatible RV64 code. For instance, -to run one of the riscv-tools assembly tests. +You can then use this executable to run any compatible RV64 code. +For instance, to run one of the riscv-tools assembly tests. -:: - ./simulator-example-DefaultExampleConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple +.. code-block:: shell + ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple -If you later create your own project, you can use environment variables to -build an alternate configuration. +If you later create your own project, you can use environment variables to build an alternate configuration. -:: - make PROJECT=yourproject CONFIG=YourConfig - ./simulator-yourproject-YourConfig ... +.. code-block:: shell + make SUB_PROJECT=yourproject + ./simulator-- ... -If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. This will generate a vpd file (this is a proprietry waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. If you have Synopsys licenses, we recommend using the DVE waveform viewers +If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. +This will generate a vpd file (this is a proprietry waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. +If you have Synopsys licenses, we recommend using the DVE waveform viewer. + +Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running. diff --git a/docs/Simulation/FPGA-Based-Simulators.rst b/docs/Simulation/FPGA-Based-Simulators.rst index 37bc3b16..9ef19d49 100644 --- a/docs/Simulation/FPGA-Based-Simulators.rst +++ b/docs/Simulation/FPGA-Based-Simulators.rst @@ -3,11 +3,15 @@ FPGA-Based Simulators FireSim ----------------------- -FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). -FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. FireSim also provides additional device models to allow full-system simulation, including memory models and network models. -FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. In order to simulate your ReBAR design using FireSim, you should follow the following steps: +`FireSim `__ is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). +FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. +FireSim also provides additional device models to allow full-system simulation, including memory models and network models. -Follow the initial EC2 setup instructions as detailed in the `FireSim documentation `__ .. Then clone your full ReBAR repository onto your Amazon EC2 FireSim manager instance. +FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. +In order to simulate your REBAR design using FireSim, you should follow the following steps: + +Follow the initial EC2 setup instructions as detailed in the `FireSim documentation `__. +Then clone your full REBAR repository onto your Amazon EC2 FireSim manager instance. Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for `running a simulation `__. diff --git a/docs/Simulation/Open-Source-Simulators.rst b/docs/Simulation/Open-Source-Simulators.rst index 87edc5ef..53ca3a43 100644 --- a/docs/Simulation/Open-Source-Simulators.rst +++ b/docs/Simulation/Open-Source-Simulators.rst @@ -3,31 +3,31 @@ Open Source Software RTL Simulators Verilator ----------------------- -Verilator is an open-source LGPL-Licensed simulator maintained by `Veripool `__ -The ReBAR framework can download, build, and execute simulations using Verilator. -To run a simulation using verilator, perform the following steps: +`Verilator `__ is an open-source LGPL-Licensed simulator maintained by `Veripool `__. +The REBAR framework can download, build, and execute simulations using Verilator. -To compile the example design, run make in the ``sims/verisim`` directory. -This will elaborate the DefaultExampleConfig in the example project. +To run a simulation using Verilator, perform the following steps: -An executable called simulator-example-DefaultExampleConfig will be produced. +To compile the example design, run ``make`` in the ``sims/verisim`` directory. +This will elaborate the ``DefaultRocketConfig`` in the example project. + +An executable called ``simulator-example-DefaultRocketConfig`` will be produced. This executable is a simulator that has been compiled based on the design that was built. -You can then use this executable to run any compatible RV64 code. For instance, -to run one of the riscv-tools assembly tests. +You can then use this executable to run any compatible RV64 code. +For instance, to run one of the riscv-tools assembly tests. -:: - ./simulator-example-DefaultExampleConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple +.. code-block:: shell + ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple -If you later create your own project, you can use environment variables to -build an alternate configuration. - -:: - make PROJECT=yourproject CONFIG=YourConfig - ./simulator-yourproject-YourConfig ... - - -If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. An open-source vcd-capable waveform viewer is `GTKWave __ +If you later create your own project, you can use environment variables to build an alternate configuration. +.. code-block:: shell + make SUB_PROJECT=yourproject + ./simulator-- ... +If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. +This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. +An open-source vcd-capable waveform viewer is `GTKWave `__. +Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index c5ee90a5..41752cf0 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,8 +1,10 @@ Simulators ======================= -ReBAR provides support and intergration for multiple simulation flows, for various user levels and requirments. -In the majority of cases during a digital design development process, simple software RTL. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. The following pages provide detailed information about the simulation possibilities within the ReBAR framework. +REBAR provides support and intergration for multiple simulation flows, for various user levels and requirments. +In the majority of cases during a digital design development process, a simple software RTL simulation will do. +When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. +The following pages provide detailed information about the simulation possibilities within the REBAR framework. .. toctree:: :maxdepth: 2 diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index 137d95a7..4f8e2ff1 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -1,3 +1,5 @@ Barstools =============================== -Barstools is a collection of useful FIRRTL transformations + +Barstools is a collection of useful FIRRTL transformations and Compilers to help the build process. +Included in the tools are a MacroCompiler (used to map Chisel memory constructs to vendor SRAMs), FIRRTL transforms (to separate harness and top-level SoC files), and more. diff --git a/docs/Tools/Chisel.rst b/docs/Tools/Chisel.rst index 1b0c37ce..3c8293a5 100644 --- a/docs/Tools/Chisel.rst +++ b/docs/Tools/Chisel.rst @@ -1,3 +1,19 @@ Chisel =========================== -TODO: Chisel intro and pointer to chisel bootcamp + +`Chisel `__ is an open-source hardware description language embedded in Scala. +It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM. + +After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog. +First is the compilation step. +If Chisel is thought as a library within Scala, then these classes being built are just Scala classes which call Chisel functions. +Thus, any errors that you get in compiling the Scala/Chisel files are errors that you have violated the typing system, messed up syntax, or more. +After the compilation is complete, elaboration begins. +The Chisel generator starts elaboration using the module and configuration classes passed to it. +This is where the Chisel "library functions" are called with the parameters given and Chisel tries to construct a circuit based on the Chisel code. +If a runtime error happens here, Chisel is stating that it cannot "build" your circuit due to "violations" between your code and the Chisel "library". +However, if that passes, the output of the generator gives you an FIRRTL file and other misc collateral! +See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog. + +For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp `__. +Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <>`__. diff --git a/docs/Tools/FIRRTL.rst b/docs/Tools/FIRRTL.rst index ab5df854..23f39f16 100644 --- a/docs/Tools/FIRRTL.rst +++ b/docs/Tools/FIRRTL.rst @@ -1,3 +1,12 @@ FIRRTL ================================ +`FIRRTL `__ is an intermediate representation of your circuit. +It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog. +Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations. +An example of a FIRRTL pass (transformation) is one that optimizes out unused signals. +Once the transformations are done, a Verilog file is emitted and the build process is done. + +For more information on please visit their `website `__. + + diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index 6b3ad2da..37e0d76e 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -1,7 +1,8 @@ Tools ============================== -The ReBAR framework relays heavily on a set of scala-based tools. While the framework attempts to hide the complexities of these tools, the following pages will introduce them, and how we can use them in order to generate flexible designs +The REBAR framework relays heavily on a set of Scala-based tools. +The following pages will introduce them, and how we can use them in order to generate flexible designs. .. toctree:: :maxdepth: 2 diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst new file mode 100644 index 00000000..a206fe93 --- /dev/null +++ b/docs/VLSI/HAMMER.rst @@ -0,0 +1,7 @@ +HAMMER +================================ + +`HAMMER `__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs. +HAMMER allows for reusability in ASIC design while still providing the designers leeway to make their own modifications. + +For more information, read the `HAMMER paper `__ and see the `GitHub repository `__. diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 5f680b4d..448fadd7 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -1,8 +1,11 @@ VLSI Production ================================ -The ReBAR framework aim to provide wrappers to a general VLSI flow. + +The REBAR framework aim to provide wrappers to a general VLSI flow. In particular, we aim to support the HAMMER flow. .. toctree:: :maxdepth: 2 :caption: VLSI Production: + + HAMMER diff --git a/docs/conf.py b/docs/conf.py index bdddec6c..6afa68ba 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# ReBAR documentation build configuration file, created by +# REBAR documentation build configuration file, created by # sphinx-quickstart on Fri Mar 8 11:46:38 2019. # # This file is execfile()d with the current directory set to its @@ -51,7 +51,7 @@ source_suffix = '.rst' master_doc = 'index' # General information about the project. -project = u'ReBAR' +project = u'REBAR' copyright = u'2019, Berkeley Architecture Research' author = u'Berkeley Architecture Research' @@ -124,7 +124,7 @@ html_sidebars = { # -- Options for HTMLHelp output ------------------------------------------ # Output file base name for HTML help builder. -htmlhelp_basename = 'ReBARdoc' +htmlhelp_basename = 'REBARdoc' # -- Options for LaTeX output --------------------------------------------- @@ -151,7 +151,7 @@ latex_elements = { # (source start file, target name, title, # author, documentclass [howto, manual, or own class]). latex_documents = [ - (master_doc, 'ReBAR.tex', u'ReBAR Documentation', + (master_doc, 'REBAR.tex', u'REBAR Documentation', u'Berkeley Architecture Research', 'manual'), ] @@ -161,7 +161,7 @@ latex_documents = [ # One entry per manual page. List of tuples # (source start file, name, description, authors, manual section). man_pages = [ - (master_doc, 'rebar', u'ReBAR Documentation', + (master_doc, 'rebar', u'REBAR Documentation', [author], 1) ] @@ -172,8 +172,8 @@ man_pages = [ # (source start file, target name, title, author, # dir menu entry, description, category) texinfo_documents = [ - (master_doc, 'ReBAR', u'ReBAR Documentation', - author, 'ReBAR', 'One line description of project.', + (master_doc, 'REBAR', u'REBAR Documentation', + author, 'REBAR', 'One line description of project.', 'Miscellaneous'), ] diff --git a/docs/index.rst b/docs/index.rst index a696f691..73b92ad4 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,47 +1,18 @@ -.. ReBAR documentation master file, created by +.. REBAR documentation master file, created by sphinx-quickstart on Fri Mar 8 11:46:38 2019. You can adapt this file completely to your liking, but it should at least contain the root `toctree` directive. -Welcome to ReBAR's documentation! +Welcome to REBAR's documentation! ================================= -ReBAR is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. New to ReBAR? Jump to the :ref:`rebar-basics` page for more info. - - -The documentation outline should look like this - - Getting Started: - - ReBAR-Basics - Initial-Setup/index - Creating-Configuration-Tutorial/index - Adding-An-Accelerator-Tutorial/index - Running-Simulations-Tutorial/index - Building-Chips-Tutorial/index - - Generators: - - Generators/Rocketchip/index - Generators/BOOM/index - Generators/Hwacha/index - - - Simulation: - Simulation/Open-Source-Simulators/index - Simulation/Commercial-Simulators/index - Simulation/FPGA-Based-Simulation/index - - - - Production: - - Production/VLSI-Physical-Design/index - Software/Toolchains/index +REBAR is a a framework for designing and evaluating full-system hardware using agile teams. +It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. +New to REBAR? Jump to the :ref:`Getting Starting` page for more info. .. toctree:: :maxdepth: 3 - :caption: Getting Started: + :caption: Contents: :numbered: Getting-Started/index From 0f34247378185ff1dd83b5c731df4e1b3c76075a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 15:51:25 -0700 Subject: [PATCH 111/120] add section on where to find verilog --- docs/Getting-Started/Running-A-Simulation.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index e67b3813..899d1d41 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -88,6 +88,9 @@ For example: Note: You need to specify all the make variables once again to match what the build gave to run the assembly tests or the benchmarks or the binaries if you are using the make option. +Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. +Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. + FPGA Accelerated Simulation --------------------------- FireSim enables simulations at 1000x-100000x the speed of standard software simulation. From 3b14ac8706d6a0abe776123e612afb40f7b0558f Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 27 May 2019 17:11:10 -0700 Subject: [PATCH 112/120] minor fixes to links | misc cleanup --- docs/Generators/BOOM.rst | 2 +- .../Adding-An-Accelerator-Tutorial.rst | 20 +++++++++++++++++-- docs/Simulation/Commercial-Simulators.rst | 2 ++ docs/Simulation/Open-Source-Simulators.rst | 2 ++ docs/Tools/Chisel.rst | 2 +- docs/conf.py | 3 ++- docs/index.rst | 2 +- 7 files changed, 27 insertions(+), 6 deletions(-) diff --git a/docs/Generators/BOOM.rst b/docs/Generators/BOOM.rst index e04bed8f..caa7807e 100644 --- a/docs/Generators/BOOM.rst +++ b/docs/Generators/BOOM.rst @@ -8,4 +8,4 @@ Like the R10k and the 21264, BOOM is a unified physical register file design (al Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). -Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages __`. +Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages `__. diff --git a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst index 6b4c58c5..17d8c51a 100644 --- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst +++ b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst @@ -14,7 +14,8 @@ In contrast, the processor communicates with a RoCC accelerators through a custo Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU. RoCC coprocessor instructions have the following form. -.. code-block:: +.. code-block:: none + customX rd, rs1, rs2, funct The X will be a number 0-3, and determines the opcode of the instruction, which controls which accelerator an instruction will be routed to. @@ -29,7 +30,8 @@ Integrating into the Generator Build System While developing, you want to include Chisel code in a submodule so that it can be shared by different projects. To add a submodule to the REBAR framework, make sure that your project is organized as follows. -.. code-block:: +.. code-block:: none + yourproject/ build.sbt src/main/scala/ @@ -39,12 +41,14 @@ Put this in a git repository and make it accessible. Then add it as a submodule to under the following directory hierarchy: ``generators/yourproject``. .. code-block:: shell + cd generators/ git submodule add https://git-repository.com/yourproject.git Then add ``yourproject`` to the REBAR top-level build.sbt file. .. code-block:: scala + lazy val yourproject = project.settings(commonSettings).dependsOn(rocketchip) You can then import the classes defined in the submodule in a new project if @@ -52,6 +56,7 @@ you add it as a dependency. For instance, if you want to use this code in the ``example`` project, change the final line in build.sbt to the following. .. code-block:: scala + lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the REBAR top level. @@ -64,6 +69,7 @@ The easiest way to create a TileLink peripheral is to use the ``TLRegisterRouter To create a RegisterRouter-based peripheral, you will need to specify a parameter case class for the configuration settings, a bundle trait with the extra top-level ports, and a module implementation containing the actual RTL. .. code-block:: scala + case class PWMParams(address: BigInt, beatBytes: Int) trait PWMTLBundle extends Bundle { @@ -98,6 +104,7 @@ The second set of arguments is the IO bundle constructor, which we create by ext The final set of arguments is the module constructor, which we create by extends ``TLRegModule`` with our module trait. .. code-block:: scala + class PWMTL(c: PWMParams)(implicit p: Parameters) extends TLRegisterRouter( c.address, "pwm", Seq("ucbbar,pwm"), @@ -116,6 +123,7 @@ The ``LazyModule`` trait runs setup code that must execute before all the hardwa For a simple memory-mapped peripheral, this just involves connecting the peripheral's TileLink node to the MMIO crossbar. .. code-block:: scala + trait HasPeripheryPWM extends HasSystemNetworks { implicit val p: Parameters @@ -138,6 +146,7 @@ Since this module has an extra `pwmout` output, we declare that in this trait, u We then connect the ``PWMTL``'s pwmout to the pwmout we declared. .. code-block:: scala + trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp { implicit val p: Parameters val outer: HasPeripheryPWM @@ -151,6 +160,7 @@ Now we want to mix our traits into the system as a whole. This code is from ``generators/example/src/main/scala/Top.scala``. .. code-block:: scala + class ExampleTopWithPWM(q: Parameters) extends ExampleTop(q) with PeripheryPWM { override lazy val module = Module( @@ -170,6 +180,7 @@ The ``ExampleTopModule`` class is the actual RTL that gets synthesized. Finally, we need to add a configuration class in ``generators/example/src/main/scala/Configs.scala`` that tells the ``TestHarness`` to instantiate ``ExampleTopWithPWM`` instead of the default ``ExampleTop``. .. code-block:: scala + class WithPWM extends Config((site, here, up) => { case BuildTop => (p: Parameters) => Module(LazyModule(new ExampleTopWithPWM()(p)).module) @@ -181,6 +192,7 @@ Finally, we need to add a configuration class in ``generators/example/src/main/s Now we can test that the PWM is working. The test program is in ``tests/pwm.c``. .. code-block:: c + #define PWM_PERIOD 0x2000 #define PWM_DUTY 0x2008 #define PWM_ENABLE 0x2010 @@ -214,6 +226,7 @@ Compiling this program with make produces a ``pwm.riscv`` executable. Now with all of that done, we can go ahead and run our simulation. .. code-block:: shell + cd verisim make CONFIG=PWMConfig ./simulator-example-PWMConfig ../tests/pwm.riscv @@ -225,6 +238,7 @@ RoCC accelerators are lazy modules that extend the ``LazyRoCC`` class. Their implementation should extends the ``LazyRoCCModule`` class. .. code-block:: scala + class CustomAccelerator(opcodes: OpcodeSet) (implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new CustomAcceleratorModule(this) @@ -273,6 +287,7 @@ This takes a sequence of functions producing ``LazyRoCC`` objects, one for each For instance, if we wanted to add the previously defined accelerator and route custom0 and custom1 instructions to it, we could do the following. .. code-block:: scala + class WithCustomAccelerator extends Config((site, here, up) => { case BuildRoCC => Seq((p: Parameters) => LazyModule( new CustomAccelerator(OpcodeSet.custom0 | OpcodeSet.custom1)(p))) @@ -288,6 +303,7 @@ IO devices or accelerators (like a disk or network driver), we may want to have To add a device like that, you would do the following. .. code-block:: scala + class DMADevice(implicit p: Parameters) extends LazyModule { val node = TLClientNode(TLClientParameters( name = "dma-device", sourceId = IdRange(0, 1))) diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Commercial-Simulators.rst index 1d2f8d35..36c3ef3b 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/Commercial-Simulators.rst @@ -22,11 +22,13 @@ You can then use this executable to run any compatible RV64 code. For instance, to run one of the riscv-tools assembly tests. .. code-block:: shell + ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple If you later create your own project, you can use environment variables to build an alternate configuration. .. code-block:: shell + make SUB_PROJECT=yourproject ./simulator-- ... diff --git a/docs/Simulation/Open-Source-Simulators.rst b/docs/Simulation/Open-Source-Simulators.rst index 53ca3a43..11d8d696 100644 --- a/docs/Simulation/Open-Source-Simulators.rst +++ b/docs/Simulation/Open-Source-Simulators.rst @@ -18,11 +18,13 @@ You can then use this executable to run any compatible RV64 code. For instance, to run one of the riscv-tools assembly tests. .. code-block:: shell + ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple If you later create your own project, you can use environment variables to build an alternate configuration. .. code-block:: shell + make SUB_PROJECT=yourproject ./simulator-- ... diff --git a/docs/Tools/Chisel.rst b/docs/Tools/Chisel.rst index 3c8293a5..947f9666 100644 --- a/docs/Tools/Chisel.rst +++ b/docs/Tools/Chisel.rst @@ -16,4 +16,4 @@ However, if that passes, the output of the generator gives you an FIRRTL file an See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog. For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp `__. -Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <>`__. +Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website `__. diff --git a/docs/conf.py b/docs/conf.py index 6afa68ba..9b7bbe43 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -36,7 +36,8 @@ extensions = ['sphinx.ext.autodoc', 'sphinx.ext.mathjax', 'sphinx.ext.ifconfig', 'sphinx.ext.viewcode', - 'sphinx.ext.githubpages'] + 'sphinx.ext.githubpages', + 'sphinx.ext.autosectionlabel'] # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] diff --git a/docs/index.rst b/docs/index.rst index 73b92ad4..68598e7a 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -8,7 +8,7 @@ Welcome to REBAR's documentation! REBAR is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. -New to REBAR? Jump to the :ref:`Getting Starting` page for more info. +New to REBAR? Jump to the :ref:`Getting Started` page for more info. .. toctree:: :maxdepth: 3 From ee62fa8bac1814c41d1d5481ba400d97e908f1c7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 17:21:19 -0700 Subject: [PATCH 113/120] renamed classes to BoomRocket to clarify | clearer comments | readd the bmark timeout --- .../example/src/main/scala/ConfigMixins.scala | 50 ++++++------- .../example/src/main/scala/Configs.scala | 70 +++++++++---------- .../example/src/main/scala/TestHarness.scala | 8 +-- generators/example/src/main/scala/Top.scala | 34 ++++----- variables.mk | 5 +- 5 files changed, 84 insertions(+), 83 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index dbfc1c34..f5e56411 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -42,62 +42,62 @@ class WithGPIO extends Config((site, here, up) => { }) // ----------------------------------------------- -// BOOM + Rocket Top Level System Parameter Mixins +// BOOM and/or Rocket Top Level System Parameter Mixins // ----------------------------------------------- /** - * Class to specify a "plain" top level BOOM + Rocket system + * Class to specify a "plain" top level BOOM and/or Rocket system */ -class WithNormalBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomAndRocketTop()(p)).module) +class WithNormalBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomRocketTop()(p)).module) } }) /** - * Class to specify a top level BOOM + Rocket system with PWM + * Class to specify a top level BOOM and/or Rocket system with PWM */ -class WithPWMBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomAndRocketTopWithPWMTL()(p)).module) +class WithPWMBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomRocketTopWithPWMTL()(p)).module) }) /** - * Class to specify a top level BOOM + Rocket system with a PWM AXI4 + * Class to specify a top level BOOM and/or Rocket system with a PWM AXI4 */ -class WithPWMAXI4BoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomAndRocketTopWithPWMAXI4()(p)).module) +class WithPWMAXI4BoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomRocketTopWithPWMAXI4()(p)).module) }) /** - * Class to specify a top level BOOM + Rocket system with a block device + * Class to specify a top level BOOM and/or Rocket system with a block device */ -class WithBlockDeviceModelBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) +class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module) top.connectBlockDeviceModel() top } }) /** - * Class to specify a top level BOOM + Rocket system with a simulator block device + * Class to specify a top level BOOM and/or Rocket system with a simulator block device */ -class WithSimBlockDeviceBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) +class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module) top.connectSimBlockDevice(clock, reset) top } }) /** - * Class to specify a top level BOOM + Rocket system with GPIO + * Class to specify a top level BOOM and/or Rocket system with GPIO */ -class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomAndRocketTopWithGPIO()(p)).module) +class WithGPIOBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomRocketTopWithGPIO()(p)).module) for (gpio <- top.gpio) { for (pin <- gpio.pins) { pin.i.ival := false.B diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 98a37bc7..114d8baa 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -16,7 +16,7 @@ class BaseRocketConfig extends Config( new freechips.rocketchip.system.DefaultConfig) class DefaultRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new BaseRocketConfig) class HwachaConfig extends Config( @@ -28,26 +28,26 @@ class RoccRocketConfig extends Config( new DefaultRocketConfig) class PWMRocketConfig extends Config( - new WithPWMBoomAndRocketTop ++ + new WithPWMBoomRocketTop ++ new BaseRocketConfig) class PWMAXI4RocketConfig extends Config( - new WithPWMAXI4BoomAndRocketTop ++ + new WithPWMAXI4BoomRocketTop ++ new BaseRocketConfig) class SimBlockDeviceRocketConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomAndRocketTop ++ + new WithSimBlockDeviceBoomRocketTop ++ new BaseRocketConfig) class BlockDeviceModelRocketConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomAndRocketTop ++ + new WithBlockDeviceModelBoomRocketTop ++ new BaseRocketConfig) class GPIORocketConfig extends Config( new WithGPIO ++ - new WithGPIOBoomAndRocketTop ++ + new WithGPIOBoomRocketTop ++ new BaseRocketConfig) class DualCoreRocketConfig extends Config( @@ -75,11 +75,11 @@ class SmallBaseBoomConfig extends Config( new boom.system.SmallBoomConfig) class DefaultBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new BaseBoomConfig) class SmallDefaultBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new SmallBaseBoomConfig) class HwachaBoomConfig extends Config( @@ -91,26 +91,26 @@ class RoccBoomConfig extends Config( new DefaultBoomConfig) class PWMBoomConfig extends Config( - new WithPWMBoomAndRocketTop ++ + new WithPWMBoomRocketTop ++ new BaseBoomConfig) class PWMAXI4BoomConfig extends Config( - new WithPWMAXI4BoomAndRocketTop ++ + new WithPWMAXI4BoomRocketTop ++ new BaseBoomConfig) class SimBlockDeviceBoomConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomAndRocketTop ++ + new WithSimBlockDeviceBoomRocketTop ++ new BaseBoomConfig) class BlockDeviceModelBoomConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomAndRocketTop ++ + new WithBlockDeviceModelBoomRocketTop ++ new BaseBoomConfig) class GPIOBoomConfig extends Config( new WithGPIO ++ - new WithGPIOBoomAndRocketTop ++ + new WithGPIOBoomRocketTop ++ new BaseBoomConfig) /** @@ -118,7 +118,7 @@ class GPIOBoomConfig extends Config( * the `WithNBoomCores` with the DefaultBoomConfig params */ class DualCoreBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ @@ -127,7 +127,7 @@ class DualCoreBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreSmallBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ @@ -137,12 +137,12 @@ class DualCoreSmallBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class RV32UnifiedBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) // --------------------- -// BOOM + Rocket Configs +// BOOM and Rocket Configs // --------------------- class BaseBoomAndRocketConfig extends Config( @@ -167,46 +167,46 @@ class SmallBaseBoomAndRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DefaultBoomAndRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithNormalBoomRocketTop ++ + new BaseBoomRocketConfig) class SmallDefaultBoomAndRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ - new SmallBaseBoomAndRocketConfig) + new WithNormalBoomRocketTop ++ + new SmallBaseBoomRocketConfig) class HwachaBoomAndRocketConfig extends Config( new hwacha.DefaultHwachaConfig ++ - new DefaultBoomAndRocketConfig) + new DefaultBoomRocketConfig) class RoccBoomAndRocketConfig extends Config( new WithRoccExample ++ - new DefaultBoomAndRocketConfig) + new DefaultBoomRocketConfig) class PWMBoomAndRocketConfig extends Config( - new WithPWMBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithPWMBoomRocketTop ++ + new BaseBoomRocketConfig) class PWMAXI4BoomAndRocketConfig extends Config( - new WithPWMAXI4BoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithPWMAXI4BoomRocketTop ++ + new BaseBoomRocketConfig) class SimBlockDeviceBoomAndRocketConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithSimBlockDeviceBoomRocketTop ++ + new BaseBoomRocketConfig) class BlockDeviceModelBoomAndRocketConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithBlockDeviceModelBoomRocketTop ++ + new BaseBoomRocketConfig) class GPIOBoomAndRocketConfig extends Config( new WithGPIO ++ - new WithGPIOBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithGPIOBoomRocketTop ++ + new BaseBoomRocketConfig) class DualCoreBoomAndOneRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ @@ -217,7 +217,7 @@ class DualCoreBoomAndOneRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) class RV32BoomAndRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index 7bad5cbc..c59a081e 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -10,12 +10,12 @@ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp // -------------------------- -// BOOM + Rocket Test Harness +// BOOM and/or Rocket Test Harness // -------------------------- -case object BuildBoomAndRocketTop extends Field[(Clock, Bool, Parameters) => BoomAndRocketTopModule[BoomAndRocketTop]] +case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]] -class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module { +class BoomRocketTestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) @@ -23,7 +23,7 @@ class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module { // force Chisel to rename module override def desiredName = "TestHarness" - val dut = p(BuildBoomAndRocketTop)(clock, reset.toBool, p) + val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p) dut.debug := DontCare dut.connectSimAXIMem() dut.connectSimAXIMMIO() diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index ddd4a20f..5ee73906 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -13,57 +13,57 @@ import testchipip._ import sifive.blocks.devices.gpio._ // ------------------------------- -// BOOM + Rocket Top Level Systems +// BOOM and/or Rocket Top Level Systems // ------------------------------- -class BoomAndRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem +class BoomRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem with HasNoDebug with HasPeripherySerial { - override lazy val module = new BoomAndRocketTopModule(this) + override lazy val module = new BoomRocketTopModule(this) } -class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) +class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) with HasNoDebugModuleImp with HasPeripherySerialModuleImp with DontTouch //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithPWMTL(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithPWMTL(implicit p: Parameters) extends BoomRocketTop with HasPeripheryPWMTL { - override lazy val module = new BoomAndRocketTopWithPWMTLModule(this) + override lazy val module = new BoomRocketTopWithPWMTLModule(this) } -class BoomAndRocketTopWithPWMTLModule(l: BoomAndRocketTopWithPWMTL) extends BoomAndRocketTopModule(l) +class BoomRocketTopWithPWMTLModule(l: BoomRocketTopWithPWMTL) extends BoomRocketTopModule(l) with HasPeripheryPWMTLModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomRocketTop with HasPeripheryPWMAXI4 { - override lazy val module = new BoomAndRocketTopWithPWMAXI4Module(this) + override lazy val module = new BoomRocketTopWithPWMAXI4Module(this) } -class BoomAndRocketTopWithPWMAXI4Module(l: BoomAndRocketTopWithPWMAXI4) extends BoomAndRocketTopModule(l) +class BoomRocketTopWithPWMAXI4Module(l: BoomRocketTopWithPWMAXI4) extends BoomRocketTopModule(l) with HasPeripheryPWMAXI4ModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithBlockDevice(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithBlockDevice(implicit p: Parameters) extends BoomRocketTop with HasPeripheryBlockDevice { - override lazy val module = new BoomAndRocketTopWithBlockDeviceModule(this) + override lazy val module = new BoomRocketTopWithBlockDeviceModule(this) } -class BoomAndRocketTopWithBlockDeviceModule(l: BoomAndRocketTopWithBlockDevice) extends BoomAndRocketTopModule(l) +class BoomRocketTopWithBlockDeviceModule(l: BoomRocketTopWithBlockDevice) extends BoomRocketTopModule(l) with HasPeripheryBlockDeviceModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithGPIO(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop with HasPeripheryGPIO { - override lazy val module = new BoomAndRocketTopWithGPIOModule(this) + override lazy val module = new BoomRocketTopWithGPIOModule(this) } -class BoomAndRocketTopWithGPIOModule(l: BoomAndRocketTopWithGPIO) - extends BoomAndRocketTopModule(l) +class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO) + extends BoomRocketTopModule(l) with HasPeripheryGPIOModuleImp diff --git a/variables.mk b/variables.mk index f73d7f7a..7545e9a3 100644 --- a/variables.mk +++ b/variables.mk @@ -29,14 +29,14 @@ SUB_PROJECT ?= example ifeq ($(SUB_PROJECT),example) SBT_PROJECT ?= example - MODEL ?= BoomAndRocketTestHarness + MODEL ?= BoomRocketTestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultRocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= BoomAndRocketTop + TOP ?= BoomRocketTop endif # for BOOM developers ifeq ($(SUB_PROJECT),boom) @@ -162,3 +162,4 @@ sim_vsrcs = \ # assembly/benchmark variables ######################################################################################### timeout_cycles = 10000000 +bmark_timeout_cycles = 100000000 From d51ab9cde6d47c79cf7ceb9e9098524404dca58b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 17:26:44 -0700 Subject: [PATCH 114/120] only change default SIM_FLAGS | revert .run and .out flags --- common.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index 3d67cebd..f7e46608 100644 --- a/common.mk +++ b/common.mk @@ -86,10 +86,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< && touch $@ + $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ ######################################################################################### # include build/project specific makefrags made from the generator From c160f597b78858ef995900d07f784ca7d09edbc2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 19:07:55 -0700 Subject: [PATCH 115/120] spelling check | better heading for accelerators --- docs/Generators/BOOM.rst | 2 +- docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst | 4 ++-- docs/Getting-Started/Development-Ecosystem.rst | 2 +- docs/Getting-Started/REBAR-Basics.rst | 2 +- docs/Getting-Started/Running-A-Simulation.rst | 2 +- docs/Getting-Started/index.rst | 2 +- docs/Simulation/Commercial-Simulators.rst | 6 +++--- docs/Simulation/index.rst | 2 +- 8 files changed, 11 insertions(+), 11 deletions(-) diff --git a/docs/Generators/BOOM.rst b/docs/Generators/BOOM.rst index caa7807e..6dcdb41f 100644 --- a/docs/Generators/BOOM.rst +++ b/docs/Generators/BOOM.rst @@ -3,7 +3,7 @@ Berkeley Out-of-Order Machine (BOOM) The `Berkeley Out-of-Order Machine (BOOM) `__ is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. It serves as a drop-in replacement to the Rocket core given by Rocket Chip. -BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 outoforder processors. +BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 out-of-order processors. Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”). Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). diff --git a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst index 17d8c51a..bad5ceef 100644 --- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst +++ b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst @@ -22,7 +22,7 @@ The X will be a number 0-3, and determines the opcode of the instruction, which The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination register and two source registers. The ``funct`` field is a 7-bit integer that the accelerator can use to distinguish different instructions from each other. -Note that communication through a RoCC interface requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with approriate driver support. +Note that communication through a RoCC interface requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with appropriate driver support. Integrating into the Generator Build System ------------------------------------------- @@ -138,7 +138,7 @@ For a simple memory-mapped peripheral, this just involves connecting the periphe Note that the ``PWMTL`` class we created from the register router is itself a ``LazyModule``. -Register routers have a TileLike node simply named "node", which we can hook up to the Rocket Chip bus. +Register routers have a TileLink node simply named "node", which we can hook up to the Rocket Chip bus. This will automatically add address map and device tree entries for the peripheral. The module implementation trait is where we instantiate our PWM module and connect it to the rest of the SoC. diff --git a/docs/Getting-Started/Development-Ecosystem.rst b/docs/Getting-Started/Development-Ecosystem.rst index 8946a319..fa407194 100644 --- a/docs/Getting-Started/Development-Ecosystem.rst +++ b/docs/Getting-Started/Development-Ecosystem.rst @@ -13,7 +13,7 @@ Chisel/FIRRTL One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language `__ and the `FIRRTL Compiler `__. Chisel is an embedded language within Scala that provides a set of libraries to help hardware designers create highly parameterizable RTL. -FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimation, circuit analysis, connectivity checks, and much more! +FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more! These two tools in combination allow quick design space exploration and development of new RTL. Generators diff --git a/docs/Getting-Started/REBAR-Basics.rst b/docs/Getting-Started/REBAR-Basics.rst index 69963b3e..5dcac5d7 100644 --- a/docs/Getting-Started/REBAR-Basics.rst +++ b/docs/Getting-Started/REBAR-Basics.rst @@ -17,7 +17,7 @@ Processor Cores An out-of-order RISC-V core. See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. -Data-Parallel Accelerators +Accelerators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ **Hwacha** diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index 899d1d41..673bf0ae 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -97,7 +97,7 @@ FireSim enables simulations at 1000x-100000x the speed of standard software simu This is enabled using FPGA-acceleration on F1 instances of the AWS (Amazon Web Services) public cloud. Therefore FireSim simulation requires to be set-up on the AWS public cloud rather than on our local development machine. -To run an FPGA-accelerated simulation using FireSim, a we need to clone the REBAR repository (or our fork of the REBAR repository) to an AWS EC2, and follow the setup instructions specificied in the FireSim Initial Setup documentation page. +To run an FPGA-accelerated simulation using FireSim, a we need to clone the REBAR repository (or our fork of the REBAR repository) to an AWS EC2, and follow the setup instructions specified in the FireSim Initial Setup documentation page. After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design. We will work from within the ``sims/firesim`` directory. diff --git a/docs/Getting-Started/index.rst b/docs/Getting-Started/index.rst index 41eb0392..61a77dec 100644 --- a/docs/Getting-Started/index.rst +++ b/docs/Getting-Started/index.rst @@ -3,7 +3,7 @@ Getting Started These guides will walk you through the basics of the REBAR framework: -- First, we will go over the different configurations avaliable. +- First, we will go over the different configurations available. - Then, we will walk through adding a custom accelerator. diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Commercial-Simulators.rst index 36c3ef3b..8c1c34d7 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/Commercial-Simulators.rst @@ -1,11 +1,11 @@ -Commericial Software RTL Simulators +Commercial Software RTL Simulators ============================== VCS ----------------------- `VCS `__ is a commercial RTL simulator developed by Synopsys. -It requires commerical licenses. +It requires commercial licenses. The REBAR framework can compile and execute simulations using VCS. VCS simulation will generally compile faster than Verilator simulations. @@ -33,7 +33,7 @@ If you later create your own project, you can use environment variables to build ./simulator-- ... If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. -This will generate a vpd file (this is a proprietry waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. +This will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. If you have Synopsys licenses, we recommend using the DVE waveform viewer. Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index 41752cf0..d61b5ed7 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,7 +1,7 @@ Simulators ======================= -REBAR provides support and intergration for multiple simulation flows, for various user levels and requirments. +REBAR provides support and integration for multiple simulation flows, for various user levels and requirements. In the majority of cases during a digital design development process, a simple software RTL simulation will do. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. The following pages provide detailed information about the simulation possibilities within the REBAR framework. From 540afea07aef44b7e8b2614c397659ba66908232 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 19:12:07 -0700 Subject: [PATCH 116/120] fix config naming --- .../example/src/main/scala/Configs.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 114d8baa..edf1be75 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -168,42 +168,42 @@ class SmallBaseBoomAndRocketConfig extends Config( class DefaultBoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class SmallDefaultBoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ - new SmallBaseBoomRocketConfig) + new SmallBaseBoomAndRocketConfig) class HwachaBoomAndRocketConfig extends Config( new hwacha.DefaultHwachaConfig ++ - new DefaultBoomRocketConfig) + new DefaultBoomAndRocketConfig) class RoccBoomAndRocketConfig extends Config( new WithRoccExample ++ - new DefaultBoomRocketConfig) + new DefaultBoomAndRocketConfig) class PWMBoomAndRocketConfig extends Config( new WithPWMBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class PWMAXI4BoomAndRocketConfig extends Config( new WithPWMAXI4BoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class SimBlockDeviceBoomAndRocketConfig extends Config( new WithBlockDevice ++ new WithSimBlockDeviceBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class BlockDeviceModelBoomAndRocketConfig extends Config( new WithBlockDevice ++ new WithBlockDeviceModelBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class GPIOBoomAndRocketConfig extends Config( new WithGPIO ++ new WithGPIOBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomRocketTop ++ From 7e6591b5ea1aff4ac77fbf6d3236fc56a55a134e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 17:58:12 -0700 Subject: [PATCH 117/120] add multi-rocc and show small example --- .../example/src/main/scala/ConfigMixins.scala | 40 +++++++++++++++++++ .../example/src/main/scala/Configs.scala | 14 +++++++ 2 files changed, 54 insertions(+) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index f5e56411..0c304d60 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -106,3 +106,43 @@ class WithGPIOBoomRocketTop extends Config((site, here, up) => { top } }) + +// ------------------ +// Multi-RoCC Support +// ------------------ + +/** + * Map from a hartId to a particular RoCC accelerator + */ +case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]]) + +/** + * Mixin to enable different RoCCs based on the hartId + */ +class WithMultiRoCC extends Config((site, here, up) => { + case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil) +}) + +/** + * Mixin to add Hwachas to cores based on hart + * + * For ex: + * Core 0, 1, 2, 3 have been defined earlier + * with hartIds of 0, 1, 2, 3 respectively + * And you call WithMultiRoCCHwacha(Seq(0,1)) + * Then Core 0 and 1 will get a Hwacha + * + * @param harts Seq of harts to specifiy which will get a Hwacha + */ +class WithMultiRoCCHwacha(harts: Seq[Int]) extends Config((site, here, up) => { + case MultiRoCCKey => { + require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1)) + up(MultiRoCCKey, site) ++ harts.distinct.map{ i => + (i -> Seq((p: Parameters) => { + implicit val q = p + implicit val v = implicitly[ValName] + LazyModule(new Hwacha()(p)) + })) + } + } +}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index edf1be75..9338f4e7 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -216,6 +216,20 @@ class DualCoreBoomAndOneRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) +class DualCoreBoomAndOneHwachaRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new WithBootROM ++ + new WithMultiRoCC ++ + new WithMultiRoCCHwacha(Seq(0)) ++ // put Hwacha just on hart0 which was renumbered to Rocket + new boom.system.WithRenumberHarts ++ + new hwacha.DefaultHwachaConfig ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + class RV32BoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ From 41b4637c293eafa1021d4145b011d52bc7087b79 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 21:13:14 -0700 Subject: [PATCH 118/120] build and name hwacha correctly --- generators/boom | 2 +- .../example/src/main/scala/ConfigMixins.scala | 16 +++++++++------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/generators/boom b/generators/boom index 92313af2..2f8c419f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 92313af2a0ed4d8a93591a08f42ede1a0ffd808a +Subproject commit 2f8c419ff8fa7d848d0d92d4977885cb1e1fa5b3 diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 0c304d60..69e2b08b 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -3,14 +3,18 @@ package example import chisel3._ import chisel3.util.{log2Up} -import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.subsystem.{RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.{XLen} +import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC} + +import boom.system.{BoomTilesKey} import testchipip._ +import hwacha.{Hwacha} + import sifive.blocks.devices.gpio._ /** @@ -132,16 +136,14 @@ class WithMultiRoCC extends Config((site, here, up) => { * And you call WithMultiRoCCHwacha(Seq(0,1)) * Then Core 0 and 1 will get a Hwacha * - * @param harts Seq of harts to specifiy which will get a Hwacha + * @param harts Seq of harts to specify which will get a Hwacha */ class WithMultiRoCCHwacha(harts: Seq[Int]) extends Config((site, here, up) => { case MultiRoCCKey => { require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1)) up(MultiRoCCKey, site) ++ harts.distinct.map{ i => (i -> Seq((p: Parameters) => { - implicit val q = p - implicit val v = implicitly[ValName] - LazyModule(new Hwacha()(p)) + LazyModule(new Hwacha()(p)).suggestName("hwacha") })) } } From 4ad54ced98326078ace1bb5cfdeb6be136659e56 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 26 May 2019 17:44:27 -0700 Subject: [PATCH 119/120] use varargs instead of seq --- generators/example/src/main/scala/ConfigMixins.scala | 6 +++--- generators/example/src/main/scala/Configs.scala | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 69e2b08b..895fa86a 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -133,12 +133,12 @@ class WithMultiRoCC extends Config((site, here, up) => { * For ex: * Core 0, 1, 2, 3 have been defined earlier * with hartIds of 0, 1, 2, 3 respectively - * And you call WithMultiRoCCHwacha(Seq(0,1)) + * And you call WithMultiRoCCHwacha(0,1) * Then Core 0 and 1 will get a Hwacha * - * @param harts Seq of harts to specify which will get a Hwacha + * @param harts harts to specify which will get a Hwacha */ -class WithMultiRoCCHwacha(harts: Seq[Int]) extends Config((site, here, up) => { +class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { case MultiRoCCKey => { require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1)) up(MultiRoCCKey, site) ++ harts.distinct.map{ i => diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 9338f4e7..cba65d32 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -220,7 +220,7 @@ class DualCoreBoomAndOneHwachaRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new WithMultiRoCC ++ - new WithMultiRoCCHwacha(Seq(0)) ++ // put Hwacha just on hart0 which was renumbered to Rocket + new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket new boom.system.WithRenumberHarts ++ new hwacha.DefaultHwachaConfig ++ new boom.common.WithRVC ++ From fa080b7857d3b1fff5639a2d87fb5f9a60321a2a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 28 May 2019 12:46:57 -0700 Subject: [PATCH 120/120] fix top level naming --- generators/example/src/main/scala/Configs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index cba65d32..d6ff3432 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -217,7 +217,7 @@ class DualCoreBoomAndOneRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreBoomAndOneHwachaRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new WithMultiRoCC ++ new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket