From e078fcba49eea6a5bfa61c3587130a07fbce1a05 Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Mon, 4 Dec 2023 01:54:59 -0800
Subject: [PATCH] REFACTOR: rename arty35t explicitly

---
 fpga/Makefile                                 | 6 +++---
 fpga/src/main/scala/arty/HarnessBinders.scala | 8 ++++----
 fpga/src/main/scala/arty/TestHarness.scala    | 2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/fpga/Makefile b/fpga/Makefile
index 3d3caf1c..cfe760f4 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -72,11 +72,11 @@ ifeq ($(SUB_PROJECT),nexysvideo)
 	FPGA_BRAND        ?= xilinx
 endif
 
-ifeq ($(SUB_PROJECT),arty)
+ifeq ($(SUB_PROJECT),arty35t)
 	# TODO: Fix with Arty
 	SBT_PROJECT       ?= fpga_platforms
-	MODEL             ?= ArtyFPGATestHarness
-	VLOG_MODEL        ?= ArtyFPGATestHarness
+	MODEL             ?= Arty35THarness
+	VLOG_MODEL        ?= Arty35THarness
 	MODEL_PACKAGE     ?= chipyard.fpga.arty
 	CONFIG            ?= TinyRocketArtyConfig
 	CONFIG_PACKAGE    ?= chipyard.fpga.arty
diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index 5cef5f80..d2ce5489 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder}
 import chipyard.iobinders._
 
 class WithArtyDebugResetHarnessBinder extends HarnessBinder({
-  case (th: ArtyFPGATestHarness, port: DebugResetPort) => {
+  case (th: Arty35THarness, port: DebugResetPort) => {
     th.dut_ndreset := port.io // Debug module reset
   }
 })
 
 class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
-  case (th: ArtyFPGATestHarness, port: JTAGResetPort) => {
+  case (th: Arty35THarness, port: JTAGResetPort) => {
     port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
   }
 })
 
 class WithArtyJTAGHarnessBinder extends HarnessBinder({
-  case (th: ArtyFPGATestHarness, port: JTAGPort) => {
+  case (th: Arty35THarness, port: JTAGPort) => {
     val jtag_wire = Wire(new JTAGIO)
     jtag_wire.TDO.data := port.io.TDO
     jtag_wire.TDO.driven := true.B
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
 })
 
 class WithArtyUARTHarnessBinder extends HarnessBinder({
-  case (th: ArtyFPGATestHarness, port: UARTPort) => {
+  case (th: Arty35THarness, port: UARTPort) => {
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
       IOBUF(th.uart_rxd_out,  port.io.txd)
       port.io.rxd := IOBUF(th.uart_txd_in)
diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala
index 0a81740a..cdb1d4e4 100644
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -10,7 +10,7 @@ import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
 
 import chipyard.harness.{HasHarnessInstantiators}
 
-class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
+class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
   // Convert harness resets from Bool to Reset type.
   val hReset = Wire(Reset())
   hReset := ~ck_rst